MOSFET DEVICE AND ITS MANUFACTURING PROCESS

Abstract

MOSFET device lying on a substrate (102) comprising: a source area (127); a drainage area (129); a canal area (113) located between the Source area (127) and the Drain area (129); a gate dielectric layer (104) that lies above the channel region (113); a gate layer (106) that lies above the gate dielectric layer (104); a first sidewall spacer (122A) adjacent to the gate dielectric layer (104) and the gate layer (106) and located above the source region (127) or the drain region (129); a second sidewall spacer (122B) adjacent to the gate dielectric layer (104) and the gate layer (106) and located above the other of the source region (127) or the drain region (129); a first pair of air gaps comprising a first air gap (138a) and a second air gap (140a) located in the first sidewall spacer (122A), wherein the first air gap (138a) is adjacent to the gate layer (106) and the second air gap (140a) is located above the source region (127) or the drain region (129), wherein the first air gap (138a) has a principal axis parallel to the gate layer (106) and the second air gap (140a) has a principal axis parallel to a principal surface of the substrate (102); and a second pair of air gaps comprising a third air gap (138b) and a fourth air gap (140b) located in the second sidewall spacer (122B), wherein the third air gap (138b) is adjacent to the gate layer (106) and the fourth air gap (140b) is located above the source region (127) or the drain region (129), wherein the third air gap (138b) has a principal axis parallel to the gate layer (106) and the fourth air gap (140b) has a principal axis parallel to a principal surface of the substrate (102), wherein the first pair of air gaps has a size different from the second pair of air gaps.

Description

STATE OF THE ART

[0001] Parasitic / superimposed capacitances resulting from capacitive effects across sidewall spacers and / or from the dielectric gate oxide layer reduce the performance of metal oxide semiconductor field-effect transistors (MOSFETs), especially for radio frequency (RF) MOSFETs. In particular, the magnitude of the parasitic / superimposed capacitances can significantly affect the switching speed of the MOSFET. The larger the capacitance, the more charge must be drawn for the MOSFET to switch, thus considerably slowing the switching speed.

[0002] Parasitic capacitances can exhibit various transition and superposition capacitances. Transition capacitances depend on the depth of the transitions. Superposition capacitances depend on the amount of superposition between the implanted regions (i.e., source and drain regions) and the gate. In addition to transition and superposition capacitances, inner margin capacitances, resulting from the interaction of charge from the side of the gate with the source and drain regions, and outer margin capacitances, resulting from the interaction of charge from the bottom of the gate with the source and drain regions, may be present. These can also adversely affect the performance of MOSFET devices. Furthermore, the use of high-k gate and spacer materials can increase the magnitude of margin fields, resulting in higher margin capacitance, which can exhibit short-channel performance.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 6 127 711 A, US 6 190 996 B1 and US 2015 / 0 263 122 A1.

[0004] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 is a vertical cross-sectional view illustrating a step in the formation of a continuous gate dielectric layer, a continuous gate layer and photoresist on a substrate in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 2 is a vertical cross-sectional view illustrating a step in structuring the continuous gate dielectric layer and the continuous gate layer in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 3 is a vertical cross-sectional view illustrating a step towards ion implantation to form source and drain expansion regions in the substrate in a semiconductor device manufacturing process, in accordance with some embodiments. Fig. Figure 4 is a vertical cross-sectional view illustrating a step in the formation of a continuous first oxide layer and a continuous nitride layer in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 5 is a vertical cross-sectional view illustrating a step in the formation of a continuous second oxide layer over the continuous nitride layer in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 6 is a vertical cross-sectional view illustrating a step in etching the continuous first oxide layer, nitride layer and second oxide layer to form sidewall spacers in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 7 is a vertical cross-sectional view illustrating a step towards ion implantation to form deep source and drain regions in the substrate in a semiconductor device manufacturing process, in accordance with some embodiments. Fig. Figure 8 is a vertical cross-sectional view illustrating a step in the silicideization of the deep source and drain regions and the gate in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 9 is a vertical cross-sectional view illustrating a step in the formation of trenches in the nitride layer of the sidewalls in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 10A is a vertical cross-sectional view illustrating a step in the formation of air gaps in the nitride layer of the sidewalls by depositing an etch stop layer in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. 10B is a close-up view of a section of Fig. 10A. Fig. Figure 11 is a vertical cross-sectional view illustrating a step in the formation of an interdielectric layer and source / drain electrodes in a manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 12 is a vertical cross-sectional view illustrating a semiconductor device having air gaps in only one of the side walls, in accordance with some embodiments. Fig. Figure 13 is a vertical cross-sectional view illustrating a semiconductor device in which a first transistor structure may have air gaps in both side walls, a second transistor structure may have air gaps in one side wall, and a third transistor structure may not have air gaps in the side walls. Fig. Figure 14 is a flowchart illustrating a manufacturing process for a semiconductor device having air gaps in accordance with some embodiments. Fig. Figure 15A is a vertical cross-sectional view illustrating a semiconductor device in which air gaps in the sidewalls are formed only over the source and / or drain expansion regions. Fig. 15B is a vertical cross-sectional view showing a step in the formation and structuring of a photoresist layer over the in Fig. 8 illustrated structure for the production of the in Fig. 15A illustrated device illustrated. Fig. 15C is a vertical cross-sectional view showing a step in the formation of trenches in the nitride layer of the sidewalls in a manufacturing process of the in Fig. 15A illustrated device illustrated. Fig. 16 is a vertical cross-sectional view showing a step towards the formation of a photoresist layer over the in Fig. Figure 8 illustrates the structure in another manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 17 is a vertical cross-sectional view illustrating a step in structuring a photoresist layer to form a first section of transistor structures with air gaps in a section of the sidewall spacers next to the gate and a second section of transistor structures with air gaps in a section of the sidewall spacers over the source / drain regions in the other manufacturing process of a semiconductor device, in accordance with some embodiments. Fig. Figure 18 is a vertical cross-sectional view illustrating a step in the formation of trenches in the first section of the transistor structures to form air gaps in a section of the sidewall spacers next to the gate and the formation of trenches in the second section of the transistor structures to form air gaps in a section of the sidewall spacers over the source / drain regions in the other manufacturing process of a semiconductor device, in accordance with some embodiments. Fig. Figure 19 is a vertical cross-sectional view illustrating a step towards the formation of air gaps in the first section of the transistor structures in the sidewall spacers next to the gate and the formation of air gaps in the second section of the transistor structures in a section of the sidewall spacers above the source / drain regions in the other manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 20 is a vertical cross-sectional view illustrating one step in the formation of an interdielectric layer and source / drain electrodes in the other manufacturing process of a semiconductor device in accordance with some embodiments. Fig. Figure 21 is a vertical cross-sectional view illustrating a semiconductor device in which a first section of transistor structures may have a single air gap in the nitride layer of the sidewalls adjacent to the structured gate dielectric layer and the structured gate layer, and a second section of transistor structures may have a single air gap in the nitride layer of the sidewalls above the source or drain extension regions, in accordance with some embodiments. Fig. Figure 22 is a vertical cross-sectional view illustrating a semiconductor device comprising a first section of transistor structures with a single air gap in the nitride layer of the sidewalls adjacent to the structured gate dielectric layer and the structured gate layer, and air gaps in the nitride layer of the sidewalls over the source and drain extension regions, and a second section of transistor structures with a single air gap in the nitride layer of the sidewalls over the source or drain extension regions and air gaps in the nitride layer of the sidewalls adjacent to the structured gate dielectric layer and the structured gate layer, in accordance with some embodiments. Fig. Figure 23 is a flowchart illustrating an alternative manufacturing process for a semiconductor device having air gaps, in accordance with some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features might not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the different examples.This repetition serves the purpose of simplification and clarity and does not itself imply any relationship between the different embodiments and / or configurations discussed.

[0007] Furthermore, spatially relative terms such as "underlying," "below," "under," "superior," "above," and the like may be used herein to facilitate description and to describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the drawings. These spatially relative terms are intended to encompass various orientations of the device in use or operation in addition to the orientation shown in the drawings. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0008] In general, the structures and methods of this disclosure can be used to form metal-oxide semiconductor field-effect transistor (MOSFET) devices in which at least some of the MOSFETs have air gaps in at least one sidewall spacer of the MOSFETs. The capacitance of a parallel plate capacitor is described by Equation 1 below. C=QV=εAd where Q is the charge on the plates, V is the voltage across the gap between the plates, ε is the dielectric constant, A is the area of ​​the plates, and d is the distance between the plates. Therefore, for a given area and distance, the capacitance can be reduced by using a material with a lower dielectric constant than air between the parallel plates. Silicon oxide (SiO2) has a dielectric constant of 3.9, while silicon nitride (Si3N4) has a dielectric constant of 7.9. In contrast, air has a dielectric constant of 1.0.Therefore, by forming air gaps instead of dielectric spacers made of higher dielectric materials such as silicon oxide or silicon nitride, transition, superposition and / or margin capacitance in the MOSFET can be reduced, thereby increasing and / or maintaining switching speed and / or improving short-channel performance, which is adversely affected by capacitance.

[0009] In relation to Fig. 1. A continuous gate dielectric layer 104L, a continuous gate layer 106L, and a photoresist layer 108 can be formed on a substrate 102. The substrate 102 can be made of a suitable material, such as silicon, silicon-on-insulator (SOI), or silicon-on-sapphire (SOS). The continuous gate dielectric layer 104L can be made of any suitable material, such as an oxide or nitride, like silicon oxide. Other suitable materials are within the scope of disclosure. The continuous gate layer 106L can be made of a metal, such as tungsten, nickel, aluminum, or alloys thereof, or the continuous gate layer 106L can be made of polysilicon. Other suitable materials are within the scope of disclosure. The photoresist layer 108 can be a positive or negative photoresist.The continuous gate dielectric layer 104L and the continuous gate layer 106L can be formed by any suitable method. For example, the continuous gate dielectric layer 104L and the continuous gate layer 106L can be formed by chemical vapor deposition (CVD), organometallic chemical vapor deposition (OMCVD), or atomic layer deposition (ALD).

[0010] In relation to Fig. 2. The photoresist layer 108 can be lithographically structured to form an etching mask for creating a gate. The photoresist layer 108 can be made of either a positive photoresist material, in which ultraviolet (UV) radiation makes the polymer more soluble and easier to remove, or a negative photoresist material, in which UV irradiation causes the polymer to cross-link, making it more difficult to remove. The photoresist layer 108 is exposed to UF light through a photolithography mask, and unwanted material is removed. An etching process can then be performed to structure the continuous gate dielectric layer 104L and the continuous gate layer 106L, forming structured gate dielectric layers 104 and structured gate layers 106. The photoresist can then be removed by an ashing process.

[0011] In relation to Fig. 3. The substrate 102 can be subjected to a first ion implantation step 114 to form source expansion regions 110 and drain expansion regions 112 in the substrate 102. The structured gate layers 106 can mask sections of the substrate between the source expansion regions 110 and the drain expansion regions 112. Therefore, the source expansion regions 110 and the drain expansion regions 112 can be self-aligned with the structured gate layers 106. In particular, if the continuous gate layer 106L is structured and used as a mask to form the source and drain extension regions 110, 112, instead of first forming the source and drain extension regions 110, 112 and then depositing and structuring the continuous gate layer 106L, there is no need to align a separate gate mask to align the structured gate layers 106 with the source and drain extension regions 110, 112.This means that by using the structured gate layer 106L as a mask, the source and drain extension regions 110 and 112 are automatically aligned (i.e., self-aligned) with the structured gate layer 106L. The source extension regions 110 and the drain extension regions 112 can be either p- or n-doped, as desired. Exemplary n-dopers include, but are not limited to, antimony, arsenic, and phosphorus. Exemplary p-dopers include, but are not limited to, boron, aluminum, and gallium. The source extension regions 110 and drain extension regions 112 have an implanted ion concentration of 2 × 10⁻⁶. 20 up to 2 × 10 21Although larger or smaller doping concentrations can be used. The areas beneath the structured gate layers 106 and structured gate dielectric layers 104, located between the source expansion areas 110 and the drain expansion areas 112, can form channel regions 113.

[0012] In relation to Fig. 4. A continuous first oxide layer 116L can be uniformly deposited over the substrate 102 and the sidewalls and top surfaces of the structured gate dielectric layers 104 and structured gate layers 106. The continuous first oxide layer 116L can be made from any suitable oxide, such as SiO2, HfO2, Al2O, Ta2O5, ZrO2, or TiO2. Other suitable materials that form the continuous first oxide layer 116L are within the scope of this disclosure. The continuous first oxide layer 116L can be formed by any suitable process. For example, the continuous first oxide layer 116L can be formed by chemical vapor deposition (CVD), organometallic chemical vapor deposition (OMCVD), or atomic layer deposition (ALD).

[0013] Next, a continuous silicon nitride layer 118L can be uniformly deposited over the continuous first oxide layer 116L. Similar to the continuous first oxide layer 116L, the silicon nitride layer 118L can be formed by any suitable method. For example, the silicon nitride layer 118L can be formed by chemical vapor deposition (CVD), organometallic chemical vapor deposition (OMCVD), or atomic layer deposition (ALD).

[0014] In relation to Fig. 5. A continuous second oxide layer 120L can be uniformly deposited over the continuous silicon nitride layer 118L. In this way, a continuous oxide / nitride / oxide sandwich layer 122L can be formed over the substrate 102 and the structured gate dielectric layer 104 and the structured gate layer 106. The continuous second oxide layer 120L can be made of the same material as the continuous first oxide layer 116L or it can be made of a different material. Similar to the continuous first oxide layer 116L, the continuous second oxide layer 120L can be formed by any suitable method. For example, the continuous second oxide layer 120L can be formed by chemical vapor deposition (CVD), organometallic chemical vapor deposition (OMCVD), or atomic layer deposition (ALD).

[0015] In relation to Fig. 6. The continuous first oxide layer 116L, the continuous silicon nitride layer 118L, and the continuous second oxide layer 120L, i.e., continuous oxide / nitride / oxide (ONO), can combine to form a sandwich structure 112L, which can be structured to form first sidewall spacers 122A and second sidewall spacers 122B adjacent to the sidewalls of the structured gate dielectric layers 104 and the structured gate layers 106. In this step, a section of the top surfaces of the source extension regions 110 and the drain extension regions 112 is exposed beyond the first and second sidewall spacers 122A, 122B. The first and second sidewall spacers 122A, 122B can be formed such that the structured first oxide layer 116 has a thickness T. O1 in the range of 2nm-20nm, the nitride layer has a thickness (T N) in the range of 2nm - 25nm and the structured second oxide layer has a thickness (T O2 ) in the range of 10nm - 50nm.

[0016] In relation to Fig. 7. A second ion implantation 124 can be performed. In this step, the exposed sections of the source expansion areas 110 and the drain expansion areas 112 can be ion-implanted to form deep source areas 126 adjacent to the source expansion areas 110 and deep drain areas 128 adjacent to the drain expansion areas 112. The deep source areas 126 and the deep drain areas 128 can have an implanted ion concentration in the range of 2 × 10 21 up to 2 × 10 22exhibit. Although larger or smaller doping concentrations can be used. The source expansion areas 110 and the deep source areas 126 can be collectively referred to as source areas 127. The drain expansion areas 112 and the deep drain areas 128 can be collectively referred to as drain areas 129. The ions implanted in the second ion implantation step 124 can be the same as or different from the ions implanted in the first ion implantation step 114.

[0017] In relation to Fig. 8. A silicide layer 130 can be formed on the top surfaces of the deep source regions 126 and the deep drain regions 128. The silicide layer 130 can be formed by depositing a thin metal layer (not shown) and heating it to react with the silicon in the deep source regions 126 and the deep drain regions 128. Furthermore, as illustrated, if the structured gate layer 106 is made of polysilicon, metal can be deposited on the top surface of the structured gate layer 106 and heated to form a silicide layer 130 on the top surface of the structured gate layer 106.Together, the structured gate dielectric layer 104, structured gate layer 106, first sidewall spacer 122A, second sidewall spacer 122B, source extension regions 110, drain extension regions 112, channel region 113, source regions 127, and drain regions 129 exhibit a transistor structure 131. In one embodiment, the transistor structure 131 can be a MOSFET. The silicide 130, which is formed over the gate electrode 106 as well as the deep source regions 126 and deep drain regions 128, can improve the conductivity of subsequently formed metal vias, which can be coupled to the gate electrode 106 as well as the deep source regions 126 and deep drain regions 128.

[0018] In relation to Fig. 9. The structured nitride layers 118 in the first sidewall spacer 122A and the second sidewall spacer 122B can be selectively etched relative to the structured first oxide layers 116 and the structured second oxide layers 120, so that first and third trenches 132a, 132b can be formed in the structured nitride layers 118 adjacent to the structured gate dielectric layer 104 and the structured gate layer 106. Furthermore, second and fourth trenches 134a, 134b can be formed over the source or drain expansion regions 110, 112. The first, second, third, and fourth trenches 132a, 132b, 134a, 134b can be selectively etched using a wet etching process, a dry etching process, or a combination of wet and dry etching processes. Therefore, the first trench 132a and the second trench 134a can be formed in the first side wall spacer 122A.The third trench 132b and fourth trench 134b can be formed in the second side wall spacer 122B. The first trench 132a and second trench 134a can be referred to as a first pair of trenches. The third trench 132b and fourth trench 134b can be referred to as a second pair of trenches. In different embodiments, the structured nitride layers 118 can be etched such that the first and third trenches 132a, 132b have a depth between 0.001 and 0.7 times the total height H. G of the gate as in Fig. Figure 10B illustrates and is discussed in detail below. In some embodiments, the first and third trenches 132a, 132b may have a depth between 0.10 and 0.5 of the total height H. G of the gate, such as between 0.2 and 0.4. In different embodiments, the structured nitride layers 118 can be etched such that the second and fourth trenches 134a, 134b have a depth of 0.001-0.7x the widths TSW of the first and second side wall spacers 122a, 122B may have values ​​between 0.10 and 0.5, and between 0.2 and 0.4.

[0019] In relation to Fig. 10A and Fig. 10B A contact etch stop layer 136 can be formed over the surface of the substrate 102, the first and second sidewall spacers 122A, 122B, and the structured gate layers 106. The contact etch stop layer 136 can be made of any suitable material, such as silicon dioxide. Other suitable materials are within the scope of this disclosure. The contact etch stop layer 136 can cover the tops of the first, second, third, and fourth trenches 132a, 132b, 134a, 134b without filling the first, second, third, and fourth trenches 132a, 132b, 134a, 134b. In this way, first and third air gaps 138a, 138b and second and fourth air gaps 140a, 140b can be formed in the structured nitride layer 118 of the first and second sidewall spacers 122a, 122B. The first air gap 138a and second air gap 140a can be referred to as a first pair of air gaps.The third air gap 138b and fourth air gap 140b can be referred to as a second pair of air gaps.

[0020] The dimensions of the first, second, third, and fourth air gaps 138a, 140a, 138b, 140b can be controlled by the thickness of the structured nitride layer 118 as well as the etching time of the selective etching of the structured nitride layer 118. The thickness of the structured nitride layer 118 can determine the thickness of air gaps 138a, 138b and the depth of air gaps 140a, 140b as shown in Fig. Figure 10B illustrates and discusses in detail below. The thickness of the structured first oxide layer 116 can be between 2 nm and 20 nm. The thickness of the structured nitride layer 118 can be between 2 nm and 25 nm. The thickness of the structured second oxide layer 120 can be between 10 nm and 50 nm. Similarly, the length of the etching time for the selective etching of the structured nitride layer 118 can determine the depth of the air gaps 128a, 128b and the thickness of the air gaps 140a, 140b. Therefore, the dimensions of the first, second, third, and / or fourth air gaps 138a, 140a, 138b, 140b can be selected as desired based on the configuration of the device being manufactured.Note that if the thickness of the structured nitride layer 118 is too great, the first and third trenches 138a, 138b may fill with contact etch stop layer material when the contact etch stop layer 136 is deposited, reducing or eliminating the first and third air gaps 138a, 138b. If the thicknesses and / or heights of the first, second, third, and / or fourth air gaps 138a, 140a, 138b, 140b are too small, the first, second, third, and / or fourth air gaps 138a, 140a, 138b, 140b may not provide the desired reduction in parasite and / or fringe capacity.

[0021] In relation to Fig. 6 and Fig. 10B has a total height H G The gate consists of the structured gate dielectric layer 104, the structured gate layer 106, and the silicide layer 130. The total spacer width T SW The first and second side wall spacers 122A, 122B have a thickness T O1the structured first oxide layer 116, the thickness T N the structured nitride layer 118 and the thickness T O2 the structured second oxide layer 120 in its thickest form, as in Fig. Figure 6 illustrates and is discussed above. As discussed above, the first and second sidewall spacers 122A and 122B can be formed such that the structured first oxide layer 116 has a thickness T. O1 in the range of 2nm - 20nm, the structured nitride layer has a thickness (T N ) in the range of 2nm - 25nm and the structured second oxide layer has a thickness (T O2 ) in the range of 10nm - 50nm.

[0022] As discussed above, replacing a higher dielectric material, such as silicon oxide or silicon nitride, with a lower dielectric material (e.g., air) between the charge-carrying plates can reduce parasitic and seam capacitances that are unintentionally generated. If only a portion of the higher dielectric material in a layer is replaced with a lower dielectric material, the dielectric constant of the mixed material (and therefore the capacitance) is determined by the weighted average of the amounts of the higher and lower dielectric materials. Therefore, increasing the size of the air gap can reduce parasitic and seam capacitances. In embodiments, the height H can be A1 of the first (or third) air gap 138a, 138b between 0.001-0.7x of the total height H G of the gate, such as between 0.10 and 0.5 times the total height H G of the gate, such as between 0.2 and 0.4 times the total height HG of the gate. The thickness T A1 The thickness of the first (or third) air gap 138a, 138b can be equal to, less than, or greater than the thickness of the structured Si3N4 layer 118. The thickness T A The first (or third) air gap 138a, 138b can be in the range of 2 nm - 25 nm. The height H A2 The thickness of the second (or fourth) air gap 140a, 140b can be equal to, less than, or greater than the thickness of the structured Si3N4 layer 118. The height H A2 The thickness of the second (or fourth) air gap 140a, 140b can be in the range of 2 nm - 25 nm. A2 of the second (or fourth) air gap 140a, 140b can be between 0.001-0.7x the widths T SWof the first and second side wall spacers 122A, 122B. In one embodiment, the size of the first pair of air gaps can be different from the second pair of air gaps. For example, in one embodiment, the first and third air gaps 138a, 138b can have a volume of 10-90% of the second and fourth air gaps 140a, 140b.

[0023] In relation to Fig. 11 An interdielectric layer 142 can be deposited over the contact etch stop layer 126. A photoresist layer (not shown) can then be deposited and patterned to form vias (not shown) in the interdielectric layer 142 and the contact etch stop layer 136, and filled with metal, such as tungsten carbide (W), copper (Cu), cobalt (Co), molybdenum (Mo), rubric (Ru), other elemental metals, or an alloy or combination thereof. Other suitable materials are within the scope of this disclosure. In this way, vias 144 coupled to the source and drain regions 127, 129 can be formed to complete the integrated semiconductor device 100.The resulting integrated semiconductor device 100 has transistor structures 131A in which both the first and second sidewall spacers 122A, 122B have a pair of air gaps (first, second, third and fourth air gaps 138a, 140a, 138b, 140b).

[0024] In some device configurations, adjacent pairs of MOSFETs share a common gate. In these configurations, it may be unnecessary to fabricate one or more of the first, second, third, or fourth air gaps 138a, 140a, 138b, 140b. Furthermore, in other device configurations, the spacing between adjacent MOSFETs may not be symmetrical. That is, the spacing on the source side between adjacent MOSFETs may differ from the spacing between MOSFETs on the drain side. In these configurations, it may likewise be unnecessary to fabricate one or more of the first, second, third, or fourth air gaps 138a, 140a, 138b, 140b. In still other configurations, the capacitances between the structured gate layer 106 and the source / drain electrodes 144 may be small enough that the first and third air gaps 138a, 138b are unnecessary.In other configurations, the capacitances between the structured gate layer 106 and the source / drain regions 127, 129 may be small enough that the second and fourth air gaps 140a, 140b are unnecessary. Fig. Figures 12, 13 and 15-23 illustrate different embodiments with different combinations of the different air gaps, such as one or more of the first, second, third or fourth air gaps 138a, 140a, 138b, 140b and methods for manufacturing these embodiments.

[0025] Fig. Figure 12 illustrates another embodiment of an integrated semiconductor device 200 in which first and second air gaps 138a, 140a can be formed only over the source regions 127, or third and fourth air gaps 138b, 140b can be formed over the drain regions 129, but not over both the source and drain regions 127, 129 of the same transistor structure 131b. For example, Figure 12 illustrates Fig. 12 first and second air gaps 138a and 140a are formed only over source areas 127, while no air gaps are formed over drain areas 129. Alternatively, first and second air gaps 138b and 140b are formed only over drain areas 129, while no air gaps are formed over source areas 127.

[0026] To the in Fig. To form the illustrated embodiment structure shown in 12, the procedure as discussed above can be carried out up to the point shown in Fig. The illustrated step 8 can be followed. Then, a photoresist layer 109 can be deposited over the entire surface and textured so that only the source regions 127 or the drain regions 129 are exposed. In this way, the photoresist 108 protects the covered first or second sidewall spacer 122A, 122B, while the exposed first or second sidewall spacer 122A, 122B is etched. Manufacturing can then proceed as described in Fig. Figure 9 illustrates how to proceed. That is, first and second trenches 132a, 134a can be formed in the exposed sidewall spacer 122A. In an alternative embodiment, third and fourth trenches 132b, 134b can be formed in the exposed sidewall spacer 122B. Next, the photoresist layer 108 can be removed and the etch stop layer 136 applied as shown in Figure 9. Fig. 10A, Fig. Figure 10B illustrates how to deposit material to effectively form first and second air gaps 138a, 140a or third and fourth air gaps 138b, 140b. The resulting integrated semiconductor device 200 has transistor structures 131B in which one of the first or second sidewall spacers 122A, 122B has a pair of air gaps (first, second, third and fourth air gaps 138a, 140a, 138b, 140b) and the other of the first or second sidewall spacer 122A, 122B has no air gaps.

[0027] Fig. Figure 13 illustrates another embodiment of an integrated semiconductor device 300. The integrated semiconductor device 300 has transistor structures 131A in which both the first and second sidewall spacers 122A, 122B have a pair of air gaps (first, second, third and fourth air gaps 138a, 140a, 138b, 140b), transistor structures 131B in which one of the first or second sidewall spacers 122A, 12B has a pair of air gaps (first, second, third and fourth air gaps 138a, 140a, 138b, 140b) and the other of the first or second sidewall spacer 122A, 122B has no air gaps, and transistor structures 131C in which neither the first nor the second sidewall spacer 122A, 122B has a pair of air gaps. exhibits.

[0028] To the in Fig. To form the illustrated embodiment structure 13, one can refer to the method discussed above in Fig. Follow the illustrated steps in 8. Similar to the one in Fig. In the illustrated embodiment 12, a photoresist layer 109 can be deposited and structured over the entire surface. In this embodiment, a first section of the MOSFETs has exposed first and second sidewall spacers 122A, 122B, a second section of the MOSFETs has only the first or second sidewall spacers 122A, 122B exposed, while a third section of the MOSFETs has no exposed sidewall spacers. Manufacturing can then proceed as in Fig. Figure 9 illustrates how to proceed. That is, first, second, third, and fourth trenches 132a, 134a, 132b, 134b can be formed in the exposed sidewall spacers 122A and 122B of the first section. Additionally, first and second trenches 132a, 134a can be formed in the first sidewall spacer 122A (or alternatively, third and fourth trenches 132b, 134b in the second sidewall spacer 122b) of a second section. Next, the photoresist layer 108 can be removed and the etch stop layer 136 deposited, as shown in Fig. 10A, Fig. 10B illustrates.

[0029] In relation to Fig. Figure 14 illustrates a flowchart of a general method 400 for manufacturing a semiconductor device 100, 200, 300 having first, second, third and fourth air gaps 138a, 140a, 138b, 140b, in accordance with some embodiments.With respect to step 402, a transistor structure 131 can be defined as having a source region 127, a drain region 129, a channel region 113 located between the source region 127 and the drain region 129, a gate dielectric layer 104 located above the channel region 113, a metal or polysilicon gate layer 106 located above the gate dielectric layer 104, a first sidewall spacer 122A located adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and above one of the source region 127 or drain region 129, and a second sidewall spacer 122B located adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and above the other of the Source area 127 or drain area 129 is located, exhibits, and will be formed.

[0030] With respect to step 404, the nitride layer 118 can be selectively etched from the first sidewall spacer 122A to the first and second oxide layers 116, 120 to form a first and second trench 132a, 134a in the first sidewall spacer 122A. The first and second trenches 132a, 134a can have a first trench 132a adjacent to the metal or polysilicon gate layer 106 and a second trench 134a located above the source or drain region 127, 129. The depth of the first and second trenches 132a, 134a can be controlled based on the etching time. That is, the longer the etching, the deeper the trenches can be formed. The actual etching time for a desired depth depends on the etchant used and the desired trench depth. For example, when etching with phosphoric acid, the etching rate can be slowed down by increasing the water content of the acid.However, the etching rate can be increased by raising the temperature. Furthermore, as discussed above, the following can be done to... Fig. 12 and Fig. 13 illustrated embodiments, one or both side wall spacers 122A, 122B are protected from the section of the MOSFETs with a photoresist layer 108, while the exposed spacers are etched to produce first, second, third and fourth trenches 132a, 134a, 132b, 134b.

[0031] With respect to step 406, an etch stop layer 136 can be deposited over the first sidewall spacer 122A to form a first air gap 138a adjacent to the metal or polysilicon gate layer 106 and a second air gap 140a located over the source or drain region 127, 129. The first air gap 138a can have a principal axis parallel to the metal or polysilicon gate layer 106, and the second air gap 140a has a principal axis parallel to a major surface of the substrate 102.

[0032] In general, the structures and methods of the present disclosure can be used to form metal-oxide semiconductor field-effect transistor (MOSFET) semiconductor devices in which at least some of the MOSFETs have air gaps in at least one sidewall spacer of the MOSFETs. The air gaps can reduce junction, superposition, and / or bridging capacitances in the MOSFET relative to a MOSFET made with higher dielectric materials by lowering the dielectric constant of the sidewall spacer 122A, 122B, thereby increasing switching speed and / or improving short-channel performance, which is adversely affected by capacitance. In some embodiments, air gaps are formed in both sidewall spacers of the MOSFETs.In other embodiments, a first section of the MOSFET has air gaps in both sidewall spacers of the MOSFETs, while a second section of the MOSFET has air gaps in only one of the sidewall spacers. In other embodiments, a first section of the MOSFET has air gaps in both sidewall spacers of the MOSFETs, a second section of the MOSFET has air gaps in only one of the sidewall spacers, and a third section of the MOSFETs has no air gaps in the sidewall spacers.

[0033] One embodiment is shown on a metal oxide semiconductor transistor located on a substrate comprising a source region 127, a drain region 129, a channel region 113 located between the source region 127 and the drain region 129, a gate dielectric layer 104 located above the channel region 113, a gate layer 106 located above the gate dielectric layer 104, a first sidewall spacer 122A located adjacent to the gate dielectric layer 104 and the gate layer 106 and above one of the source region 127 or drain region 129, and a second sidewall spacer 122B located adjacent to the gate dielectric layer 104 and the gate layer 106 and above the other of the source region 127 or drain region 129. and has first and second air gaps 138a, 140a, which are located in the first side wall spacer 122A,which has a first air gap 138a adjacent to the structured gate layer 106 and a second air gap 140a located above the source or drain region 127, 129, wherein the first air gap 138a has a principal axis parallel to the gate layer 106 and the second air gap 140a has a principal axis parallel to a principal surface of the substrate 102.

[0034] Fig. Figure 15A illustrates another embodiment of an integrated semiconductor device 500 in which second and fourth air gaps 140a, 140b may be formed in the first and second sidewalls 122A, 122B above the source or drain extension region 110, 112, but not adjacent to the gate layer 106. In a first embodiment of the method for fabricating the integrated semiconductor device 500, a “thick” continuous nitride layer 118L may be deposited. If the thickness T NSince the thickness of the structured nitride layer 118 is above a threshold thickness, the first and third grooves 132a, 132b that may be formed therein can also have a thickness exceeding a threshold thickness. As a result, the first and third grooves 132a and 132b can fill with material from the contact etch stop layer 136 if the contact etch stop layer 136 is formed above the first and second sidewall spacers 122A, 122B. Therefore, in some embodiments, the first and third air gaps 138a, 138b may not be formed in the first and second sidewall spacers 122A, 122B. However, in such embodiments, the second and fourth grooves 134a, 134b may not be filled due to the horizontal orientation of the second and fourth grooves 134a, 134b.In such an embodiment, a transistor structure 131 can be formed in which only the second and fourth air gaps 140a, 140b are formed in the first and second sidewalls 122A, 122B above the source or drain expansion region 110, 112. The resulting integrated semiconductor device 500 has transistor structures 131D in which both the first and second sidewall spacers 122A, 122B have an air gap (second and fourth air gaps 140a, 140b) above the source and drain expansion region 110, 112.

[0035] A second embodiment of the method for manufacturing an integrated semiconductor device 500 is described in Fig. 15B and Fig. 15C illustrates. Regarding Fig. In the second embodiment of method for manufacturing integrated semiconductor device 500, 15B can deposit a photoresist layer 108 over the in Fig. The structure illustrated in section 8, which is discussed above, is deposited. The photoresist 108 can then be structured so that only the horizontal ends of the structured silicon nitride layer 118 are exposed.

[0036] In relation to Fig. 15C can then selectively etch the silicon nitride layer as in Fig. 9 illustrated and discussed above. After the desired thickness of the second and fourth trenches 134a, 134b in the first and second sidewall spacers 122A, 122B is achieved, the photoresist layer 108 can be removed and a contact etch stop layer 136 applied as shown in Fig. 10A and Fig. Figure 10B illustrates and discusses above. The interlayer dielectric 142 can then be deposited and the source and drain electrodes 144 as shown in Figure 10B. Fig. 11 illustrated and discussed above.

[0037] Fig. Figures 16-20 illustrate steps in another method for fabricating an integrated semiconductor device 600 according to embodiments. With regard to Fig. 16 can apply a photoresist layer 108 over the in Fig. The structure illustrated above, discussed in section 8, can be separated. Regarding Fig. 17. The photoresist layer 108 can be textured to expose the first and second sidewall spacers 122A, 122B. As illustrated, the top surface of the silicided layer 130 of the textured gate layer 106 can also be exposed. As in relation to Fig. As illustrated in Figure 9 and discussed above, the selective etchings used to etch the structured silicon nitride layer 118 do not sufficiently etch the silicide layer 130. In an alternative embodiment of the method, only the first and second sidewall spacers 122A, 122B can be exposed when the photoresist 108 is structured.

[0038] In relation to Fig. 18 The structured silicon nitride layer 118, adjacent to the structured gate dielectric layer 104 and the structured gate layer 106, can be selectively etched to form first and third trenches 132a, 132b. However, the sections of the structured silicon nitride layer 118 above the source or drain extension region 110, 112 are not etched because they are protected by the photoresist layer 108.

[0039] In relation to Fig. 19. The photoresist layer 108 can be removed by any suitable method, such as ashing. Next, a contact etch stop layer 136 can be formed over the surface of the substrate 102, the first and second sidewall spacers 122A, 122B, and the structured gate layers 106. As discussed above, the contact etch stop layer 136 can be made of any suitable material. The contact etch stop layer 136 can cover the top surfaces of the first and third trenches 132a, 132b. In this way, first and third air gaps 138a, 138b can be formed in the structured nitride layer 118 of the first and second sidewall spacers 122A, 122B without forming second and fourth air gaps 140a, 140b over the source or drain expansion regions 110, 112.

[0040] In relation to Fig. 20. An interdielectric layer 142 can be deposited over the contact etch stop layer 136. Then, a photoresist layer (not shown) can be deposited and patterned to form vias (not shown) in the interdielectric layer 142 and the contact etch stop layer 136, and filled with metal, such as W, Cu, Co, Mo, Ru, other elemental metals, or an alloy or combination thereof. Other suitable materials are within the scope of this disclosure.In this way, vias 144 coupled to the source and drain region 127, 129 can be formed to complete the integrated semiconductor device 600, which has transistor structures 131E, having air gaps 138a and 138b in the structured nitride layer 118 of the first and second sidewall spacer 122A, 122B, without forming second and fourth air gaps 140a, 140b over the source or drain extension region 110, 112.

[0041] Fig. Figure 21 illustrates another embodiment of an integrated semiconductor device 700, in which a first transistor structure 131F may have a single air gap 138a in the structured nitride layer 118 in one of the first or second sidewall spacers 122A, 122B, adjacent to the structured gate dielectric layer 104 and the structured gate layer 106, and a second transistor structure 131G may have a single air gap 140b in the structured nitride layer 118 of one of the first or second sidewall spacers 122A, 122B above the source or drain extension area 110, 112, in accordance with some embodiments.In an alternative embodiment (not shown), all of the transistor structures can have a single air gap 138a in the structured nitride layer 118 in one of the first or second sidewall spacers 122A, 122B, adjacent to the structured gate dielectric layer 104 and the structured gate layer 106. In yet another embodiment (not shown), all of the transistor structures can have a single air gap 140b in the structured nitride layer 118 of one of the first or second sidewall spacers 122A, 122B above the source or drain expansion region 110, 112.

[0042] Fig. Figure 22 illustrates another embodiment of an integrated semiconductor device 800. In this embodiment, a first transistor structure 131H can have a first sidewall spacer 122A with a pair of air gaps 138a, 140a and a second sidewall spacer 122B, which has only a single sidewall spacer 140b over the source or drain expansion region 110, 112. A second transistor structure 131I can have a first sidewall spacer 122A with a pair of air gaps 138a, 140a and a second sidewall spacer 122B, which has only a single sidewall spacer 138b adjacent to the structured gate dielectric layer 104 and the structured gate layer 106.In an alternative embodiment (not shown), all of the transistor structures can have a pair of air gaps 138a, 140a or 138b, 140b in one of the first or second side wall spacers 122A, 122B and an air gap 138a, 138b, 140a, 140b in the other of the first or second side wall spacer 122A, 122B.

[0043] In relation to Fig. 23 A flowchart illustrates a general method 900 for manufacturing a semiconductor device 600, 700, 800, in which a section of the transistor structures lacks at least one of the second or fourth air gaps 140a, 140b, in accordance with some embodiments.With respect to step 902, a transistor structure 131 can be defined as comprising a source region 127, a drain region 129, a channel region 113 located between the source region 127 and the drain region 129, a gate dielectric layer 104 located above the channel region 113, a metal or polysilicon gate layer 106 located above the gate dielectric layer 104, a first sidewall spacer 122A located adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and above one of the source region 127 or drain region 129, and a second sidewall spacer 122B located adjacent to the gate dielectric layer 104 and the metal or polysilicon gate layer 106 and above the other of the Source area 127 or Drain area 129, are formed on a substrate 102.

[0044] With regard to step 904, the transistor structure 131 and exposed sections of the substrate 102 can be covered with a photoresist 108 to protect sections of the first and second sidewall spacers 122A, 122B that lie above the source or drain area 127, 129.

[0045] With regard to step 906, the nitride layer 118 of the first sidewall spacer 122A can be selectively etched to the first and second oxide layers 116, 120 to form initial trenches 132a in the first sidewall spacer 122A. The initial trench 132a can be adjacent to the metal or polysilicon gate layer 106. The depth of the initial trenches 132a can be controlled based on the etching time. That is, the longer the etching, the deeper the trenches that can be formed. Furthermore, as discussed above, to further enhance the quality of the trenches, the following steps can be taken: Fig.In the embodiments illustrated in Figures 19-22, one or both side wall spacers 122A, 122B of the transistor structures are protected with a photoresist layer 108, while the exposed spacers are etched to produce first, second, third and fourth trenches 132a, 134a, 132b, 134b.

Claims

[1] MOSFET device lying on a substrate (102) comprising: a source area (127); a drainage area (129); a canal area (113) located between the Source area (127) and the Drain area (129); a gate dielectric layer (104) that lies above the channel region (113); a gate layer (106) that lies above the gate dielectric layer (104); a first sidewall spacer (122A) adjacent to the gate dielectric layer (104) and the gate layer (106) and located above the source region (127) or the drain region (129); a second sidewall spacer (122B) adjacent to the gate dielectric layer (104) and the gate layer (106) and located above the other of the source region (127) or the drain region (129); a first pair of air gaps comprising a first air gap (138a) and a second air gap (140a) located in the first sidewall spacer (122A), wherein the first air gap (138a) is adjacent to the gate layer (106) and the second air gap (140a) is located above the source region (127) or the drain region (129), wherein the first air gap (138a) has a principal axis parallel to the gate layer (106) and the second air gap (140a) has a principal axis parallel to a principal surface of the substrate (102); and a second pair of air gaps comprising a third air gap (138b) and a fourth air gap (140b) located in the second sidewall spacer (122B), wherein the third air gap (138b) is adjacent to the gate layer (106) and the fourth air gap (140b) is located above the source region (127) or the drain region (129), wherein the third air gap (138b) has a principal axis parallel to the gate layer (106) and the fourth air gap (140b) has a principal axis parallel to a principal surface of the substrate (102), wherein the first pair of air gaps has a size different from the second pair of air gaps. [2] MOSFET device according to one of the preceding claims, wherein the height of the first air gap (138a) is between 0.001 and 0.7 of the height of the gate layer (106) and the gate dielectric layer (104). [3] MOSFET device according to one of the preceding claims, wherein the first side wall spacer (122A) and the second side wall spacer (122B) have a sandwich structure comprising a first oxide layer, a second oxide layer and a nitride layer located between the first and second oxide layers. [4] MOSFET device according to claim 3, wherein the second oxide layer comprises a material different from the first oxide layer. [5] MOSFET device according to claim 3 or 4, wherein the first air gap (138a) and the second air gap (140a) are located in the nitride layer. [6] IC-MOSFET device on a substrate (102) comprising: several MOSFET devices, wherein at least one of the several MOSFET devices has side wall spacers (122A, 122B) which have air gaps (138, 140); a first MOSFET device of the several MOSFET devices, wherein the first MOSFET device has: - a first side wall spacer (122A); and - a second side wall spacer (122B), wherein both the first side wall spacer (122A) have second air gaps (140a) and the second side wall spacer (122B) have fourth air gaps (140b) above source regions (127) and drain regions (129) of the first MOSFET device; and a second MOSFET device of the multiple MOSFET devices, wherein the second MOSFET device has: - a first side wall spacer (122A) having second air gaps (140a) or fourth air gaps (140b) above source regions (127) or drain regions (129) of the second MOSFET device, wherein the first side wall spacer (122A) of the first MOSFET device and the second side wall spacer (122B) of the first MOSFET device have first air gaps (138a) and third air gaps (138b) adjacent to a gate layer (106) of the first MOSFET device, wherein the first side wall spacer (122A) of the second MOSFET device has a first air gap (138a) or a third air gap (138b) adjacent to a gate layer (106) of the second MOSFET device, wherein the second MOSFET device has a second side wall spacer (122B) which has no air gaps. [7] IC according to claim 6, comprising a DRAM or an SRAM. [8] Method for fabricating a MOSFET device on a substrate (102), comprising: Forming a MOSFET device comprising a source region (127), a drain region (129), a channel region (113) located between the source region (127) and the drain region (129), a gate dielectric layer (104) located above the channel region (113), a metal or polysilicon gate layer (106) located above the gate dielectric layer (104), a first sidewall spacer (122A) adjacent to the gate dielectric layer (104) and the metal or polysilicon gate layer (106) and located above either the source region (127) or the drain region (129), and a second sidewall spacer (122B) adjacent to the gate dielectric layer (104) and the metal or polysilicon gate layer (106). (106) borders and lies above the other of the Source area (127) or Drain area (129); Etching the first sidewall spacer (122A) to form a first pair of trenches in the first sidewall spacer (122A), wherein the first pair of trenches comprises a first trench (132a) adjacent to the metal or polysilicon gate layer (106) and a second trench (134a) located above the source area (127) or the drain area (129); Deposition of an etch stop layer (136) over the first side wall spacer (122A) to form a first air gap (138a) adjacent to the metal or polysilicon gate layer (106) and a second air gap (140a) located over the source (127) or drain region (129), wherein the first air gap (138a) has a principal axis parallel to the metal or polysilicon gate layer (106) and the second air gap (140a) has a principal axis parallel to a principal surface of the substrate (102); Etching the second sidewall spacer (122B) to form a second pair of trenches in the second sidewall spacer (122B), the second pair of trenches comprising a third trench (132b) adjacent to the metal or polysilicon gate layer (106) and the gate dielectric layer (104), and a fourth trench (134b) located above the source region (127) or the drain region (129); and Deposition of the etch stop layer (136) over the second sidewall spacer (122B) to form a third air gap (138b) adjacent to the metal or polysilicon gate layer (106) and a fourth air gap (140b) located over the source (127) or drain region (129), wherein the third air gap (138b) has a principal axis parallel to the metal or polysilicon gate layer (106) and the fourth air gap (140b) has a principal axis parallel to a principal surface of the substrate (102), wherein a first pair of air gaps, comprising the first (138a) and second air gap (140a), has a size different from a second pair of air gaps, comprising the third (138b) and fourth air gap (140b). [9] Method according to claim 8, wherein the first side wall spacer (122A) and the second side wall spacer (122B) are formed by depositing a first oxide layer, a nitride layer over the first oxide layer and a second oxide layer over the nitride layer. [10] Method according to claim 9, wherein the first pair of trenches is formed by selective etching of the silicon nitride layer relative to the first oxide layer and the second oxide layer. [11] Method according to claim 10, wherein selective etching comprises wet etching and dry etching. [12] Method according to any one of the preceding claims 8 to 11, wherein forming the source (127) and drain (129) region comprises: Formation of source and drain expansion regions by performing an initial ion implantation using the metal or polysilicon gate layer (106) and the gate dielectric layer (104) as a mask; and Forming a deep source area and a deep drain area by performing a second ion implantation using the first (122A) and second sidewall spacer (122B) as a mask. [13] Method according to any one of the preceding claims 8 to 12, further comprising: Deposition of a metal above the deep source region, the deep drain region and the metal or polysilicon gate layer (106), if the metal or polysilicon gate layer (106) contains polysilicon; and Heating to form a metal silicide layer over the deep source area, the deep drain area and the polysilicon gate layer (106).

Images