Device unit, master unit and a connection arrangement for point-to-point communication according to the IO-Link communication standard

Abstract

Device unit for point-to-point communication with a master unit according to the IO-Link communication standard, where the IO-Link communication standard defines two operating modes: a first SIO mode in which a switching signal is transmitted from the device unit to the master unit and a second IO-Link mode in which the master unit communicates with the device unit via digital signals where, during operation, the master unit can request a change of operating mode from SIO mode to IO-Link mode by means of a request signal, wherein the device unit has an IO-Link interface with two power supply connections L+ / L- for powering the device unit and a signal connection C / Q for signal transmission according to the selected operating mode, characterized by that an impedance matching circuit is provided at signal terminal C / Q, which does not affect the switching signal in SIO mode and reduces the reflections of the communication signals in IO-Link mode, so that no bit errors occur in digital communication even at distances of over 20 m between the device unit and the master unit.

Description

[0001] The invention relates to a device unit, master unit and a connection arrangement for point-to-point communication according to the IO-Link communication standard, according to the preamble of claim 1, 2 and 7 respectively.

[0002] IO-Link is a manufacturer-independent, standardized communication system for connecting intelligent sensors and actuators to a controller. This communication system is standardized in IEC 61131-9 under the name Singledrop digital communication interface for small sensors and actuators (SDCI).

[0003] This standard defines both the electrical connection data and a digital communication protocol through which the sensors and actuators exchange data with the master.

[0004] An IO-Link system consists of an IO-Link master, which is connected via a point-to-point connection to one or more IO-Link devices (IO-Link modules), also referred to as device units below. The IO-Link master provides the interface to the higher-level controller (e.g., PLC) via a fieldbus and manages the communication with the connected IO-Link devices. Fig. 8).

[0005] An IO-Link master can have one or more IO-Link ports, but only one IO-Link device can be connected to each port. IO-Link uses point-to-point communication and is therefore not a fieldbus in the traditional sense.

[0006] An IO-Link device is an intelligent sensor or actuator. In the context of IO-Link, "intelligent" means that a device has, for example, a serial number or parameter data (e.g., sensitivities, switching delays, or characteristic curves) that can be read and written via the IO-Link protocol. This allows parameters to be changed, in some cases, by the PLC during operation.

[0007] The configuration parameters of the sensors and actuators are device-specific; therefore, parameter information for each device is available in the form of an IODD (IO Device Description).

[0008] With the help of IO-Link, sensors can be automatically parameterized, system states diagnosed, and measured values ​​transmitted without loss.

[0009] Various IO-Link communication circuits and IO-Link communication methods are known from the publications EP2211464A1, DE102012009494A1 and DE102014106752A1.

[0010] From the publication DE102007032845A1, a bus repeater and a method for coupling two bus segments via a bus repeater are generally known for fieldbuses.

[0011] From DE19710137A1 a method for extending an ASi bus system is known.

[0012] German patent application DE 10 2018 109 576 B3 discloses an intermediate unit for bidirectional data transmission between an IO-Link device and an IO-Link master, incorporating an impedance matching circuit. The impedance matching circuit is actively controllable to prevent unwanted voltage spikes on the signal line.

[0013] According to the IO-Link specification, a connection between master and device of up to 20 m cable length is permitted. Longer connections can lead to bit errors.

[0014] The object of the invention is to provide a device unit, master unit and a connection arrangement for point-to-point communication according to the IO-Link communication standard which complies with the IO-Link specifications and which also allows for longer cable lengths of more than 20 m without causing bit errors.

[0015] This problem is solved by the features specified in the characterizing part of claim 1, 2, 7.

[0016] A key idea of ​​the invention is that, in a device unit for point-to-point communication with a master unit according to the IO-Link communication standard, an impedance matching circuit is provided at the signal terminal C / Q of the IO-Link interface, which does not impair the switching signal in SIO mode and reduces the reflections of the communication signals in IO-Link mode.

[0017] Advantageous further developments are specified in the dependent claims.

[0018] The invention will now be explained in more detail using exemplary embodiments and with reference to the drawings.

[0019] They show schematically: Fig. 1 device unit and master unit Fig. 1a Block diagram IO-Link device Fig. 1b Pin assignment on the port of an IO-Link device Fig. 1c IO-Link Device as a sensor Fig. 1d schematic circuit arrangement to Fig. 1 Fig. 2. Voltage-time diagram Fig. 3. Circuit arrangement with improved line impedance Fig. 4. Voltage-time diagram Fig. 5a first embodiment of the invention Fig. 5b second embodiment of the invention Fig. 6 Connection arrangement with repeater units according to the invention Fig. 7. Voltage-time curve during a wake-up request Fig. 8 IO-Link device

[0020] Fig. Figure 1 shows a device unit and a master unit according to the IO-Link specifications.

[0021] The device unit has an IO-Link interface with two power supply connections L+ / L- for powering the device unit and a signal connection C / Q for signal transmission.

[0022] The connection between the device unit and the master unit is schematically represented as a cable with 3 wires, but not according to length; rather, it represents the capacitance of each wire. Signal propagation times vary with the length of the connection.

[0023] The power amplifiers are represented as current sources on both the device and master sides, with their design defined in the specifications. Essentially, these current sources are switches with a defined current limit.

[0024] The impedance of an unshielded connection is approximately 60-80 ohms (C / Q line to L+ and L-)

[0025] The impedances of the IO-Link interfaces are not matched to these line impedances. Due to this lack of matching at the respective sender and receiver (device unit and master unit, respectively), line reflections occur during communication.

[0026] These conduction reflections can have several causes: • The transmitter impedance is low (much smaller than the line impedance) • The receiver's impedance is low (much smaller than the line impedance) • The receiver's impedance is very high (much greater than the line impedance)

[0027] The IO-Link receiver, whether device unit or master unit, is by definition a high-impedance input.

[0028] Reflections or overshoots are dissipated, if necessary, via protective components (e.g., Zener and suppressor diodes). If the master unit sends a digital signal via its low-impedance output to the device unit, which has a high-impedance input, the signal is reflected back with the same polarity. Since the master unit's output is low-impedance, the digital signal is reflected back with the opposite polarity. This can result in multiple reflections, which decay slowly depending on the circumstances.

[0029] Fig. Figure 1a shows a block diagram of an IO-Link device with a sensor / actuator unit, a microcontroller µC and an IO-Link interface (IO-Link PHY) with a port unit for the external connections L+, L- (GND) and C / Q.

[0030] Fig. Figure 1c shows a typical IO-Link device as a sensor with a microcontroller. In SIO mode, either the upper or lower switch (So, Su) of the output stage is closed.

[0031] This diagram illustrates the problem. The receiver only recognizes the digital signals when both switches So and Su are open.

[0032] The request to the IO-Link device to switch from SIO mode to IO-Link mode is made on the mast side via the Wakeup Request.

[0033] If the C / Q output is at L+ potential, the master will set its C / Q output to L- potential. This causes a short-circuit current to flow in the output stage, which is detectable.

[0034] The same applies if the C / Q output is at low potential!

[0035] Fig. Figure 1b shows the pin assignment on the port of an IO-Link device.

[0036] Fig. 1d shows a opposite Fig. 1 Simplified schematic circuit arrangement of a conventional IO-Link communication between an IO-Link master and an IO-Link device, each with a conventional power stage hE1 or hE2.

[0037] Fig. Figure 2 shows a voltage-time diagram according to the circuit arrangement shown. Fig. 1 or Fig. 1c The time-delayed signal is the reflected signal with oscillations, also known as overshoot. Since the first signal maximum occurs after the falling edge, it could lead to a bit error at the receiver if the time shift is approximately -1 / 2 a bit.

[0038] Fig. Figure 3 shows a circuit arrangement that would be better matched to the line impedance of the connecting cable. Resistors R26 and R27 are provided on both the transmitter and receiver sides. The value of each resistor is approximately 40 Ω, which corresponds roughly to the line impedance of 60 Ω.

[0039] Fig. Figure 4 also shows the corresponding signal waveforms in a voltage-time diagram. Overshoots that could lead to bit errors are no longer present. Although some overshoots still exist, none of the signal voltages exceed the switching thresholds of the IO-Link receiver.

[0040] However, this circuit arrangement does not comply with the IO-Link specifications.

[0041] With a series resistor R26 at the C / Q signal connection, a device unit could no longer generate the switching signal according to the PLC standard IEC61131-2, because the voltage drop with the additional resistor would be too large.

[0042] Furthermore, the master unit could not generate a signal interpretable as a wake-up request from the sensor side because, at a current of 500 mA, the entire voltage would drop across the series resistor R27. At 500 mA and 400 ohms, this would result in a 20 V voltage drop. While this isn't the entire voltage, the voltage drop is simply too large. The second resistor on the opposite side may also be present, further reducing the signal voltage.

[0043] Fig. Figure 5a shows a first embodiment of the invention. Both the device unit and the master unit have two output stages, E1 and E2. One output stage, E1, is for SIO mode, and the other, E2, is for IO-Link mode.

[0044] If the device unit is in SIO mode and the master unit generates a wakeup request, the device unit receives this wakeup request and both units put the two output stages E1 into a high-impedance state. IO-Link communication then takes place exclusively via the output stages E2, which each have a series resistor R26 or R27.

[0045] Fig. Figure 5b shows a second embodiment of the invention. In the circuit, the series resistor R28 and R29 can be bypassed by means of a switch U4, U5.

[0046] In SIO mode, both switches U4 and U5 are closed; in IO-Link mode, they are both open.

[0047] In SIO mode, the wakeup request generated on the master side is detected and both units switch to IO-Link mode.

[0048] The main advantage offered by the invention is that both the switching signals in SIO mode and the digital signals in IO-Link mode are transmitted in accordance with the IO-Link specification, while at the same time interfering reflections during the transmission of the digital signals are avoided.

[0049] Fig. Figure 6 shows a further embodiment of the invention. Here, a connection arrangement for point-to-point communication between a device unit and a master unit according to the IO-Link communication standard consists of a first repeater unit and a second repeater unit, which are connected to each other via a connecting cable L3. The length of the cable L3 is not limited to 20 m.

[0050] Since the digital signals are transmitted virtually without reflection on cable L3, because the impedances of the respective interfaces are matched to the impedances of the transmission cable, even longer distances can easily be bridged.

[0051] In Fig. Figure 7 shows the voltage-time curve during a master-side wake-up request. If the master's port is set to IO-Link mode, the IO-Link master attempts to communicate with the connected IO-Link device. To do this, the IO-Link master sends a defined signal (wake-up pulse) and waits for the response from the IO-Link device. The wake-up procedure is described, among other places, in the IO-Link Communication Specification Version 1.0 January 2009, Order No. 10.002.

[0052] If the sensor is in IO-Link mode, then the following applies to a typical wake-up procedure: IO-Link basically only provides switching outputs.

[0053] The switching output C / Q on the IO-Link device delivers a maximum of 200 mA.

[0054] The associated IO-Link master has a digital input according to IEC 61131-2. This digital input operates as a current sink of 5 to 15 mA, depending on the applied voltage level.

[0055] The detection levels for a high / low signal are between 10.5 and 13 V (high) and 8 and 11.5 V (low).

[0056] To switch the C / Q line to the high-impedance state, a current / voltage event of 80µs duration and a maximum of 500 mA in the opposite polarity is impressed on the C / Q line by the master.

[0057] The IO-Link device detects this as a short circuit and deactivates the output's driver stage. This makes the line high-impedance, meaning only the current sink in the IO-Link master is active. Communication can now begin.

Claims

[1] Device unit for point-to-point communication with a master unit according to the IO-Link communication standard, where the IO-Link communication standard defines two operating modes: a first SIO mode in which a switching signal is transmitted from the device unit to the master unit and a second IO-Link mode in which the master unit communicates with the device unit via digital signals where, during operation, the master unit can request a change of operating mode from SIO mode to IO-Link mode by means of a request signal, wherein the device unit has an IO-Link interface with two power supply connections L+ / L- for powering the device unit and a signal connection C / Q for signal transmission according to the selected operating mode, characterized by , that an impedance matching circuit is provided at signal terminal C / Q, which does not affect the switching signal in SIO mode and reduces the reflections of the communication signals in IO-Link mode, so that no bit errors occur in digital communication even at distances of over 20 m between the device unit and the master unit. [2] Master unit for point-to-point communication with a device unit according to the IO-Link communication standard, where the IO-Link communication standard defines two operating modes: a first SIO mode in which a switching signal is transmitted from the device unit to the master unit and a second IO-Link mode in which the master unit communicates with the device unit via digital signals where, during operation, the master unit can request a change of operating mode from SIO mode to IO-Link mode by means of a request signal, wherein the master unit has an IO-Link interface with two power supply connections L+ / L- for powering a device unit and a signal connection C / Q for signal transmission according to the selected operating mode, characterized by , that an impedance matching circuit is provided at signal terminal C / Q, which does not affect the switching signal in SIO mode and reduces the reflections of the communication signals in IO-Link mode, so that no bit errors occur in digital communication even at distances of over 20 m between the device unit and the master unit. [3] Unit according to one of claims 1 or 2 characterized by , that the impedance matching circuit ensures that in IO-Link mode the impedance is matched to the line impedance of the signal line and in the switched state in SIO mode (on state) the impedance is low. [4] Unit according to claim 3, characterized by, that the impedance matching circuit has a series resistance with a switchable bypass, wherein the series resistance is bypassed in SIO mode and is not bypassed in IO-Link mode. [5] Unit according to claim 3, characterized by that two parallel-connected output stages are provided, whereby the output stages are operated alternately, and a first power amplifier can be activated for SIO mode and a second power amplifier can be activated for IO-Link mode, the signal terminal C / Q of the second output stage has a series resistance for impedance matching. [6] Unit according to any one of the preceding claims, characterized by , that the impedance matching circuit has a capacitor connected to the circuit zero point. [7] Connection arrangement for point-to-point communication between a device unit and a master unit according to the IO-Link communication standard characterized bythat the connection arrangement consists of a first repeater subunit and a second repeater subunit, each of which It has an IO-Link interface with two power supply connections L+ / L- for powering the device unit and a signal connection C / Q for signal transmission according to the selected operating mode, wherein an impedance matching circuit is provided at the signal connection C / Q, which does not affect the switching signal in SIO mode and reduces the reflections of the communication signals in IO-Link mode, so that no bit errors occur in digital communication even at distances of over 20 m between the repeater parts. [8] Connection arrangement according to claim 7, characterized by , that the impedance matching circuit ensures that in IO-Link mode the impedance is matched to the line impedance of the signal line and is low-impedance in the switched state in SIO mode (on state). [9] Connection arrangement according to claim 7, characterized by , that the impedance matching circuit has a series resistance with a switchable bypass, wherein the series resistance is bypassed in SIO mode and is not bypassed in IO-Link mode. [10] Connection arrangement according to claim 7, characterized by that two parallel-connected output stages are provided, whereby the output stages are operated alternately, and a first power amplifier can be activated for SIO mode and a second power amplifier can be activated for IO-Link mode, the signal terminal C / Q of the second output stage has a series resistance for impedance matching.

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