PROCEDURE

Abstract

Procedure comprehensive: Forming a dummy dielectric over a plurality of semiconductor layers (52, 54); Forming a dummy gate (76) over the dummy dielectric; Deposition of a gate spacer element (81, 83) adjacent to the dummy gate (76) and the dummy dielectric; Recessing the dummy gate (76) to form a recess (86, 100, 106) which exposes the gate spacer element; Implanting an impurity in a non-directional manner in a first region of the gate spacer element (81, 83) to increase the etch rate of the first region of the gate spacer element (81, 83), while a second region of the gate spacer element remains unmodified by the implantation; Removal of the dummy dielectric, the first region of the gate spacer element and remaining sections of the dummy gate (76) to expose the semiconductor layers (52, 54) in the recess (86, 100, 106); Structuring the semiconductor layers (52, 54) to form nanostructures (55, 55N, 55P); and Forming a gate structure (85) in the recess (86, 100, 106), wherein the gate structure (85) encloses the nanostructures (55, 55N, 55P) and the gate structure (85) contacts the second region of the gate spacer element.

Description

STATE OF THE ART

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] By continuously reducing the minimum feature size, which allows more components to be integrated into a given area, the semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). However, the reduction in minimum feature sizes brings with it additional problems that must be addressed.

[0003] US 2016 / 0049488 A1 discloses a semiconductor structure with wide-bottom and / or wide-top gates. US 2014 / 0080276 A1 discloses processing a three-dimensional structure arranged on a substrate to change the etching rate of material.

[0004] The invention is defined by the method according to claim 1. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. Fig. 1 illustrates an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional view, consistent with some embodiments. The Fig. 2 to 17B are various views of further intermediate stages of fabricating nano-FETs in accordance with some embodiments. Fig. 18 illustrates nano-FETs in accordance with some embodiments. DETAILED DESCRIPTION

[0006] The following disclosure provides numerous different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be construed as limiting in any way. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact with each other, but may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first and second features may not be in direct contact with each other. Furthermore, the present disclosure may repeat reference numbers and / or characters in the various examples.This repetition is for the purpose of simplicity and clarity, and does not in itself prescribe any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, terms of spatial relationships, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the purpose of more easily describing the relationship of one element or feature illustrated in the figures to another element or feature. The terms of spatial relationships are intended to encompass various orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the terms of spatial relationships used herein may thus be interpreted accordingly.

[0008] In accordance with some embodiments, funnel-shaped gate electrodes are formed in a gate replacement process for nano-FETs. During the gate replacement process, recesses for the replacement gates may be expanded to have a funnel shape. The recesses may be expanded by implanting an impurity into upper portions of the gate spacers for the nano-FETs and then removing the upper portions of the gate spacers with an etch selective for the impurity. Expanding the recesses to have a funnel shape may help prevent the formation of seams (or voids) when filling the replacement gates.

[0009] Fig. Figure 1 illustrates an example of a simplified nano-FET in a three-dimensional view, consistent with some embodiments. Some features of the nano-FETs (discussed below) have been omitted for clarity. The nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), wrap-around gate field-effect transistors (GAAFETs), or the like.

[0010] The nano-FETs include nanostructures 55 over fins 66 extending from a substrate 50, where the nanostructures 55 serve as channel regions for the nano-FETs. Trench isolation (STI) regions 68 are disposed over the substrate 50 and between adjacent ones of the fins 66, which may protrude above and between adjacent STI regions 68. Although the STI regions 68 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein may refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the isolation regions. Furthermore, although a lower portion of the fins 66 is illustrated as a single, continuous material with the substrate 50, the lower portion of the fins 66 and / or the substrate 50 may include a single material or a plurality of materials.In this context, the fins 66 refer to the section extending between the adjacent STI areas 68.

[0011] Gate structures 85 enclose the nanostructures 55 (e.g., the channel regions of the nano-FETs). The gate structures 85 include gate dielectrics 112 and gate electrodes 114. The gate dielectrics 112 are disposed along top surfaces, sidewalls, and bottom surfaces of the nanostructures 55, and may extend along sidewalls and over top surfaces of the fins 66. The gate electrodes 114 are disposed over the gate dielectrics 112. With respect to the gate structures 85, epitaxial source / drain regions 92 are disposed on opposite sides of the nanostructures 55. In embodiments in which multiple transistors are formed, different transistors may share the epitaxial source / drain regions 92.In embodiments in which a transistor is formed from multiple nanostructures 55, adjacent epitaxial source / drain regions 92 may be electrically connected, for example, by fusing the epitaxial source / drain regions 92 by epitaxial growth or by coupling the source / drain regions 92 to a same source / drain contact. One or more interlayer dielectric layers (ILDs) (discussed below) are disposed over the epitaxial source / drain regions 92 and / or the gate electrodes 114, through which contacts (discussed below) to the epitaxial source / drain regions 92 and the gate electrodes 114 are formed.

[0012] Some of the embodiments discussed herein are discussed in the context of nano-FETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices, such as planar FETs, or fin field-effect transistors (FinFETs).

[0013] Fig. 1 further illustrates reference cross-sections used in later figures. Cross-section AA is arranged along a longitudinal axis of a gate electrode 114 and in a direction, for example, perpendicular to the direction of current flow between the epitaxial source / drain regions 92 of a nano-FET. Cross-section BB is arranged perpendicular to cross-section AA and along a longitudinal axis of a fin 66 and, for example, in a direction of current flow between the epitaxial source / drain regions 92 of the nano-FET. Cross-section CC is arranged parallel to cross-section AA and extends through epitaxial source / drain regions 92 of the nano-FET. For clarity, subsequent figures refer to these reference cross-sections.

[0014] The Fig. 2 to 6 are three-dimensional views of intermediate stages of fabricating nano-FETs in accordance with some embodiments. Fig. 2 to 6 show a similar three-dimensional view as Fig. 1.

[0015] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or a gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0016] The substrate 50 includes an n-type region 50N and a p-type region 50P. The n-type region 50N may be used to form n-type devices, such as NMOS transistors, e.g., n-nano-FETs, and the p-type region 50P may be used to form p-type devices, such as PMOS transistors, e.g., p-nano-FETs. The n-type region 50N may be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active components, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P may be provided.

[0017] The substrate 50 may be lightly doped with a p-type or n-type impurity. An anti-breakdown (APT) implantation may be performed on an upper portion of the substrate 50 to form an APT region. During the APT implantation, dopants may be implanted in the n-type region 50N and the p-type region 50P. The dopants may have a conductivity type opposite to a conductivity type of the source / drain regions to be formed in each of the n-type regions 50N and the p-type regions 50P. The APT region may extend beneath subsequently formed source / drain regions in the nano-FETs formed in a subsequent process. The APT region may be used to reduce leakage current from the source / drain regions to the substrate 50. In some embodiments, the doping concentration in the APT region may be in the range of approximately 10 18 cm -3 up to about 1019 cm -3 lay.

[0018] A multilayer stack 64 is formed over the substrate 50. The multilayer stack 64 includes alternating layers of first semiconductor layers 52 and second semiconductor layers 54. As discussed in more detail below, the second semiconductor layers 54 are removed, and the first semiconductor layers 52 are patterned to form channel regions of nano-FETs in the p-type region 50P, and the first semiconductor layers 52 are removed, and the second semiconductor layers 54 are patterned to form channel regions of nano-FETs in the n-type region 50N. In another embodiment, the first semiconductor layers 52 may be removed, and the second semiconductor layers 54 may be patterned to form channel regions of nano-FETs in the n-type region 50N, and the second semiconductor layers 54 may be removed, and the first semiconductor layers 52 may be patterned to form channel regions of nano-FETs in the p-type region 50P.

[0019] For illustrative purposes, the multilayer stack 64 is shown as having three layers each of the first semiconductor layer 52 and the second semiconductor layer 54. It is contemplated that the multilayer stack 64 may include any number of the first semiconductor layers 52 and the second semiconductor layers 54. Each of the layers of the multilayer stack 64 may be grown epitaxially using a process such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like, and may be grown epitaxially to a thickness in the range of approximately 8 nm to approximately 10 nm. In various embodiments, the first semiconductor layers 52 may be formed from a first semiconductor material suitable for p-nano-FETs, such as silicon germanium (e.g., Si x Ge 1-x, where x can range from 0 to 1), pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like, and the second semiconductor layers 54 can be formed from a second semiconductor material suitable for n-nano-FETs, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For illustrative purposes, the multilayer stack 64 is shown having a bottommost semiconductor layer suitable for p-nano-FETs. In some embodiments, the multilayer stack 64 can be formed such that the bottommost layer is a semiconductor layer suitable for n-nano-FETs.

[0020] The first semiconductor material and the second semiconductor material may be materials that exhibit high etch selectivity among each other with respect to a same etching process. Thus, the first semiconductor layers 52 of the first semiconductor material may be removed without removing the second semiconductor layers 54 of the second semiconductor material in the n-type region 50N, and the second semiconductor layers 54 of the second semiconductor material may be removed without removing the first semiconductor layers 52 of the first semiconductor material in the p-type region 50P.

[0021] In Fig. 3, fins 66 are formed in the multilayer stack 64 and the substrate 50. The fins 66 are semiconductor strips. In some embodiments, the fins 66 may be formed in the multilayer stack 64 and the substrate 50 by etching trenches in the multilayer stack 64 and the substrate 50. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching may be anisotropic.

[0022] The fins may be patterned using any suitable method. For example, the fins may be patterned using one or more photolithographic processes, including double-patterning or multi-patterning processes. Typically, double-patterning and multi-patterning processes combine photolithography and self-aligning processes, thereby enabling the creation of structures having, for example, pitch dimensions smaller than those achievable using a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed together with the patterned sacrificial layer using a self-aligning process.The sacrificial layer is then removed and the remaining spacers can be used to pattern the fins.

[0023] The fins 66 may have widths ranging from approximately 8 nm to approximately 40 nm. For illustrative purposes, the fins 66 in the n-type region 50N and the p-type region 50P are depicted as having substantially the same widths. In some embodiments, the fins 66 in one region (e.g., the n-type region 50N) may be wider or narrower than the fins 66 in the other region (e.g., the p-type region 50P).

[0024] In Fig. 4, STI regions 68 are formed adjacent to the fins 66. The STI regions 68 may be formed by depositing an insulating material over the substrate 50 and the fins 66 and between each adjacent fin 66. The insulating material may be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, and may be formed by high density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process may also be used. In the illustrated embodiment, the insulating material is a silicon oxide formed by an FCVD process. An annealing process may be performed after the insulating material is formed. In one embodiment, the insulating material is formed such that excess insulating material covers the fins 66.Although the insulating material is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a cladding (not shown) may first be formed along a surface of the substrate 50 and fins 66. A fill material, such as those discussed above, may then be formed over the cladding.

[0025] A removal process is then applied to the insulating material to remove excess insulating material over the fins 66. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the fins 66 so that top surfaces of the fins 66 and the insulating material are coplanar after completion of the planarization process.

[0026] The insulating material is then recessed to form the STI regions 68. The insulating material is recessed such that upper portions of the fins 66 in the n-type region 50N and the p-type region 50P protrude between adjacent STI regions 68. In the illustrated embodiment, the upper surfaces of the STI regions 68 are coplanar with the upper surfaces of the substrate 50. In some embodiments, the upper surfaces of the STI regions 68 are disposed above or below the upper surfaces of the substrate 50. Further, as shown, the upper surfaces of the STI regions 68 may have a flat surface, a convex surface, a concave surface (such as a crown), or a combination thereof. The upper surfaces of the STI regions 68 may be formed flat, convex, and / or concave by appropriate etching.The STI regions 68 may be recessed using an acceptable etching process, such as one that is selective to the insulating material material (e.g., one that etches the insulating material material at a higher rate than the fin 66 material). For example, oxide removal, for example, using dilute hydrofluoric acid (dHF), may be used.

[0027] The process described above is only one example of how the fins 66 may be formed. In some embodiments, the fins 66 may be formed through an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures may be grown epitaxially in the trenches, and the dielectric layer may be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 66. The epitaxial structures may include the alternating semiconductor materials discussed above, such as the first semiconductor materials and the second semiconductor materials.In embodiments in which epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, which may eliminate the need for prior and subsequent implantations, and in situ doping and implantation doping may also be used together.

[0028] Furthermore, corresponding wells / tubs may be formed in fins 66 and / or substrate 50. In some embodiments, a p-well may be formed in n-type region 50N, and an n-well may be formed in p-type region 50P. In another embodiment, p-wells or n-wells may be formed in both n-type region 50N and p-type region 50P.

[0029] In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P can be achieved using a photoresist or other masks. For example, a photoresist can be formed over the fins 66 and the STI regions 68 in the n-region 50N. The photoresist is patterned to expose the p-region 50P of the substrate 50. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist has been patterned, an n-type impurity implantation is performed in the p-region 50P, and the photoresist can serve as a mask to substantially prevent n-type impurities from being implanted into the n-region 50N. The n-type impurities can be phosphorus, arsenic, antimony, or the like, which can be present up to a concentration in the range of approximately 10 13 cm -3up to about 10 14 cm -3 implanted into the area. After implantation, the photoresist is removed, for example, by a suitable ashing process.

[0030] After implantation of the p-type region 50P, a photoresist is formed over the fins 66 and the STI regions 68 in the p-type region 50P. The photoresist is patterned to expose the n-type region 50N of the substrate 50. The photoresist may be formed using a spin-on technique and may be patterned using acceptable photolithography techniques. Once the photoresist has been patterned, a p-type impurity implantation is performed in the n-type region 50N, and the photoresist may serve as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurities may be boron, boron fluoride, indium, or the like, which may be present up to a concentration in the range of approximately 10 13 cm-3 up to about 10 14 cm -3 implanted into the area. After implantation, the photoresist is removed, for example, by a suitable ashing process.

[0031] After the implantation of the n-type region 50N and the p-type region 50P, an anneal may be performed to repair implantation damage and activate the implanted p- and / or n-type impurities. In some embodiments, the grown epitaxial fin materials may be doped in situ (in-situ) during growth, which may eliminate the need for implantation; however, in situ doping and implantation doping may also be used together.

[0032] In Fig. 5, a dummy dielectric layer 70 is formed on the fins 66. The dummy dielectric layer 70 may include, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown in accordance with acceptable techniques. A dummy gate layer 72 is formed over the dummy dielectric layer 70, and a mask layer 74 is formed over the dummy gate layer 72. The dummy gate layer 72 may be applied over the dummy dielectric layer 70 and then planarized, for example, by a CMP. The mask layer 74 may be applied / deposited over the dummy gate layer 72.The dummy gate layer 72 may be a conductive material or a non-conductive material, and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer 72 may be deposited by physical vapor deposition (PVD), CVD, sputtering, or other techniques for depositing the selected material. The dummy gate layer 72 may be made of other materials that exhibit high etch selectivity from etching isolation regions, for example, the STI regions 68 and / or the dummy dielectric layer 70. The mask layer 74 may, for example, comprise one or more layers of silicon nitride, silicon oxynitride, or the like.In this example, a single dummy gate layer 72 and a single mask layer 74 are formed across the n-type region 50N and the p-type region 50P. Although the dummy dielectric layer 70 is shown covering the STI regions 68, it should be understood that the dummy dielectric layer 70 may be formed in other ways. In some embodiments, such as when the dummy dielectric layer 70 is thermally grown, the dummy dielectric layer 70 is formed to cover only the fins 66.

[0033] In Fig. 6, the mask layer 74 is patterned using acceptable photolithography and etching techniques to form masks 78. The pattern of the masks 78 is then transferred to the dummy gate layer 72 using a suitable etching technique to form dummy gates 76. Further, the pattern of the masks 78 can optionally be transferred to the dummy dielectric layer 70 using an acceptable etching technique to form the dummy dielectrics 60. The dummy gates 76 cover portions of the fins 66, which are patterned during subsequent processing to form nanostructures that then function as channel regions for the nano-FETs. The pattern of the masks 78 can be used to physically separate adjacent dummy gates 76 from each other. The dummy gates 76 may also have longitudinal directions substantially perpendicular (within process tolerances) to the longitudinal directions of the fins 66.The masks 78 can optionally be removed after structuring, for example by a suitable etching technique.

[0034] The Fig. 7A to 17B are cross-sectional views of further intermediate stages in the fabrication of nano-FETs in accordance with some embodiments. Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 16A and Fig. 17A are along the reference cross-section AA in Fig. 1, and show features in both the n-region 50N and the p-region 50P. The Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 16B and Fig. 17B are along the reference cross-section BB in Fig. 1, and show features in both the n-region 50N and the p-region 50P. The Fig. 11C and Fig. 11D are along the reference cross section CC in Fig. 1, and show features in both the n-region 50N and the p-region 50P.

[0035] In the Fig. 7A and Fig. 7B, a first spacer layer 80 and a second spacer layer 82 are formed. The first spacer layer 80 is formed on top surfaces of the STI regions 68, top surfaces and sidewalls of the fins 66 and the masks 78 (if present), and sidewalls of the dummy gates 76 and the dummy dielectrics 60. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed from silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like. The first spacer layer 80 may be formed by thermal oxidation or deposited by CVD, ALD, or the like. The second spacer layer 82 may be formed from silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like. The second spacer layer 82 may be deposited by CVD, ALD, or the like.

[0036] In some embodiments, the first spacer layer 80 and the second spacer layer 82 are each formed of silicon oxycarbonitride (e.g., SiO x N y C 1-x-y, where x and y range from 0 to 1) and have different compositions of silicon oxycarbonitride. In particular, the first spacer layer 80 may be composed of more nitrogen (by atomic percent) than the second spacer layer 82, and the second spacer layer 82 may be composed of more oxygen (by atomic percent) than the first spacer layer 80. Forming the first spacer layer 80 from nitrogen-rich silicon oxycarbonitride increases its etch selectivity toward the dummy dielectrics 60 with respect to an etch process (discussed in more detail below) used to remove the dummy dielectrics 60.Forming the second spacer layer 82 from oxygen-rich silicon oxycarbonitride reduces the relative dielectric constant of the second spacer layer 82, which subsequently allows spacers to be formed which have higher electrical insulation.

[0037] In embodiments where the first spacer layer 80 and the second spacer layer 82 are each formed of silicon oxycarbonitride, the silicon oxycarbonitride layers may be deposited using dielectric material precursors, such as a silicon source precursor (e.g., hexachlorodisilane (Si2Cl6, HCD)), an oxygen source precursor (e.g., oxygen gas (O2)), a carbon source precursor (e.g., propylene (C3H6)), and a nitrogen source precursor (e.g., ammonia (NH3)). In embodiments where deposition is by CVD, the composition(s) of the silicon oxycarbonitride layers may be controlled by controlling the flow rates of the source precursors during CVD.For example, the silicon source precursor may be delivered at a rate ranging from about 100 sccm to about 1000 sccm, the oxygen source precursor may be delivered at a rate ranging from about 1000 sccm to about 20,000 sccm, the carbon source precursor may be delivered at a rate ranging from about 1000 sccm to about 10,000 sccm, and the nitrogen source precursor may be delivered at a rate ranging from about 5,000 sccm to about 30,000 sccm.

[0038] Implants for lightly doped source / drain (LDD) regions may be formed after the first spacer layer 80 has been formed, or after both the first spacer layer 80 and the second spacer layer 82 have been formed. In embodiments with various device types similar to the implants discussed above, a mask, such as a photoresist, may be formed over the n-type region 50N while exposing the p-type region 50P, and suitable types (e.g., type p) of impurities may be implanted into the fins 66 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P while exposing the n-type region 50N, and suitable types (e.g., type n) of impurities may be implanted into the fins 66 in the n-type region 50N. The mask may then be removed.The n-type impurities may be any of the previously discussed n-type impurities, and the p-type impurities may be any of the previously discussed p-type impurities. The lightly doped source / drain regions may have an impurity concentration in the range of approximately 10. 15 cm -3 up to about 10 19 cm -3 Annealing can be used to repair implantation damage and activate the implanted impurities.

[0039] In the Fig. 8A and Fig. 8B, the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83, respectively. The first spacer layer 80 and the second spacer layer 82 may each be etched using a suitable etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), or the like. In some embodiments, the materials of the first spacer layer 80 and the second spacer layer 82 have a high etch selectivity with respect to a same etching process, such that the first spacer layer 80 may serve as an etch stop layer when patterning the second spacer layer 82, and such that the second spacer layer 82 may serve as a mask when patterning the first spacer layer 80.For example, the second spacer layer 82 may be etched using an anisotropic etching process in which the first spacer layer 80 serves as an etch stop layer, with remaining portions of the second spacer layer 82 forming the second spacers 83. Thereafter, the first spacer layer 80 may be etched using an isotropic etching process in which the second spacers 83 serve as an etch mask, with remaining portions of the first spacer layer 80 forming the first spacers 81.

[0040] In the illustrated embodiment, the first spacers 81 and the second spacers 83 are disposed on sidewalls of the fins 66, the dummy gates 76, and the masks 78 (if present). In another embodiment, the second spacer layer 82 may be removed from above the first spacer layer 80 adjacent to the masks 78 (if present), the dummy gates 76, and / or the dummy dielectrics 60.

[0041] It should be noted that the above disclosure describes a general process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers, different sequences of steps (e.g., the first spacers 81 may be formed before forming the second spacers 83, additional spacers may be formed and removed, etc.), and / or the like may be used. Furthermore, the n- and p-type devices may be formed using different structures and steps.

[0042] In the Fig. 9A and Fig. 9B, first recesses 86 are formed in the fins 66. The first recesses 86 extend through the first semiconductor layers 52 and the second semiconductor layers 54, and may also extend into the substrate 50. In various embodiments, the first recesses 86 may extend to a top surface of the substrate 50 without etching the substrate 50; the substrate 50 may be etched such that the bottom surfaces of the first recesses 86 are located below the top surfaces of the STI regions 68; or the like. The first recesses 86 may be formed by etching the fins 66 using anisotropic etching processes, such as RIE, NBE, or the like.The first spacers 81, the second spacers 83, and the masks 78 mask portions of the first semiconductor layers 52, the second semiconductor layers 54, and the substrate 50 during the etching processes used to form the first recesses 86. A single etching process may be used to etch each of the layers of the fins 66. In other embodiments, multiple etching processes may be used to etch the layers of the fins 66. Timed etching processes may be used to stop the etching of the first recesses 86 after the first recesses 86 have reached a desired depth.

[0043] In the Fig. 10A and Fig. 10B, the first recesses 86 are optionally extended. In particular, portions of sidewalls of the first semiconductor layers 52 exposed by the first recesses 86 in the n-type region 50N may be etched to form sidewall recesses 88 in the n-type region 50N, and portions of sidewalls of the second semiconductor layers 54 exposed by the first recesses 86 in the p-type region 50P may be etched to form sidewall recesses 88 in the p-type region 50P. Although sidewalls of the first semiconductor layers 52 and the second semiconductor layers 54 in the sidewall recesses 88 are illustrated as being straight, the sidewalls may be concave or convex. The sidewalls may be etched using isotropic etching processes, such as wet etching or the like.The p-type region 50P may be protected using a mask, while etching agents selectively relative to the first semiconductor materials are used to etch the first semiconductor layers 52 such that the second semiconductor layers 54 and the substrate 50 remain relatively unetched compared to the first semiconductor layers 52 in the n-type region 50N. Similarly, the n-type region 50N may be protected using a mask, while etching agents selectively relative to the second semiconductor materials are used to etch the second semiconductor layers 54 and the substrate 50 such that the first semiconductor layers 52 and the substrate 50 remain relatively unetched compared to the second semiconductor layers 54 in the n-type region 50N.In embodiments in which the first semiconductor layers 52 are formed of silicon germanium and the second semiconductor layers 54 are formed of silicon or silicon carbide, a wet etching process with tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like may be used to etch sidewalls of the first semiconductor layers 52 in the n-type region 50N, and a wet etching process with hydroxide-hydrogen peroxide mixture (APM), sulfuric acid-hydrogen peroxide mixture (SPM), or the like may be used to etch sidewalls of the second semiconductor layers 54 in the p-type region 50P.

[0044] Internal spacers 90 are formed in the sidewall recesses 88. As discussed in more detail below, source / drain regions are subsequently formed in the first recesses 86, and the first semiconductor layers 52 in the n-type region 50N and the second semiconductor layers 54 in the p-type region 50P are subsequently replaced with corresponding gate structures. The internal spacers 90 serve as isolation features between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the internal spacers 90 can be used to prevent damage to the subsequently formed source / drain regions from subsequent etching processes, such as the etching processes used to subsequently form the gate structures.

[0045] The inner spacers 90 may be formed by depositing an inner spacer layer in the first recesses 86 and the sidewall recesses 88. The inner spacer layer may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The inner spacer layer may be formed from a material such as silicon nitride or silicon oxynitride, although low dielectric constant (low-k) materials having a k value of less than approximately 3.5 may also be used. The inner spacer layer may then be etched to form the inner spacers 90. The etching may be an anisotropic etch process, such as RIE, NBE, or the like.Although the outer sidewalls of the inner spacers 90 are illustrated as being recessed relative to the sidewalls of the second semiconductor layers 54 in the n-type region 50N and recessed relative to the sidewalls of the first semiconductor layers 52 in the p-type region 50P, the outer sidewalls of the inner spacers 90 may extend beyond or be flush with the sidewalls of the second semiconductor layers 54 and / or the first semiconductor layers 52. In other words, the inner spacers 90 may partially fill, completely fill, or overfill the sidewall recesses 88. Furthermore, although the sidewalls of the inner spacers 90 are illustrated as being straight, the sidewalls of the inner spacers 90 may be concave or convex.

[0046] In the Fig. 11A and Fig. 11B, epitaxial source / drain regions 92 are formed in the first recesses 86. The epitaxial source / drain regions 92 are formed in the first recesses 86 such that each of the dummy gates 76 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 81 and the second spacers 83 are used to separate the epitaxial source / drain regions 92 from the dummy gates 76 by an appropriate lateral distance such that the epitaxial source / drain regions 92 do not short-circuit subsequently formed gates of the nano-FETs.Furthermore, the inner spacers 90 can be used to separate the epitaxial source / drain regions 92 from the first semiconductor layers 52 in the n-type region 50N and from the second semiconductor layers 54 in the p-type region 50P by an appropriate lateral distance such that the epitaxial source / drain regions 92 do not short-circuit subsequently formed gates of the nano-FETs. The epitaxial source / drain regions 92 can be formed in contact with the inner spacers 90 (if present) and can extend beyond sidewalls of the second semiconductor layers 54 in the n-type region 50N and beyond sidewalls of the first semiconductor layers 52 in the p-type region 50P (if the sidewall recesses 88 are present). The epitaxial source / drain regions 92 can apply stress to the second semiconductor layers 54 in the n-type region 50N and to the first semiconductor layers 52 in the p-type region 50P, which improves performance.

[0047] The epitaxial source / drain regions 92 in the n-type region 50N may be formed by masking the p-type region 50P. The epitaxial source / drain regions 92 are then grown epitaxially in the first recesses 86 in the n-type region 50N. The epitaxial source / drain regions 92 may include any acceptable material suitable for n-type nano-FETs. For example, if the second semiconductor layers 54 are silicon, the epitaxial source / drain regions 92 in the n-type region 50N may include materials that exert tensile stress on the second semiconductor layers 54, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 in the n-type region 50N may have raised surfaces from respective surfaces of the fins 66, and may have facets.

[0048] The epitaxial source / drain regions 92 in the p-type region 50P may be formed by masking the n-type region 50N. The epitaxial source / drain regions 92 are then grown epitaxially in the first recesses 86 in the p-type region 50P. The epitaxial source / drain regions 92 may include any acceptable material suitable for p-type nano-FETs. For example, if the first semiconductor layers 52 are silicon germanium, the epitaxial source / drain regions 92 in the p-type region 50P may include materials that exert compressive stress on the first semiconductor layers 52, such as silicon germanium, boron-doped silicon germanium, germanium, germanide tin, or the like. The epitaxial source / drain regions 92 in the p-region 50P may also have raised surfaces from respective surfaces of the fins 66, and may have facets.

[0049] The epitaxial source / drain regions 92 and / or the fins 66 may be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by an annealing operation. The source / drain regions may have an impurity concentration in the range of approximately 10 19 cm -3 up to about 10 21 cm -3 The n- and / or p-type impurities for source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 92 may be doped in situ during growth.

[0050] As a result of the epitaxial processes used to form the epitaxial source / drain regions 92, upper surfaces of the epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of the fins 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of a same nano-FET to merge together, as shown by Fig. 11C. In other embodiments, adjacent epitaxial source / drain regions 92 remain separated from each other after completion of the epitaxial process, as shown by Fig. 11D. In the Fig. 11A and Fig. In the embodiments illustrated in FIG. 11B, the first spacers 81 and the second spacers 83 may be formed to cover portions of the sidewalls of the fins 66 that extend above the STI regions 68, thereby blocking epitaxial growth. In some further embodiments, the spacer etch used to form the first spacers 81 and the second spacers 83 may be adapted to remove the spacer material, thereby allowing the epitaxially grown regions to extend to the top surfaces of the STI regions 68.

[0051] The epitaxial source / drain regions 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 may include first semiconductor material layers 92A, second semiconductor material layers 92B, and third semiconductor material layers 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layers 92A, the second semiconductor material layers 92B, and the third semiconductor material layers 92C may be formed from different semiconductor materials and / or doped to different dopant concentrations. In some embodiments, the first semiconductor material layers 92A may have a lower dopant concentration than the second semiconductor material layers 92B and a higher dopant concentration than the third semiconductor material layers 92C.In embodiments in which the epitaxial source / drain regions 92 include three semiconductor material layers, the first semiconductor material layers 92A may be grown from the fins 66, the second semiconductor material layers 92B may be grown from the first semiconductor material layers 92A, and the third semiconductor material layers 92C may be grown from the second semiconductor material layers 92B.

[0052] In the Fig. 12A and Fig. 12B, a first interlayer dielectric (ILD) 96 is deposited over the epitaxial source / drain regions 92, the first spacers 81, the second spacers 83, the masks 78 (if present) or the dummy gates 76, and the STI regions 68. The first ILD layer 96 may be formed from a dielectric material and may be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like; nitrides such as silicon nitride; or the like. Other insulating materials formed by any acceptable process may also be used.In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD layer 96 and the epitaxial source / drain regions 92, the first spacers 81, the second spacers 83, the masks 78 (if present) or the dummy gates 76, and the STI regions 68. The CESL 94 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the first ILD layer 96.

[0053] In the Fig. 13A and Fig. 13B, a planarization process, such as CMP, may be performed to align the top surface of the first ILD layer 96 with the top surfaces of the masks 78 (if present) or the dummy gates 76. The planarization process may also remove the masks 78 on the dummy gates 76 and portions of the first spacers 81 and the second spacers 83 along the sidewalls of the masks 78. After the planarization process, top surfaces of the dummy gates 76, the first spacers 81, the second spacers 83, and the first ILD layer 96 are coplanar (within process variations). Consequently, the top surfaces of the dummy gates 76 are exposed through the ILD layer 96.In some embodiments, the masks 78 may remain, in which case the planarization process brings the top surface of the first ILD layer 96 into line with the top surface of the masks 78, the first spacers 81, and the second spacers 83.

[0054] In the Fig. 14A and Fig. 14B, the first semiconductor layers 52 in the n-type region 50N and the second semiconductor layers 54 in the p-type region 50P are removed. The remaining semiconductor layers form nanostructures 55N, 55P, which are arranged between adjacent pairs of the epitaxial source / drain regions 92. In particular, the remaining second semiconductor layers 54 in the n-type region 50N form the nanostructures 55N, which serve as channel regions for n-type nanoFETs, and the remaining first semiconductor layers 52 in the p-type region 50P form the nanostructures 55P, which serve as channel regions for p-type nanoFETs. The formation of the nanostructures 55N, 55P is described below with reference to the Fig. 15A to 15G are discussed in more detail.

[0055] The dummy gates 76 and optionally the dummy dielectrics 60 are removed and replaced by gate structures 85 that enclose the nanostructures 55. The gate structures 85 include gate dielectrics 112 and gate electrodes 114. The formation of the gate structures 85 is described below with respect to the Fig. 15A to 15G. As discussed in more detail below, the gate electrodes 114 are formed in a funnel shape, with lower portions of the gate electrodes 114 having parallel opposing sidewalls and upper portions of the gate electrodes 114 having sloped opposing sidewalls. Forming funnel-shaped gate electrodes 114 can help prevent the formation of seams (or voids) in the gate electrodes 114, which can improve the work function of the gate electrodes 114 and reduce the internal gate resistance (R g) of the gate electrodes 114. The performance and yield of the resulting nano-FETs can thus be improved.

[0056] The Fig. 15A to 15G are cross-sectional views of intermediate stages of a process for forming the nanostructures 55 (see Fig. 15D) and the exchange gate structures 85 (see Fig. 15G) in accordance with some embodiments. The Fig. 15A to 15G are along the reference cross-section BB in Fig. 1. An n-range 15N in Fig. 14B, which is part of the n-region 50N, and a p-region 15P in Fig. 14B, which is part of the p-type region 50P, are shown in more detail. In the illustrated process, the dummy dielectrics 60 and the dummy gates 76 are removed and replaced with gate dielectrics 112 and gate electrodes 114, respectively. In some embodiments, the dummy dielectrics 60 are removed in a first region of a die (e.g., a core logic region) and remain in a second region of the die (e.g., an input / output region). In other words, the illustrated gate replacement process may be performed in the first region of the die (e.g., the core logic region), and a gate replacement process in which the dummy dielectrics 60 are not removed may be performed in the second region of the die (e.g., the input / output region).

[0057] In Fig. 15A, the dummy gates 76 and the masks 78 (if present) are etched in one or more etching steps such that the recesses 100 are formed. Each of the recesses 100 exposes sidewalls of the first spacers 81. The recesses 100 may be small. For example, the recesses 100 may have widths W1 in the range of approximately 4 nm to approximately 24 nm, and may have depths D1 in the range of approximately 50 nm to approximately 120 nm. The widths W1 of the recesses 100 may have a standard deviation of approximately 1 nm. The widths W1 of the recesses 100 correspond to the lengths of the channel regions for the nano-FETs. Forming the channel regions for the nano-FETs with a short length may improve the performance of the resulting nano-FETs. However, forming the channel regions with a short length results in the recesses 100 having a high aspect ratio (e.g., a high ratio of depth D1 to width W1).When the recesses 100 have a high aspect ratio, seams (or voids) are likely to form in material deposited in the recesses 100, particularly as the recesses 100 are further enlarged (as discussed in more detail below). As discussed in more detail below, expanding the upper portions of the recesses 100 to have a funnel shape may help prevent the formation of such seams.

[0058] The dummy gates 76 can be recessed by a wet or dry etch. For example, the etching process can include a dry etching process using reactant gas(es) that selectively etches the dummy gates 76 at a higher rate than the first ILD layer 96, the first spacers 81, or the second spacers 83. Timed etching processes can be used to stop the etching of the dummy gates 76 after the recesses 100 have reached a desired depth. In particular, the depth of the recesses 100 is controlled such that the fins 66 and the dummy dielectrics 60 remain covered after the formation of the recesses 100.In some embodiments, the dummy gates 76 are recessed by an anisotropic dry etching process performed with methane (CH4), fluorine (F), ammonia (NH3), or the like, which is performed for a duration in the range of approximately 30 seconds to approximately 180 seconds, thereby enabling the remaining portions of the dummy gates 76 to have a height H1 (measured from the top surfaces of the fins 66) of less than approximately 5 nm. Performing the anisotropic dry etching process with parameters in these ranges enables the recesses 100 to be formed to a sufficient depth to protect both the fins 66 and the dummy dielectrics 60, as well as to ensure that the recesses 100 can be sufficiently expanded during subsequent processing.Performing the anisotropic dry etching process with parameters outside these ranges does not allow the recesses 100 to be formed to a depth sufficient to protect both the fins 66 and the dummy dielectrics 60, nor does it ensure that the recesses 100 can be sufficiently expanded during subsequent processing.

[0059] In Fig. 15B, an impurity is implanted into first regions of the spacers 81, 83 to modify an etch rate of the first regions of the spacers 81, 83 compared to second regions of the gate spacers that have not been implanted with the impurity. As discussed in more detail below, the first regions of the spacers 81, 83 are etched to widen the recesses 100 to reduce or prevent the formation of voids or seams during subsequent formation of replacement gate structures. The second regions of the spacers 81, 83 remain unmodified or less modified during / after the impurity implantation. In embodiments in which the spacers 81, 83 are formed from silicon oxycarbonitride, as discussed above, the impurity may be oxygen, and the implantation may be performed by a plasma oxidation process.In another embodiment, in which the spacers 81, 83 are formed from silicon oxycarbonitride, as discussed above, the impurity may be nitrogen, and the implantation may be performed using a plasma nitriding process. The impurity implantation modifies regions 81M of the first spacers 81 and regions 83M of the second spacers 83, with unmodified regions 81N of the first spacers 81 and unmodified regions 83N of the second spacers 83 remaining unaffected by the impurity implantation (or at least less affected than the modified regions 81M, 83M). In some embodiments, the impurity implantation also modifies regions 96M of the first ILD layer 96, with unmodified regions 96N of the first ILD layer 96 remaining unaffected by the impurity implantation.In some embodiments, the impurity implantation also modifies regions 76M of the dummy gates 76, leaving unmodified regions 76N of the dummy gates 76 unaffected by the impurity implantation. The exposed portions of the CESL 94 are thin, and thus the CESL 94 remains substantially unaffected by the impurity implantation.

[0060] The modified regions 81M and the modified regions 83M are rich in impurities. For example, the modified regions 81M, 83M may both contain silicon oxycarbonitride having a higher concentration (in atomic percent) of oxygen or nitrogen than the unmodified regions 81N and the unmodified regions 83N. In some embodiments, the unmodified regions 81N, 83N retain their original composition. In other words, the final composition of the unmodified regions 81N, 83N is the same as the original composition of the unmodified regions 81N, 83N. In some embodiments, the unmodified regions 81N, 83N are modified very slightly, but less than the modified regions 81M, 83M.In other words, the final composition of the unmodified regions 81N, 83N is closer to their original composition than the final composition of the modified regions 81M, 83M. As discussed in more detail below, an etching is subsequently performed selectively for the modified (e.g., impurity-rich) regions to remove the modified regions 81M and the modified regions 83M, thereby widening the recesses 100.

[0061] In some embodiments, the impurity implantation is performed through a plasma implantation process. The plasma implantation process may be performed in a chamber, with a chuck within the chamber holding the substrate 50 in place. Precursor gases are supplied to the chamber, and a plasma generator may be used to generate plasma from the precursor gases. The plasma generator may be an inductively coupled plasma (ICP) generator, a transformer-coupled plasma (TCP) generator, a remote plasma generator, or the like.

[0062] During the plasma implantation process, a gas source is supplied to the substrate 50 (e.g., by flow). The gas source contains an impurity source precursor gas and a carrier gas. Suitable impurity source precursor gases include, for example, oxygen gas (O2) if oxygen is implanted, and nitrogen gas (N2) if nitrogen is implanted. Suitable carrier gases include, but are not limited to, xenon, helium, argon, neon, krypton, radon, the like, or combinations thereof.In embodiments in which oxidation is performed, the gas source includes, for example, oxygen gas as the contaminant source precursor gas and argon, oxygen, helium, neon, or xenon as the carrier gas, wherein the contaminant source precursor gas may be provided at a flow rate in the range of about 0 sccm to about 500 sccm, and the carrier gas may be provided at a flow rate in the range of about 10 sccm to about 1000 sccm.Likewise, in embodiments in which nitriding is performed, the gas source includes nitrogen gas as the contaminant source precursor gas and argon, ammonia, nitrogen, helium, neon, or xenon as the carrier gas, wherein the contaminant source precursor gas may be provided at a flow rate in the range of about 0 sccm to about 500 sccm, and the carrier gas may be provided at a flow rate in the range of about 10 sccm to about 1000 sccm.

[0063] Radio frequency (RF) power is generated by the plasma generator to create a plasma from the gas source. The plasma contains impurity ions 102 (e.g., oxygen ions, nitrogen ions, etc.) and impurity radicals 104 (e.g., oxygen radicals, nitrogen radicals, etc.). A bias voltage is applied between the plasma generator and the chuck that holds the substrate 50. In some embodiments, an applied RF bias voltage is pulsed between a low power and a high power. In some embodiments, an applied direct current (DC) bias voltage is pulsed between a low voltage and a high voltage. During the application of the bias voltage, the impurity ions 102 are accelerated across the plasma and implanted into the spacers 81, 83 to form the modified regions 81M, 83M.The impurity ions 102 are also implanted into the first ILD layer 96 to form the modified regions 96M. The plasma generator power may range from approximately 30 watts to approximately 4000 watts. When the bias voltage is not applied, in such embodiments, the impurity ions 102 have a total energy in the range of approximately 0.5 eV to approximately 25 eV, and the impurity radicals 104 have a total energy in the range of approximately 0.5 eV to approximately 10 eV. The plasma implantation process may be performed using an RF bias voltage having a low power of approximately zero and a high power of up to approximately 100 watts. The plasma implantation process may be performed using a DC bias voltage having a low voltage of approximately zero and a high voltage of up to approximately 100 V.In such embodiments, the application of the bias voltage increases the total energy of the impurity ions 102 by an amount in the range of about 3 eV to about 10 eV, and does not increase the total energy of the impurity radicals 104.

[0064] During the plasma implantation process, the impurity ions 102 collide with the impurity radicals 104, which can lead to a low directivity of the implantation, causing shadowing during implantation. In other words, the implantation occurs in a non-directional manner. In accordance with some embodiments, the generated plasma contains few impurity ions 102 and many impurity radicals 104. For example, the generated plasma can have a plasma density in the range of approximately 10 9 up to about 10 12Generating the plasma with many impurity radicals 104 causes the impurity ions 102 to collide with more impurity radicals 104 during implantation, thereby increasing the amount of shadowing and directing fewer impurity ions 102 to the remaining portions of the dummy gates 76. As a result, a majority of the impurity ions 102 are implanted at an acute angle of incidence with respect to the main surface of the structure (e.g., a top surface of the first ILD layer 96 or a main surface of the substrate 50). The angle of incidence may be small, such as in the range of approximately 3 degrees to approximately 50 degrees.

[0065] The extent of shadowing during the plasma implantation process can be increased by controlling the environment during plasma generation. In particular, the temperature, pressure, and plasma generation power, as well as the bias voltage magnitude, can influence the amount of impurity ions 102 and impurity radicals 104 generated. In accordance with some embodiments, the plasma is generated at a low temperature, low pressure, low plasma generation power, and low bias voltage magnitude. For example, the plasma may be generated at a temperature ranging from about room temperature (e.g., about 20°C) to about 650°C, at a pressure ranging from about 0.67 Pa to about 66.7 Pa (about 5 mTorr to about 500 mTorr), with the plasma generation power and bias voltage magnitude discussed above.Such a plasma-generating environment results in a large amount of shadowing during implantation. The plasma implantation process can be performed for a duration ranging from approximately 3 seconds to approximately 300 seconds, resulting in a dosage of implanted oxygen in the range of approximately 10. 12 cm -3 up to about 10 19 cm -3Performing the plasma implantation process with parameters within these ranges allows the modified regions 81M, 83M to have sufficient etch selectivity relative to the unmodified regions 81N, 83N, such that the unmodified regions 81N, 83N are protected from etching during the subsequent removal of the modified regions 81M, 83M. Performing the plasma implantation process with parameters outside these ranges may not allow the modified regions 81M, 83M to have sufficient etch selectivity relative to the unmodified regions 81N, 83N, such that the unmodified regions 81N, 83N are not protected from etching during the subsequent removal of the modified regions 81M, 83M.

[0066] When the recesses 100 have a high aspect ratio, implanting the impurity ions 102 with a large amount of shadowing results in fewer impurity ions 102 being implanted into lower portions of the recesses than into upper portions of the recesses 100. Due to the large amount of shadowing, the modified regions 81M, 83M are further formed by implanting the upper surfaces and exposed sidewalls of the spacers 81, 83, whereby the modified regions 81M, 83M have the shape of right-angled triangles. The shape of the spacers 81, 83 resulting from the triangular-shaped modified regions 81M, 83M will be discussed in more detail below.

[0067] In Fig. 15C, the remaining portions of the dummy gates 76 are removed in one or more etching steps such that the recesses 100 are widened to expose the dummy dielectrics 60. The dummy gates 76 may be removed by a wet or dry etch that etches both the modified regions 76M and the unmodified regions 76N of the dummy gates 76. For example, the etching process may comprise a dry etch process using reactant gas(es) that selectively etches the dummy gates 76 at a higher rate than the first ILD layer 96, the first spacers 81, or the second spacers 83. In some embodiments, the dummy gates 76 are removed by an anisotropic dry etch process performed with the same etchants as those described with respect to Fig. 15A (e.g., the anisotropic dry etch process initially used to recess the dummy gates 76), but the parameters of the anisotropic dry etch process are modified to increase the etch selectivity with respect to the material of the dummy gates 76. During the dry etch, a bias voltage is applied between a plasma generator and a chuck that holds the substrate 50. In some embodiments, the anisotropic dry etch initially used to recess the dummy gates 76 and the anisotropic dry etch used to remove the remaining portions of the dummy gates 76 are performed with different bias voltages, e.g., a different DC bias voltage and / or a different RF bias voltage.In some embodiments, the dry etch to remove the remaining portions of the dummy gates 76 may be performed using a DC bias having a low voltage of approximately zero and a high voltage of up to approximately 300 V. In some embodiments, the dry etch to remove the remaining portions of the dummy gates 76 may be performed using an RF bias having a low power of approximately zero and a high power of up to approximately 1000 watts. Performing the dry etch with bias(es) in these regions may increase the anisotropy of the dry etch, which may increase the etch selectivity toward the material of the dummy gates 76.

[0068] The modified regions 81M, 83M of the spacers 81, 83 are then removed in one or more etching steps, thereby widening the upper portions of the recesses 100. The etching steps are selective toward the impurity implanted into the spacers 81, 83. For example, if the spacers 81, 83 contain silicon oxycarbonitride and the modified regions 81M, 83M are oxygen-rich or nitrogen-rich, the etching process may include a dry etch using reactant gas(es) that are selective toward oxides or nitrides, respectively. Since the modified regions 81M, 83M have a higher concentration of impurity than the unmodified regions 81N, 83N, the etching process etches the modified regions 81M, 83M at a higher rate than the unmodified regions 81N, 83N.For example, the etch rate of the modified regions 81M, 83M may be approximately 1.1 to approximately 10 times higher than the etch rate of the unmodified regions 81N, 83N with respect to the etching process. In some embodiments, the dummy dielectrics 60 may be formed from a material having a high impurity composition, whereby the etching process may also etch the dummy dielectrics 60 at a high rate. For example, if the dummy dielectrics 60 are oxides and the impurity implanted into the modified regions 81M, 83M is oxygen, the etch selectivity towards oxygen-rich regions may also etch the dummy dielectrics 60. In particular, during the removal of the modified regions 81M, 83M, the dummy dielectrics 60 may be removed to further deepen the recesses 100. Finally, as mentioned above, modified regions 96M of the first ILD layer 96 may also be formed.The modified regions 96M of the first ILD layer 96 may also be etched at a high rate by the etching process to form the recesses 106.

[0069] In some embodiments, the etching process is an anisotropic dry etch performed with nitrogen trifluoride (NF3), ammonia (NH3), hydrogen fluoride (HF), or the like. The etching gas solution may flow over the substrate 50, such as in the recesses 100, while no plasma is generated. The dry etch may be performed for a duration ranging from about 1 second to about 250 seconds and at a temperature from about room temperature (e.g., about 20°C) to about 350°C. The dry etch converts the material of the modified regions 81M, 83M, the modified regions 96M, and the dummy dielectrics 60 into byproducts that may be removed from the recesses 100, for example, by a vacuum.For example, if the impurity is oxygen, the anisotropic dry etch can be performed with HF, NH3, NF3, or combinations thereof to produce byproducts such as ammonium fluorosilicate, silicon tetrafluoride, water, or combinations thereof. If the impurity is nitrogen, the anisotropic dry etch can also be performed with HF, NH3, NF3, or combinations thereof to produce byproducts such as ammonium fluorosilicate, silicon tetrafluoride, or combinations thereof.

[0070] In a further embodiment in which the dummy dielectrics 60 are not formed from a material having a high impurity composition, the modified regions 81M, 83M of the spacers 81, 83 and the modified regions 96M of the first ILD layer 96 may be removed in a first etching process, and the dummy dielectrics 60 may be removed in a second etching process.

[0071] After the etching process, the unmodified regions 81N, 83N of the spacers 81, 83 and the unmodified regions 96N of the first ILD layer 96 remain. The remaining portions of the first spacers 81 have upper portions 81U and lower portions 81L. The remaining portions of the second spacers 83 have upper portions 83U and lower portions 83L. The upper portions 81U, 83U and the lower portions 81L, 83L together form funnel shapes for the recesses 100. The upper portions 81U, 83U have inclined opposite sidewalls that meet at an apex. The opposite sidewalls of the upper portions 81U, 83U form an interior angle θ1. The angle θ1 can range from approximately 3 degrees to approximately 50 degrees. The widths of the upper sections 81U, 83U decrease continuously in a direction away from the upper surfaces of the fins 66.The widths of the lower sections 81L, 83L are constant along the direction away from the upper surfaces of the fins 66. The lower sections 81L, 83L have parallel opposite side walls.

[0072] As mentioned above, in some embodiments, the regions 81N, 83N of the spacers 81, 83 are not completely unmodified, but are less modified than the regions 81M, 83M. In particular, the regions 81N, 83N can be implanted with less impurity than the regions 81M, 83M. Consequently, in such embodiments, the upper portions 81U, 83U of the spacers 81, 83 can contain a little of the impurity, while the lower portions 81L, 83L of the spacers 81, 83 do not contain the impurity. For example, if oxygen is implanted, the upper portions 81U, 83U can contain SiO x N y C 1-x-ywhere x and y are in the range from 0 to 1 and x is greater than y, and the lower portions 81L, 83L of the spacers 81, 83 may be SiO x N y C 1-x-y where x and y are in the range 0 to 1 and x is less than, equal to, or greater than y.

[0073] The recesses 100 are enlarged by removing the modified regions 81M, 83M and the dummy dielectrics 60. For example, the recesses 100 may have depths D2 in the range of approximately 55 nm to approximately 125 nm, and may have lower widths W2 in the range of approximately 4 nm to approximately 24 nm and upper widths W3 in the range of approximately 6 nm to approximately 40 nm. Due to the removal of the dummy gates 76 and the dummy dielectrics 60, the depths D2 are greater than the depths D1 (see Fig. 15A). The lower widths W2 are arranged at the bottoms of the recesses 100 and are larger than the widths W1 (see Fig. 15A), since the unmodified regions 81N, 83N of the spacers 81, 83 are etched slightly, although they are etched less than the modified regions 81M, 83M of the spacers 81, 83. The bottom widths W2 of the recesses 100 may have a standard deviation of approximately 2 nm. The standard deviation of the bottom widths W2 may be larger than the standard deviation of the widths W1. The bottom widths W2 of the recesses 100 correspond to the lengths of the channel regions for the nano-FETs. Forming the channel regions for the nano-FETs with a short length can improve the performance of the resulting nano-FETs. The top widths W3 are located at the tops of the recesses 100 and are larger than the bottom widths W2.

[0074] The spacers 81, 83 have inner edges 81C, 83C at the interfaces of the upper sections 81U, 83U, and the lower sections 81L, 83L, respectively. In the illustrated embodiment, the inner edges 81C, 83C have sharply defined profiles. In some embodiments (discussed in more detail below), the inner edges 81C, 83C do not have sharply defined profiles, but rather have rounded profiles. The inner edges 81C are located at a height H2 from the upper surfaces of the fins 66, which may range from approximately 4 nm to approximately 38 nm.

[0075] Widening the recesses 100 to have a funnel shape can help prevent pinch-off effects during filling of the recesses 100, thereby preventing the formation of seams. A ratio of the upper widths W3 to the lower widths W2 can range from about 1.1 to about 11, and a ratio of the depth D2 to the height H2 can range from about 1.2 to about 32. Widening the recesses 100 to have dimensional ratios in these ranges helps form a funnel shape, which helps prevent pinch-off effects during subsequent filling. Forming the recesses 100 to have dimensional ratios outside of these ranges may not help form a funnel shape, which would help prevent pinch-off effects during subsequent filling.For example, if the ratio of the upper widths W3 to the lower widths W2 is larger than the specified range, parasitic capacitance may be induced between the resulting gate structures, due, among other things, to excessive dielectric losses between the gate structures. Pinch-off effects may also occur if the ratio of the upper widths W3 to the lower widths W2 is lower than the specified range.

[0076] In Fig. 15D, the first semiconductor layers 52 in the n-type region 50N and the second semiconductor layers 54 in the p-type region 50P are removed to expand the recesses 100. Thus, the nanostructures 55N are formed in the n-type region 50N, and the nanostructures 55P are formed in the p-type region 50P.

[0077] The first semiconductor layers 52 in the n-type region 50N may be removed by masking the p-type region 50P and performing an etching process in the n-type region 50N. In some embodiments, the etching process is an isotropic etching process, such as a wet etch using etchants that selectively etch the first semiconductor layers 52 at a faster rate than the second semiconductor layers 54 or the substrate 50. In embodiments in which the first semiconductor layers 52 are formed of silicon germanium, the first semiconductor layers 52 in the n-type region 50N may be removed by a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.

[0078] The second semiconductor layers 54 in the p-type region 50P may be removed by masking the n-type region 50N and performing an etching process in the p-type region 50P. In some embodiments, the etching process is an isotropic etching process, such as a wet etch using etchants that selectively etch the second semiconductor layers 54 at a faster rate than the first semiconductor layers 52 or the substrate 50. In embodiments in which the second semiconductor layers 54 are formed of silicon or silicon carbide, the second semiconductor layers 54 in the p-type region 50P may be removed by a wet etching process using dilute ammonium hydroxide-hydrogen peroxide (APM), sulfuric acid-hydrogen peroxide (SPM), or the like.

[0079] In Fig. 15E, a gate dielectric layer 108 is formed. The gate dielectric layer 108 is conformally deposited in the recesses 100, 106. In the n-type region 50N, the gate dielectric layer 108 is formed on top surfaces, sidewalls, and bottom surfaces of the nanostructures 55N. In the p-type region 50P, the gate dielectric layer 108 is formed on top surfaces, sidewalls, and bottom surfaces of the nanostructures 55P. The gate dielectric layer 108 is also deposited on top surfaces of the first ILD layer 96, the CESL 94, the first spacers 81, the second spacers 83, and the STI regions 68.

[0080] Fig. 15H is a detailed view of an area 15H in Fig. 15E, which shows the gate dielectric layer 108 in detail. The gate dielectric layer 108 comprises one or more dielectric layers, such as an oxide, a metal oxide, a metal silicate, the like, or combinations thereof. In some embodiments, the gate dielectric layer 108 may, for example, include an interfacial layer 108A of silicon oxide formed by thermal or chemical oxidation and a metal oxide layer 108B over the interfacial layer 108A. In some embodiments, the gate dielectric layer 108 comprises a high-k dielectric material, and in these embodiments, the gate dielectric layer 108 may have a k value greater than about 7.0, and may include a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.The methods for forming the gate dielectric layer 108 may include molecular beam deposition (MBD), ALD, CVD, PECVD, and the like. In some embodiments, the same gate dielectric layer 108 is deposited in the n-type region 50N and the p-type region 50P. In some embodiments, different gate dielectric layers 108 are deposited in the n-type region 50N and the p-type region 50P.

[0081] In Fig. 15F, a gate electrode layer 110 is deposited over the gate dielectric layer 108, filling the remaining portions of the recesses 100. Fig. 15H is a detailed view of an area 15H in Fig. 15F, which shows the gate electrode layer 110 in detail. The gate electrode layer 110 may contain a metallic material, such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Fig. For example, in Figure 15F, a single gate electrode layer 110 is shown, however, the gate electrode layer 110 may include any number of insert layers / claddings 110A, any number of work function tuning layers 110B, and a fill material 110C, as shown in Fig. 15H. Any combination of the layers forming the gate electrode layer 110 may be deposited in the n-type region 50N between adjacent nanostructures 55N, and may be deposited in the p-type region 50P between adjacent nanostructures 55P.

[0082] In Fig. 15G, a planarization process, such as CMP, may be performed to remove the excess portions of the gate dielectric layer 108 and the gate electrode layer 110 material, wherein these excess portions are disposed outside the recesses 100, for example, above the top surface of the first ILD layer 96. The remaining portions of the gate dielectric layer 108 and the gate electrode layer 110 form the gate dielectrics 112 and the gate electrodes 114, respectively. The gate dielectrics 112 and the gate electrodes 114 form the gate structures 85 of the resulting nano-FETs. The gate structures 85 are in physical contact with the remaining portions of the spacers 81, 83. After the planarization process, the gate structures 85 may have a height H3 (measured from the top surfaces of the nanostructures 55) in the range of approximately 4 nm to approximately 30 nm.The final height H3 of the gate structures 85 is less than the depth D2 of the recesses 100 due to the planarization process (see . Fig. 15C). As discussed in more detail below, the gate structures 85 have a funnel shape. In some embodiments, the ratio of the upper widths of the gate structures 85 to the lower widths of the gate structures 85 may range from about 1.1 to about 11.

[0083] In some embodiments, the upper portions 81U, 83U of the spacers 81, 83 remain after the planarization process. The gate electrodes 114 thus have upper portions 114U and lower portions 114L, which together form a funnel shape. The widths of the upper portions 114U continuously increase in a direction away from the upper surfaces of the nanostructures 55. The widths of the lower portions 114L are constant along the direction away from the upper surfaces of the nanostructures 55. The widths of the gate dielectrics 112 are constant along the sidewalls of the gate electrodes 114. The gate electrodes 114 have inner edges 114C at the interfaces of the upper portions 114U and the lower portions 114L. Side walls of the gate electrodes 114 form an interior angle θ2 at the inner edges 114C of the gate electrodes 114, wherein the difference between the interior angle θ2 and the interior angle θ1 (see Fig. 15C) is equal to 180 degrees. In other words, the angle θ2 can range from approximately 183 degrees to approximately 230 degrees. In the illustrated embodiment, the inner edges 114C have sharply defined profiles. In some embodiments (discussed in more detail below), the inner edges 114C do not have sharply defined profiles, but rather have rounded profiles.

[0084] The formation of the gate dielectrics 112 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectrics 112 in each of the regions are formed from the same materials, and the formation of the gate electrodes 114 may occur simultaneously, such that the gate electrodes 114 in each of the regions are formed from the same materials. In some embodiments, the gate dielectrics 112 in each of the regions may be formed by separate processes, such that the gate dielectrics 112 may be made of different materials and / or have a different number of layers, and / or the gate electrodes 114 in each of the regions may be formed by separate processes, such that the gate electrodes 114 may be made of different materials and / or have a different number of layers.Different masking steps can be used to mask and reveal corresponding areas using separate processes.

[0085] The information relating to the Fig. The embodiments described in Figures 15A to 15G are discussed in the context of a plasma oxidation process or a plasma nitriding process. However, it should be considered that any impurity may be implanted into the spacers 81, 83 (see Fig. 15B) to modify an etching rate of portions of the spacers 81, 83. Then, any etching (see Fig. 15C), which is selective to the implanted impurity, may be performed to remove the modified portions of the spacers 81, 83 and to widen the recesses 100.

[0086] In the Fig. 16A and Fig. 16B, a second ILD layer 118 is deposited / applied over the first ILD layer 96. The second ILD layer 118 may be formed from a dielectric material and may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include oxides, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like; nitrides, such as silicon nitride; or the like. After its formation, the second ILD layer 118 may be planarized, for example, by CMP. In some embodiments, an etch stop layer is formed between the first ILD layer 96 and the second ILD layer 118.The etch stop layer may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, having a different etch rate than the material of the second ILD layer 118.

[0087] In some embodiments, prior to forming the second ILD layer 118, gate masks 116 may be formed over the gate dielectrics 112 and the gate electrodes 114. The gate masks 116 may protect the gate dielectrics 112 and the gate electrodes 114 during subsequent contact formation, and subsequently formed gate contacts may penetrate the gate masks 116. As an example of forming the gate masks 116, the gate dielectrics 112 and the gate electrodes 114 may be recessed such that recesses are formed directly between opposing portions of the second spacers 83. One or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, are filled into the recesses. A planarization process is performed to remove excess portions of the dielectric material that extend beyond the first ILD layer 86.The remaining portions of the dielectric material in the recesses form the gate masks 116.

[0088] In the Fig. 17A and Fig. 17B, ​​gate contacts 120 are formed extending through the second ILD layer 118 and the gate masks 116 (if present), and source / drain contacts 122 are formed extending through the second ILD layer 118, the first ILD layer 96, and the CESL 94. Openings for the gate contacts 120 are formed through the second ILD layer 118 and the gate masks 116, and openings for the source / drain contacts 122 are formed through the second ILD layer 118, the first ILD layer 96, and the CESL 94. The openings may be formed using acceptable photolithography and etching techniques. A spacer / liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The intermediate layer may contain titanium, titanium nitride, tantalum, tantalum nitride or the like.The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD layer 118. The remaining spacer / liner and the conductive material form the gate contacts 120 and the source / drain contacts 122 in the openings. The gate contacts 120 are connected (e.g., by physical and electrical coupling) to the gate electrodes 114, and the source / drain contacts 122 are connected to the epitaxial source / drain regions 92. The gate contacts 120 and the source / drain contacts 122 may be formed in different processes or in the same process.Although the gate contacts 120 and the source / drain contacts 122 are shown in the same cross-section, the contacts may be formed in different cross-sections, which may prevent short-circuiting of the contacts.

[0089] In some embodiments, silicide regions are formed between the epitaxial source / drain regions 92 and the source / drain contacts 122. In some embodiments, the silicide regions are formed by depositing a metal in the openings for the source / drain contacts 122 (e.g., on the epitaxial source / drain regions 92) followed by performing a thermal annealing process. The metal may be one capable of reacting with the semiconductor materials of the epitaxial source / drain regions 92 (e.g., silicon, silicon-germanium, germanium, etc.) to form silicide regions, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals or their alloys, or the like. After the thermal annealing process, any unreacted portion of the deposited metal can then be removed, for example by an etching process.Although referred to as silicide regions, the regions formed on the epitaxial source / drain regions 92 may also be germanide regions, silicon germanide regions (e.g., regions containing silicide and germanide), or the like.

[0090] Fig. Figure 18 shows cross-sectional views of nano-FETs in accordance with some embodiments. An n-region 15N in Fig. 17B, ​​which is part of the n-region 50N, and a p-region 15P in Fig. 17B, ​​which is part of the p-type region 50P, are shown in detail. As shown, the gate masks 116 may have sloped sidewalls.

[0091] Embodiments may achieve advantages. Performing an impurity implantation makes it possible to modify first regions of the spacers 81, 83 (e.g., regions 81M, 83M) more than second regions of the spacers 81, 83 (e.g., regions 81N, 83N). Thus, an etch selective to the impurity may then be performed to remove the first regions of the spacers 81, 83 (e.g., regions 81M, 83M), substantially without etching the second regions of the spacers 81, 83 (e.g., regions 81N, 83N). Thus, the recesses 100 have upper portions that continuously increase in width in a direction away from the fins 66. Forming the recesses 100 with such a shape can help prevent pinch-off effects when filling the recesses 100 with the gate electrode layer 110. Thus, the gap filling window for the gate electrode layer 110 can be improved.Improving the gap-fill window for the gate electrode layer 110 can prevent or reduce the formation of seams (or voids) in the gate electrodes 114. The work function and the internal gate resistance (R g ) of the gate electrodes 114 can thus be improved, thereby increasing the performance and yield of the resulting FinFETs.

[0092] In one embodiment, a method comprises: forming a dummy dielectric over a plurality of semiconductor layers; forming a dummy gate over the dummy dielectric; depositing a gate spacer adjacent to the dummy gate and the dummy dielectric; deepening the dummy gate to form a recess exposing the gate spacer; implanting an impurity in a first region of the gate spacer to increase an etch rate of the first region of the gate spacer, wherein a second region of the gate spacer remains unmodified by the implantation; removing the dummy dielectric, the first region of the gate spacer, and remaining portions of the dummy gate to expose the semiconductor layers in the recess; patterning the semiconductor layers to form nanostructures;and forming a gate structure in the recess, wherein the gate structure encloses the nanostructures, and the gate structure contacts the second region of the gate spacer;

[0093] In some embodiments of the method, implanting the impurity in the first region of the gate spacer comprises: flowing a gas source comprising an impurity source precursor gas and a carrier gas over the semiconductor layers; generating a plasma from the gas source, the plasma comprising impurity ions and impurity radicals; and accelerating the impurity ions in the plasma toward the gate spacer in a non-directional manner. In some embodiments of the method, the impurity is oxygen, and the impurity source precursor gas includes oxygen gas. In some embodiments of the method, the impurity is nitrogen, and the impurity source precursor gas includes nitrogen gas.In some embodiments of the method, the plasma is generated at a temperature in a range of 20°C to 650°C, a pressure in a range of 0.67 Pa to 66.7 Pa (5 mTorr to 500 mTorr), and a radio frequency (RF) power in a range of 30 to 4000 watts, and accelerating the impurity ions comprises applying a direct current (DC) bias having a low voltage of zero and a high voltage of up to 100 kV. In some embodiments of the method, the plasma is generated at a temperature in a range of 20°C to 650°C, a pressure in a range of 0.67 Pa to 66.7 Pa (5 mTorr to 500 mTorr), and a radio frequency (RF) power in a range of 30 to 4000 watts, and accelerating the impurity ions comprises applying a radio frequency (RF) bias voltage having a low power of zero and a high power of up to 100 watts.In some embodiments of the method, the plasma has a plasma density in a range of 10. 9 up to 10 12In some embodiments of the method, removing the dummy dielectric and the first region of the gate spacer comprises performing an anisotropic dry etch in the recess, wherein the anisotropic dry etch etches the dummy dielectric and the first region of the gate spacer at a higher rate than the second region of the gate spacer. In some embodiments of the method, the impurity is oxygen, the gate spacer includes silicon oxycarbonitride, the anisotropic dry etch is performed with nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer into the byproducts of ammonium fluorosilicate, silicon tetrafluoride, or water.In some embodiments of the method, the impurity is nitrogen, the gate spacer contains silicon oxycarbonitride, the anisotropic dry etch is performed with nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer into the byproducts ammonium fluorosilicate or silicon tetrafluoride. In some embodiments of the method, after removing the dummy dielectric, the first region of the gate spacer, and the remaining portions of the dummy gate, the recess has an upper width and a lower width, the upper width being greater than the lower width, and a ratio of the upper width to the lower width being in a range of 1.1 to 11.In some embodiments of the method, recessing the dummy gate comprises performing a first anisotropic dry etch process with methane at a first bias voltage, and removing the remaining portions of the dummy gate comprises performing a second anisotropic dry etch process with methane at a second bias voltage, wherein the second bias voltage is different from the first bias voltage.

[0094] In some examples, a structure comprises: a nanostructure; an epitaxial source / drain region adjacent to the nanostructure; a gate dielectric encasing the nanostructure; a gate electrode over the gate dielectric, the gate electrode comprising a top portion and a bottom portion, wherein a first width of the top portion continuously increases in a first direction away from a top surface of the nanostructure, and a second width of the bottom portion is constant along the first direction; and a gate spacer between the gate dielectric and the epitaxial source / drain region.

[0095] In some examples, the gate electrode has an inner edge at interfaces of the upper portion and the lower portion, wherein sidewalls of the gate electrode form an angle at the inner edge, wherein the angle is in a range of 183 degrees to 230 degrees. In some examples of the structure, the gate spacer has an upper portion and a lower portion, wherein a third width of the upper portion continuously decreases in the first direction, and a fourth width of the lower portion is constant along the first direction. In some examples, the structure further comprises: a gate mask over the gate electrode and the gate dielectric, the gate mask having sloped sidewalls; and a gate contact extending through the gate mask to contact the gate electrode.In some examples of the structure, the gate spacer includes silicon oxycarbonitride having a first concentration of oxygen in an upper portion of the gate spacer and a second concentration of oxygen in a lower portion of the gate spacer, wherein the second concentration is lower than the first concentration. In some examples of the structure, the gate spacer includes silicon oxycarbonitride having a first concentration of nitrogen in an upper portion of the gate spacer and a second concentration of nitrogen in a lower portion of the gate spacer, wherein the second concentration is lower than the first concentration.

[0096] In one example, a structure comprises: a nanostructure; a gate structure enclosing the nanostructure; and a first pair of gate spacers adjacent to the gate structure, wherein the first pair of gate spacers are spaced apart by a first distance in a lower portion of the gate structure, the first pair of gate spacers are spaced apart by a second distance in an upper portion of the gate structure, the second distance being greater than the first distance.

[0097] In an example of the structure, the ratio of the second distance to the first distance is in a range of 1.1 to 11.

Claims

[1] Procedure comprising: Forming a dummy dielectric over a plurality of semiconductor layers (52, 54); forming a dummy gate (76) over the dummy dielectric; depositing a gate spacer (81, 83) adjacent to the dummy gate (76) and the dummy dielectric; recessing the dummy gate (76) to form a recess (86, 100, 106) exposing the gate spacer; implanting an impurity in a non-directional manner in a first region of the gate spacer (81, 83) to increase an etch rate of the first region of the gate spacer (81, 83), wherein a second region of the gate spacer remains unmodified by the implantation; Removing the dummy dielectric, the first region of the gate spacer, and remaining portions of the dummy gate (76) to expose the semiconductor layers (52, 54) in the recess (86, 100, 106); Structuring the semiconductor layers (52, 54) to form nanostructures (55, 55N, 55P); and Forming a gate structure (85) in the recess (86, 100, 106), wherein the gate structure (85) encloses the nanostructures (55, 55N, 55P) and the gate structure (85) contacts the second region of the gate spacer. [2] The method of claim 1, wherein implanting the impurity in the first region of the gate spacer comprises: Flowing a gas source containing an impurity source precursor gas and a carrier gas over the semiconductor layers (52, 54); Generating a plasma from the gas source, the plasma comprising impurity ions (102) and impurity radicals; and Accelerating the impurity ions (102) in the plasma towards the gate spacer in an undirected manner. [3] The method of claim 2, wherein the impurity is oxygen and the impurity source precursor gas contains oxygen gas. [4] The method of claim 2, wherein the impurity is nitrogen and the impurity source precursor gas comprises nitrogen gas. [5] A method according to any one of claims 2 to 4, wherein the plasma is generated at a temperature in a range of 20°C to 650°C, a pressure in a range of 0.67 Pa to 66.7 Pa (5 mTorr to 500 mTorr), and a radio frequency (RF) power in a range of 30 to 4000 watts, and wherein accelerating the impurity ions (102) comprises applying a direct current (DC) bias having a low voltage of zero and a high voltage of up to 100 kV. [6] A method according to any one of claims 2 to 4, wherein the plasma is generated at a temperature in a range of 20°C to 650°C, a pressure in a range of 0.67 Pa to 66.7 Pa (5 mTorr to 500 mTorr) and a radio frequency (RF) power in a range of 30 to 4000 watts, and wherein accelerating the impurity ions (102) comprises applying a radio frequency (RF) bias voltage having a low power of zero and a high power of up to 100 watts. [7] A method according to any one of claims 2 to 6, wherein the plasma has a plasma density in a range of 10 9 up to 10 12 has. [8] The method of any one of claims 1 to 7, wherein removing the dummy dielectric and the first portion of the gate spacer comprises: Performing an anisotropic dry etch in the recess (86, 100, 106), wherein the anisotropic dry etch etches the dummy dielectric and the first region of the gate spacer at a higher rate than the second region of the gate spacer. [9] The method of claim 8, wherein the impurity is oxygen, the gate spacer comprises silicon oxycarbonitride, the anisotropic dry etch is performed with nitrogen trifluoride, ammonia, or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer into the by-products of ammonium fluorosilicate, silicon tetrafluoride, or water. [10] The method of claim 8, wherein the impurity is nitrogen, the gate spacer comprises silicon oxycarbonitride, the anisotropic dry etch is performed with nitrogen trifluoride, ammonia or hydrogen fluoride, and the anisotropic dry etch converts the first region of the gate spacer into the by-products ammonium fluorosilicate or silicon tetrafluoride. [11] The method of any one of claims 1 to 10, wherein after removing the dummy dielectric, the first region of the gate spacer, and the remaining portions of the dummy gate (76), the recess (86, 100, 106) has an upper width and a lower width, the upper width being greater than the lower width, and a ratio of the upper width to the lower width being in a range of 1.1 to 11. [12] The method of any one of claims 1 to 11, wherein recessing the dummy gate (76) comprises performing a first anisotropic dry etching process with methane at a first bias voltage, and wherein removing the remaining portions of the dummy gate (76) comprises performing a second anisotropic dry etching process with methane at a second bias voltage, the second bias voltage being different from the first bias voltage.

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