Manufacturing method for a semiconductor device

Abstract

A method of manufacturing a semiconductor device comprising the following steps: forming a first layer (307) over a raised semiconductor region (302); Applying a lower anti-reflective layer (309) over the first layer (307), the lower anti-reflective layer (309) having a first diffusivity for a first chemical; Structuring the lower anti-reflection layer (309); after patterning the lower anti-reflective layer (309), reducing the first diffusivity to a second diffusivity for the first chemical, wherein reducing the first diffusivity to a second diffusivity comprises applying either isopropyl alcohol or hexamethyldisilazane to the lower anti-reflective layer (309); and Removing a portion of the first layer (307) using the first chemical (503) while the lower anti-reflective layer (309) is present.

Description

background

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers over a semiconductor substrate. The various material layers are patterned by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is continually improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, allowing more components to be integrated into a given area. However, reducing the smallest feature size creates additional problems that need to be addressed.

[0003] Document US 2012 / 0 305 525 A1 discloses a method for reducing streaking on a sidewall of a recess, the method comprising treating a patterned photoresist layer with a repair gas selected from the group consisting of CF4, HBr, O2, and He. Document US 2004 / 0 202 964 A1 discloses a method for improving adhesion between a photoresist and an underlying oxynitride layer, wherein a surface treatment is performed on the oxynitride layer using a developing solution to repair the damaged oxynitride layer. Document US 2017 / 0 062 349 A1 discloses a semiconductor structure comprising a wafer and an alignment mark. The wafer has a dicing region comprising a central region, a middle region surrounding the central region, and a peripheral region surrounding the middle region.The alignment mark is arranged in the dicing region, wherein the alignment mark has a mirror-symmetric pattern. US 2015 / 0 017 808 A1 discloses a method for forming a micropattern of a semiconductor device, wherein a photoresist is treated to expose a space containing an insoluble polymer film used to remove a film containing an acid quencher. Short description of the drawings

[0004] Aspects of the present invention can best be understood from the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of various elements may be exaggerated or reduced as desired. Fig. 1 shows a perspective view of the fabrication of semiconductor fins according to some embodiments. Fig. 2 shows the fabrication of source / drain regions according to some embodiments. Fig. 3 shows the fabrication of a bottom anti-reflective layer and a photoresist according to some embodiments. Fig. 4 shows the removal of the photoresist according to some embodiments. Fig. 5 shows a treatment of the bottom anti-reflective layer according to some embodiments. Fig. 6 shows a first removal process according to some embodiments. Fig. 7 shows a second removal process according to some embodiments. Fig. 8 shows the removal of the bottom anti-reflective layer according to some embodiments. Fig. 9 shows the deposition of a filler material according to some embodiments. Fig. 10 shows the manufacture of a cap according to some embodiments. Fig. 11 shows the fabrication of a protective layer according to some embodiments. Fig. 12 shows a first removal process with the protective layer according to some embodiments. Fig. 13 shows a second removal process with the protective layer according to some embodiments. Detailed description

[0005] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to facilitate the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and may also include embodiments in which additional elements may be fabricated between the first and second elements such that the first and second elements are not in direct contact. Furthermore, in the present invention, reference numerals and / or letters may be repeated in the various examples.This repetition is for simplicity and clarity and does not, in itself, prescribe any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein to conveniently describe the relationship of one element or structure to one or more other elements or structures illustrated in the figures. The spatially relative terms are intended to encompass other orientations of the device in use or operation, in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in another orientation), and the spatially relative descriptors used herein may be interpreted accordingly.

[0007] Embodiments are described below using specific examples including bubble-avoiding FinFET manufacturing processes and semiconductor devices fabricated with a reduced number of bubbles. However, the embodiments are not limited to the examples provided herein, and the concepts can be implemented in a wide range of embodiments.

[0008] Now let’s come to Fig. 1, which shows a perspective view of a semiconductor device 100, such as a FinFET device. In one embodiment, the semiconductor device 100 includes a substrate 101 and first trenches 103. The substrate 101 may be a silicon substrate, but other substrates, such as a silicon-on-insulator (SOI) substrate, a strained SOI substrate, and a silicon germanium-on-insulator substrate, may also be used. The substrate 101 may be a p-type semiconductor, but in other embodiments, it may be an n-type semiconductor.

[0009] The first trenches 103 may be created as a first step in the later production of first isolation regions 105. The first trenches 103 may be formed using a masking layer (in Fig. 1 not shown individually) using a suitable etching process. For example, the masking layer may be a hard mask comprising silicon nitride deposited using a process such as chemical vapor deposition (CVD), but other materials such as oxides, oxide nitrides, silicon carbide, combinations thereof, or the like, and other processes such as plasma-enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), or silicon oxide deposition followed by nitriding may also be used. After its formation, the masking layer may be patterned using a suitable photolithographic process to expose the parts of the substrate 101 that are to be removed to create the first trenches 103.

[0010] After a masking layer has been formed and patterned, the first trenches 103 are created in the substrate 101. The exposed substrate 101 may be removed using a suitable method such as reactive ion etching (RIE) to create the first trenches 103 in the substrate 101, but any suitable method may be used. In one embodiment, the first trenches 103 may be created with a first depth of less than about 500 nm, e.g., about 250, from the surface of the substrate 101.

[0011] However, as one of ordinary skill in the art will appreciate, the method described above for creating the first trenches 103 is merely one possible method and is not intended to be the only embodiment. Rather, any suitable method capable of creating the first trenches 103 may be used, and any suitable method including any number of masking and removal processes may be used.

[0012] In the masking and etching process, not only are the first trenches 103 created, but fins 107 are also formed from the portions of the substrate 101 that are not removed. For simplicity, the fins 107 are depicted in the figures as fins separated from the substrate 101 by a dashed line, but a physical indication of the separation may or may not be present. These fins 107 may be used to fabricate a channel region of multi-gate FinFET transistors, as will be explained later. Fig. 1 only two fins 107 are shown which are made from the substrate 101, but any number of fins 107 can be used.

[0013] The fins 107 can be fabricated to have a width at the surface of the substrate 101 of about 5 nm to about 80 nm, e.g., about 30 nm. Furthermore, the fins 107 can be spaced apart by a distance of about 10 nm to about 100 nm, e.g., about 50 nm. By spacing the fins 107 in this manner, the fins 107 can each form a separate channel region while still being close enough to share a common gate (as will be explained in more detail later).

[0014] After the first trenches 103 and the fins 107 have been formed, the first trenches 103 may be filled with a dielectric material, and the dielectric material may be recessed in the first trenches 103 to form the first isolation regions 105. The dielectric material may be an oxide material, a high-density plasma (HDP) oxide, or the like. After optionally cleaning and lining the first trenches 103, the dielectric material may be deposited by chemical vapor deposition (CVD) [e.g., with a high aspect ratio (HARP) process], high-density plasma chemical vapor deposition (HDP-CVD), or by another suitable fabrication method known in the art.

[0015] The first trenches 103 may be filled by overfilling them and the substrate 101 with the dielectric material and then removing the excess material outside the first trenches 103 and the fins 107 using a suitable method such as chemical mechanical polishing (CMP), etching, a combination thereof, or the like. In one embodiment, the removal process also removes dielectric material located above the fins 107, so that the removal of the dielectric material exposes the surface of the fins 107 for further processing steps.

[0016] After the first trenches 103 have been filled with the dielectric material, the dielectric material may be recessed from the surface of the fins 107. The recessing may be performed such that at least a portion of the sidewalls of the fins 107 adjacent to the top surface of the fins 107 is exposed. The dielectric material may be recessed using a wet etch by dipping the top surface of the fins 107 into an etchant such as HF, but other etchants, such as H 2 , and other processes can be used, such as reactive ion etching, dry etching with etchants such as NH 3 / NF 3, chemical oxide removal, or chemical dry cleaning. The dielectric material may be recessed to a distance from the surface of the fins 107 of about 5 nm to about 50 nm, e.g., about 40 nm. Furthermore, the recessing may also remove any remaining dielectric material above the fins 107 to ensure that the fins 107 are exposed for further processing.

[0017] As one of ordinary skill in the art will appreciate, the steps described above are only a portion of the overall process flow used to fill and recess the dielectric material. For example, lining, cleaning, annealing, and gap filling steps, combinations thereof, and the like may also be used to create and fill the first trenches 103 with the dielectric material. All of these possible steps are intended to be fully within the scope of the present embodiment.

[0018] After the first isolation regions 105 have been formed, a dummy gate dielectric 109, a dummy gate electrode 111 over the dummy gate dielectric 109, and first spacers 113 may each be formed over the fins 107. In one embodiment, the dummy gate dielectric 109 may be formed by thermal oxidation, chemical vapor deposition, sputtering, or other methods known and used in the art for forming a gate dielectric. Depending on the method for forming the gate dielectric, the thickness of the dummy gate dielectric 109 on the fins 107 may be different from the thickness of the gate dielectric on the sidewalls of the fins 107.

[0019] The dummy gate dielectric 109 may be a material such as silicon dioxide or silicon oxynitride with a thickness of about 0.5 nm to about 10 nm, e.g., about 1 nm. The dummy gate dielectric 109 may be made of a material with a high dielectric constant (high-k material), e.g., having a relative permittivity of greater than about 5, such as lanthanum oxide (La 2 O 3 ), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), hafnium oxide nitride (HfON) or zirconium oxide (ZrO 2 ) or combinations thereof, with an equivalent oxide thickness of about 0.05 nm to about 10 nm, e.g., about 1 nm or less. Furthermore, a combination of silicon dioxide, silicon oxynitride, and / or high-k materials may also be used for the dummy gate dielectric 109.

[0020] The dummy gate electrode 111 may comprise a conductive or non-conductive material selected from the group consisting of polysilicon, W, Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, Ni, combinations thereof, or the like. The dummy gate electrode 111 may be deposited by chemical vapor deposition (CVD), sputter deposition, or other methods known and used in the art for depositing conductive materials. The thickness of the dummy gate electrode 111 may be about 0.5 nm to about 20 nm. The top surface of the dummy gate electrode 111 may be a non-planar top surface, which may be planarized prior to patterning the dummy gate electrode 111 or the gate etch. At this point, ions may or may not be introduced into the dummy gate electrode 111. Ions can be introduced, for example, using ion implantation techniques.

[0021] After their formation, the dummy gate dielectric 109 and the dummy gate electrode 111 can be patterned to produce a series of stacks 115 above the fins 107. The stacks 115 define a plurality of channel regions located on each side of the fins 107 beneath the dummy gate dielectric 109. The stacks 115 can be formed on the dummy gate electrode 111 by depositing and patterning a gate mask (in Fig. 1 not individually shown), for example, using deposition and photolithographic techniques known in the art. For the gate mask, commonly used masking and sacrificial materials, including silicon oxide, silicon oxynitride, SiCON, SiC, SiOC, and / or silicon nitride, may be used, and may be deposited to a thickness of about 0.5 nm to about 20 nm. The dummy gate electrode 111 and the dummy gate dielectric 109 may be etched using a dry etch process to produce patterned stacks 115.

[0022] After the stacks 115 have been patterned, the first spacers 113 can be fabricated. The first spacers 113 can be fabricated on opposite sides of the stacks 115. The first spacers 113 are typically formed by protective deposition of a spacer layer (in Fig. 1 not individually shown) on the previously fabricated structure. The spacer layer may comprise SIN, oxide nitride, SiC, SiON, SiOCN, SiOC, oxide, and the like, and may be formed using methods normally used to form such a layer, such as chemical vapor deposition (CVD), plasma-enhanced CVD, sputtering, and other methods known in the art. The spacer layer may comprise a different material with different etching properties than the dielectric material in the first isolation regions 105, or it may comprise the same material as the first isolation regions 105. The first spacers 113 may then be patterned, for example, with one or more etches to remove the spacer layer from the horizontal surfaces of the structure, thus creating the first spacers 113.

[0023] In one embodiment, the first spacers 113 may be fabricated with a thickness of about 0.5 nm to about 50 nm. Furthermore, after the first spacers 113 are fabricated, a first spacer 113 adjacent to one stack 115 may be separated by a first distance of about 5 nm to about 200 nm, e.g., about 20 nm, from a first spacer 113 adjacent to another stack 115. However, any suitable thicknesses and distances may be used.

[0024] Fig. 2 illustrates removal of fins 107 from the areas not protected by stacks 115 and first spacers 113 and regrowth of source / drain regions 201. Removal of fins 107 from the areas not protected by stacks 115 and first spacers 113 may be performed by reactive ion etching (RIE) using stacks 115 and first spacers 113 as hard masks or by another suitable removal technique. Removal may continue until fins 107 are either planar with the surface of first isolation regions 105 (as illustrated) or are below the surface of first isolation regions 105.

[0025] After these portions of the fins 107 have been removed, a hard mask (not individually shown) is placed and patterned to cover the dummy gate electrode 111 to prevent growth thereon, and the source / drain regions 201 may be regrown in contact with the individual fins 107. In one embodiment, the source / drain regions 201 may be regrown, and in some embodiments, they may be grown to create a stressor that imparts mechanical strain to the channel regions of the fins 107 located beneath the stacks 115. In an embodiment where the fins 107 comprise silicon and the FinFET is a p-type device, the source / drain regions 201 may be regrown using a selective epitaxial process with a material such as silicon, or alternatively, a material such as silicon germanium that has a different lattice constant than the channel regions.Precursors such as silane, dichlorosilane, monogermane, and the like can be used for the epitaxial growth process, and it can last from about 5 minutes to about 120 minutes, for example, about 30 minutes.

[0026] In one embodiment, the source / drain regions 201 may be fabricated to have a thickness of about 0.5 nm to about 100 nm and a height above the first isolation regions 105 of about 1 nm to about 50 nm, e.g., about 20 nm. In this embodiment, the source / drain regions 201 may be fabricated to have a height above the top of the first isolation regions 105 of about 5 nm to about 250 nm, e.g., about 100 nm. However, any suitable height may be used.

[0027] After the source / drain regions 201 have been formed, suitable dopants that complement dopants in the fins 107 may be implanted into the source / drain regions 201. For example, p-type dopants such as boron, gallium, indium, or the like may be implanted to form a PMOS device. Alternatively, n-type dopants such as phosphorus, arsenic, antimony, or the like may be implanted to form an NMOS device. These dopants may be implanted using the stacks 115 and the first spacers 113 as masks. One of ordinary skill in the art will appreciate that numerous other methods, steps, or the like may be used to implant the dopants.For example, one of ordinary skill in the art will recognize that a variety of implantation processes can be performed using various combinations of spacers and pads to create source / drain regions with a specific shape or with specific properties suitable for a particular purpose. Any of these processes can be used to implant the dopants, and the foregoing description is not intended to limit the present embodiments to the steps presented herein.

[0028] At this point, the hard mask that covered the dummy gate electrode 111 during the formation of the source / drain regions 201 is removed. In one embodiment, the hard mask may be removed, for example, using a wet or dry etching process that is selective for the hard mask material. However, any suitable removal method may be used.

[0029] Fig. 2 also shows a fabrication of an interlayer dielectric (ILD) layer 203 (which is shown in Fig. 2 with dashed lines to more clearly show the underlying structures) over the stacks 115 and the source / drain regions 201. The ILD layer 203 may comprise a material such as borophosphosilicate glass (BPSG), but any suitable dielectrics may be used. The ILD layer 203 may be formed using a process such as PECVD, but alternatively, other processes such as LPCVD may be used. The ILD layer 203 may be formed to a thickness of about 10 nm to about 300 nm. After its formation, the ILD layer 203 may be planarized with the first spacers 113, e.g., using a planarization process such as CMP, but any suitable process may be used.

[0030] Fig. 3 shows a sectional view of Fig. 2 along a line 3 - 3' to illustrate removing and replacing the material of the dummy gate electrode 111 and the dummy gate dielectric 109 having a plurality of layers by a first gate stack 1002 (which is shown in Fig. 3 is not shown, but later in Fig. 10 and described with reference thereto). In Fig. 3, not only the first gate stack 1002 is shown in a first region 302 of the substrate 101, but also a second region 304 (for a second gate stack 1004) of the substrate 101 is shown, wherein the second region 304 may be directly adjacent to the first region 302 or otherwise separated by a distance (which is shown in Fig. 4 by a dashed line) may be separated from the first region 302. In one embodiment, the first gate stack 1002 may be a gate stack for a first transistor (e.g., an NMOS FinFET transistor), while the second gate stack 1004 may be for a second transistor (e.g., a first PMOS FinFET transistor). However, any suitable devices may be used.

[0031] In one embodiment, the dummy gate electrode 111 and the dummy gate dielectric 109 may be removed, for example, using one or more wet or dry etching processes that use etchants that are selective for the material of the dummy gate electrode 111 and the dummy gate dielectric 109. However, any suitable removal processes may be used.

[0032] After the dummy gate electrode 111 and the dummy gate dielectric 109 have been removed, a process for forming the first gate stack 1002 and the second gate stack 1004 may begin by depositing a series of layers. In one embodiment, the series of layers may include an optional interface layer (not individually shown), a first dielectric material 301, an optional first n-metal work function layer 303, and a first p-metal work function layer 305.

[0033] The optional interface layer may be formed prior to the deposition of the first dielectric material 301. In one embodiment, the interface layer may be a material such as silicon dioxide formed using a method such as in-situ vapor generation (ISSG). In another embodiment, the interface layer may be a high-k material such as HfO 2 , HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO or Ta2 O 5 or a combination thereof, or the like, deposited to a thickness of about 0.5 nm to about 2 nm, e.g., about 1 nm. However, any suitable material or method may be used.

[0034] After the interface layer has been formed, the first dielectric material 301 over the interface layer can be removed. In one embodiment, the first dielectric material 301 is a high-k material such as HfO 2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, LaO, ZrO or Ta 2 O 5 or a combination thereof, or the like, deposited using a method such as atomic layer deposition, chemical vapor deposition, or the like. The first dielectric material 301 may be deposited to a thickness of about 0.5 nm to about 20 nm, e.g., about 1.2 nm, but any suitable material and thickness may be used.

[0035] The first n-metal work function layer 303 may be formed over the first dielectric material 301. In one embodiment, the first n-metal work function layer 303 may be a material such as W, Cu, AlCu, TiAlC, TiAlN, Ti, TiN, Ta, TaN, Co, Ni, Ag, Al, TaAl, TaAlC, TaC, TaCN, TaSiN, Mn, Zr, another suitable n-type work function material, or a combination thereof. The first n-metal work function layer 303 may be deposited, for example, by ALD, CVD, or the like, to a thickness of about 0.5 nm to about 500 nm, e.g., about 3 nm. However, any suitable materials and methods for forming the first n-metal work function layer 303 may be used.

[0036] The first p-metal work function layer 305 may be formed over the first n-metal work function layer 303 (if present) or over the first dielectric material 301 (if the first n-metal work function layer 303 is not present). In one embodiment, the first p-metal work function layer 305 may be formed from a metallic material such as LaO, TiN, Ti, TiAlN, TaC, TaCN, TaSiN, TaSi 2 , NiSi 2 , Mn, Zr, ZrSi 2 , TaN, Ru, Al, Mo, MoSi 2, WN, other metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxide nitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, a combination thereof, or the like. Furthermore, the first p-type metal work function layer 305 may be deposited using a deposition method such as atomic layer deposition, chemical vapor deposition, sputtering, or the like to a thickness of about 0.08 nm to about 1 nm, e.g., about 0.12 nm, but any suitable deposition method or thickness may be used.

[0037] Fig. 3 also shows the formation of a hard mask layer 307, as well as placement and patterning of a lower anti-reflective layer 309 over the first region 302. In one embodiment, the hard mask layer 307 may be a masking material such as aluminum oxide, but any suitable masking material, such as titanium nitride (TiN), tungsten carbide (WC), or silicon (Si), a combination thereof, or the like, may be used. The hard mask layer 307 may be formed using a deposition technique such as atomic layer deposition, chemical vapor deposition, sputtering, or the like, with a thickness of about 0.5 nm to about 10 nm, e.g., about 2 nm. However, any suitable materials, manufacturing techniques, and thicknesses may be used.

[0038] In one embodiment, the lower anti-reflection layer 309 has different optical properties than a later-placed photoresist 313, and functions to prevent uncontrolled and unwanted reflection of energy (e.g., light) back into the overlying photoresist 313 during exposure of the photoresist 313, thereby preventing reflected light from causing reactions in an undesirable area of ​​the photoresist 313. For example, the lower anti-reflection layer 309 may have a different refractive index (n), extinction coefficient (k), or thickness (T) than the photoresist 313. Additionally, the lower anti-reflection layer 309 may be used to provide a planar surface, which helps reduce the negative effects of energy incident at an angle.

[0039] In one embodiment, the material used to form the lower anti-reflective coating 309 comprises a polymer resin, a catalyst, and a crosslinking agent, all of which are added to a BARC (lower anti-reflective coating) solvent for dispersion. The polymer resin may comprise a polymer in which various monomers, along with a chromophoric group, are linked together by the crosslinking agent. In a specific embodiment, the crosslinking monomer may comprise a hydrocarbon chain, which in turn may comprise, for example, a hydroxyl group, a carboxylic acid group, a carboxylic ester group, epoxy groups, urethane groups, or amide groups, or a combination thereof, or the like.Additionally, the crosslinking agent may include a melamine-based agent, a urea-based agent, an ethyleneurea-based agent, a propyleneurea-based agent, a glycoluril-based agent, an aliphatic cyclic hydrocarbon having a hydroxyl group, a hydroxyalkyl group, or a combination thereof, oxygen-containing derivatives of aliphatic cyclic hydrocarbons, glycoluril compounds, etherified amino resins, a polyether polyol, a polyglycidyl ether, a vinyl ether, a triazine, a combination thereof, or the like. However, any suitable monomers, polymers, and crosslinking agents may be used.

[0040] The material for the lower anti-reflective layer 309 may be applied to cover an upper exposed surface and may be applied using a method such as spin coating, dip coating, air knife coating, curtain coating, wire bar coating, gravure coating, lamination, extruder coating, a combination thereof, or the like. In one embodiment, the material for the lower anti-reflective layer 309 may initially be applied to a thickness of about 10 nm to about 1000 nm, e.g., about 100 nm. Once the material for the lower anti-reflective layer 309 is in place, it may be heat-dried to drive off the BARC solvent and react the crosslinking agents to crosslink the polymers together, forming the lower anti-reflective layer 309.

[0041] After the lower anti-reflective layer 309 has been placed, the material of the lower anti-reflective layer 309 may have physical properties that may cause certain defects to occur during further processing. For example, in some embodiments, the deposited lower anti-reflective layer 309 may have a diffusivity (i.e., the rate at which a chemical can diffuse through the material of the anti-reflective layer 309) that may allow materials from later-applied chemicals, such as a first wet etchant 601 (described later with reference to Fig. 6 is described in more detail), after a certain exposure time, to diffuse through the lower anti-reflection layer 309 and to react with the layers below.

[0042] Fig. 3 also shows patterning the lower anti-reflective layer 309 using a middle layer 311 and the photoresist 313. In one embodiment, the middle layer 311 may be an organic or inorganic layer having a different etch resistance than the photoresist 313. In a specific embodiment, the middle layer 311 is a hard mask material, such as a low-temperature oxide, aluminum oxide, silicon, silicon nitride, another oxide, an oxide nitride, silicon carbide, a combination thereof, or the like. The hard mask material for the middle layer 311 may be deposited using a process such as CVD, but other processes such as PECVD, LPCVD, spin coating, or even silicon oxide fabrication followed by nitriding may also be used.Any suitable method or combination of methods may be used to fabricate or otherwise place the material for the middle layer 311, and all such methods or combinations are intended to be fully within the scope of the embodiments. The middle layer 311 may be fabricated to a thickness of about 10 nm to about 80 nm, e.g., about 30 nm.

[0043] Photoresist 313 is placed over middle layer 311 to provide a patterned mask so that middle layer 311 can be patterned into the desired pattern. In one embodiment, photoresist 313 is a photosensitive material that is spread over middle layer 311 and then exposed to a patterned energy source (e.g., light) to trigger a chemical reaction in the portions of the photosensitive material that are exposed. This chemical reaction causes a change in physical properties that can be used in a development process to separate the exposed portion of the photosensitive material from the unexposed portion of the photosensitive material to create a patterned photoresist.

[0044] After the photoresist 313 has been patterned into the desired structure, it can be used as a mask for patterning the material of the middle layer 311. For example, the pattern of the photoresist 313 can be transferred to the middle layer 311 using an anisotropic etching process, such as a reactive ion etch (RIE), wherein ions of a suitable etchant, such as CF 4 -O 2 , can be used in a dry etch to remove parts of the middle layer 311 that are freed from the patterned photoresist 313. Alternatively, however, another suitable etchant, such as CHF 3 / O 2 , CH 2 F 2 , CH 3 F or the like, or another suitable method such as wet stripping may be used.

[0045] After the pattern of photoresist 313 has been transferred to middle layer 311, middle layer 311 can be used to transfer the pattern of photoresist 313 to lower anti-reflective layer 309 to expose hard mask layer 307 in second region 304. In one embodiment, lower anti-reflective layer 309 can be etched using an etching process in which photoresist 313 and middle layer 311 (now patterned) are used as a masking layer. The etching process can be a dry etching process using an etchant such as oxygen, nitrogen, hydrogen, ammonia, sulfur hexafluoride, difluoromethane, nitrogen trifluoride, chlorine trifluoride, chlorine, carbon monoxide, carbon dioxide, helium, boron dichloride, argon, fluorine, trifluoromethane, tetrafluoromethane, perfluorocyclobutane, perfluoropropane, a combination thereof, or the like.However, another suitable etching method, such as a wet etch or a wet etch performed simultaneously with the etching of the middle layer 311, may be used, and other suitable etchants may be used.

[0046] Fig. 4 shows that after patterning the lower anti-reflective layer 309, the photoresist 313 and the middle layer 311 may be removed. In one embodiment, the photoresist 313 may be removed, for example, using a stripping process that increases the temperature of the photoresist 313 to a point where the photoresist 313 is thermally decomposed, and then the decomposed photoresist 313 may be easily removed.

[0047] After the photoresist 313 has been removed, the middle layer 311 may also be removed. In one embodiment, the middle layer 311 may be removed using one or more etching processes, such as a wet or dry etching process. However, any suitable removal method may be used.

[0048] Fig. 5 shows a treatment process (which is Fig. 5 by the arrows labeled 501), which can be used to treat and protect the lower anti-reflection layer 309, reduce the diffusivity of etchants through the lower anti-reflection layer 309, and prevent unwanted penetration of later-used chemicals through the lower anti-reflection layer 309. In the Fig. 5, the treatment is a non-reactive physical treatment that does not chemically modify the structure of the lower anti-reflection layer 309 (further embodiments will be described later with reference to the Fig. 11 to 13). In a particular embodiment, the treatment process 501 may be a filling treatment in which pores (e.g., through capillary forces) and other openings in the lower anti-reflective layer 309 are filled, thereby preventing later-applied chemicals from penetrating these pores and other openings if the later-applied chemicals attempt to make their way through the lower anti-reflective layer 309.

[0049] In this embodiment, the treatment process 501 may be performed by applying a first treatment chemical (which is described in Fig. 5 by the symbols "X" labeled 503). In one embodiment, the first treatment chemical 503 may be a chemical having physical properties that allow it to penetrate into the pores of the lower anti-reflective layer 309. For example, in some embodiments, the first treatment chemical 503 may have a viscosity of less than 5 cp, e.g., from about 1 cp to about 3 cp, and may also have a surface tension of less than about 40 mN / m, e.g., from about 10 mN / m to about 30 mN / m. Furthermore, the first treatment chemical 503 may have a specific gravity of from about 0.7 to about 2, e.g., from about 0.79. Finally, the first treatment chemical 503 may have a water solubility of about 10 -1 g / ml to about 10 -4 g / ml and does not react chemically with chemicals applied later.

[0050] In a specific example, the first treatment chemical 503 may be a hydrocarbon, such as isopropyl alcohol (IPA), hexane, acetone, or benzene, a combination thereof, or the like. However, other suitable chemicals, such as other n-alkanes, other hydrocarbon alkanes, or the like, may also be used. Any suitable chemicals that can inhibit the migration of subsequently applied chemicals through the lower anti-reflective layer 309 may be used.

[0051] The treatment process 501 may be initiated by placing the first treatment chemical 503 in physical contact with the bottom anti-reflective layer 309. In one embodiment, the first treatment chemical 503 may be applied using a method such as spin coating, dip coating, air knife coating, curtain coating, wire bar coating, gravure coating, lamination, extruder coating, a combination thereof, or the like. However, any suitable method for applying the first treatment chemical 503 may be used.

[0052] The first treatment chemical 503 may be applied at a temperature of about 5°C to about 80°C, e.g., about 25°C. Furthermore, the treatment process 501 may be continued for a duration sufficient to fill the pores and openings in the lower anti-reflective layer 309, e.g., for a duration of about 30 s to about 240 s, e.g., about 120 s. However, any suitable durations and temperatures may be used.

[0053] During the treatment process 501, the first treatment chemical 503 enters the pores and other openings in the lower anti-reflective layer 309 and saturates the lower anti-reflective layer 309 by utilizing capillary forces. By filling and remaining in these pores and other openings, the first treatment chemical 503 slows or completely prevents the migration of subsequently applied chemicals through the lower anti-reflective layer 309 (discussed in more detail later). By slowing the migration of the subsequently applied chemicals, they are no longer able to reach the underlying hard mask layer 307.And by preventing the subsequently deposited chemicals from reaching the underlying hard mask layer 307, the subsequently deposited chemicals are no longer able to react with the underlying hard mask layer 307, preventing defects such as blistering from occurring. This allows for an extension of available cleaning times and an increase in the wet cleaning window for small process nodes (e.g., N5, N3, etc.) and smaller fin pitches.

[0054] Fig. 6 shows a removal of the hard mask layer 307 from the second region 304. In one embodiment, the hard mask layer 307 may be removed with a wet etching process using a wet etchant (which is described in Fig. 6 by the symbols X denoted by 601), which is selective for removing the material selected for the hard mask layer 307 (e.g., aluminum oxide). Therefore, in an embodiment in which the hard mask layer 307 is aluminum oxide, the removal of the hard mask layer 307 may be performed with a first wet etchant 601, such as ammonium hydroxide (NH 4 OH), phosphoric acid (H 3 PO 4 ), hydrogen peroxide, a combination thereof, or the like.

[0055] In a specific embodiment, the hard mask layer 307 may be removed using a dilute ammonium hydroxide solution. The wet etching solution may, for example, contain ammonium hydroxide and water in a ratio of 1:20. In another embodiment, the hard mask layer 307 may be removed using a mixture of ammonium hydroxide and hydrogen peroxide dissolved in a solvent such as water. The wet etching solution may, for example, contain 29% ammonium hydroxide and 31% hydrogen peroxide, with the remainder of the solution being water. However, any suitable etchants and etching solutions may be used.

[0056] In one embodiment, the wet etching process may be performed at a temperature sufficient to react the first wet etchant 601 with the material of the hard mask layer 307, such as at a temperature of about 5°C to about 70°C, e.g., about 25°C. Furthermore, the wet etching process may be performed for a duration of about 20 s to about 300 s, e.g., about 144 s. However, any suitable durations and temperatures may be used.

[0057] Because the first treatment chemical 503 is still present in the pores and openings of the lower anti-reflective layer 309, the diffusivity (i.e., the rate of diffusion through the lower anti-reflective layer 309) of the first wet etchant 601 can be reduced, and therefore, diffusion of the first wet etchant 601 into and / or through the lower anti-reflective layer 309 is reduced or even prevented. Therefore, the first wet etchant 601 does not penetrate the lower anti-reflective layer 309 as long as the wet etching process is performed for a period of time shorter than allowing the first wet etchant 601 to penetrate the lower anti-reflective layer 309, thereby preventing a reaction between the hard mask layer 307 and the first wet etchant 601. This can prevent defects resulting from such a reaction (e.g.,Bubble defects that are difficult to remove with stripping processes and that can lead to failure of wafer acceptance tests due to threshold breakdown voltage, failure to meet a target work function, etc.).

[0058] Fig. 7 illustrates removal of the first p-metal work function layer 305 from the second region 304. In one embodiment, the first p-metal work function layer 305 may be removed using one or more etching processes, such as a wet etching process or a dry etching process, that is selective for the material of the first p-metal work function layer 305 (e.g., lanthanum oxide). However, any suitable removal method may be used.

[0059] In one embodiment, the first p-metal work function layer 305 may be formed with a wet etching process using a second wet etchant (which is described in Fig. 7 by the symbols X labeled 701) that is selective for removing the material selected for the first p-metal work function layer 305 (e.g., lanthanum oxide). Therefore, in an embodiment where the p-metal work function layer 305 is lanthanum oxide, the removal of the first p-metal work function layer 305 may be performed with a second wet etchant 701, such as hydrochloric acid, phosphoric acid, hydrogen peroxide, a combination thereof, or the like.

[0060] In a specific embodiment, the first p-metal work function layer 305 may be removed using a mixture of hydrochloric acid and water. For example, in this embodiment, the mixture may contain hydrochloric acid and water in a ratio of 1:25. In another embodiment, the first p-metal work function layer 305 may be removed using a mixture of hydrochloric acid and hydrogen peroxide added to a solvent such as water. In this embodiment, the second wet etchant 701 may contain 37% hydrochloric acid and 31% hydrogen peroxide, with the remainder of the solution being water. However, any suitable etchants may be used.

[0061] In one embodiment, the wet etch process for removing the first p-metal work function layer 305 may be performed at a temperature sufficient to react the second wet etchant 701 with the material of the first p-metal work function layer 305, such as at a temperature of about 5°C to about 70°C, e.g., about 50°C. Furthermore, the wet etch process may be performed for a duration of about 20 s to about 280 s, e.g., about 154 s. However, any suitable durations and temperatures may be used.

[0062] Because the first treatment chemical 503 is still present in the pores and openings of the lower anti-reflective layer 309, diffusion of the second wet etchant 701 into and / or through the lower anti-reflective layer 309 is reduced or even prevented. Therefore, as long as the wet etching process is performed for a period shorter than a time period allowing the second wet etchant 701 to penetrate the lower anti-reflective layer 309, the second wet etchant 701 does not penetrate the lower anti-reflective layer 309, thereby preventing a reaction between the hard mask layer 307 and the second wet etchant 701. This can prevent defects resulting from such a reaction (e.g., bubble defects).

[0063] For example, if the first treatment chemical 503 is not present in the pores of the lower anti-reflective layer 309, the second wet etchant 701 (containing, for example, hydrochloric acid) can reach the surface of the hard mask layer 307 (for example, aluminum oxide). When the second wet etchant 701 actually reaches the surface, the reactions represented by the following equations 1 and 2 can occur: Al 2 O 3 + 3H 2 O → 2Al(OH) 3 Eq. 1, Al(OH) 3 + 3 HCl → AlCl 3 + 3H 2 O Eq. 2.

[0064] And since AlCl 3If the second wet etchant 701 is water-soluble, it acts to lift the overlying lower anti-reflective layer 309 and cause a bubble. However, if the first treatment chemical 503 is present, these reactions can be prevented by preventing the second wet etchant 701 from reaching the hard mask layer 307.

[0065] For example, in an embodiment where the second wet etchant 701 is applied for 210 s and the treatment process 501 is performed for 60 s, the number of bubble defects may be reduced from 182 (for a device for which the treatment process 501 was not performed) to 154. Furthermore, in embodiments where the second wet etchant 701 is applied for 154 s and the treatment process 501 is performed for either 30 s or 60 s, the number of bubble defects may be reduced from 216 (for a device for which the treatment process 501 was not performed) to 2 (for a treatment process 501 with a duration of 30 s) and even 0 (for a treatment process 501 with a duration of 60 s).

[0066] After the first p-type metal work function layer 305 has been removed, the structure may be cleaned, and subsequently, the bottom anti-reflection layer 309 may be removed. In one embodiment, the structure may be cleaned by applying the first wet etchant 601 for a short duration of about 5 s to about 120 s, e.g., about 10 s, and then rinsing the structure with a rinsing liquid, such as deionized water, for a duration of about 10 s to about 120 s, e.g., about 30 s. However, any suitable cleaning processes may be used at this stage.

[0067] While a method has been described above in which the treatment process 501 is performed prior to removing the hard mask layer 307, this is intended to be illustrative only and is not intended to limit the embodiments. Rather, the bottom anti-reflective layer 309 may be treated at any time in the process, helping to prevent unwanted diffusion of loose chemicals through the bottom anti-reflective layer 309. For example, in some embodiments, the middle layer 311 and the hard mask layer 307 may comprise the same material (e.g., aluminum oxide), and it would be beneficial to pattern the hard mask layer 307 in the same process step in which the middle layer 311 is removed.In this embodiment, the treatment process 501 may be performed only after the patterning of the hard mask layer 307 and before the patterning of the first p-type metal work function layer 305, since the middle layer 311 is still present to initially protect the bottom anti-reflection layer 309. The treatment process 501 may be integrated into the process at any time, and all of these times are intended to be fully within the scope of the embodiments.

[0068] While specific chemical etchants have been mentioned herein for removing and / or patterning the hard mask layer 307 and the first p-metal work function layer 305, the treatment process for the lower anti-reflective layer 309 to prevent blistering is not intended to be limited to the aforementioned loose chemicals. Rather, the treatment process for protecting underlying layers can be used for a wide range of loose chemicals that can be used to remove and / or pattern many different materials during the fabrication of semiconductor devices. For example, loose chemicals such as sulfuric acid (H 2 SO 4 ), phosphoric acid (H 3 PO 4 ), hydrochloric acid, hydrogen fluoride (HF), ammonium hydroxide, hydrogen peroxide (H 2 O 2), aluminum fluoride, ozone, combinations thereof, and the like are used to prepare a wide range of etchants and etching solutions. Processes employing these bulk chemicals are expected to benefit from the concepts presented herein, and the use of all such chemicals is intended to be fully within the scope of the embodiments.

[0069] Fig. 8 shows that after cleaning the structure, the lower anti-reflective layer 309 may be removed. In one embodiment, the lower anti-reflective layer 309 may be removed using an etching process or a stripping process. In one embodiment where the lower anti-reflective layer 309 is removed using a stripping process, a temperature of the lower anti-reflective layer 309 is increased until the lower anti-reflective layer 309 thermally decomposes, and it may then be removed. However, any other suitable method for removing the lower anti-reflective layer 309 may be used.

[0070] Fig. 9 shows that after removing the lower anti-reflective layer 309, an adhesive layer (not individually shown) and a filler material 901 may be formed. In one embodiment, the adhesive layer may be formed to assist in adhering the upper filler material 901 to the lower materials and to provide a nucleation layer for the formation of the filler material 901. In one embodiment, the adhesive layer may be a material such as titanium nitride, and it may be formed using a process similar to ALD with a thickness of about 1 nm to about 10 nm, e.g., about 5 nm. However, any suitable materials and processes may be used.

[0071] After the adhesive layer has been formed, the filler material 901 is deposited to fill a remainder of the opening with the adhesive layer. In one embodiment, the filler material 901 may be a material such as Al, Cu, AlCu, W, Ti, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, Ta, TaN, Co, or Ni, a combination thereof, or the like, and may be deposited using a deposition method such as plating, CVD, ALD, PVD, a combination thereof, or the like. Furthermore, the filler material 901 may be deposited to a thickness of about 100 nm to about 200 nm, e.g., about 150 nm. However, any suitable material may be used.

[0072] Fig. 10 shows that after depositing the filling material 901 to fill and overfill the opening, the materials in each of the openings of the first region 302 and the second region 304 may be planarized to form a first gate stack 1002 and a second gate stack 1004. In one embodiment, the materials may be connected to the first spacers 113 (see Fig. 1) can be planarized using a CMP process, for example, but any suitable method, such as grinding or etching, can be used.

[0073] After the materials of the first gate stack 1002 and the second gate stack 1004 have been deposited and planarized, these materials may be recessed and capped with a capping layer 1001. In one embodiment, the materials of the first gate stack 1002 and the second gate stack 1004 may be recessed, for example, using a wet or dry etch process that uses etchants selective for the materials of the first gate stack 1002 and the second gate stack 1004. In one embodiment, the materials of the first gate stack 1002 and the second gate stack 1004 may be recessed to a depth of about 5 nm to about 150 nm, e.g., about 120 nm. However, any suitable methods and depths may be used.

[0074] After the materials of the first gate stack 1002 and the second gate stack 1004 have been recessed, the capping layer 1001 may be deposited and planarized with the first spacers 113. In one embodiment, the capping layer 1001 is a material such as SiN, SiON, SiCON, SiC, or SiOC, a combination thereof, or the like, deposited using a deposition technique such as ALD, CVD, sputtering, or the like. The capping layer 1001 may be deposited to a thickness of about 0.5 nm to about 20 nm and may then be planarized using a planarization technique such as chemical mechanical polishing such that the capping layer 1001 is coplanar with the first spacers 113.

[0075] Fig. Figure 11 shows a further embodiment in which the treatment process 501, instead of simply filling pores to prevent diffusion, now creates a protective layer 1101 by contacting a portion of the lower anti-reflective layer 309 with a first reactant (which is Fig. 11 by the symbols X designated 1003). In one embodiment, the protective layer 1101 can be formed by incorporating the first reactant 1003 into the lower anti-reflective layer 309.

[0076] In one embodiment, the first reactant 1003 may be an organic reactant suitable for reacting with the material of the lower anti-reflective layer 309 and forming the protective layer 1101. Although the exact reactant used to form the protective layer 1101 depends at least in part on the material chosen for the lower anti-reflective layer 309, in some embodiments, the first reactant 1003 may be a material such as hexamethyldisilazane (HMDS), citric acid, or acetic acid, a combination thereof, or the like. However, any suitable material may be used.

[0077] In another specific embodiment, the first reactant 1003 may be an organic reactant suitable for forming a self-aligned monolayer (SAM) along a top surface of the bottom anti-reflective layer 309. In this embodiment, the first reactant 1003 reacts with the exposed end groups of the bottom anti-reflective layer 309 and forms a monolayer of the self-aligned monolayer with the outermost end groups of the bottom anti-reflective layer 309. In this embodiment, the first reactant 1003 may be an organic molecule having an OH or carboxylic acid group, such as R-OH, R-COOH, a combination thereof, or the like, where R represents a carbon chain with a suitable number of carbon atoms. However, any suitable reactant may be used.

[0078] In one embodiment, the first reactant 1003 may be introduced into the lower anti-reflective layer 309 using a wet or dry etching process, depending on the desired reactant. For example, in an embodiment where the first reactant 1003 is HMDS, the first reactant 1003 may be introduced in a liquid form using a method such as spin coating, dip coating, air knife coating, curtain coating, wire bar coating, gravure coating, lamination, extruder coating, a combination thereof, or the like. However, any suitable method may be used.

[0079] Furthermore, in an embodiment in which the first reactant 1003 is brought into contact with the lower anti-reflective layer 309 in a liquid form, the process may be performed at a temperature of about 5°C to about 80°C, e.g., about 25°C. Furthermore, the process may be performed for a duration of about 5 s to about 240 s, e.g., about 60 s. However, any suitable process conditions may be used.

[0080] After the first reactant 1003 is brought into contact with the lower anti-reflective layer 309, the first reactant 1003 diffuses into the lower anti-reflective layer 309 and also reacts with its material to form the protective layer 1101. In a specific embodiment where the first reactant 1003 is HMDS, the protective layer 1101 may be a reaction product of the first reactant 1003 and the material of the lower anti-reflective layer 309. However, any suitable material may be deposited for the protective layer 1101.

[0081] Furthermore, the protective layer 1101 can be formed to a depth and thickness sufficient to reduce or even prevent diffusion of later-applied chemicals. Therefore, in some embodiments, the protective layer 1101 can be formed to a thickness of about 0.5 nm to about 10 nm, e.g., about 1 nm, although the depth may depend at least in part on the materials and chemicals chosen for the lower anti-reflective layer 309. However, any suitable depths and thicknesses may be used.

[0082] Fig. 12 shows removal of the hard mask layer 307 from the second region 304 when the protective layer 1101 is in place. In one embodiment, the hard mask layer 307 may be removed as described above with reference to Fig. 6 (e.g., with a wet etching process using the first wet etchant 601, such as ammonium hydroxide). However, any suitable removal method may be used to remove the hard mask layer 307 from the second region 304.

[0083] Additionally, the protective layer 1101 present during the removal of the hard mask layer 307 helps reduce or prevent diffusion of the first wet etchant 601 into or through the lower anti-reflective layer 309. Therefore, the first wet etchant 601 is less likely to make its way through the lower anti-reflective layer 309 and come into physical contact with the underlying layers, and these chemicals are less likely to react with the underlying layers and cause defects.

[0084] Fig. 13 shows removal of the first p-metal work function layer 305 from the second region 304 when the protection layer 1101 is in place. In one embodiment, the first p-metal work function layer 305 may be removed as described above with reference to Fig. 7 (e.g., with a wet etching process using the second wet etchant 701, such as hydrochloric acid). However, any suitable removal method may be used to remove the first p-type metal work function layer 305 from the second region 304.

[0085] Additionally, the protective layer 1101 present during the removal of the first p-metal work function layer 305 helps reduce or prevent diffusion of the second wet etchant 701 into or through the lower anti-reflection layer 309. Therefore, the second wet etchant 701 is less likely to make its way through the lower anti-reflection layer 309 and come into physical contact with the underlying layers, and these chemicals are less likely to react with the underlying layers and cause defects.

[0086] After the first p-metal work function layer 305 has been removed from the second region 304, further processing can be carried out as described above with reference to the Fig.8 to 10. For example, the lower anti-reflective layer 309 (together with the protective layer 1101) may be removed using etching and / or stripping processes, the fill material 901 is deposited, and the capping layer 1001 is formed. However, any suitable processes may be performed sequentially.

[0087] By using the methods described herein, unwanted defects may be prevented during patterning of the hard mask layer 307 and / or during patterning of the first p-metal work function layer 305. In particular, by inhibiting or preventing the migration of etch chemicals through the lower anti-reflection layer 309, these chemicals are no longer able to react with the underlying layers and cause bubbles to appear. Therefore, the absence of bubbles may reduce overall damage, particularly as device sizes are reduced to ever smaller process nodes.

[0088] The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited in the dependent claims.

Claims

[1] A method of manufacturing a semiconductor device comprising the following steps: forming a first layer (307) over a raised semiconductor region (302); Applying a lower anti-reflective layer (309) over the first layer (307), the lower anti-reflective layer (309) having a first diffusivity for a first chemical; Structuring the lower anti-reflection layer (309); after patterning the lower anti-reflective layer (309), reducing the first diffusivity to a second diffusivity for the first chemical, wherein reducing the first diffusivity to a second diffusivity comprises applying either isopropyl alcohol or hexamethyldisilazane to the lower anti-reflective layer (309); and Removing a portion of the first layer (307) using the first chemical (503) while the lower anti-reflective layer (309) is present. [2] The method of claim 1, wherein reducing the first diffusivity is at least partially accomplished by a physical process. [3] The method of claim 2, wherein the physical process fills pores of the lower anti-reflection layer (309) with a second chemical. [4] The method of claim 3, wherein the second chemical comprises isopropyl alcohol. [5] Method according to one of the preceding claims, wherein the reduction of the first diffusivity is carried out at least partially by a chemical process. [6] The method of claim 5, wherein the chemical process causes a portion of the lower anti-reflection layer (309) to react with a first reactant. [7] The process of claim 6, wherein the first reactant is hexamethyldisilazane. [8] A method of manufacturing a semiconductor device comprising the following steps: Depositing a hard mask layer (307) over a work function layer (303, 305) over a semiconductor fin (107); depositing a lower anti-reflective layer (309) over the hard mask layer (307); Structuring the lower anti-reflection layer (309); Treating the lower anti-reflection layer (309) after patterning the lower anti-reflection layer (309), wherein treating the lower anti-reflection layer (309) reduces a diffusivity of a first etchant (503) through the lower anti-reflection layer (309), and wherein treating the lower anti-reflection layer (309) comprises applying either isopropyl alcohol or hexamethyldisilazane to the lower anti-reflection layer (309); and Removing a portion of the hard mask layer (307) with the first etchant while the lower anti-reflective layer (309) is present. [9] The method of claim 8, wherein the hard mask layer (307) comprises aluminum oxide. [10] The method of claim 8 or 9, wherein the work function layer (303, 305) comprises lanthanum oxide. [11] The method of any one of claims 8 to 10, wherein treating the lower anti-reflection layer (309) comprises a physical treatment. [12] The method of claim 11, wherein the physical treatment comprises applying the isopropyl alcohol to the lower anti-reflection layer (309). [13] The method of any one of claims 8 to 10, wherein treating the lower anti-reflection layer (309) comprises a chemical treatment. [14] Method according to claim 13, wherein the chemical treatment creates a protective layer at least partially in the lower anti-reflection layer (309). [15] A method of manufacturing a semiconductor device comprising the following steps: Depositing a layer of lanthanum oxide (305) over a semiconductor fin (107); Depositing a layer of aluminum oxide (307) over the layer of lanthanum oxide (305); Placing a lower anti-reflective layer (309) over the layer of aluminum oxide (307); Structuring the lower anti-reflection layer (309); Introducing a material into the lower anti-reflection layer (309) after patterning the lower anti-reflection layer (309), the material comprising isopropyl alcohol or hexamethyldisilazane; Etching a portion of the aluminum oxide layer (307) while the lower anti-reflection layer (309) is present; and Etching part of the lanthanum oxide layer (305) while the lower anti-reflection layer (309) is present. [16] The method of claim 15, wherein the etching of the portion of the layer of aluminum oxide (307) is carried out at least partially with ammonium hydroxide. [17] A method according to claim 15 or 16, wherein the etching of the part of the layer of lanthanum oxide (305) is carried out at least partially with hydrochloric acid. [18] A method according to any one of claims 15 to 17, wherein introducing the material adds the isopropyl alcohol. [19] The method of any one of claims 15 to 18, wherein introducing the material reacts the lower anti-reflection layer (309) with a first reactant. [20] The process of claim 19, wherein the first reactant is hexamethyldisilazane.

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