STRUCTURE AND PROCEDURES

Abstract

Structure, exhibiting: a gate stack (80) over a channel area (58) of a substrate (50); a source / drain area (70) adjacent to the canal area (58); a first interlayer dielectric layer (74), ILD layer, over the source / drain region (70); a silicide (96) between the first ILD layer (74) and the source / drain area (70), wherein the silicide (96) is in contact with a top surface of the source / drain area (70) and a bottom surface of the source / drain area (70) and extends into a subcut (94) between the source / drain area (70) and the overlying ILD layer (74); a first source / drain contact (102) with a first part and a second part, wherein the first part of the first source / drain contact (102) is located in the undercut (94) between the silicide (96) and the first ILD layer (74), the second part of the first source / drain contact (102) extends through the first ILD layer (74) and is in contact with the silicide (96); a gate spacer (66) that separates the source / drain region (70) from the gate stack (80); and a contact etch stop layer (72), CESL, extending along a side wall of the gate spacer (66), where: the structure further comprises a cavity between the CESL (72) and the source / drain region (70), wherein the cavity exposes surfaces of the gate spacer (66), the silicide (96) and the first source / drain contact (102); or the CESL (72) extends along the top surface of the source / drain region (70) and the structure further comprises a cavity between the first ILD layer (74) and the source / drain region (70), the cavity exposing surfaces of the CESL (72), the silicide (96) and the first source / drain contact (102).

Description

BACKGROUND

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically formed by successively depositing insulating or dielectric layers, conductive layers, and semiconductor layers of material over a semiconductor substrate, and structuring the various material layers using lithography to create circuit components and elements.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area. However, as the minimum feature sizes decrease, additional problems arise that need to be addressed. Source / drain contacts for semiconductor devices and methods for their manufacture are known, for example, from US 2019 / 0 097 051 A1, DE 10 2014 100 397 A1, US 2017 / 0 222 008 A1, US 2020 / 0 044 025 A1, US 2016 / 0 359 012 A1, US 9 443 769 B2, DE 10 2019 121 750 A1 and US 2017 / 0 110 578 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates an example of a FinFET in a three-dimensional view according to some embodiments. Fig. 2 and Fig. Figure 3 shows three-dimensional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 4A, Fig. 4B, Fig. 5A, Fig. 5B, Fig. 6A, Fig. 6B, Fig. 7A, Fig. 7B, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, and Fig. Figure 14B shows cross-sectional views of further intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 15A and Fig. Figure 15B shows cross-sectional views of FinFETs according to some other embodiments. Fig. 16A and Fig. Figure 16B shows cross-sectional views of FinFETs according to some other embodiments. Fig. 17A and Fig. Figure 17B shows cross-sectional views of FinFETs according to some other embodiments. Fig. 18A and Fig. Figure 18B shows cross-sectional views of FinFETs according to some other embodiments. Fig. 19A and Fig. Figure 19B shows cross-sectional views of FinFETs according to some other embodiments. Fig. 20A and Fig. Figure 20B shows cross-sectional views of FinFETs according to some other embodiments. Fig. 21A and Fig. Figure 21B shows cross-sectional views of FinFETs according to some other embodiments. DETAILED DESCRIPTION

[0004] The present invention provides structures with the features of claim 1 and 4, as well as a method with the features of claim 7. Exemplary embodiments are given in the dependent claims. The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements are not in direct contact.Additionally, this disclosure may repeat reference numbers and / or letters in the various examples. This repetition serves the purpose of simplicity and clarity and does not itself establish any relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, spatial terms such as "below," "under," "lower," "above," "upper," and the like can be used here for simple description to convey the relationship of one element or feature to one or more other elements or features depicted in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used here can be interpreted accordingly.

[0006] In some embodiments, undercuts are formed in a contact etch stop layer (CESL), with the undercuts being located between source / drain regions and an overlying interlayer dielectric layer (ILD layer(s)). Forming the undercuts exposes surfaces of the source / drain regions, thus allowing silicides and contacts for the source / drain regions to come into contact with a larger surface area of ​​the source / drain regions. The contact resistance to the source / drain regions can therefore be reduced, thereby improving the performance of the resulting transistors.

[0007] Fig. Figure 1 illustrates a simplified three-dimensional view of Fin field-effect transistors (FinFETs) according to some embodiments. Some other features of the FinFETs (discussed below) have been omitted for clarity. The illustrated FinFETs can be electrically coupled in such a way that they function, for example, as one transistor or as multiple transistors, such as four transistors.

[0008] The FinFETs have fins 52 extending from a substrate 50. Shallow trench isolation regions (STI regions) 56 are arranged above the substrate 50, and the fins 52 project above and between adjacent STI regions 56. Although the STI regions 56 are described / illustrated as separate from the substrate 50, as used here, the term "substrate" can refer to just the semiconductor substrate or to a semiconductor substrate with isolation regions. Additionally, although the fins 52 are illustrated as a single, continuous material of the substrate 50, the fins 52 and / or the substrate 50 can consist of a single material or multiple materials. In this context, the fins 52 refer to the portions that extend between adjacent STI regions 56.

[0009] Gate structures 80 are located over channel regions of the fins 52. The gate structures 80 have gate dielectrics 82 and gate electrodes 84. The gate dielectrics 82 are located along side walls and over top surfaces of the fins 52, and the gate electrodes 84 are located over the gate dielectrics 82. Source / drain regions 70 are arranged on opposite sides of the fins 52 with respect to the gate dielectrics 82 and gate electrodes 84. Gate spacers 66 separate the source / drain regions 70 from the gate structures 80. In embodiments where multiple transistors are formed, different transistors can share the source / drain regions 70. In embodiments where a transistor is formed from several fins 52, adjacent source / drain regions 70 can be electrically coupled, such as by coalescing the source / drain regions 70 through epitaxial growth or by coupling the source / drain regions 70 with a common source / drain contact.One or more interlayer dielectric layer(s) (ILD layer(s)) (discussed in more detail below) are located over the source / drain regions 70 and / or gate electrodes 84, through which contacts (discussed in more detail below) to the source / drain regions 70 and the gate electrodes 84 are formed.

[0010] Fig. Figure 1 further illustrates several reference cross-sections. Cross-section AA is located along a longitudinal axis of a fin 52 and in a direction of, for example, current flow between the source / drain regions 70 of a FinFET. Cross-section BB is perpendicular to cross-section AA and extends through source / drain regions 70 of the FinFETs. Subsequent figures refer to these reference cross-sections for clarity.

[0011] Some embodiments discussed here are related to FinFETs formed using a gate-last process. Other embodiments may employ a gate-first process. Similarly, some embodiments consider aspects used in planar devices, such as planar FETs.

[0012] Fig. 2 and Fig. Figure 3 shows three-dimensional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 2 and Fig. 3 show a similar view to Fig. 1, except that three gate structures are shown.

[0013] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may be silicon; germanium; a compound semiconductor comprising silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor comprising silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0014] The substrate 50 has a region 50N and a region 50P. Region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-FinFETs. Region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. Region 50N can be physically separated from region 50P, and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between region 50N and region 50P.

[0015] Fins 52 are formed extending from the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be formed in the substrate 50 by etching grooves in the substrate 50. The etching can be any acceptable etching process, such as reactive ion etching (RIE) or the like. The etching can be anisotropic.

[0016] The fins can be structured by any suitable method. For example, the fins can be structured using one or more photolithography processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller pitches than those obtainable using a single direct photolithography process. For instance, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers can be used to structure the fins.In some embodiments, the spacers (or another mask) can remain on the fins 52.

[0017] STI regions 56 are formed above the substrate 50 and between adjacent fins 52. As an example of the formation of the STI regions 56, an insulating material is formed above the intermediate structure. The insulating material can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., chemical vapor deposition (CVD)-based material deposition in a remote plasma system followed by post-curing to transform into another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by an acceptable process can be used. In the illustrated embodiment, the insulating material is silicon dioxide formed by an FCVD process.An annealing process can be carried out once the insulating material has formed. In one embodiment, the insulating material is formed such that excess insulating material covers the fins 52. Although the STI areas 56 are illustrated as being layered individually, some embodiments can use multiple layers. For example, in some embodiments, a lining can first be formed along a surface of the substrate 50 and the fins 52. Subsequently, a filler material, such as those discussed above, can be formed over the lining. A removal process is applied to the insulating material to remove excess insulating material covering the fins 52. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, can be used.The planarization process exposes the fins 52, so that the cover surfaces of the fins 52 and the insulating material are coplanar after completion of the planarization process. In embodiments where a mask remains on the fins 52, the planarization process can expose or remove the mask, so that the cover surfaces of the mask or the fins 52 and the insulating material are coplanar after completion of the planarization process. The insulating material is then recessed, with the remaining portions of the insulating material forming the STI regions 56. The insulating material is recessed such that upper portions of the fins 52 protrude in region 50N and in region 50P between adjacent STI regions 56. The exposed portions of the fins 52 exhibit what become channel regions of the resulting FinFETs.

[0018] Furthermore, the cover surfaces of the STI regions 56 can have a flat surface, as illustrated, a convex surface, a concave surface (as in dishing), or a combination thereof. The cover surfaces of the STI regions 56 can be formed flat, convex, and / or concave by suitable etching. The STI regions 56 can be deepened using an acceptable etching process, such as one that is selective for the insulating material (e.g., etching the insulating material at a faster rate than the fin material 52). For example, oxide removal using, say, dilute hydrofluoric acid (dHF acid) can be employed.

[0019] The process described above is just one example of how the fins 52 can be formed. In some embodiments, the fins 52 can be formed by an epitaxial growth process. For example, a dielectric layer can be formed over a surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be allowed to grow epitaxially in the trenches, and the dielectric layer can be deepened so that the homoepitaxial structures protrude from the dielectric layer to form the fins 52. Additionally, in some embodiments, heteroepitaxial structures can be used for the fins 52.For example, after the insulating material of the STI regions 56 has been planarized with the fins 52, the fins 52 can be recessed, and a material different from that of the fins 52 can be epitaxially grown over the recessed fins 52. In such embodiments, the fins 52 comprise both the recessed material and the epitaxially grown material located above the recessed material. In a further embodiment, a dielectric layer can be formed over a surface of the substrate 50, and grooves can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the grooves using a material different from that of the substrate 50, and the dielectric layer can be recessed so that the heteroepitaxial structures project from the dielectric layer to form the fins 52.In some embodiments where homoepitactic or heteroepitactic structures are grown epitaxially, the epitaxially grown materials may be doped in situ during growth, which may prevent prior and subsequent implantations, although in situ and implantation doping can be used together.

[0020] Furthermore, it can be advantageous to epitaxially grow a material in region 50N (e.g., an NMOS region) that differs from the material in region 50P (e.g., a PMOS region). In various embodiments, upper parts of the fins 52 can be made of silicon-germanium (Si₂). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, the materials available for forming III-V compound semiconductors include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0021] Furthermore, suitable wells can be formed in the fins 52 and / or the substrate 50. In some embodiments, a P-well can be formed in region 50N and an N-well can be formed in region 50P. In some embodiments, a P-well or an N-well is formed in both region 50N and region 50P.

[0022] In embodiments with different well types, the various implantation steps for region 50N and region 50P can be achieved using a photoresist or other masks. For example, a photoresist can be formed over the fins 52 and the STI regions 56 in region 50N. The photoresist is patterned to expose region 50P of the substrate 50, similar to a PMOS region. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-impurity implantation is performed in region 50P, and the photoresist can act as a mask to essentially prevent n-impurities from being implanted into region 50N, similar to an NMOS region. The n-impurities can be phosphorus, arsenic, antimony, or the like, and can be present in the region at a concentration of 10 or less. 18cm -3 , as in the range of about 10 16 cm -3 up to about 10 18 cm -3 , are implanted. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0023] Following implantation of region 50P, a photoresist is formed over the fins 52 and the STI regions 56 within region 50P. The photoresist is patterned to expose region 50N of substrate 50, such as the NMOS region. The photoresist can be formed using a spin-on technique and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-impurity implantation can be performed in region 50N, and the photoresist can act as a mask to essentially prevent p-impurities from being implanted into region 50P, such as a PMOS region. The p-impurities can be boron, boron fluoride, indium, or the like, and can be present in the region at a concentration of 10⁻⁵ or less. 18 cm -3 , as in the range of about 10 16 cm -3 up to about 10 18 cm -3, are implanted. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0024] Following implantation of region 50N and region 50P, annealing can be performed to repair implant damage and activate the implanted p- and / or n-impurities. In some embodiments, the grown materials of epitaxial fins can be doped in situ during growth, which may eliminate the need for implantation, although in situ and implantation doping can be used together.

[0025] In Fig. 3. Dummy dielectrics 60 are formed over the fins 52, and dummy gates 62 are formed over the dummy dielectrics 60. The dummy dielectrics 60 and dummy gates 62 can be collectively referred to as a "dummy gate stack", each dummy gate stack comprising one dummy dielectric 60 and one dummy gate 62. The dummy gate stacks extend along the sidewalls of the fins 52.

[0026] As an example of the formation of dummy dielectrics 60 and dummy gates 62, a dummy dielectric layer is formed on the fins 52. The dummy dielectric layer can be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown according to acceptable techniques. A dummy gate layer is formed over the dummy dielectric layer, and a mask layer is formed over the dummy gate layer. The dummy gate layer can be deposited over the dummy dielectric layer and then planarized, as by CMP. The mask layer can be deposited over the dummy gate layer.The dummy gate layer can be a conductive or non-conductive material and can be selected from a group comprising amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer can be deposited by physical vapor deposition (PVD), continuous vapor deposition (CVD), sputtering, or other techniques known in the art and used to deposit the selected material. The dummy gate layer can be made of other materials that exhibit high etch selectivity when etching the STI regions 56. The mask layer can, for example, comprise silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer and a single mask layer are formed over region 50N and region 50P.The mask layer is then structured using acceptable photolithography and etching techniques to form masks 64. The structure of the masks 64 is then transferred to the dummy gate layer by an acceptable etching technique to form the dummy gates 62. The structure of the masks 64 can optionally be further transferred to the dummy dielectric layer to form the dummy dielectrics 60. The dummy gates 62 each cover channel regions 58 of the fins 52. The structure of the masks 64 can be used to physically separate each of the dummy gates 62 from adjacent dummy gates. The dummy gates 62 can also have a longitudinal direction that is substantially perpendicular (within process constraints) to the longitudinal direction of corresponding fins 52. Although the dummy dielectrics 60 cover the STI areas 56 in the illustration, it should be clear that the dummy dielectrics 60 can be formed in other ways.In some embodiments, such as when the dummy dielectric layer is thermally grown, the dummy dielectrics 60 are formed in such a way that they only cover the fins 52.

[0027] Fig. Figures 4A through 14B are cross-sectional views of further intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A and Fig. 14A are cross-sectional views, illustrated along reference cross-section AA in Fig. 1, except that three gate structures are shown. Fig. 4B, Fig. 5B, Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B and Fig. Figure 14B shows cross-sectional views, illustrated along reference cross-section BB in Fig. 1, except that only two Finns are depicted. Fig. Figures 4A to 14B illustrate features in area 50N and area 50P. For example, structures that are in Fig. Figures 4A to 14B are illustrated and applicable to both region 50N and region 50P. Any differences (if any) in the structures of region 50N and region 50P are described here.

[0028] In Fig. 4A and Fig. 4B Gate spacers 66 are formed on exposed surfaces of the dummy gates 62, the masks 64, and / or the fins 52. The gate spacers 66 can be formed by forming an insulating material and subsequently etching the insulating material. The insulating material of the gate spacers 66 can be silicon nitride, silicon carbonitride, silicon oxycarbonitride, a combination thereof, or the like, and can be formed by heat oxidation, deposition, a combination thereof, or the like. In some embodiments, the gate spacers 66 are formed from a multilayer insulating material and have several layers. For example, the gate spacers 66 can have several layers of silicon carbonitride, several layers of silicon oxycarbonitride, or a layer of silicon oxide arranged between two layers of silicon nitride. The etching of the gate spacers 66 can be anisotropic.After etching, the gate spacers can have 66 straight side walls or curved side walls.

[0029] Before or during the formation of the gate spacers 66, implantations for lightly doped source / drain (LDD) regions (not explicitly illustrated) can be performed. In embodiments with various device types, similar to the implants discussed, a mask, such as a photoresist, can be formed over region 50N while exposing region 50P, and a suitable type (e.g., p-type) of impurities can be implanted into the exposed fins 52 in region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over region 50P while exposing region 50N, and a suitable type (e.g., n-type) can be implanted into the exposed fins 52 in region 50N. The mask can then be removed. The n-type impurities can be any of the previously discussed n-type impurities, and the p-type impurities can be any of the previously discussed p-type impurities.The lightly doped source / drain areas can have a concentration of impurities of about 10. 15 cm -3 up to about 10 19 cm -3 Tempering can be used to repair implant damage and to activate implanted impurities.

[0030] Epitaxial source / drain regions 70 are then formed in the fins 52. These regions are positioned such that each dummy gate 62 is located between corresponding adjacent pairs of epitaxial source / drain regions 70. In some embodiments, the epitaxial source / drain regions 70 may extend into portions of the fins 52 below the top surfaces of the STI regions 56. In some embodiments, gate spacers 66 are used to separate the epitaxial source / drain regions 70 from the dummy gates 62 by an appropriate lateral distance, ensuring that the epitaxial source / drain regions 70 do not short-circuit the subsequently formed gates of the resulting FinFETs. The epitaxial source / drain areas 70 can exert tension in the channel areas 58 of the fins 52, thereby improving performance.

[0031] The epitaxial source / drain regions 70 in region 50N, e.g., the NMOS region, can be formed by masking region 50P, e.g., the PMOS region, and etching source / drain regions of the fins 52 in region 50N to create depressions in the fins 52. The epitaxial source / drain regions 70 in region 50N are then allowed to grow epitaxially within these depressions. The epitaxial source / drain regions 70 can consist of any acceptable material, as is appropriate for n-FinFETs. For example, if the fins 52 are silicon, the epitaxial source / drain regions 70 in region 50N can consist of materials that exert tensile stress in the channel region 58, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain areas 70 in area 50N may have surfaces that project from corresponding surfaces of the fins 52 and may have facets.

[0032] The epitaxial source / drain regions 70 in region 50P, e.g., the PMOS region, can be formed by masking region 50N, e.g., the NMOS region, and etching source / drain regions of the fins 52 in region 50P to create depressions in the fins 52. The epitaxial source / drain regions 70 in region 50P are then allowed to grow epitaxially within these depressions. The epitaxial source / drain regions 70 can consist of any acceptable material, as is appropriate for p-FinFETs. For example, if the fins 52 are silicon, the epitaxial source / drain regions 70 in region 50P can consist of materials capable of exerting compressive stress in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain areas 70 in area 50P may also have surfaces that project from the corresponding surfaces of the fins 52 and may have facets.

[0033] The epitaxial source / drain regions 70 and / or the fins 52 can be implanted with dopants to form source / drain regions, similar to the process previously discussed for forming lightly doped source / drain regions, followed by annealing. The source / drain regions can have an impurity concentration in the range of approximately 10 19 cm -3 up to about 10 21 cm -3 The n- and / or p-impurities for source / drain regions can be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 70 can be doped in situ during growth.

[0034] As a result of the epitaxial processes used to form the epitaxial source / drain regions 70, the upper surfaces of the epitaxial source / drain regions 70 have facets that extend laterally beyond the sidewalls of the fins 52. In some embodiments, these facets cause adjacent epitaxial source / drain regions 70 of the same FinFET to merge, as described by Fig. Figure 4B illustrates this. For example, fused epitaxial source / drain regions 70 can be formed when a transistor is formed from multiple fins 52. In other embodiments, adjacent epitaxial source / drain regions 70 remain separate after completion of the epitaxial process. For example, non-fused epitaxial source / drain regions 70 can be formed when a transistor is formed from a single fin 52 or when a transistor is formed from multiple fins 52. The gate spacers 66 illustrated in the embodiment are formed to cover a portion of the fin 52 sidewalls that extend over the STI regions 56, thereby blocking epitaxial growth.In some other embodiments, the spacer etching used to form the gate spacers 66 can be adjusted to remove the spacer material so that the epitaxially grown area can extend to the surface of the STI areas 56.

[0035] It is noted that the preceding disclosure generally describes a process for forming spacers, LDD regions, and source / drain regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, different sequences of steps may be used, spacers may be formed and removed, and / or the like. In some embodiments, the gate spacers 66 may be formed after the epitaxial source / drain regions 70. Furthermore, the n- and p-devices may be formed using other structures and steps. In some embodiments, dummy spacers may be formed in region 50N during the formation of the epitaxial source / drain regions 70 in region 50N. The dummy spacers in region 50N may then be removed.Dummy spacers can then be created in region 50P during the formation of the epitaxial source / drain regions 70 in region 50P. The dummy spacers in region 50P can then be removed. The gate spacers 66 can then be created after the epitaxial source / drain regions 70 have been created in both region 50N and region 50P.

[0036] In Fig. 5A and Fig. 5B, a CESL 72 is deposited over the epitaxial source / drain regions 70, the gate spacers 66, the masks 64 (if present) or the dummy gates 62, and the STI regions 56. The CESL 72 is formed from a non-dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like. In one embodiment, the CESL 72 is formed from silicon nitride.

[0037] A first ILD layer 74 is then deposited over the CESL 72. The first ILD layer 74 is formed from a dielectric material with a different etch rate than the CESL 72 material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can include oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like; nitrides such as silicon nitride; or the like. Other insulating materials formed by an acceptable process can be used. After formation, the first ILD layer 74 can be planarized, as by CMP.

[0038] The CESL 72 is formed to a large thickness T1, such as a thickness T1 in the range of approximately 3 nm to approximately 10 nm. As discussed in more detail below, undercuts are formed in the CESL 72 between the epitaxial source / drain regions 70 and the first ILD layer 74. Subsequently formed source / drain contacts extend into the undercuts, thereby increasing the contact surface area of ​​the epitaxial source / drain regions 70. Forming the CESL 72 to a large thickness T1 helps to provide sufficient space for the subsequent formation of the source / drain contacts.

[0039] In Fig. 6A and Fig. 6B A planarization process, such as a CMP, can be performed to align the cover surface of the first ILD layer 74 with the cover surfaces of the masks 64 (if present) or the dummy gates 62. The planarization process can remove the masks 64 on the dummy gates 62 and portions of the gate spacers 66 along the sidewalls of the masks 64. The planarization process can also remove portions of the CESL 72 above the dummy gates 62 and the gate spacers 66. After the planarization process, the cover surfaces of the dummy gates 62, the gate spacers 66, the CESL 72, and the first ILD layer 74 are coplanar. Therefore, the cover surfaces of the dummy gates 62 are exposed by the first ILD layer 74. In some embodiments, the masks 64 can remain, in which case the planarization process brings the cover surface of the first ILD layer 74 to the same plane as the cover surfaces of the masks 64.

[0040] In Fig. 7A and Fig. In 7B, the dummy gates 62 and optionally the dummy dielectrics 60 are removed and replaced by gate structures 80. The gate structures 80 comprise gate dielectrics 82 and gate electrodes 84. As an example of the formation of the gate structures 80, the dummy gates 62 and the masks 64 (if present) are removed in one or more etching steps, forming depressions. Portions of the dummy dielectrics 60 within the depressions may also be removed. In some embodiments, only the dummy gates 62 are removed, and the dummy dielectrics 60 remain and are exposed through the depressions. In some embodiments, the dummy dielectrics 60 are removed from depressions in a first region of a die (e.g., a core logic region) and remain in depressions in a second region of the die (e.g., an input / output region). In some embodiments, the dummy gates 62 are removed by an anisotropic dry etching process.For example, the etching process can be a dry etching process using reactive gas(es) that selectively etches (etches) the dummy gates 62 without etching the first ILD layer 74, the CESL 72, or the gate spacers 66. Each depression exposes and / or lies above a channel region 58 of a corresponding fin 52. Each channel region 58 is located between adjacent pairs of epitaxial source / drain regions 70. During removal, the dummy dielectrics 60 can be used as etch stop layers when etching the dummy gates 62. The dummy dielectrics 60 can then optionally be removed after the dummy gates 62 have been removed. After removal, the gate dielectrics 82 are conformally deposited in the recesses, such as on the top surfaces and side walls of the fins 52 and on the side walls of the gate spacers 66. The gate dielectrics 82 can also be formed on the top surface of the first ILD layer 74.According to some embodiments, the gate dielectrics 82 contain silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectrics 82 contain a high-k dielectric material, and in these embodiments, the gate dielectrics 82 may have a k-value greater than approximately 7.0 and may contain a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The formation processes of the gate dielectrics 82 may include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In embodiments where portions of the dummy dielectrics 60 remain in the recesses, the gate dielectrics 82 contain a material of the dummy dielectrics 60 (e.g., silicon oxide). The gate electrodes 84 are each deposited over the gate dielectrics 82 and fill the remaining parts of the recesses.The gate electrodes 84 can contain a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although, for example, a single-layer gate electrode 84 is illustrated, each gate electrode 84 can have any number of lining layers, any number of work function tuning layers, and a filler material. After filling the gate electrodes 84, a planarization process, such as CMP, can be performed to remove the excess portions of the gate dielectrics 82 and the gate electrode material 84, with the excess portions located above the top surface of the first ILD layer 74. The remaining portions of the gate electrode material 84 and the gate dielectrics 82 form the gate structures 80 of the resulting FinFETs. The gate structures 80 can also be referred to as “gate stacks” or “metal gates”.The gate structures 80 can extend along side walls of the canal areas 58 of the fins 52.

[0041] The formation of the gate structures 80 in region 50N and region 50P can occur simultaneously, such that the gate dielectrics 82 in each region are formed from the same materials and the gate electrodes 84 in each region are formed from the same materials. In some embodiments, the gate structures 80 in each region can be formed by different processes, so that the gate dielectrics 82 in each region can be made of different materials and the gate electrodes 84 in each region can be made of different materials. Different masking steps can be used to mask and expose appropriate regions when different processes are employed.

[0042] In Fig. 8A and Fig. In 8B, a second ILD layer 90 is deposited over the first ILD layer 74. The second ILD layer 90 can be formed from a dielectric material and can be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials can include oxides such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like; nitrides such as silicon nitride; or the like. After formation, the second ILD layer 90 can be planarized, as by CMP. In some embodiments, an etch stop layer is formed between the first ILD layer 74 and the second ILD layer 90. The etch stop layer may have a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride or the like, with a different etch rate than the material of the second ILD layer 90.In some embodiments, gate masks can be formed over the gate dielectrics 82 and gate electrodes 84 before the formation of the second ILD layer 90, which can protect the gate dielectrics 82 and gate electrodes 84 during contact formation.

[0043] In Fig. 9A and Fig. Source / drain contact openings 92 are formed by the ILD layers 74 and 90. The openings can be formed using acceptable photolithography and etching techniques. The etching can be performed by dry etching that is selective for the material of the ILD layers 74 and 90 (e.g., the material of the ILD layers 74 and 90 etches at a faster rate than the material of the CESL 72). Thus, the CESL 72 stops the etching of the source / drain contact openings 92. If, for example, the ILD layers 74, 90 are formed from silicon oxide, the etching can be a dry etching (e.g., plasma etching), such as reactive ion etching (RIE), and can be carried out using one or more reactive gases such as hexafluoro-1,3-butadiene (C4F6), octafluorocyclopentene (C5F8), octafluorocyclobutane (C4F8), or the like. A plasma can be generated during the etching using H2, O2, CO2, or the like, as shown by the cross-section of Fig. As shown in Figure 9B, the source / drain contact openings 92 expose first parts of the CESL 72A, e.g., parts above the epitaxial source / drain regions 70, but do not expose second parts of the CESL 72B, e.g., parts below the epitaxial source / drain regions 70 and on the STI regions 56. In particular, some parts of the first ILD layer 74 remain above the second parts of the CESL 72B. The parts of the first ILD layer 74 that remain above the second parts of the CESL 72B have a thickness T. 2, which can be in the range of approximately 0 nm to approximately 50 nm. Leaving some parts of the first ILD layer 74 at the bottoms of the source / drain contact openings 92 can help to protect the STI areas 56 during a subsequent process for forming undercuts in the CESL 72.

[0044] In Fig. 10A and Fig. 10B opens the CESL 72, thereby exposing the epitaxial source / drain regions 70. The CESL 72 is opened by extending the source / drain contact openings 92 through the CESL 72 using an etching process. As can be seen from the cross-section of Fig. As shown in Figure 10A, the source / drain contact openings 92 in the CESL 72, after etching, have a width W1 that can range from approximately 8 nm to approximately 200 nm. As seen in the cross-section of Fig. As shown in 10B, the second parts of CESL 72B are not removed by the etching, but the first parts of CESL 72A are (see Fig. 9B) are removed. Thus, after etching, the top surfaces of the epitaxial source / drain regions 70 are exposed, but the bottom surfaces of the epitaxial source / drain regions 70 are not exposed.

[0045] The etching process for opening the CESL 72 differs from the etching process for forming the source / drain contact openings 92 through the ILD layers 74, 90, which is described above in relation to Fig. 9A and Fig. 9B is discussed (e.g., with different etching parameters, different etchants, and / or a different type of etching). The etching can be wet or dry and selective for the CESL 72 material (e.g., etching the CESL 72 material at a faster rate than the ILD layer material 74, 90). As noted above, the CESL 72 is formed to a large thickness T1 (see Fig. 5A). As such, in some embodiments the etching can be anisotropic. For example, if CESL 72 is formed from silicon nitride, the etching can be dry etching (e.g., plasma etching), such as reactive ion etching (RIE), and can be carried out using one or more reactant gases such as fluoromethane (CH3F) or the like. A plasma can be generated during etching with H2, O2, CO2, or the like.

[0046] In Fig. 11A and Fig. In 11B, the lower parts of the source / drain contact openings 92 are laterally extended (e.g., widened), thereby forming undercuts 94 (e.g., cavities) between the epitaxial source / drain regions 70 and the first ILD layer 74. The surface area of ​​the epitaxial source / drain regions 70 exposed by the source / drain contact openings 92 is thus increased. Subsequently formed source / drain contacts are created that extend at least partially into the undercuts 94, thereby increasing the contact area of ​​the epitaxial source / drain regions 70. As shown by the cross-section of Fig. As shown in Figure 11A, the undercuts 94 can expose parts of the side walls of the gate spacers 66. As shown by the cross-section of Fig. As shown in Figure 11B, the second parts of CESL 72B are etched to form the undercuts 94 at least partially below the epitaxial source / drain regions 70. Thus, after etching, parts of the bottom surfaces of the epitaxial source / drain regions 70 are exposed.

[0047] The etching process for laterally expanding (e.g., widening) the lower parts of the source / drain contact openings 92 differs from the etching process for opening the CESL 72, which in relation to Fig. 10A and Fig. 10B is discussed (e.g., with different etching parameters, different etchants, and / or a different type of etching). The etching can be wet or dry etching that is selective for the CESL 72 material (e.g., the CESL 72 material etches at a faster rate than the ILD layer material 74, 90). In some embodiments, the etching is isotropic (or at least etches the CESL 72 with a higher degree of isotropy than the etching process used to open the CESL 72). For example, if the CESL 72 is formed from silicon nitride, the etching can be wet etching, such as chemical wet etching, and can be carried out using one or more etching chemicals such as phosphoric acid (H3PO4), e.g., a phosphoric acid solution (e.g., H3PO4:H2O).The etching process can be carried out for extended periods, ranging from approximately 10 to 30 seconds, and at high temperatures, ranging from approximately 100 to 180 °C. This allows the undercuts 94 to extend beneath the first ILD layer 74 over a distance of approximately 5 to 10 nm. Large undercuts 94 provide sufficient space for the subsequent formation of the source / drain contacts.

[0048] After the formation of the undercuts 94, the etched portions of the epitaxial source / drain regions 70 may have reduced heights. The heights of the epitaxial source / drain regions 70 may be reduced by one or more of the etching processes used to open the CESL 72 (see Fig. 10A and Fig. 10B) and / or forming the undercuts 94 (see Fig. 11A and Fig. 11B). For example, the heights of the epitaxial source / drain regions 70 can be reduced by a distance D1, which may be approximately 1% to approximately 6% of the original heights of the epitaxial source / drain regions 70. In some embodiments, the distance D1 may be approximately 0.5 nm to approximately 3 nm. The dimensions (e.g., heights) of the undercuts 94 can thus be increased, which helps to provide sufficient space for the subsequent formation of source / drain contacts in the undercuts 94.

[0049] In Fig. 12A and Fig. 12B Silicides 96 are formed in the source / drain contact openings 92 and the undercuts 94, as on parts of the epitaxial source / drain regions 70 exposed by the source / drain contact openings 92 and the undercuts 94. The silicides 96 can be formed by depositing a metal in the source / drain contact openings 92 and performing an annealing process. The metal can be, for example, titanium, cobalt, nickel, or the like, and can be deposited by, for example, ALD, CVD, PVD, or the like. The silicides 96 are physically and electrically coupled to the epitaxial source / drain regions 70. As shown by the cross-section of Fig. As shown in Figure 12A, the silicides 96 are in contact with parts of the side walls of the gate spacers 66, which are exposed by the undercuts 94. As can be seen from the cross-section of Fig. As shown in Figure 11B, the silicide 96 also contact the bottom surfaces of the epitaxial source / drain regions 70 and the second parts of the CESL 72B, which are exposed by the undercuts 94. Thus, at least some parts of the silicide 96 are located between the epitaxial source / drain regions 70 and the first ILD layer 74.

[0050] The formation of the silicide 96 in the undercuts 94 helps to increase the surface area of ​​the epitaxial source / drain regions 70 with which the silicide 96 are in contact. Furthermore, as noted above, the heights of the epitaxial source / drain regions 70 can be reduced by one or more of the etching processes used to open the CESL 72 (see Fig. 10A and Fig. 10B) and / or forming the undercuts 94 (see Fig. 11A and Fig. 11B). The Silicide 96 can thus have large thicknesses T3, such as thicknesses T3 in the range of about 2 nm to about 5 nm (like about 1 nm). Increasing the surface area and thickness of the Silicide 96 can help to reduce the contact resistance to the epitaxial source / drain regions 70.

[0051] In Fig. 13A and Fig. 13B Source / drain contacts 102 are formed in the source / drain contact openings 92 and the undercuts 94 (see Fig. 12A). A lining, such as a diffusion barrier, an adhesion layer, or the like, and a conductive material are formed in the source / drain contact openings 92 and the undercuts 94 on the silicides 96. The lining may be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD layer 90. The remaining lining and conductive material form the source / drain contacts 102 in the source / drain contact openings 92 and the undercuts 94. The source / drain contacts 102 are physically and electrically coupled to the silicides 96 and are thus connected to the epitaxial source / drain regions 70.After formation, the source / drain contacts 102 extend through the ILD layers 74 and 90. As seen through the cross-section of . Fig. As shown in Figure 13A, the source / drain contacts 102 are in contact with parts of the side walls of the gate spacers 66, e.g. with the parts exposed by the undercuts 94 (see Figure 13A). Fig. 12A). Likewise, the source / drain contacts 102 are in contact with the remaining parts of the CESL 72, which extend along the side walls of the gate spacers 66. Furthermore, the first ILD layer 74 is in contact with the top surfaces of the lower parts of the source / drain contacts 102, and the first ILD layer 74 also surrounds the upper parts of the source / drain contacts 102.

[0052] Forming the silicide 96 and the source / drain contacts 102 in the undercuts 94 helps to increase the contact area of ​​the epitaxial source / drain regions 70. Increasing the contact area can help to reduce the contact resistance to the epitaxial source / drain regions 70, especially when the resulting FinFETs are formed at a small technology node. Furthermore, as noted above, the heights of the epitaxial source / drain regions 70 can be reduced by one or more of the etching processes used to open the CESL 72 (see Fig. 10A and Fig. 10B) and / or the subcuts 94 form (see Fig. 11A and Fig. 11B). The portions of the source / drain contacts 102 that extend along the surfaces of the epitaxial source / drain regions 70 (e.g., those portions in the undercuts 94) can thus have large thicknesses T4, such as thicknesses T4 in the range of approximately 1 nm to approximately 5 nm. Increasing the thickness of the source / drain contacts 102 can help to reduce the contact resistance to the epitaxial source / drain regions 70. Finally, the parasitic capacitance between the gate electrodes 84 and the source / drain contacts 102 can be reduced. Thus, the performance of the FinFETs can be improved.

[0053] In Fig. 14A and Fig. In 14B, gate contacts 104 are formed by the second ILD layer 90. Openings for the gate contacts 104 are formed by the second ILD layer 90. The openings can be formed using acceptable photolithography and etching techniques. A lining, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The lining can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from one surface of the second ILD layer 90. The remaining lining and the conductive material form the gate contacts 104 in the openings.The gate contacts 104 are physically and electrically coupled to the gate electrodes 84 and thus connected to them. The gate contacts 104 can penetrate the gate masks (if present) via the gate electrodes 84.

[0054] The sequence of some of the steps discussed above can be changed in other embodiments. For example, the source / drain contacts 102 and the gate contacts 104 can be formed in different processes or in the same process. In some embodiments, the gate contacts 104 are formed simultaneously with the source / drain contacts 102; for example, the openings for the gate contacts 104 are formed simultaneously with the openings for the source / drain contacts 102. The gate electrodes 84 can be formed essentially by the etching processes required to open the CESL 72 (see Fig. 10A and Fig. 10B) and / or form the subcuts 94 (see Fig. 11A and Fig. 11B) should be used, unetched. Furthermore, although the source / drain contacts 102 and the gate contacts 104 are illustrated in the same cross-section, each of the source / drain contacts 102 and the gate contacts 104 can be formed in different cross-sections, which can prevent short-circuiting of the contacts.

[0055] Fig. 15A and Fig. Figure 15B shows cross-sectional views of FinFETs according to some other embodiments. This embodiment is similar to the embodiment described in relation to Fig. 14A and Fig. The device is described in Figure 14B, except that the source / drain contacts 102 have separate lower source / drain contacts 102A and upper source / drain contacts 102B. The lower source / drain contacts 102A extend through the first ILD layer 74, and the upper source / drain contacts 102B extend through the second ILD layer 90. The lower source / drain contacts 102A are therefore located between the upper source / drain contacts 102B and the silicides 96.

[0056] As an example of the formation of the lower source / drain contacts 102A, openings and undercuts for the lower source / drain contacts 102A can be formed in the first ILD layer 74 and the CESL 72 before the formation of the second ILD layer 90. The openings can be formed using a similar process to that described in relation to Fig. 9A to 11B are discussed. The silicide 96 and the lower source / drain contacts 102A are then formed in the openings and undercuts using a similar process to the one discussed in relation to Fig. As discussed in sections 12A to 13B, the following is formed: After formation, the cover surfaces of the gate spacers 66, the CESL 72, the first ILD layer 74, the gate electrodes 84 and the lower source / drain contacts 102A are coplanar.

[0057] As an example of the formation of the upper source / drain contacts 102B, openings for the upper source / drain contacts 102B are formed by the second ILD layer 90 after its formation. The openings can be formed using acceptable photolithography and etching techniques. A lining, such as a diffusion barrier, an adhesion layer, or the like, and a conductive material are formed in the openings. The lining can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from one surface of the second ILD layer 90. The remaining lining and conductive material form the upper source / drain contacts 102B in the openings.The upper source / drain contacts 102B are connected to the lower source / drain contacts 102A, and the lower source / drain contacts 102A are connected to the epitaxial source / drain regions 70. The upper source / drain contacts 102B and gate contacts 104 can be formed in different processes or in the same process. After formation, the cover surfaces of the second ILD layer 90, the upper source / drain contacts 102B, and the gate contacts 104 are coplanar.

[0058] It should be clear that some embodiments incorporate features from the embodiments described in Fig. 14A to 15B illustrate how these can be combined. For example, source / drain contacts in a first region of a die (e.g., an inlet / outlet region) can be continuous conductive features that extend through multiple ILD layers (as in Fig. 14A and Fig. 14B), while source / drain contacts in a second region of the die (e.g., a core logic region) may exhibit separate upper and lower conductive features in corresponding ILD layers (as shown in Fig. 15A and Fig. 15B shown).

[0059] Fig. 16A and Fig. Figure 16B shows cross-sectional views of FinFETs according to some other embodiments. This embodiment is similar to the embodiment described in relation to Fig. 14A and Fig. as described in Figure 14B, except that some parts of the undercuts 94 remain after the formation of the source / drain contacts 102. Parts of the undercuts 94 may remain if the materials of the silicide 96 and / or the source / drain contacts 102 are formed by a low-step-coverage deposition process. For example, if CVD is used to deposit the metal for the silicide 96, some parts of the undercuts 94 may not be filled. As shown by the cross-section of Fig. As shown in Figure 16A, some parts of the undercuts 94 can remain between the gate spacers 66 and each of the silicides 96 and the source / drain contacts 102, exposing them. As can be seen from the cross-section of Fig. As shown in Figure 16B, other parts of the undercuts 94 may remain between the epitaxial source / drain regions 70 and the first ILD layer 74, exposing them. The undercuts 94 in each cross-section may be continuous or discontinuous. The remaining undercuts 94 may be referred to as air gaps or cavities. The cavities are filled with air, a vacuum, or the like and therefore have a low k-value, thus reducing the capacitance between the source / drain contacts 102 and the gate electrodes 84.

[0060] It should be clear that some embodiments incorporate features from the embodiments described in Fig. 14A, Fig. 14B, Fig. 16A and Fig. 16B illustrates how they can be combined. For example, some parts of the undercuts 94 can remain over the epitaxial source / drain regions 70 (see Fig. 16A), while no undercuts remain below the epitaxial source / drain areas 70 and the first ILD layer 74 (see Fig. 14B). Likewise, some parts of the undercuts 94 may remain under the epitaxial source / drain regions 70 (see Fig. 16B), while no undercuts remain over the epitaxial source / drain areas 70 and the first ILD layer 74 (see Fig. 14A).

[0061] Fig. 17A and Fig. Figure 17B shows cross-sectional views of FinFETs according to some other embodiments. This embodiment is similar to the embodiment described in relation to Fig. 16A and Fig. 16B is described, except that the Source / Drain contacts 102 have separate lower Source / Drain contacts 102A and upper Source / Drain contacts 102B.

[0062] Fig. 18A and Fig. Figure 18B shows cross-sectional views of FinFETs according to some other embodiments. This embodiment is similar to the embodiment described in relation to Fig. 14A and Fig. 14B is described, except that the silicides 96 are in contact with less surface area of ​​the epitaxial source / drain regions 70. Referring again to Fig. 11A and Fig. 11B The silicides 96 can be formed such that they are in contact with less surface area of ​​the epitaxial source / drain regions 70 by reducing the dimensions of the undercuts 94. Specifically, the undercuts 94 can be formed so that they extend a shorter distance below the first ILD layer 74, so that the undercuts 94 do not expose parts of the sidewalls of the gate spacers 66 and so that parts of the CESL 72 remain between the first ILD layer 74 and the epitaxial source / drain regions 70. Thus, sidewalls of the CESL 72 above the epitaxial source / drain regions 70 are exposed by the undercuts 94. The widths of the undercuts 94 can be reduced by varying the etching parameters used to form the undercuts 94.For example, the etching can be performed for a shorter duration, such as in the range of approximately 2 to 10 seconds, or at a lower temperature, such as in the range of approximately 25 to 100 °C, which allows the undercuts 94 below the first ILD layer 74 to extend over a distance of approximately 1 nm to 5 nm. Forming the undercuts 94 with smaller dimensions helps to reduce the manufacturing costs of the FinFETs.

[0063] Fig. 19A and Fig. Figure 19B shows cross-sectional views of FinFETs according to some other embodiments. This embodiment is similar to the embodiment described in relation to Fig. 18A and Fig. 18B is described, except that the Source / Drain contacts 102 have separate lower Source / Drain contacts 102A and upper Source / Drain contacts 102B.

[0064] Fig. 20A and Fig. Figure 20B shows cross-sectional views of FinFETs according to some other embodiments. This embodiment is similar to the embodiment described in relation to Fig. 19A and Fig. as described in 19B, except that some parts of the undercuts 94 remain after the formation of the source / drain contacts 102. Parts of the undercuts 94 may remain if the materials of the silicide 96 and / or the source / drain contacts 102 are formed by a low-step-coverage deposition process. For example, if CVD is used to deposit the metal for the silicide 96, some parts of the undercuts 94 may not be filled. As can be seen from the cross-section of Fig. As shown in Figure 20A, undercuts 94 can remain between the CESL 72 and each of the silicide 96 and the source / drain contacts 102. As can be seen from the cross-section of Fig. As shown in Figure 20B, the undercuts 94 can remain between the epitaxial source / drain areas 70 and the first ILD layer 74.

[0065] It should be clear that some embodiments incorporate features from the embodiments described in Fig. 18A, Fig. 18B, Fig. 20A and Fig. 20B illustrates how they can be combined. For example, some parts of the undercuts 94 can remain over the epitaxial source / drain regions 70 (see Fig. 20A), while no undercuts remain below the epitaxial source / drain areas 70 and the first ILD layer 74 (see Fig. 18B). Likewise, some parts of the subcuts 94 can be found under the epitaxial source / drain regions 70 (see Fig. 20B) remain, while no undercuts remain over the epitaxial source / drain areas 70 and the first ILD layer 74 (see Fig. 18A).

[0066] Fig. 21A and Fig. Figure 21B shows cross-sectional views of FinFETs according to some other embodiments. This embodiment is similar to the embodiment described in relation to Fig. 20A and Fig. 20B is described, except that the Source / Drain contacts 102 have separate lower Source / Drain contacts 102A and upper Source / Drain contacts 102B.

[0067] Embodiments can offer advantages. Forming the undercuts 94 allows the silicides 96 and the source / drain contacts 102 to be in contact with a larger surface area of ​​the epitaxial source / drain regions 70. Increasing the contact area can help reduce the contact resistance to the epitaxial source / drain regions 70, especially when the resulting FinFETs are formed at a small technology node. Furthermore, forming the undercuts 94 allows the thicknesses of the silicides 96 and the portions of the source / drain contacts 102 within the undercuts 94 to be increased. Increasing the thicknesses of the silicides 96 and the source / drain contacts 102 can help reduce the contact resistance to the epitaxial source / drain regions 70.Finally, by reducing the amount of dielectric material around the epitaxial source / drain regions 70, the parasitic capacitance between the gate electrodes 84 and the source / drain contacts 102 can be reduced. This can improve the performance of the FinFETs.

Claims

[1] Structure, exhibiting: a gate stack (80) over a channel area (58) of a substrate (50); a source / drain area (70) adjacent to the canal area (58); a first interlayer dielectric layer (74), ILD layer, over the source / drain region (70); a silicide (96) between the first ILD layer (74) and the source / drain area (70), wherein the silicide (96) is in contact with a top surface of the source / drain area (70) and a bottom surface of the source / drain area (70) and extends into a subcut (94) between the source / drain area (70) and the overlying ILD layer (74); a first source / drain contact (102) with a first part and a second part, wherein the first part of the first source / drain contact (102) is located in the undercut (94) between the silicide (96) and the first ILD layer (74), the second part of the first source / drain contact (102) extends through the first ILD layer (74) and is in contact with the silicide (96); a gate spacer (66) that separates the source / drain region (70) from the gate stack (80); and a contact etch stop layer (72), CESL, extending along a side wall of the gate spacer (66), where: the structure further comprises a cavity between the CESL (72) and the source / drain region (70), wherein the cavity exposes surfaces of the gate spacer (66), the silicide (96) and the first source / drain contact (102); or the CESL (72) extends along the top surface of the source / drain region (70) and the structure further comprises a cavity between the first ILD layer (74) and the source / drain region (70), the cavity exposing surfaces of the CESL (72), the silicide (96) and the first source / drain contact (102). [2] Structure according to claim 1, further comprising: a second ILD layer (90) on top of the first ILD layer (74); a second source / drain contact (102B) extending through the second ILD layer (90), wherein the second source / drain contact (102B) is in contact with the first source / drain contact (102A); and a gate contact (104) extending through the second ILD layer (90), wherein the gate contact (104) is in contact with the gate stack (80), wherein the cover surfaces of the first ILD layer (74), the first source / drain contact (102A) and the gate stack (80) are coplanar, and where the cover surfaces of the second ILD layer (90), the second source / drain contact (102B) and the gate contact (104) are coplanar. [3] Structure according to claim 1, further comprising: a second ILD layer (90) on top of the first ILD layer (74), wherein the first source / drain contact (102) extends through the second ILD layer (90); and a gate contact (104) extending through the second ILD layer (90), wherein the gate contact (104) is in contact with the gate stack (80), where the cover surfaces of the second ILD layer (90), the first source / drain contact (102) and the gate contact (104) are coplanar. [4] Structure, exhibiting: a gate stack (80) on a substrate (50); a gate spacer (66) adjacent to the gate stack (80); a source / drain area (70) adjacent to the gate spacer (66); a silicide (96) on the source / drain region (70), wherein the silicide (96) is in contact with a side wall of the gate spacer (66); a source / drain contact (102) on the silicide (96), wherein the source / drain contact (102) is in contact with the side wall of the gate spacer (66); and an intermediate dielectric layer (74), ILD layer, on a lower part of the source / drain contact (102), wherein the ILD layer (74) surrounds an upper part of the source / drain contact (102), wherein the silicide (96) and the lower part of the source / drain contact (102) extend into an undercut (94) between the source / drain area (70) and the overlying ILD layer (74), the structure further includes a cavity that exposes a bottom surface of the source / drain area (70), a surface of the ILD layer (74) and a surface of the silicide (96). [5] Structure according to claim 4, further comprising: a contact etch stop layer (72), CESL, which is in contact with a top surface of the source / drain contact (102), the side wall of the gate spacer (66) and a side wall of the ILD layer (74). [6] Structure according to claim 4 or 5, wherein the silicide (96) has a first part and a second part, wherein the first part is arranged between the source / drain contact (102) and a top surface of the source / drain region (70) and the second part is arranged between the ILD layer (74) and the bottom surface of the source / drain region (70). [7] Procedures, comprehensive: Deposition of a contact etch stop layer (72), CESL, over a source / drain region (70); Deposition of an interlayer dielectric layer (74), ILD layer, over the CESL (72); Etching an opening (92) in the ILD layer (74); Enlarging the opening (92) through the CESL (72) with a first etching process, wherein the first etching process is anisotropic; Widening a lower part of the opening (92) with a second etching process to form an undercut (94) between the ILD layer (74) and the source / drain region (70), wherein the second etching process is isotropic; Formation of a silicide (96) in the opening (92) and the undercut (94), wherein the silicide (96) is in contact with the source / drain region (70); and Forming a source / drain contact (102) in the opening (92) and the undercut (94), wherein the source / drain contact (102) is in contact with the silicide (96) and part of the undercut (94) remains as a cavity after the formation of the source / drain contact (102). [8] Method according to claim 7, further comprising: Forming a gate spacer (66) adjacent to the source / drain area (70), wherein the undercut (94) after widening the lower part of the opening (92) exposes a side wall of the gate spacer (66). [9] Method according to claim 8, wherein after forming the source / drain contact (102) and the silicide (96) a part of the undercut (94) remains as a cavity between the side wall of the gate spacer (66) and each of the source / drain contact (102) and the silicide (96). [10] Method according to any one of claims 7 to 9, wherein the CESL (72) is formed of silicon nitride, the ILD layer (74) is formed of silicon oxide, the first etching process is a dry etching carried out using fluoromethane, and the second etching process is a wet etching carried out using phosphoric acid, wherein the second etching process is carried out for a duration in the range of 10 seconds to 30 seconds and at a temperature in the range of 100 °C to 180 °C. [11] Method according to any one of claims 7 to 10, wherein the undercut (94) after widening the lower part of the opening (92) exposes a side wall of the CESL (72). [12] Method according to any one of claims 7 to 11, wherein after forming the source / drain contact (102) and the silicide (96) a part of the undercut (94) remains as a cavity between the side wall of the CESL (72) and each of the source / drain contact (102) and the silicide (96). [13] Method according to any one of claims 7 to 9 and 11 to 12, wherein the CESL (72) is formed of silicon nitride, the ILD layer (74) is formed of silicon oxide, the first etching process is a dry etching carried out using fluoromethane, and the second etching process is a wet etching carried out using phosphoric acid, wherein the second etching process is carried out for a duration in the range of 2 seconds to 10 seconds and at a temperature in the range of 25°C to 100°C.

Images