STORAGE DEVICE AND INTEGRATED CHIP WITH RESISTIVE STORAGE CELL WITH A SWITCHING LAYER WITH ONE OR MORE DOTANDS AND METHOD FOR MANUFACTURING

Abstract

Storage device (200) with: a substrate (202); a lower electrode (106) above the substrate (202); an upper electrode (116) above the lower electrode (106); and a data storage structure (108) arranged between the upper electrode (116) and the lower electrode (106), wherein the data storage structure (108) comprises a lower switching layer (110) above the lower electrode (106) and an upper switching layer (112) above the lower switching layer (110), wherein the lower switching layer (110) has a dielectric material doped with a first dopant; wherein the storage device (200) is configured to be switchable between a high-impedance state and a low-impedance state, wherein in the high-resistance state an intrinsically conductive filament is arranged in the lower switching layer (110), wherein the intrinsically conductive filament has a bottom side which is in contact with a top side of the lower electrode (106) and a top side which is spaced apart from the upper electrode (116) by the upper switching layer (112), wherein in the low-resistance state the intrinsic conductive filament remains arranged in the lower switching layer (110) and an upper conductive filament is produced such that it extends from the top of the intrinsic conductive filament through the upper switching layer (112) to a top surface of the upper switching layer (112); and wherein the concentration of the first dopant increases continuously from a top (110t) of the lower switching layer (110) to a first point below the top of the lower switching layer (110), while the concentration of the first dopant decreases continuously from the first point in a direction to a bottom (110b) of the lower switching layer (110).

Description

background

[0001] Numerous modern electronic devices contain electronic memory configured to store data. Electronic memory can be volatile or non-volatile. Volatile memory stores data while it is powered on, while non-volatile memory retains data even when the power is off. Resistive random-access memory (RRAM) is a promising candidate for next-generation non-volatile memory technology due to its simple structure and compatibility with CMOS logic processes (CMOS: complementary metal-oxide semiconductor). An RRAM cell has a dielectric data storage structure with variable resistance placed between two electrodes arranged in compound metallization layers.

[0002] Publication US 2016 / 0049584A1 describes a resistive memory cell comprising a diffusion barrier layer, a lower electrode, a dielectric storage layer, a cover layer and an upper electrode, wherein the dielectric storage layer comprises a hydrogen-doped hafnium oxide layer, a hafnium oxide layer and an aluminum oxide layer.

[0003] Document US 2015 / 0333257A1 describes a resistive storage cell comprising a treated oxide layer between a lower and an upper electrode, wherein the oxide layer has been treated with a hydrogen-containing plasma. If the plasma treatment process results in unsaturated bonds, the treated oxide material can subsequently be exposed to at least one passivating material (e.g., hydrogen, nitrogen, fluorine, deuterium, etc.) to passivate at least some of the unsaturated bonds.

[0004] Publication US 2018 / 0175292A1 describes the fabrication of layered correlated electron materials, wherein a first group of layers comprises a first concentration of a dopant species and a second group of layers comprises a second concentration of a dopant species.

[0005] The publication DE 10 2018 126 665 A1 describes the manufacture of a resistive direct access memory cell, wherein a dielectric layer is formed over a conductive structure, a recess is formed in the dielectric layer, and a lower electrode of the resistive direct access memory cell is formed over the dielectric layer and in the recess.

[0006] Publication WO 2020 / 243 417 A1 represents the prior art and describes the fabrication of a resistive direct access memory cell, wherein a first hafnium oxide layer is deposited over a substrate, the first hafnium oxide layer is exposed to a plasma treatment process comprising hydrogen and argon, and subsequently a second hafnium oxide layer is deposited on the first hafnium oxide layer.

[0007] The task is to improve appropriate storage devices.

[0008] The problem is solved by the storage device according to claim 1, the integrated chip according to claim 10 and the method according to claim 17. Further embodiments are set out in the dependent claims. Brief description of the drawings

[0009] Aspects of the present invention are best understood with reference to the detailed description below in conjunction with the accompanying drawings. It should be noted that, in accordance with common industry practice, various elements are not drawn to scale. Rather, for the sake of clarity of discussion, the dimensions of the various elements may be arbitrarily enlarged or reduced. Fig. Figure 1 shows a schematic representation of some embodiments of a storage device with a storage cell that has a low forming voltage. Fig. Figure 2 shows a sectional view of some embodiments of a storage device with a memory cell having a doped lower switching layer. The Fig. 3A and Fig. Figure 3B shows sectional views of some embodiments of a storage device with a memory cell having a doped lower switching layer. Fig. 3C shows a graphical representation illustrating some embodiments with a concentration of dopants in the doped lower switching layer of the Fig. 1 to 3B corresponds to this. The Fig. Figures 4A to 4C, as well as 5A and 5B, show sectional views of some alternative embodiments of the storage device of Fig. 2. Fig. Figure 6 shows a sectional view of some embodiments of an integrated chip with memory cells, each having a low forming voltage and arranged in a connection structure located over a substrate. The Fig. Figures 7 to 14 show sectional views of some embodiments of a first method for manufacturing a memory cell with a data storage structure having a lower switching layer doped with one or more dopants. The Fig. Figures 15 to 24 show sectional views of some embodiments of a second method for manufacturing a memory cell with a data storage structure having a lower switching layer doped with one or more dopants. Fig. Figure 25 shows a flowchart according to some embodiments of a method for manufacturing a memory cell with a data storage structure having a lower switching layer doped with one or more dopants. Detailed description

[0010] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. These are, of course, merely examples and are not intended to be limiting. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0011] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0012] An RRAM cell (RRAM: resistive random-access memory) has a data storage structure (e.g., one or more oxide layers) located between an upper electrode and a lower electrode. The RRAM cell is mounted on a semiconductor substrate. A variable resistance of the data storage structure represents a data unit, such as a data bit. Depending on a voltage applied between the upper and lower electrodes, the variable resistance undergoes a reversible change between a high-resistance state and a low-resistance state, corresponding to data states of the data unit. The high-resistance state is high in that the variable resistance exceeds a threshold value, and the low-resistance state is low in that the variable resistance falls below the threshold value.

[0013] Before an RRAM cell can be used to store data, a first conductive path (i.e., a conductive filament) is typically created across the data storage structure. Creating this first conductive path facilitates subsequent write operations (which create the conductive path). To create the first conductive path, a forming voltage is applied across the top and bottom electrodes at the end of the RRAM manufacturing process. In some types of RRAM cells, the conductive path may contain vacancies (e.g., oxygen vacancies). In these devices, the forming voltage can break bonds between oxygen atoms and metal atoms in the data storage structure, knocking oxygen atoms out of a lattice of the data storage structure and creating localized oxygen vacancies.These localized oxygen vacancies tend to align themselves to form a conductive path that extends through the data storage structure. Subsequently, setting or reset voltages can be applied across the upper and lower electrodes to change the specific resistance of the data storage structure between the high-resistance and low-resistance states. Generally, the forming voltage is higher than the setting voltage. Typically, one or more transistors, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), placed on / above the semiconductor substrate, provide voltages for the RRAM cell, allowing the forming, setting, and reset voltages to be applied across the upper and lower electrodes.

[0014] In some embodiments where the conductive path is created before the RRAM cell is used to store data, the data storage structure can be or have an undoped metal oxide structure, e.g., undoped hafnium oxide (HfOx). In these embodiments, the conductive path cannot be confined to a specific region of the data storage structure, so the conductive path arises randomly within the data storage structure. And to break a sufficient number of bonds between the oxygen and metal atoms, the formation voltage can be relatively high. However, if the feature sizes of the one or more transistors are reduced, the relatively high formation voltage becomes problematic (e.g., because the reduced feature sizes of the one or more transistors lower breakdown voltages).The relatively high forming voltage can exceed the permissible output voltage of one or more transistors. Consequently, one or more transistors can be damaged and / or destroyed if operated in such a way as to output this relatively high forming voltage.

[0015] In some embodiments, the present description relates to a memory cell comprising a data storage structure with a lower switching layer doped with a first dopant and exhibiting a low forming voltage. The memory cell further comprises an upper electrode and a lower electrode, with the data storage structure positioned between the upper and lower electrodes. The data storage structure includes an upper switching layer above the lower switching layer. Both the upper and lower switching layers comprise a dielectric material, e.g., hafnium oxide (HfO₂), aluminum oxide (Al₂O₃), etc., and the lower switching layer is doped with the first dopant (e.g., hydrogen). The first dopant reacts strongly with oxygen, enabling it to break bonds between the metal and oxygen atoms in the lower switching layer during its formation.This creates intrinsically conductive oxygen vacancies that can align with each other to form one or more intrinsically conductive paths in the lower junction layer. Thus, the lower junction layer has one or more intrinsically conductive paths that arise without the formation voltage being applied across the memory cell. Furthermore, these intrinsically conductive paths can serve as a conductive path seed for generating upper conductive paths in the upper junction layer during a subsequent formation step. Because the intrinsically conductive oxygen vacancies arise before the formation step is performed on the memory cell, the number of locally confined oxygen vacancies created by the formation step is limited.This partially reduces the magnitude of the forming voltage and / or the duration of the forming step, thereby reducing the energy consumption of the memory cell and increasing the number of setting and resetting steps that can be performed on the memory cell.

[0016] Furthermore, the lower circuit layer can be co-doped with the first dopant and a second dopant (e.g., nitrogen), with the second dopant occupying a site adjacent to the intrinsically conductive oxygen vacancies. This allows the intrinsically conductive paths to be limited to one or more regions of the lower circuit layer (e.g., a central region). This prevents degradation of the intrinsically conductive paths during memory cell operation, thereby increasing the lifetime and stability of the memory cell. Accordingly, an integrated chip containing the memory cell can have one or more transistors with reduced feature sizes that can reliably supply the reduced forming voltage to the memory cell.This allows for a reduction in the structural size of the memory cell and the one or more transistors, thereby reducing and / or preventing damage to the memory cell and / or the one or more transistors.

[0017] Fig. Figure 1 shows a schematic representation of some embodiments of a storage device 100 with a storage cell 104 which has a low forming voltage.

[0018] The memory device 100 comprises the memory cell 104, which is electrically connected to a transistor 102, such that the memory device 100 has a one-transistor-one-resistive memory cell (1T1R) configuration. In some embodiments, the transistor 102 can, for example, be a metal-oxide-semiconductor field-effect transistor (MOSFET). The memory cell 104 comprises a lower electrode 106, an upper electrode 116, a capping layer 114, and a data storage structure 108, which is arranged between the lower electrode 106 and the capping layer 114. In alternative embodiments, the capping layer 114 is omitted. A bit line BL is electrically connected via the lower electrode 116 to one end of the data storage structure 108, and a source line SL is electrically connected via the transistor 102 to an opposite end of the data storage structure 108.A word line (WL) is electrically connected to a gate electrode of transistor 102. Thus, by applying a suitable WL voltage to the gate electrode of transistor 102, the memory cell 104 is connected between the bit line BL and the source line SL. Consequently, in some embodiments, by providing suitable bias conditions, the memory cell 104 can be switched between two electrical resistance states, namely a low-resistance state and a high-resistance state, in order to store data.

[0019] In some embodiments, the data storage structure 108 comprises a lower switching layer 110 and an upper switching layer 112, each containing a dielectric material. The dielectric material can be, for example, a metal oxide, such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), aluminum oxide (Al2O3), etc. Furthermore, the lower switching layer 110 is doped with a first dopant. In some embodiments, the first dopant can be hydrogen. It should be understood that a first dopant comprising a different element is also within the scope of disclosure. Thus, in various embodiments, the lower switching layer 110 contains the dielectric material (e.g., HfO2, Ta2O5, Al2O3, etc.) and hydrogen. In other embodiments, the first dopant (e.g., hydrogen) constitutes approximately 1.5% to 30% of the chemical composition of the lower switching layer 110.It should be understood that a lower switching layer 110, which has different proportions of the first dopant in its chemical composition, is also within the scope of disclosure. In various embodiments, the lower switching layer 110 consists entirely or substantially of the dielectric material (e.g., HfO). 2, Ta2O5, Al2O3 etc.) and the first dopant, so that the lower switching layer 110 has no other dopant.

[0020] In further embodiments, the lower switching layer 110 is co-doped with the first dopant and a second dopant. In some embodiments, the second dopant can be or comprise nitrogen, such that the second dopant is different from the first dopant. It should be understood that a second dopant comprising a different element is also within the scope of disclosure. In some embodiments, the lower switching layer 110 consists entirely or substantially of the dielectric material (e.g., HfO₂, Ta₂O₅, Al₂O₃, etc.), the first dopant, and the second dopant. In various embodiments, the second dopant (e.g., nitrogen) constitutes approximately 3% to 20% of the chemical composition of the lower switching layer 110. It should be understood that a lower switching layer 110 having different proportions of the second dopant in its chemical composition is also within the scope of disclosure.When the lower switching layer 110 is co-doped with the first and second dopants, the proportion of the first dopant in the chemical composition of the lower switching layer 110 is, for example, lower than the proportion of the second dopant in the chemical composition. In these embodiments, the first dopant constitutes approximately 1.5% to 10% of the chemical composition of the lower switching layer 110. The memory cell 104 can be configured as an RRAM cell such that the data storage structure 108 comprises one or more materials with variable resistance configured to undergo a reversible phase change between a high-resistance state and a low-resistance state.

[0021] In some embodiments, a first conductive path (i.e., a first conductive filament) is typically generated in a region 118 across the data storage structure 108 before the memory cell 104 can be used to store data. The region 118 comprises a first region 118a located in the lower switching layer 110 and a second region 118b located in the upper switching layer 112. Generating the first conductive path facilitates subsequent write operations (which create the conductive path). The first conductive path has oxygen vacancies located in the region 118, extending from a top surface of the lower electrode 106 to a bottom surface of the capping layer 114.

[0022] The first dopant (e.g., hydrogen) reacts strongly with oxygen, so that during the fabrication of the lower interconnect layer 110, the first dopant can break bonds between metal and oxygen atoms in the lower interconnect layer 110. This creates intrinsically conductive oxygen vacancies that can align with each other to form an intrinsically conductive path (i.e., an intrinsically conductive filament) in the first region 118a of the lower interconnect layer 110. Furthermore, after the fabrication of the memory cell 104, a formation step is performed on the memory cell 104. The formation step involves applying a formation voltage across the upper electrode 116 and the lower electrode 106 through the transistor 102 and the bit line BL. This creates oxygen vacancies in the upper interconnect layer 112 that tend to align with each other to form an upper first conducting path (i.e., an intrinsically conductive filament)An upper first conductive filament is formed in the second region 118b of the upper switching layer 112. Thus, the first conductive path comprises the intrinsically conductive path in the first region 118a and the upper first conductive path in the second region 118b. Subsequently, setting or reset voltages can be applied across the lower and upper electrodes 106 and 116 using transistor 102 and bit line BL to change the specific resistance of the data storage structure 108 between the high-resistance state and the low-resistance state.

[0023] In various embodiments, the intrinsic conductive path in the lower switching layer 110 can serve as a conductive path seed for generating the upper first conductive path in the upper switching layer 112. This aligns the upper first conductive path with the intrinsic conductive path. Since the intrinsic conductive path is generated before the formation step is performed at the memory cell 104, the number of oxygen vacancies created by the formation step is reduced. This partially reduces the magnitude and / or duration of the formation voltage across the memory cell 104, thereby lowering the energy consumption of the memory cell 104. Furthermore, the second dopant (e.g., nitrogen) can occupy a position adjacent to the intrinsic conductive oxygen vacancies of the upper switching layer 112, thus limiting the intrinsic conductive path to the first region 118a.This partially increases the lifetime and / or stability of the memory cell 104 during the execution of the formation step, a setting step, and / or a reset step. Because the lower switching layer 110 has the first and second dopants, the formation voltage can be reduced, thus enabling a reduction in the feature size of the transistor 102 and / or the memory cell 104.

[0024] Fig. Figure 2 shows a sectional view of some embodiments of a storage device 200, which has the storage cell 104 arranged over a substrate 202.

[0025] The storage device 200 has a dielectric interconnect 214 over the substrate 202. In some embodiments, the substrate 202 can be, for example, a semiconductor material such as a monocrystalline silicon / CMOS substrate, silicon germanium (SiGe), a silicon-on-insulator (SOI) material, or another suitable semiconductor substrate material. Furthermore, in some embodiments, the substrate 202 can, for example, have a first type of doping (e.g., p-type). The transistor 102 is arranged in / over the substrate 202.In some embodiments, the transistor 102 may, for example, be or comprise a MOSFET, a high-voltage transistor, a bipolar junction transistor (BJT), an n-channel metal-oxide semiconductor (nMOS) transistor, a p-channel metal-oxide semiconductor (pMOS) transistor, a gate-all-around FET (GAA-FET), a gate-enclosing FET, a multi-bridge-channel FET (MBCFET), a nanowire FET, a nanoring FET, a nanosheet FET (NSFET), or the like. It should be understood that a transistor 102 configured as another semiconductor device is also within the scope of disclosure. In further embodiments, the transistor 102 may comprise source / drain regions 204, a dielectric gate layer 206, a gate electrode 208, and / or a sidewall spacer structure 210. The source / drain regions 204 can be arranged in the substrate 202 and / or have a second doping type (e.g.(to be n-conducting), which is the opposite of the first doping method.

[0026] In the dielectric interconnect 214, a lower conductive via 212 is arranged over a source / drain region 204 of the transistor 102. In some embodiments, the dielectric interconnect 214 can, for example, be or comprise one or more intermetal dielectric (IMD) layers. The one or more IMD layers can, for example, each be or comprise silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, another suitable dielectric material, or a combination thereof. A low-k dielectric material used here can, for example, be or comprise a dielectric material with a dielectric constant less than approximately 3.9, 3, 2, or 1. In the dielectric interconnect 214, a lower conductive wire 216 is arranged over the lower conductive via 212.An upper conductive wire 218 is arranged above the lower conductive wire 216. In some embodiments, the lower conductive wire 216 is configured as a lower electrode via, and the upper conductive wire 218 is configured as an upper electrode via. The memory cell 104 is arranged vertically in the dielectric interconnect 214 between the lower conductive wire 216 and the upper conductive wire 218. An upper conductive via 220 is arranged above the upper conductive wire 218, and a second upper conductive wire 222 is arranged above the upper conductive via 220.In some embodiments, the lower conductive via 212, the upper conductive via 220 and the second upper conductive wire 222 can each be, for example, ruthenium, copper, aluminium, tungsten and / or another conductive material or a combination thereof.

[0027] The memory cell 104 comprises the lower electrode 106, the upper electrode 116, the capping layer 114, and the data storage structure 108, which is arranged between the lower electrode 106 and the capping layer 114. The data storage structure 108 has a lower switching layer 110 and an upper switching layer 112 above the lower switching layer 110. During operation, the memory cell 104 relies on redox reactions to generate and break at least part of the conductive path in the region 118 of the data storage structure 108 between the lower electrode 106 and the capping layer 114. The region 118 includes, for example, a first region 118a, which is arranged in the lower switching layer 110, and a second region 118b, which is arranged in the upper switching layer 112.The presence of a conductive path across the data storage structure 108 in the region 118 results in a low-impedance state, while a high-impedance state results when at least part of the conductive path in the region 118 is missing. In some embodiments, the first region 118a comprises the intrinsically conductive path, and the second region 118b comprises an upper conductive path (which is, for example, referred to in ). Fig. 1 has been described), such that the conducting path comprises the intrinsic conducting path and the upper conducting path, which extend across the region 118 of the data storage structure 108. In these embodiments, the memory cell 104 can be configured to include the upper conducting path in the second region 118b of the upper switching layer 112 (see Fig. 3B) resolves. Thus, by applying appropriate bias voltages to the memory cell 104, it can be switched between the high-resistance state and the low-resistance state in order to generate or resolve at least part of the conductive path in the region 118.

[0028] The lower switching layer 110 and the upper switching layer 112 each comprise a dielectric material. The dielectric material can be, for example, a high-k dielectric material, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O3), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), silicon dioxide (SiO2), another dielectric material, or a combination thereof. A high-k dielectric material used here can, for example, be a dielectric material with a dielectric constant higher than approximately 3.9, 9.34, 9.9, or 11.54. Furthermore, the lower switching layer 110 is doped with a first dopant, or it is co-doped with the first dopant and a second dopant, wherein the first dopant is different from the second dopant. In some embodiments, the first dopant can be or comprise hydrogen or another suitable element.In further embodiments, the second dopant can be or comprise nitrogen or another suitable element. In still further embodiments, the first dopant (e.g., hydrogen) is configured to reduce the formation voltage of the storage cell 104, and the second dopant (e.g., nitrogen) is configured to further reduce the formation voltage and / or extend the lifetime of the storage cell 104. In yet further embodiments, the upper switching layer 112 can be or comprise a dielectric material that does not contain the first and / or the second dopant, such that the upper switching layer 112 comprises an undoped dielectric material.In these embodiments, the undoped dielectric material can be or comprise an undoped high-k dielectric material, undoped hafnium oxide (HfO2), undoped zirconium oxide (ZrO2), undoped aluminum oxide (Al2O3), undoped tantalum oxide (Ta2O5), undoped hafnium aluminum oxide (HfAlO), undoped hafnium zirconium oxide (HfZrO), undoped silicon dioxide (SiO2), another dielectric material, or a combination thereof.

[0029] In various embodiments, the first dopant (e.g., hydrogen) constitutes approximately 1.5% to 30% of the chemical composition of the lower switching layer 110. It should be understood that a lower switching layer 110 with different proportions of the first dopant in its chemical composition is also within the scope of disclosure. In some embodiments, if the first dopant constitutes a relatively low proportion (e.g., less than approximately 1.5%) of the chemical composition of the lower switching layer 110, the forming voltage of the memory cell 104 cannot be reduced. In some embodiments, if the first dopant constitutes a relatively high proportion (e.g.,more than approximately 30% of the chemical composition of the lower switching layer 110 is due to the relatively high number of intrinsically conductive oxygen vacancies in the lower switching layer 110. This increases the magnitude of the reset voltage used to switch the memory cell 104 from the low-resistance state to the high-resistance state. This allows for a reduction in the number of discrete data states of the memory cell 104.

[0030] Furthermore, in some embodiments, the lower switching layer 110 can be co-doped with the first and second dopants, such that the second dopant (e.g., nitrogen) constitutes approximately 3% to 20% of the chemical composition of the lower switching layer 110. It should be understood that a lower switching layer 110 with different proportions of the second dopant in its chemical composition is also within the scope of disclosure. In various embodiments, if the second dopant constitutes a relatively low proportion (e.g., less than approximately 3%) of the chemical composition of the lower switching layer 110, the lifetime of the memory cell 104 may not be sufficiently extended, and / or the forming voltage of the memory cell 104 may not be sufficiently reduced. In still other embodiments, if the second dopant constitutes a relatively high proportion (e.g.,more than approximately 20%) of the chemical composition of the lower switching layer 110 reduces the lifetime of the memory cell 104, thereby decreasing the number of setting or resetting steps that can be performed on the memory cell 104.

[0031] The lower interconnect layer 110 can, for example, have a first atomic fraction of the first dopant (e.g., hydrogen) and a second atomic fraction of the second dopant (e.g., nitrogen). In some embodiments, the first atomic fraction is approximately 1.5%, 5%, 10%, 15%, 20%, 25%, or 30%, or it is approximately 3% to 10%, approximately 1.5% to 30%, or it has another suitable value. In further embodiments, the second atomic fraction is approximately 3%, 5%, 10%, 15%, 20%, 25%, or 30%, or it is approximately 3% to 20%, or it has another suitable value. In still further embodiments, if the lower interconnect layer 110 is co-doped with the first and the second dopants, the first atomic fraction is smaller than the second atomic fraction; for example, the first atomic fraction can be approximately 10% and the second atomic fraction can be approximately 20%.In these embodiments, the ratio of the second atomic fraction to the first atomic fraction can be approximately 2:1, 3:1, 4:1, or 5:1, or it can have another suitable value. In various embodiments, the sum of the first atomic fraction and the second atomic fraction can be approximately 1.5% to 30%.

[0032] The lower switching layer 110 has a thickness t1, and the upper switching layer 112 has a thickness t2. In some embodiments, the thickness t1 is approximately 1.5 nm, 1.75 nm, or 2 nm, or approximately 1.5 nm to 2 nm, or it has another suitable value. In other embodiments, if the thickness t1 is relatively small (e.g., less than approximately 1.5 nm), the forming voltage of the memory cell 104 may not be sufficiently reduced. This is partly because the one or more intrinsic conductive paths in the lower switching layer 110 may be relatively small and may not serve as conductive path seed(s) for the upper conductive path(s) in the upper switching layer 112. In further embodiments, if the thickness t1 is relatively large (e.g. greater than about 2 nm), the intrinsic conductive paths may not extend continuously from a bottom to a top of the lower switching layer 110.In various embodiments, the thickness t2 is approximately 2 nm, 2.25 nm, 2.5 nm, 2.75 nm, or 3 nm, or approximately 2 nm to 3 nm, or it has another suitable value. In some embodiments, if the thickness t2 is relatively small (e.g., less than approximately 2 nm), a high leakage current may occur between the lower electrode 106 and the capping layer 114. In still other embodiments, if the thickness t2 is relatively large (e.g., greater than approximately 3 nm), the forming voltage of the memory cell 104 may increase. In some embodiments, the thickness t1 of the lower switching layer 110 is smaller than the thickness t2 of the upper switching layer 112.

[0033] In some embodiments, the memory cell 104 can be configured as an RRAM cell, a programmable metallization cell (PMC), a metal cation RRAM cell, or the like. In some embodiments, the lower conductive wire 216 and / or the upper conductive wire 218 can each be, for example, copper, aluminum, tungsten, another conductive material, or a combination thereof. In an embodiment in which the memory cell 104 is configured as an RRAM cell, the capping layer 114 can be tantalum, tantalum nitride, titanium, titanium niride, hafnium, zirconium, another conductive material, or a combination thereof.In further embodiments, where the memory cell 104 is configured as a programmable metallization cell, such as a conductive bridging RAM (CBRAM), the capping layer 114 can be or comprise copper, gold, silver, tellurium, copper tellurium, aluminum, aluminum nitride, an alloy thereof, another conductive material, or a combination thereof. In still further embodiments, the lower and upper electrodes 106 and 116 can each be, for example, titanium, tantalum, titanium nitride, tantalum nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, another conductive material, or a combination thereof.

[0034] In further embodiments, the lower switching layer 110 can comprise a stack of switching layers (not shown), each comprising a dielectric material [e.g., a high-k dielectric material, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), silicon dioxide (SiO2), etc.] doped with the first dopant or co-doped with the first and second dopants. In these embodiments, each switching layer in the stack of switching layers comprises the first dopant (e.g., hydrogen) and one or more intrinsic pathways.

[0035] The Fig. 3A and Fig. Figure 3B shows sectional views of some embodiments with other states of memory cell 104 of the Fig. 1 and / or 2 of memory cell 104. In some embodiments, this shows Fig. 3A represents a first state 300a in which the memory cell 104 is in a high-impedance state (e.g., storing a logic o). In further embodiments, Fig. 3B represents a second state, 300b, in which memory cell 104 is in a low-impedance state (e.g., storing a logic 1). Fig. 3A and Fig. Figure 3B shows a memory cell with a conductive path formed by oxygen vacancies, but it should be understood that the disclosed data storage structure 108 is not limited to a memory cell with such paths. In some embodiments, for example, the data storage structure 108 can be used in storage devices that have a conductive path formed by conductive ions and oxygen vacancies, or by conductive ions but not oxygen vacancies.

[0036] Fig. Figure 3A shows an embodiment of the first state 300a of the memory cell 104 in which no forming step and / or no setting step has been performed on the memory cell 104. The memory cell 104 has the lower electrode 106, the lower switching layer 110, the upper switching layer 112, the capping layer 114 and the upper electrode 116 (which are, for example, in the Fig. 1 and / or 2 are shown and / or have been described with reference to them). In some embodiments, the capping layer 114 comprises a metal layer 114a having a metallic material (e.g. tantalum, tantalum nitride, titanium, titanium nitride, hafnium, zirconium or the like) over a metal oxide layer 114b having a metal oxide (e.g. an oxide of the metallic material).

[0037] In some embodiments, after the production of the memory cell 104 and before performing a forming and / or adjustment step on the memory cell 104, the lower switching layer 110 has a plurality of self-conducting oxygen vacancies 302, which are arranged in a first region 118a of the lower switching layer 110. In these embodiments, during the production of the memory cell 104, the lower switching layer 110 is treated with a first dopant, e.g., hydrogen (H₂). + ), which reacts relatively strongly with oxygen. In these embodiments, the first dopant is configured to break bonds between the metal atoms and the oxygen atoms in the lower switching layer 110, so that a compound of oxygen and the first dopant, e.g. a hydroxide (OH ), is formed. -), and the intrinsically conductive oxygen vacancies 302 in the lower switching layer 110. The intrinsically conductive oxygen vacancies 302 tend to align themselves with each other such that one or more intrinsically conductive paths (i.e., intrinsically conductive filaments) are formed in one or more regions of the lower switching layer 110 (e.g., in the first region 118a). The one or more intrinsically conductive paths extend continuously from a bottom surface 110b of the lower switching layer 110 to a top surface 110t of the lower switching layer 110. In various embodiments, the one or more intrinsically conductive paths can serve as conductive path seeds for one or more upper conductive paths that are formed in the upper switching layer 112 during a subsequent formation and / or adjustment step (see, e.g., Fig. 3B) are generated. This partially reduces the forming voltage and / or increases the number of setting / resetting steps that can be performed on memory cell 104.

[0038] Furthermore, the data storage structure 108 has a thickness Td. In some embodiments, the thickness Td is approximately 3.5 nm to approximately 5 nm. It should be understood that a thickness Td with other values ​​is also within the scope of disclosure. A position of a peak value of a concentration of the first dopant (e.g., hydrogen) and / or the second dopant (e.g., nitrogen) in the lower switching layer 110 can be represented by a horizontal line 304, wherein the horizontal line 304 is parallel to the bottom surface 110b of the lower switching layer 110. In some embodiments, a first distance d1 between the horizontal line 304 and the bottom surface 110b of the lower switching layer 110 is approximately 5% to 40% of the thickness Td (e.g., 0.05 Td to 0.4 Td). It should be understood that a first distance d1 with a different value is also within the scope of disclosure.In further embodiments, a second distance d2 between the horizontal surface 304 and the upper surface 110t of the lower switching layer 110 is smaller than the first distance d1. In still further embodiments, the concentration of the first dopant and / or the second dopant can increase continuously from the upper surface 110t of the lower switching layer 110 to the horizontal surface 304, and the concentration of the first dopant and / or the second dopant can decrease continuously from the horizontal surface 304 to the lower surface 110b of the lower switching layer 110. Therefore, in some embodiments, the peak value of the concentration of the first and / or the second dopant is closer to a lower surface of the upper switching layer 112 than to a top surface of the lower electrode 106 (see, e.g., Figure 1). Fig. 3C), so that a width w1 of the intrinsically conductive path can increase from the underside 110b of the lower switching layer 110 to its upperside 110t. This in turn allows the intrinsically conductive path to act as a conductive path seed for the upper conductive path during the subsequent forming and / or setting step (see, e.g., Fig. 3B) serves.

[0039] In various embodiments, the lower switching layer 110 is co-doped with the first and second dopants, the second dopant (e.g., nitrogen) being configured to connect the intrinsically conductive oxygen vacancies 302, thus occupying a site directly adjacent to the intrinsically conductive oxygen vacancies 302. This facilitates limiting the intrinsically conductive path to the first region 118a and mitigates the disruption of the intrinsically conductive path in a subsequent reset step. Therefore, the second dopant can further reduce the formation voltage and / or further increase the lifetime and stability of the memory cell 104.

[0040] Fig. Figure 3B shows an embodiment of the second state 300b of the memory cell 104, in which the formation step has been carried out on the memory cell 104. In some embodiments, a formation voltage is applied across the lower and upper electrodes 106 and 116 during the formation step. In these embodiments, the formation voltage is configured to knock oxygen atoms out of a lattice of the upper switching layer 112 (and / or the lower switching layer 110), and the metal oxide layer 114b is configured to accept the oxygen atoms, so that oxygen vacancies 306 are formed in the upper switching layer 112.In some embodiments, the intrinsically conductive oxygen vacancies 302 in the lower switching layer 110 can act as a conductive path seed, such that the oxygen vacancies 306 tend to align themselves in the second region 118b, directly above the first region 118a, forming an upper conductive path (i.e., an upper conductive filament) in the upper switching layer 112. The intrinsically conductive path in the first region 118a and the upper conductive path in the second region 118b define a conductive path (i.e., a first conductive path) that extends from the lower electrode 106 through the data storage structure 108 to the capping layer 114. Thus, after the formation step, the memory cell 104 is in a low-resistance state (e.g., it stores a logic 1).Subsequently, reset or setting voltages can be applied across the lower and upper electrodes 106 and 116 to resolve and / or generate the upper conductive path in the second region 118b of the upper switching layer 112. In some embodiments, the width w2 of the upper conductive path in the second region 118b is greater than the width w1 of the intrinsically conductive path in the first region 118a.

[0041] In some embodiments, the formation voltage can be reduced and / or eliminated because the lower switching layer 110 contains the first dopant (e.g., hydrogen) and the second dopant (e.g., nitrogen). In some embodiments, the formation voltage is lowered when the atomic fraction of the first and / or the second dopant in the lower switching layer 110 increases. For example, the formation voltage can be reduced from approximately 2.75 V to 2.44 V when the atomic fraction of the first and / or the second dopant is increased. It should be understood that a formation voltage with other values ​​is also within the scope of disclosure. In various embodiments, the formation voltage can be approximately equal to a setting voltage of the memory cell 104, so that the formation process is eliminated and a setting step is performed on the memory cell 104 to reach the second state 300b.This in turn reduces the energy consumption of the memory cell 104, and enables a reduction in the structural size of the memory cell 104, while reducing damage to the memory cell 104.

[0042] In further embodiments, after applying the forming voltage or the setting voltage across the storage cell 104, the compound of oxygen and the first dopant, e.g. a hydroxide (OH) - ), in the lower switching layer 110 to the metal oxide layer 114b of the capping layer 114. Subsequently, by applying a reset voltage across the memory cell 104, the oxygen atoms and / or the compound, e.g. a hydroxide (OH) -), from the metal oxide layer 114b to the upper switching layer 112 and / or the lower switching layer 110. This causes at least part of the upper conductive path in the upper switching layer 112 to be dissolved, so that the memory cell 104 is in a high-resistance state (e.g., it stores a logic 0). In some embodiments, after the reset voltage is applied, the connection, e.g., a hydroxide (OH), can be re-established. - ), are located in the upper switching layer 112, such that the upper switching layer 112 contains the first dopant. In various embodiments, the atomic fraction of the first dopant (e.g., hydrogen) in the upper switching layer 112 is smaller than the atomic fraction of the first dopant in the lower switching layer 110.

[0043] In some embodiments, the memory cell 104 is switched between the high-impedance state ( Fig. 3A) and the low-resistance state ( Fig. 3B) switched. This switching process involves applying the reset voltage to achieve the low-impedance state. In Fig. 3B uses the setting voltage to create the upper conducting path in the second region 118b. Then the reset voltage is applied to memory cell 104, which removes the upper conducting path in the second region 118b, leaving only the intrinsically conductive path in the first region 118a and putting memory cell 104 into a high-impedance state ( Fig. 3A). This process can be repeated several times if necessary. The switching time is reduced compared to conventional resistive memory cells because the intrinsic path is present in both the high-resistance and low-resistance states. Furthermore, because the lower switching layer 110 has the intrinsic path in the first region 118a, the size (e.g., height) of the upper conducting path in the second region 118b is reduced (e.g., compared to conventional resistive memory cells). Since the size of the upper conducting path is reduced, the magnitudes of the setting and reset voltages used to generate and clear the upper conducting path are also reduced. By reducing the magnitudes of the setting and reset voltages, the number of switching steps that can be performed on the memory cell 104 increases.This allows the bit error rate (BER) to be reduced across a plurality of memory cells, each having the lower and upper switching layers 110 and 112.

[0044] Fig. Figure 3C shows a graphical representation 300c, which illustrates some embodiments with a doping profile of one or more dopants across the thickness Td of the data storage structure 108. Fig. 1 to 3B corresponds to the y-axis of graphical representation 300c. The x-axis of graphical representation 300c corresponds to a thickness of the data storage structure 108. The x-axis of graphical representation 300c corresponds to a doping concentration of the first dopant (e.g., hydrogen) or a doping concentration of the first and second dopants (e.g., nitrogen) in the data storage structure 108.

[0045] A doping concentration curve 314 relates to some embodiments of a doping concentration of one or more dopants (e.g., the first dopant or the first and second dopants) in the data storage structure 108. As can be seen from the curve 314, the doping concentration of the one or more dopants increases continuously from the top 110t of the lower switching layer 110 to the horizontal 304, and it decreases continuously from the horizontal 304 in one direction to the bottom 110b of the lower switching layer 110. Thus, in some embodiments, a doping profile of the first dopant or of the first and second dopants in the data storage structure 108 follows a Gaussian distribution. It should be understood that a doping profile of the first dopant or of the first and second dopants in the data storage structure 108 that has a different distribution is also within the scope of disclosure.A peak value of the doping concentration of one or more dopants is located along the horizontal 304. Thus, as can be seen from the curve 314, the peak value of the doping concentration is closer to the top 110t of the lower switching layer 110 than to its bottom 110b.

[0046] Fig. Figure 4A shows a sectional view of some embodiments of a storage device 400a, which are similar to some alternative embodiments of the storage device 200. Fig. 2 correspond.

[0047] The dielectric interconnect structure 214 comprises a plurality of dielectric layers. The dielectric layers include a first intermetal dielectric (IMD) layer 402, an etch stop layer 404, a second IMD layer 406, and a third IMD layer 408. In some embodiments, the etch stop layer 404 can be or comprise silicon nitride, silicon carbide, silicon oxide nitride, silicon oxide carbide, another dielectric material, or a combination thereof. In still further embodiments, the first, second, and third IMD layers 402, 406, and 408, respectively, can each be or comprise a low-k dielectric material, an extremely low-k dielectric material, or another suitable dielectric material. In some embodiments, the memory cell 104 has inclined, opposing outer side walls. A side wall spacer structure 410 is arranged above and around the layers of the memory cell 104.In further embodiments, the side wall spacer structure 410 can be or comprise silicon nitride, silicon carbide, silicon oxide nitride, silicon oxide carbide, another dielectric material or a combination thereof.

[0048] Fig. Figure 4B shows a sectional view of some embodiments of a storage device 400b, which are similar to some alternative embodiments of the storage device 400a. Fig. 4A correspond, wherein the capping layer (114 of Fig. 4A) is omitted, so that the upper electrode 116 directly contacts the data storage structure 108. In further embodiments, the upper electrode 116 has one or more upper electrode layers, so that the capping layer (114 of Fig. 4A) is a bottom upper electrode layer of the upper electrode 116 (not shown). In these embodiments, the upper electrode 116 can be or comprise copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, hafnium, zirconium, gold, silver, tellurium, copper tellurium, aluminum nitride, platinum, nickel, ruthenium, iridium, another conductive material, or a combination thereof.

[0049] Fig. Figure 4C shows a sectional view of some embodiments of a storage device 400c, which are similar to some alternative embodiments of the storage device 400b. Fig. 4B, wherein the lower switching layer 110 has a plurality of intrinsic paths arranged in a plurality of regions 412 distributed across a width of the lower switching layer 110.

[0050] Fig. Figure 5A shows a sectional view of some embodiments of a storage device 500a, which are similar to some alternative embodiments of the storage device 400a. Fig. 4A corresponds.

[0051] Memory cell 104 contains a memory layer stack 502, comprising the lower electrode 106, the lower switching layer 110, the upper switching layer 112, the capping layer 114, and the upper electrode 116. The memory layer stack 502 has a central region 502m above the lower conductive wire 216 and a peripheral region 502p laterally offset from the lower wire 216. A bottom surface of the central region 502m of the memory layer stack 502 is located beneath a bottom surface of the peripheral region 502p of the memory layer stack 502.

[0052] In some embodiments, the layers in the storage layer stack 502 are each non-planar. This is because the layers are arranged in / above a trench defined by sidewalls of the etch stop layer 404. For example, the lower electrode 106 extends continuously from a top surface of the etch stop layer 404 and along sidewalls of the etch stop layer 404 to a top surface of the lower conductive wire 216. Furthermore, layers in the storage layer stack 502 that are located above the lower electrode 106 conform to a shape of the lower electrode 106. Therefore, the lower switching layer 110, the upper switching layer 112, the capping layer 114, and the upper electrode 116 are each non-planar.

[0053] Fig. Figure 5B shows a sectional view of some embodiments of a storage device 500b, which are similar to some alternative embodiments of the storage device 500a. Fig. 54A correspond, wherein the capping layer (114 of Fig. 5A) is omitted, so that the upper electrode 116 directly contacts the data storage structure 108. In further embodiments, the upper electrode 116 has one or more upper electrode layers, so that the capping layer (114 of Fig. 5A) is a bottom upper electrode layer of the upper electrode 116. In these embodiments, the upper electrode 116 can be or comprise copper, aluminum, tungsten, tantalum, tantalum nitride, titanium, titanium nitride, hafnium, zirconium, gold, silver, tellurium, copper tellurium, aluminum nitride, platinum, nickel, ruthenium, iridium, another conductive material, or a combination thereof.

[0054] Fig. Figure 6 shows a sectional view of some embodiments of an integrated chip 600, which has a connection structure 604 over a substrate 202.

[0055] The integrated chip 600 has memory cells 104a and 104b arranged in the interconnect structure 604 between adjacent metal layers of the interconnect structure 604. Furthermore, one or more STI structures 608 (STI: shallow trench insulation) are arranged in the substrate 202, which may comprise a dielectric material (e.g., silicon dioxide, silicon carbide, silicon nitride, etc.) located in a trench of the substrate 202.

[0056] Two access transistors 610 and 612 are arranged in / above the substrate 202 between the STI structures 608. The access transistors 610 and 612 comprise access gate electrodes 614 and 616, respectively, access gate dielectrics 618 and 620, respectively, access sidewall spacers 622, and source / drain regions 624. The source / drain regions 624 are arranged in the substrate 202 between the access gate electrodes 614 and 616 and the STI structures 608 and are doped such that they have a first conductivity type that is opposite to a second conductivity type of a channel region under the access gate dielectrics 618 and 620, respectively.

[0057] The access gate electrodes 614 and 616 can be, for example, doped polysilicon or a metal such as aluminum, copper, or a combination thereof. The access gate dielectrics 618 and 620 can be, for example, an oxide such as silicon dioxide, a high-k dielectric material such as aluminum oxide or hafnium oxide, or a combination thereof. Furthermore, the access sidewall spacers 622 can be, for example, silicon nitride (e.g., Si3N4), silicon carbide, another dielectric material, or a combination thereof. In some embodiments, the access transistors 610 and 612 can each be electrically connected to a word line (WL), allowing a corresponding WL signal (e.g., a current and / or a voltage) to be applied to the access gate electrodes 614 and 616.

[0058] Above the substrate 202 is the interconnection structure 604, which connects devices (e.g., the access transistors 610 and 612 and / or the memory cells 104a and 104b). The interconnection structure 604 comprises a plurality of IMD layers 626, 628, and 630 and a plurality of metallization layers 632, 634, and 636, which are stacked alternately. The IMD layers 626, 628, and 630 can be made, for example, from a low-k material, such as undoped silicate glass or an oxide such as silicon dioxide, or from an extremely low-k material, or a combination thereof. The metallization layers 632, 634 and 636 feature metal conduits 638, 640 and 642 produced in trenches, and they can be made of a metal such as copper, aluminium, ruthenium or a combination thereof.Contacts 644 extend from the lower metallization layer 632 to the source / drain regions 624 and / or the access gate electrodes 614 and 616, and vias 646 extend between the metallization layers 632, 634, and 636. The vias 646 and / or the lower electrodes 106 extend through dielectric protective layers 650 and 652 (which may be made of a dielectric material and may act as etch stop layers during fabrication). The dielectric protective layers 650 and 652 may be made of silicon nitride, silicon carbide, another suitable dielectric material, or a combination thereof. The contacts 644 and the vias 646 may be made of a metal, such as copper, aluminum, tungsten, or ruthenium.

[0059] Memory cells 104a and 104b are configured to store respective data states and are arranged in the interconnection structure 604 between adjacent metal layers. Memory cells 104a and 104b each have the lower electrode 106, the lower switching layer 110, the upper switching layer 112, the capping layer 114, and / or the upper electrode 116. A first memory cell 104a is electrically connected to a first bit line BL1 via a metal conductor 642, and a second memory cell 104b is electrically connected to a second bit line BL2 via another metal conductor 642. Therefore, a corresponding WL signal (e.g. a voltage and / or a current) can be applied to the access gate electrodes 614 and 616 to electrically connect the first memory cell 104a to the first bit line BL1 and a source line (SL) and to electrically connect the second memory cell 104b to the second bit line BL2 and the SL.The SL is electrically connected to a central source / drain region 624, which is shared by the access transistors 610 and 612. Thus, in some embodiments, applying the corresponding WL signal allows access to an output signal of the first bit line BL1 and / or the second bit line BL2 at the SL. In other embodiments, corresponding bias voltages can be applied to the access transistors 610 and 612 and the memory cells 104a and 104b via the WL, SL, BL1, and BL2, enabling a formation step, a setting step, a reset step, and / or a read operation to be performed on the first memory cell 104a and / or the second memory cell 104b.

[0060] The Fig. Figures 7 to 14 show sectional views 700 to 1400 of some embodiments of a first method for manufacturing a storage device comprising a memory cell with a data storage structure having a lower switching layer that, according to the invention, is doped with one or more dopants. The sectional views 700 to 1400, which are shown in the Fig. Figures 7 to 14 are indeed described for a first method, but it should be understood that the structures shown in these figures are not limited to the first method, but can be used as structures independently and separately from the method. Fig. Although steps 7 to 14 are described as a series of steps, it should be understood that these steps are not limiting, insofar as the order of the steps can be changed in other embodiments, and the disclosed methods can also be used for other structures. In other embodiments, some of the illustrated and / or described steps can be omitted completely or partially.

[0061] As shown in section view 700 of Fig. As shown in Figure 7, a first IMD layer 402 is fabricated over a substrate 202, and a lower conductive wire 216 is fabricated in the first IMD layer 402. In some embodiments, the substrate 202 can be, for example, a semiconductor body such as a monocrystalline silicon / CMOS substrate material, silicon germanium (SiGe), a silicon-on-insulator (SOI) material, or another suitable semiconductor substrate material, and / or the substrate 202 can have a first doping type (e.g., be p-type). The IMD layer 402 can be, for example, silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, another suitable dielectric material, or a combination thereof. Furthermore, the lower conductive wire 216 can be, for example, copper, aluminum, tungsten, another conductive material, or a combination thereof.

[0062] As also in Fig. As shown in Figure 7, an etch stop layer 404 is produced over the first IMD layer 402, and a lower electrode 106 is produced in the etch stop layer 404 directly above the lower conductive wire 216. In some embodiments, the etch stop layer 404 can be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or another suitable deposition method, or it can be grown using a wax-up process. Subsequently, the lower electrode 106 is produced in the etch stop layer 404. In some embodiments, a method for producing the lower electrode 106 comprises the following steps: producing a masking layer (not shown) over the etch stop layer 404; structuring the etch stop layer 404 according to the masking layer, thereby creating a lower electrode opening in the etch stop layer and above the lower conductive wire 216; Separation (e.g.by PVD, CVD, electroless plating, electroplating, sputtering, etc.) of a lower electrode material over the etch stop layer 404, thereby filling the lower electrode opening; and performing a planarization process, e.g., chemical-mechanical polishing (CMP), on the lower electrode material, so that the lower electrode 106 is formed. In further embodiments, a top surface of the lower electrode 106 is coplanar with a top surface of the etch stop layer 404. The etch stop layer 404 can, for example, be or comprise silicon nitride, silicon carbide, silicon oxide carbide, silicon oxide nitride, another dielectric material, or a combination thereof. Furthermore, the lower electrode 106 can be, for example, titanium, tantalum, titanium niride, tantalum nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, another conductive material or a combination thereof.

[0063] The Fig. 8A and Fig. Figure 8B shows sectional views 800a and 800b of a first embodiment of the first method. Furthermore, it shows Fig. 9 a sectional view 900, which corresponds to an alternative second embodiment of the first method. For example, in the first embodiment of the first method, the first method of Fig. 7 to the Fig. 8A and Fig. 8B and then from Fig. 8B to the Fig. continue from 10 to 14 (i.e., Fig. 9 is skipped). In a further embodiment, in the second embodiment of the second method, the second method can be... Fig. 7 to Fig. 9 and then from Fig. 9 to the Fig. continue from 10 to 14 (i.e., the Fig. 8A and Fig. 8B will be skipped).

[0064] As shown in section view 800a of Fig. As shown in Figure 8A, an undoped lower switching layer 802 is produced above the lower electrode 106 and the etch stop layer 404. In some embodiments, the undoped lower switching layer 802 can be produced by CVD, ALD, PVD, or by another suitable deposition or growth process with a thickness t1 of approximately 1.5 nm to 2 nm, approximately 1.5 nm to 1.75 nm, or approximately 1.75 nm to 2 nm, or another suitable value. In further embodiments, the undoped lower switching layer 802 can, for example, be or comprise a dielectric data storage material, such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), silicon dioxide (SiO2), another dielectric material or a combination thereof.In some embodiments, the undoped lower switching layer 802 can be manufactured as a stack of dielectric layers, each of which can be or comprise the dielectric data storage material (e.g. HfO2, ZrO2, Al2O3, Ta2O5, HfAlO, HfZrO, SiO2, another dielectric material or a combination thereof).

[0065] As shown in section view 800b of Fig. As shown in 8B, a doping process is carried out on the undoped lower switching layer (802 of Fig. 8A) is carried out so that a lower switching layer 110 is formed above the lower electrode 106. In some embodiments, the doping process includes the following: implanting one or more dopants 806 into the undoped lower switching layer (802 of Fig. 8A); and performing a thermal tempering process on the undoped lower switching layer (802 of Fig. 8A), thereby creating the lower switching layer 110. In some embodiments, the one or more dopants 806 comprise the first dopant, e.g., hydrogen (H₂). + ); the second dopant, e.g. nitrogen (N2); a doping compound, e.g. ammonia (NH3) or the like, comprising the first and second dopants; another suitable dopant or a combination thereof.

[0066] Thus, in some embodiments, the lower switching layer 110 is manufactured such that it comprises the dielectric data storage material (e.g., HfO2, ZrO2, Al2O3, Ta2O5, HfAlO, HfZrO, SiO2, another dielectric material, or a combination thereof) doped with a first dopant (e.g., hydrogen) or co-doped with the first and second dopants (e.g., nitrogen). Furthermore, the lower switching layer 110 can, for example, be manufactured such that it has a first atomic fraction of the first dopant and / or a second atomic fraction of the second dopant. In some embodiments, the first atomic fraction can be approximately 3% to 10% or approximately 1.5% to 30%, or it can have another suitable value. In other embodiments, the second atomic fraction is approximately 3% to 20%. In one embodiment, the lower switching layer 110 does not have the second dopant, so that the second atomic fraction is 0.In another embodiment, in which the lower switching layer 110 is co-doped with the first and the second dopants, the first atomic fraction is smaller than the second atomic fraction.

[0067] The first dopant (e.g., hydrogen) is configured to react with oxygen atoms in the lower switching layer 110, forming a compound, e.g., a hydroxide (OH⁻). -), from the first dopant and oxygen in the lower switching layer 110. In further embodiments, the first dopant breaks bonds between the metal atoms and the hydrogen atoms in the lower switching layer 110, thereby creating a plurality of intrinsically conductive oxygen vacancies 302 in the lower switching layer 110. The intrinsically conductive oxygen vacancies 302 tend to align themselves such that one or more intrinsically conductive paths (i.e., intrinsically conductive filaments) are formed in one or more regions 804 of the lower switching layer.In further embodiments, the doping process is carried out such that the concentration of the first dopant and / or the second dopant continuously increases from a top surface 110t of the lower switching layer 110 to a horizontal surface 304, and the concentration of the first dopant and / or the second dopant continuously decreases from the horizontal surface 304 to a bottom surface 110b of the lower switching layer 110 (as in . Fig. 3A is shown and / or has been explained with reference to it).

[0068] As shown in section view 900 of Fig. As shown in Figure 9, an alternative lower switching layer 110 is produced above the lower electrode 106 and the etch stop layer 404. In some embodiments, the lower switching layer 110 can be produced, for example, by CVD, PVD, ALD, co-sputtering, or another suitable deposition or growth process, in which the lower switching layer 110 is co-doped in situ with the first dopant (e.g., hydrogen) or with the first and second dopant (e.g., nitrogen). Thus, the lower switching layer 110 is manufactured such that it has a dielectric data storage material (e.g. HfO2, ZrO2, Al2O3, Ta2O5, HfAlO, HfZrO, SiO2, another dielectric material or a combination thereof) that is doped with a first dopant (e.g. hydrogen) or is co-doped in situ with the first dopant and the second dopant (e.g. nitrogen).

[0069] In one embodiment, a method for producing the lower switching layer 110 can involve the deposition of a dielectric data storage material (e.g., HfO₂). 2, ZrO2, Al2O3, Ta2O5, HfAlO, HfZrO, SiO2, etc.) using a deposition process (e.g., CVD, PVD, ALD, co-sputtering, etc.), while the dielectric data storage material is simultaneously treated with the first dopant (e.g., hydrogen) and / or the second dopant (e.g., nitrogen). In further embodiments, the lower switching layer 110 can be produced in a processing chamber, the processing chamber being heated to a temperature of approximately 250 °C to 300 °C or the like. In still further embodiments, the lower switching layer 110 is produced with a thickness t1 of approximately 1.5 nm to 2 nm.

[0070] Another method for fabricating the lower switching layer 110 may involve performing a deposition process (e.g., ALD, CVD, PVD, sputtering, etc.) to deposit the dielectric data storage material in a plasma environment, wherein the plasma comprises, for example, nitrogen (e.g., N2), hydrogen (e.g., H2), hydrated ammonia (e.g., NH4OH or H5NO), ammonia (e.g., NH3), a combination thereof, or the like. In some embodiments, fabricating the lower switching layer 110 comprises introducing a first precursor and a second precursor into a processing chamber containing the substrate 202. The first precursor may, for example, be or comprise hafnium tetrachloride (HfCl4), tantalum(V) chloride (TaCl5), or another precursor. The second precursor can be, for example, hydrated ammonia (e.g., NH4OH or H5NO), another suitable precursor (e.g.,containing the first dopant and / or the second dopant) or a combination thereof. Thus, in some embodiments, the lower switching layer 110 can be deposited while being co-doped in situ with the first and the second dopants. Furthermore, as above with reference to . Fig. As described in Figure 8B, by creating the lower switching layer 110 with the first dopant (e.g. hydrogen) one or more intrinsic pathways comprising intrinsic oxygen vacancies 302 are generated in one or more regions 804 of the lower switching layer 110.

[0071] In further embodiments, the lower switching layer 110 can, for example, be manufactured such that it contains a first atomic fraction of the first dopant and / or a second atomic fraction of the second dopant. In some embodiments, the first atomic fraction can be approximately 3% to 10% or approximately 1.5% to 30%, or another suitable value. In further embodiments, the second atomic fraction can be approximately 3% to 20%. In one embodiment, the lower switching layer 110 does not contain the second dopant, so the second atomic fraction is 0. In another embodiment, in which the lower switching layer 110 is co-doped with both the first and the second dopants, the first atomic fraction is smaller than the second atomic fraction.

[0072] As shown in section view 1000 of Fig. As shown in Figure 10, an upper switching layer 112 is produced above the lower switching layer 110, and an upper electrode 116 is produced above the upper switching layer 112, thereby defining a storage layer stack 1002 above the lower electrode 106. The storage layer stack 1002 comprises the lower switching layer 110, the upper switching layer 112, and the upper electrode 116. In some embodiments, the upper switching layer 112 can be produced by CVD, PVD, ALD, or another suitable deposition or growth process with a thickness t2 of approximately 2 nm to 3 nm. In other embodiments, the thickness t2 of the upper switching layer 112 is greater than the thickness t1 of the lower switching layer 110.Furthermore, the upper switching layer 112 can be, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), hafnium aluminum oxide (HfAlO), hafnium zirconium oxide (HfZrO), silicon dioxide (SiO2), another dielectric material, or a combination thereof. Thus, in some embodiments, both the upper switching layer 112 and the lower switching layer 110 comprise the dielectric data storage material. Additionally, a masking layer 1006 is produced over the upper electrode 116 such that the masking layer 1006 covers a central region of the storage layer stack 1002, while a peripheral region of the storage layer stack 1002 remains uncovered and / or exposed.

[0073] Furthermore, the upper electrode 116 can be produced, for example, by CVD, PVD, sputtering, electroplating, electroless plating, or by another suitable deposition or growth process. In some embodiments, the upper electrode 116 can be or comprise titanium, tantalum, titanium nitride, tantalum nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, another conductive material, or a combination thereof. In further embodiments, the production of the upper switching layer 112 comprises introducing a first precursor and a third precursor into a processing chamber containing the substrate 202. The first precursor can be, for example, hafnium tetrachloride (HfCl4), tantalum(V) chloride (TaCl5), or another precursor. The third precursor can be, for example, water (H2O), another suitable precursor, or a combination thereof.In further embodiments, a capping layer (not shown) is produced between the upper electrode 116 and the upper switching layer 112, wherein the capping layer is essentially the same as the capping layer 114 of the . Fig. 1 to 3B is similar. In an alternative embodiment, the upper electrode 116 comprises a plurality of upper electrode layers such that a bottommost upper electrode layer is configured as the capping layer (as, for example, with reference to Fig. 4B or Fig. 5B has been explained).

[0074] As shown in section view 1100 of Fig. As shown in 11, a structuring process is performed on the memory layer stack (1002 of Fig. 10) according to the masking layer (1006 of Fig. 10) is carried out, resulting in a data storage structure 108 and a memory cell 104. The structuring process can, for example, include performing a wet etching process, a dry etching process, and / or another suitable etching process, or a combination thereof. In various embodiments, the memory cell 104 comprises the lower electrode 106, the lower switching layer 110, the upper switching layer 112, and the upper electrode 116. In one embodiment, a method for producing the lower switching layer 110 comprises the deposition process of Fig. 8A, the doping process of Fig. 8B and the structuring process of Fig. 11. In a further embodiment, a method for producing the lower switching layer 110 comprises the manufacturing process of Fig. 9 and the structuring process of Fig. 11. Furthermore, the data storage structure 108 has the lower switching layer 110 and the upper switching layer 112.

[0075] As shown in section view 1200 of Fig. As shown in Figure 12, a sidewall spacer structure 410 is produced above the memory cell 104, and a second IMD layer 406 is produced above the sidewall spacer structure 410. In some embodiments, the sidewall spacer structure 410 and / or the second IMD layer 406 are each produced, for example, by CVD, PVD, ALD, or by another suitable deposition or growth process. In some embodiments, the sidewall spacer structure 410 can be or comprise silicon nitride, silicon carbide, silicon oxide nitride, silicon oxide carbide, another suitable dielectric material, or a combination thereof. In further embodiments, the second IMD layer 406 can be or comprise silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, another suitable dielectric material, or a combination thereof.

[0076] As shown in section view 1300 of Fig. As shown in Figure 13, an upper conductive wire 218 is produced above the upper electrode 116. In some embodiments, a method for producing the upper conductive wire 218 comprises the following steps: depositing a masking layer (not shown) over the second IMD layer 406; structuring the second IMD layer 406 and the sidewall spacer structure 410 according to the masking layer, thereby creating an upper conductive wire opening over the upper electrode 116; depositing (e.g., by CVD, PVD, sputtering, electroplating, electroless plating, or by another suitable deposition or growth process) a conductive material (e.g., copper, aluminum, tungsten, another conductive material, or a combination thereof) over the second IMD layer 406 and the upper electrode 116; and performing a planarization process (e.g.,a CMP process) into the conductive material, creating the upper conductive wire 218.

[0077] As shown in section view 1400 of Fig. As shown in Figure 14, a third IMD layer 408 is fabricated above the second IMD layer 406, and an upper conductive via 220 and a second upper conductive wire 222 are fabricated in the third IMD layer 408. In some embodiments, the third IMD layer 408 is fabricated, for example, by CVD, PVD, ALD, or by another suitable fabrication or growth process. In further embodiments, the upper conductive via 220 and the second upper conductive wire 222 can be fabricated by a single-Damascene process, a dual-Damascene process, or another suitable fabrication process. In some embodiments, the third IMD layer 408 can be, for example, silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, another suitable dielectric material, or a combination thereof.In further embodiments, the upper conductive via 220 and the second upper conductive wire 222 can each be, for example, copper, aluminum, titanium nitride, tantalum nitride, tungsten, ruthenium, another conductive material or a combination thereof.

[0078] The Fig. Figures 15 to 24 show sectional views 1500 to 2400 of some embodiments of a second method for manufacturing a storage device comprising a memory cell with a data storage structure having a lower switching layer that, according to the invention, is doped with one or more dopants. The sectional views 1500 to 2400, which are shown in the Fig. Figures 15 to 24 are indeed described for a second method, but it should be understood that the structures shown in these figures are not limited to the second method, but can be used as structures independently and separately from the method. Fig. Although steps 15 to 24 are described as a series of steps, it should be understood that these steps are not limiting, insofar as the order of these steps can be changed in other embodiments, and the disclosed methods can also be used for other structures. In other embodiments, some of the illustrated and / or described steps can be omitted completely or partially.

[0079] As shown in section view 1500 of Fig. As shown in Figure 15, a first IMD layer 402 is produced over a substrate 202, and a lower conductive wire 216 is produced in the first IMD layer 402. In some embodiments, the first IMD layer 402 and the lower conductive wire 216 are produced as shown in Figure 15. Fig. Figure 7 is shown and / or described with reference to it. Subsequently, an etch stop layer 404 is produced over the lower conductive wire 216. In some embodiments, the etch stop layer 404 can be produced by CVD, PVD, ALD, or by another suitable deposition or growth process. The etch stop layer 404 can, for example, be or comprise silicon nitride, silicon carbide, another dielectric material, or a combination thereof.

[0080] As shown in section view 1600 of Fig. As shown in Figure 16, a structuring process is carried out on the etch stop layer 404, creating a bottom electrode opening 1602 in the etch stop layer 404 and exposing a top surface of the lower conductive wire 216. In some embodiments, the structuring process includes creating a masking layer (not shown) over the etch stop layer 404 and treating unmasked areas of the etch stop layer 404 with one or more etchants. In other embodiments, the structuring process includes performing a wet etching process, a dry etching process, another suitable etching process, or a combination thereof.

[0081] As shown in section view 1700 of Fig. As shown in Figure 17, a lower electrode 106 is deposited over the lower conductive wire 216 and the etch stop layer 404, thereby filling the lower electrode opening 1602. In some embodiments, the lower electrode 106 can be or comprise titanium, tantalum, titanium nitride, tantalum nitride, platinum, nickel, hafnium, zirconium, ruthenium, iridium, another conductive material, or a combination thereof. In further embodiments, the lower electrode 106 is produced, for example, by CVD, PVD, ALD, or another suitable deposition or growth process as a conformal layer that adapts to a shape of opposing sidewalls and / or a top surface of the etch stop layer 404 that define the lower electrode opening 1602.

[0082] The Fig. 18A and Fig. Figure 18B shows sectional views 1800a and 1800b of a first embodiment of the second method. Furthermore, it shows Fig. 19 a sectional view 1900, which corresponds to an alternative second embodiment of the second method. For example, in the first embodiment of the second method, the second method can be distinguished from the Fig. 15 to 17 to the Fig. 18A and Fig. 18B and then from Fig. 18B to the Fig. continue from 20 to 24 (i.e., Fig. 19 is skipped). In a further embodiment, in the second embodiment of the second method, the second method can be distinguished from the Fig. 15 to 17 Fig. 19 and then from Fig. 19 to the Fig. continue from 20 to 24 (i.e., the Fig. 18A and Fig. 18B are skipped).

[0083] As shown in section view 1800a from Fig. As shown in Figure 18A, an undoped lower switching layer 1802 is deposited above the lower electrode 106 and the etch stop layer 404. In these embodiments, the undoped lower switching layer 1802 is deposited as a conformal layer that adapts to the shape of the lower electrode 106. In some embodiments, the undoped lower switching layer 1802 is essentially the same as the undoped lower switching layer 802 of Fig. 8A similarly. In these embodiments, the undoped lower switching layer 1802 is produced by methods similar to those used for the production of the undoped lower switching layer 802 of Fig. 8A have been explained and / or described.

[0084] As shown in section view 1800b of Fig. As shown in 18B, a doping process is carried out on the undoped lower switching layer (1802 of Fig. 18A) so that a lower switching layer 110 is formed above the lower electrode 106. In some embodiments, the doping process is carried out as described in Fig. 8B is shown and / or described with reference to it. Thus, the lower switching layer 110 has a plurality of self-conducting oxygen vacancies 302, which form a plurality of self-conducting paths in one or more regions 804 of the lower switching layer 110 (as is shown, for example, in Fig. 8B is shown and / or described with reference to it).

[0085] As shown in the 1900 section view. Fig. As shown in Figure 19, an alternative lower switching layer 110 is produced above the lower electrode 106. In these embodiments, the lower switching layer 110 is produced as a conformal layer that adapts to the shape of the lower electrode 106. In some embodiments, the lower switching layer 110 is produced as shown in Figure 19. Fig. 9 is shown and / or described with reference to it. As a result, the lower switching layer 110 has a plurality of self-conducting oxygen vacancies 302, which form a plurality of self-conducting paths in one or more regions 804 of the lower switching layer 110 (as is shown, for example, in Fig. 9 is shown and / or described with reference to it).

[0086] As shown in the section view 2000 from Fig. As shown in Figure 20, an upper switching layer 112 is produced above the lower switching layer 110, and an upper electrode 116 is produced above the upper switching layer 112, thereby defining a storage layer stack 1002 above the lower electrode 106. The storage layer stack 1002 comprises the lower switching layer 110, the upper switching layer 112, and the upper electrode 116. In some embodiments, the upper switching layer 112 and the upper electrode 116 are produced as shown in Figure 20. Fig. 10 is shown and / or described with reference to it. In addition, a masking layer 2002 is produced above the upper electrode 116.

[0087] As shown in section view 2100 from Fig. As shown in 21, structuring processes are performed on the memory layer stack (1002 of Fig. 20) and the lower electrode 106, creating a memory cell 104 and a data storage structure 108 above the lower conductive wire 216. The memory cell 104 comprises the lower electrode 106, the lower switching layer 110, the upper switching layer 112, and the upper electrode 116. In some embodiments, the memory layer stack (1002 of Fig. 20) and the lower electrode 106 according to the masking layer (2002 by Fig. 20) structured. In further embodiments, the structuring process comprises performing a wet etching process, a dry etching process and / or another suitable etching process or a combination thereof. In one embodiment, a method for producing the lower switching layer 110 comprises the deposition process of Fig. 18A, the doping process of Fig. 18B and the structuring process of Fig. 21. In an alternative embodiment, a method for manufacturing the lower switching layer 110 comprises the manufacturing process of Fig. 19 and the structuring process of Fig. 21. In one embodiment, the side walls of the lower electrode 106, the lower switching layer 110 and the upper switching layer 112 can be flat, while the upper electrode 116 exposes part of the top surface of the upper switching layer 112.

[0088] As shown in section view 2200 from Fig. As shown in Figure 22, a sidewall spacer structure 410 is produced above the memory cell 104, and a second IMD layer 406 is produced above the sidewall spacer structure 410 and the etch stop layer 404. In some embodiments, the sidewall spacer structure 410 and / or the second IMD layer 406 are each produced, for example, by CVD, PVD, ALD, or by another suitable deposition or growth process. In some embodiments, the sidewall spacer structure 410 can be or comprise silicon nitride, silicon carbide, silicon oxide nitride, silicon oxide carbide, another suitable dielectric material, or a combination thereof. In further embodiments, the second IMD layer 406 can be or comprise silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, another suitable dielectric material, or a combination thereof.

[0089] As shown in section view 2300 of Fig. As shown in Figure 23, an upper conductive wire 218 is produced above the upper electrode 116. In some embodiments, a method for producing the upper conductive wire 218 may include the following steps: depositing a masking layer (not shown) over the second IMD layer 406; structuring the second IMD layer 406, the sidewall spacer structure 410, and / or the upper electrode 116 according to the masking layer, thereby creating an upper conductive wire opening over the upper electrode 116; depositing (e.g., by CVD, PVD, sputtering, electroplating, electroless plating, or by another suitable deposition or growth process) a conductive material (e.g., copper, aluminum, tungsten, another conductive material, or a combination thereof) over the second IMD layer 406 and the upper electrode 116; and carrying out a planning process (e.g.a CMP process) into the conductive material, creating the upper conductive wire 218.

[0090] As shown in section view 2400 of Fig. As shown in Figure 24, a third IMD layer 408 is fabricated above the second IMD layer 406, and an upper conductive via 220 and a second upper conductive wire 222 are fabricated in the third IMD layer 408 and above the upper conductive wire 218. In some embodiments, the third IMD layer 408 is fabricated, for example, by CVD, PVD, ALD, or by another suitable fabrication or growth process. In further embodiments, the upper conductive via 220 and the second upper conductive wire 222 can be fabricated by a single-Damascene process, a dual-Damascene process, or another suitable fabrication process. In some embodiments, the third IMD layer 408 can be, for example, silicon dioxide, a low-k dielectric material, an extremely low-k dielectric material, another suitable dielectric material, or a combination thereof.In further embodiments, the upper conductive via 220 and the second upper conductive wire 222 can each be, for example, copper, aluminum, titanium nitride, tantalum nitride, tungsten, ruthenium, another conductive material or a combination thereof.

[0091] Fig. Figure 25 shows a method 2500 for manufacturing a storage device comprising a memory cell with a data storage structure having a lower switching layer that, according to the invention, is doped with one or more dopants. Although the method 2500 is presented and / or described here as a series of steps or events, it should be understood that the method is not limited to the sequence or steps shown. Therefore, in some embodiments, the steps can be performed in a different sequence than shown and / or simultaneously. Furthermore, in some embodiments, the steps or events shown can be subdivided into several steps or events that can be performed at different times or simultaneously with other steps or sub-steps.In some embodiments, some of the illustrated steps or events may be omitted, and other non-illustrated steps or events may be used.

[0092] In step 2502, a lower electrode is produced over a substrate. Fig. Figure 7 shows the sectional view 700, which corresponds to some embodiments of step 2502. Fig. 16 and Fig. Figure 17 shows the sectional views 1600 and 1700, which correspond to some alternative embodiments of step 2502.

[0093] In step 2504, a lower switching layer is produced above the lower electrode such that it has a dielectric material doped with a first dopant. In some embodiments, the lower switching layer has a second dopant that is different from the first dopant. Fig. 8A and Fig. Figure 8B shows the sectional views 800a and 800b, which correspond to some embodiments of step 2504. Fig. Figure 9 shows the sectional view 900, which corresponds to an alternative embodiment of step 2504. Fig. 18A and Fig. Figure 18B shows the sectional views 1800a and 1800b, which correspond to some further embodiments of step 2504. Fig. Figure 19 shows the sectional view 1900, which corresponds to another alternative embodiment of step 2504.

[0094] In step 2506, an upper switching layer is produced above the lower switching layer, and an upper electrode is produced above the upper switching layer. Fig. Figure 10 shows the section view 1000, which corresponds to some embodiments of step 2506. Fig. Figure 20 shows the section view 2000, which corresponds to some alternative embodiments of step 2506.

[0095] In step 2508, the lower switching layer, the upper switching layer and the upper electrode are structured, creating a memory cell above the substrate. Fig. Figure 11 shows the sectional view 1100, which corresponds to some embodiments of step 2508. Fig. Figure 21 shows the sectional view 2100, which corresponds to some alternative embodiments of step 2508.

[0096] In step 2510, an upper conductive wire is produced above the memory cell. Fig. Figure 13 shows the sectional view 1300, which corresponds to some embodiments of step 2510. Fig. Figure 23 shows the sectional view 2300, which corresponds to some alternative embodiments of step 2510.

[0097] In step 2512, an upper conductive via and a second upper conductive wire are produced above the upper conductive wire. Fig. Figure 14 shows the sectional view 1400, which corresponds to some embodiments of step 2512. Fig. Figure 24 shows the sectional view 2400, which corresponds to some alternative embodiments of step 2512.

[0098] In some embodiments, the present invention thus relates to a memory cell comprising an upper electrode, a lower electrode and a data storage structure arranged between the upper and the lower electrode, wherein the data storage structure comprises a lower switching layer having a dielectric material doped with a first dopant.

[0099] In some embodiments, the present application provides a storage device comprising: a substrate; a lower electrode above the substrate; an upper electrode above the lower electrode; and a data storage structure arranged between the upper and lower electrodes, wherein the data storage structure comprises a lower switching layer above the lower electrode and an upper switching layer above the lower switching layer, the lower switching layer comprising a dielectric material doped with a first dopant. In one embodiment, the lower switching layer is further doped with a second dopant that is different from the first dopant. In one embodiment, the first dopant is hydrogen, and the second dopant is nitrogen.In one embodiment, the lower switching layer has a first atomic fraction of the first dopant and a second atomic fraction of the second dopant, wherein the second atomic fraction is larger than the first atomic fraction. In another embodiment, the first atomic fraction is larger than an atomic fraction of the first dopant in the upper switching layer, and the second atomic fraction is larger than an atomic fraction of the second dopant in the upper switching layer.In one embodiment, the storage device is configured to switch between a high-resistance state and a low-resistance state. In the high-resistance state, an intrinsically conductive filament is arranged in the lower switching layer. The intrinsically conductive filament has a bottom surface that is in contact with a top surface of the upper electrode and a top surface that is spaced from the upper electrode by the upper switching layer. In the low-resistance state, the intrinsically conductive filament remains in the lower switching layer, and an upper conductive filament is provided such that it extends from the top surface of the intrinsically conductive filament through the upper switching layer to a top surface of the upper switching layer. In one embodiment, the width of the intrinsically conductive filament is less than the width of the upper conductive filament.In one embodiment, the thickness of the lower switching layer is less than the thickness of the upper switching layer. In another embodiment, the upper switching layer contains the dielectric material and does not contain the first dopant.

[0100] In some embodiments, the present application provides an integrated chip comprising: a substrate; a lower conductive wire above the substrate; an upper conductive wire above the lower conductive wire; and an RRAM cell (RRAM: resistive random access memory) arranged between the lower conductive wire and the upper conductive wire, wherein the RRAM cell comprises a capping layer above the lower conductive wire, a lower electrode below the capping layer, a lower switching layer above the lower electrode, and an upper switching layer arranged between the lower switching layer and the capping layer, wherein the lower and upper switching layers each comprise a dielectric material, and wherein the lower switching layer is co-doped with a first dopant and a second dopant, the first dopant being different from the second dopant.In one embodiment, the atomic fraction of the first and second dopants in the lower switching layer is greater than the atomic fraction of the first and second dopants in the upper switching layer. In another embodiment, the concentration of the first dopant increases continuously from the top of the lower switching layer to a first point below the top of the lower switching layer, while the concentration of the first dopant decreases continuously from the first point in one direction towards the bottom of the lower switching layer. In another embodiment, the distance between the first point and the top of the lower switching layer is smaller than the distance between the first point and the bottom of the lower switching layer.In one embodiment, the integrated chip further comprises an etch stop layer over the lower conductive wire, wherein the lower electrode is arranged in a recess defined by the etch stop layer, and the lower switching layer has a central region directly above the lower conductive wire and a peripheral region laterally offset from the recess, with a bottom surface of the central region located beneath a bottom surface of the peripheral region. In one embodiment, the bottom surface of the central region is located beneath a top surface of the etch stop layer. In another embodiment, a side wall of the lower switching layer is laterally spaced between an outer side wall of the lower electrode and an outer side wall of the capping layer.

[0101] In some embodiments, the present application provides a method for manufacturing a storage device comprising the following steps: manufacturing a lower electrode over a substrate; manufacturing a lower switching layer over the lower electrode such that the lower switching layer has a dielectric material doped with a first dopant; depositing an upper switching layer over the lower switching layer such that the atomic fraction of the first dopant in the upper switching layer is smaller than the atomic fraction of the first dopant in the lower switching layer; manufacturing an upper electrode over the upper switching layer; and structuring the lower switching layer, the upper switching layer, and the upper electrode to form a storage cell.In one embodiment, the fabrication of the lower switching layer comprises depositing a lower undoped switching layer over the lower electrode, wherein the lower undoped switching layer comprises the dielectric material, and doping the lower undoped switching layer with the first dopant and a second dopant that is different from the first dopant, so that the lower switching layer is formed over the lower electrode. In another embodiment, the fabrication of the lower switching layer comprises depositing the dielectric material over the lower electrode while it is co-doped in situ with the first dopant and a second dopant that is different from the first dopant.In one embodiment, after the lower switching layer has been manufactured and before the upper switching layer has been manufactured, one or more self-conducting filaments extend from a bottom side of the lower switching layer to a top side of the lower switching layer.

Claims

[1] Storage device (200) with: a substrate (202); a lower electrode (106) above the substrate (202); an upper electrode (116) above the lower electrode (106); and a data storage structure (108) arranged between the upper electrode (116) and the lower electrode (106), wherein the data storage structure (108) comprises a lower switching layer (110) above the lower electrode (106) and an upper switching layer (112) above the lower switching layer (110), wherein the lower switching layer (110) has a dielectric material doped with a first dopant; wherein the storage device (200) is configured to be switchable between a high-impedance state and a low-impedance state, wherein in the high-resistance state an intrinsically conductive filament is arranged in the lower switching layer (110), wherein the intrinsically conductive filament has a bottom side which is in contact with a top side of the lower electrode (106) and a top side which is spaced apart from the upper electrode (116) by the upper switching layer (112), wherein in the low-resistance state the intrinsic conductive filament remains arranged in the lower switching layer (110) and an upper conductive filament is produced such that it extends from the top of the intrinsic conductive filament through the upper switching layer (112) to a top surface of the upper switching layer (112); and wherein the concentration of the first dopant increases continuously from a top (110t) of the lower switching layer (110) to a first point below the top of the lower switching layer (110), while the concentration of the first dopant decreases continuously from the first point in a direction to a bottom (110b) of the lower switching layer (110). [2] Storage device according to claim 1, wherein the lower switching layer (110) is further doped with a second dopant which is different from the first dopant. [3] Storage device (200) according to claim 2, wherein the first dopant comprises hydrogen and the second dopant comprises nitrogen. [4] Storage device (200) according to claim 2 or 3, wherein the lower switching layer (110) has a first atomic fraction of the first dopant and a second atomic fraction of the second dopant, wherein the second atomic fraction is larger than the first atomic fraction. [5] Storage device (200) according to claim 4, wherein the first atomic fraction is larger than an atomic fraction of the first dopant in the upper switching layer (112) and the second atomic fraction is larger than an atomic fraction of the second dopant in the upper switching layer (112). [6] Storage device (200) according to one of the preceding claims, wherein a width (w1) of the intrinsically conductive filament is smaller than a width (w2) of the upper conductive filament. [7] Storage device (200) according to one of the preceding claims, wherein a thickness (t1) of the lower switching layer (110) is smaller than a thickness (t2) of the upper switching layer (112). [8] Storage device (200) according to one of the preceding claims, wherein the upper switching layer (112) comprises the dielectric material but does not have the first dopant. [9] Storage device (200) according to one of the preceding claims, wherein the thickness (t1) of the lower switching layer (110) is 1.5 nm to 2 nm, and the thickness (t2) of the upper switching layer (112) is 2 nm to 3 nm. [10] Integrated chip (200) with: a substrate (202); a lower conductive wire (216) above the substrate (202); an upper conductive wire (218) above the lower conductive wire (216); and a resistive random access memory cell (104) arranged between the lower conductive wire (216) and the upper conductive wire (218), wherein the resistive random access memory cell (104) comprises a capping layer (114) over the lower conductive wire (216), a lower electrode (106) below the capping layer (114), a lower switching layer (110) above the lower electrode (106), and an upper switching layer (112) arranged between the lower switching layer (110) and the capping layer (114), wherein the lower and upper switching layers (110, 112) each comprise a dielectric material, wherein the lower switching layer (110) is co-doped with a first dopant and a second dopant, the first dopant being different from the second dopant; wherein the concentration of the first dopant increases continuously from a top (110t) of the lower switching layer (110) to a first point below the top of the lower switching layer (110), while the concentration of the first dopant decreases continuously from the first point in a direction to a bottom (110b) of the lower switching layer (110). [11] Integrated chip according to claim 10, wherein the atomic fraction of the first and second dopants in the lower switching layer (110) is greater than the atomic fraction of the first and second dopants in the upper switching layer (112). [12] Integrated chip (200) according to one of claims 10 or 11, wherein the thickness (t1) of the lower switching layer (110) is 1.5 nm to 2 nm, and the thickness (t2) of the upper switching layer (112) is 2 nm to 3 nm. [13] Integrated chip according to claim 12, wherein a distance between the first point and the top (110t) of the lower switching layer (110) is smaller than a distance between the first point and the bottom (110b) of the lower switching layer (110). [14] Integrated chip (500a, 500b) according to any one of claims 10 to 13, further comprising: an etch stop layer (404) over the lower conductive wire (216), wherein the lower electrode (106) is arranged in a recess defined by the etch stop layer (404), wherein the lower switching layer (110) has a central area (502m) directly above the lower conductive wire (216) and a peripheral area (502p) which is laterally offset from the recess, wherein a bottom side of the central area (502m) is located below a bottom side of the peripheral area (502p). [15] Integrated chip (200) according to claim 14, wherein the underside of the middle region (502m) is located under a top surface of the etch stop layer (404). [16] Integrated chip (200) according to one of claims 10 to 15, wherein a side wall of the lower switching layer (110) is laterally spaced between an outer side wall of the lower electrode (106) and an outer side wall of the capping layer (114). [17] Method for manufacturing a storage device (200) comprising the following steps: Establishing a lower electrode (106) over a substrate (202); Producing a lower switching layer (110) over the lower electrode (106) such that the lower switching layer (110) has a dielectric material doped with a first dopant; Deposition of an upper switching layer (112) over the lower switching layer (110) such that the atomic fraction of the first dopant in the upper switching layer (112) is smaller than the atomic fraction of the first dopant in the lower switching layer (110); Creating an upper electrode (116) above the upper switching layer (112); and Structuring the lower switching layer (110), the upper switching layer (112) and the upper electrode (116) so that a resistive direct access memory cell (104) is created; the fabrication of the lower switching layer (110) comprises the following: Deposition of the dielectric material above the lower electrode (106) while it is co-doped in situ with the first dopant and a second dopant that is different from the first dopant. [18] Method according to claim 17, wherein after the production of the lower switching layer (110) and before the production of the upper switching layer (112) one or more self-conducting filaments extend from a bottom side (110b) of the lower switching layer (110) to a top side (110t) of the lower switching layer (110). [19] Method according to one of claims 17 or 18, wherein the thickness (t1) of the lower switching layer (110) is 1.5 nm to 2 nm, and the thickness (t2) of the upper switching layer (112) is 2 nm to 3 nm. [20] Method according to any one of claims 17 to 19, wherein the concentration of the first dopant increases continuously from a top side (110t) of the lower switching layer (110) to a first point below the top side of the lower switching layer (110), while the concentration of the first dopant decreases continuously from the first point in a direction to a bottom side (110b) of the lower switching layer (110).

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