Storage cells and storage devices with a dielectric layer with high electron affinity for improving a cyclic flow and method for manufacturing

Abstract

Memory cell (102), comprising: a lower electrode (106); an upper electrode (108) that lies above the lower electrode (106); and a dielectric stack (104) comprising several dielectric layers (104h, 104l1, 104l2) stacked between the lower and upper electrodes (106, 108); wherein the multiple dielectric layers (104h, 104l1 104l1, 104l2) have a first dielectric layer (104h) and the first dielectric layer (104h) those of the dielectric layers (104h, 104l) n 104l1, 104l2) is the one that is closest to the lower electrode (106) and has the highest electron affinity (X1) from the dielectric layers (104h, 104l1 104l1, 104l2), wherein the multiple dielectric layers (104h, 104l, 104l1, 104l2) have a second dielectric layer (104l1) and a third dielectric layer (10412), and wherein the second dielectric layer (104l1) is located between the first and the third dielectric layer (104h, 104l2), wherein the second dielectric layer (104l1) has an electron affinity (X2) between that of the first dielectric layer (104h) and that of the third dielectric layer (104l2), or wherein the third dielectric layer (10412) has an electron affinity (X3) between that of the first dielectric layer (104h) and that of the second dielectric layer (104l1).

Description

BACKGROUND

[0001] Many current electronic devices incorporate non-volatile memory. Non-volatile memory is electronic storage capable of retaining data in the absence of power. Some promising candidates for the next generation of non-volatile memory include oxygen-ion resistive random-access memory (RRAM) and metal-ion resistive random-access memory (RRAM). Both types of RRAM have relatively simple structures and are compatible with complementary metal-oxide-semiconductor logic (CMOS) fabrication processes.

[0002] A memory cell, a storage device, and a manufacturing method are known from publication WO 2019 / 066 849 A1. Further memory cells and storage devices are known from publications KR 10 2017 0 093 281 A, US 2018 / 0 309 054 A1, US 2014 / 0 367 631 A1, DE 10 2007 021 761 B4, US 2007 / 0 018 219 A1, DE 10 2015 102 767 A1, and US 2016 / 0 218 283 A1. The objective is to improve corresponding memory cells and storage devices. This objective is achieved by the memory cell according to claim 1, the storage device according to claim 7, and the method according to claim 14. Further details are set out in the dependent patent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 illustrates a cross-sectional view of some embodiments of a memory cell in which a high electron affinity dielectric layer (HEA dielectric layer) is located at a lower electrode. Fig. Figure 2 illustrates a graph of some embodiments of electron affinities for dielectric layers, which feature the dielectric HEA layer, in the memory cell of Fig. 1. Fig. Figure 3 illustrates a table that lists electron affinities for different materials. Fig. 4A and Fig. Figure 4B illustrates cross-sectional views of some embodiments of the memory cell of Fig. 1 during an actuation or reset operation. Fig. Figure 5 illustrates a cross-sectional view of some alternative embodiments of the memory cell of Fig. 1, in which the memory cell further has a cap layer. Fig. Figure 6 illustrates a cross-sectional view of some alternative embodiments of the memory cell of Fig. 1, in which the memory cell has three or more dielectric layers. Fig. Figure 7 illustrates a cross-sectional view of some embodiments of the memory cell of Fig. 6, in which the storage cell is limited to three dielectric layers. Fig. 8A and Fig. Figure 8B illustrates graphs of different embodiments of electron affinities for dielectric layers, which feature the dielectric HEA layer, in the memory cell of Fig. 7. Fig. Figure 9 illustrates a cross-sectional view of some alternative embodiments of the memory cell of Fig. 6, in which the memory cell further has a cap layer. Fig. Figure 10 illustrates a cross-sectional view of some embodiments of the memory cell of Fig. 1, in which the memory cell is integrated into a connection structure of an integrated circuit chip (IC chip). Fig. 11A and Fig. Figure 11B illustrates cross-sectional views of various alternative embodiments of the memory cell of Fig. 10. Fig. 12A and Fig. Figure 12B illustrates cross-sectional views of some embodiments of an IC chip comprising multiple memory cells integrated into individual one-transistor-one-resistor (1T1R) cells, each as shown in Fig. 10 are configured. Fig. Figure 13 illustrates an upper layout of some embodiments of the IC chip of Fig. 12A and Fig. 12B. Fig. Figure 14 illustrates a schematic diagram of some embodiments of a 1T1R cell in Fig. 12A and Fig. 12B. Fig. Figures 15A-15C illustrate schematic diagrams of various alternative embodiments of the 1T1R cell from Fig. 14, in which access transistors are varied. Fig. Figures 16-23 illustrate a series of cross-sectional views of some embodiments of a method for forming memory cells integrated with 1T1R cells, comprising individual dielectric HEA layers on appropriate lower electrodes. Fig. Figure 24 illustrates a block diagram of some embodiments of the method of Fig. 16-23. Fig. Figures 25-29 illustrate a series of cross-sectional views of some alternative embodiments of the method of Fig. 16-23, in which layers, from which the storage cells are formed, are structured using planarization. Fig. Figure 30 illustrates a block diagram of some embodiments of the method of Fig. 25-29. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and may also include embodiments in which additional elements may be formed between the first and second elements, so that the first and second elements are not in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not itself establish any relationship between the various designs and / or configurations discussed.

[0005] Furthermore, spatial terms such as "below," "under," "lower," "above," "upper," and the like can be used here for simple description to convey the relationship of one element or feature to one or more other elements or features depicted in the figures. These spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatial descriptors used here can be interpreted accordingly.

[0006] Some resistive random-access memory (RRAM) cells have a lower electrode, an upper electrode positioned above the lower electrode, and a single dielectric layer between the lower and upper electrodes. The single dielectric layer contains a metal oxide and has a single material composition throughout. During a drive operation, a positively polarized drive voltage is applied from the upper electrode to the lower electrode to form a conductive filament in the single dielectric layer. The conductive filament electrically couples the lower electrode to the upper electrode, placing the RRAM cell in a low-resistance state (LRS). During a reset operation, a negatively polarized reset voltage is applied from the upper electrode to the lower electrode to at least partially dissolve the conductive filament.As such, the RRAM cell is in a high resistance state (HRS). Since the resistance of the RRAM cell changes during the setting and resetting process, this resistance can be used to represent a bit of data. For example, the LRS can represent a binary "1", while the HRS can represent a binary "0", or vice versa.

[0007] One challenge with RRAM cells is that they can become stuck in the LRS during cyclic read / write operations. This typically occurs after many cycles. While stuck, the RRAM cell can be considered a hard reset bit. Furthermore, the read current through the RRAM cell can be greater than or approximately the same as when the RRAM cell is in the LRS. The RRAM cell typically remains stuck for many cycles and can thus be considered a hard error bit. As such, the RRAM cell can be subjected to error correction code (ECC) correction by an ECC device if it is one of many identical RRAM cells defining an RRAM array.However, ECC devices can be designed to correct random soft error bits, not hard error bits, and therefore hard error bits can consume ECC capacity intended for random soft error bits. To the extent that the hard error bits consume too much ECC capacity, an ECC device can become overloaded and unable to correct random soft error bits. This, in turn, can lead to an RRAM array failure.

[0008] Various embodiments of the present disclosure relate to a memory cell comprising a high electron affinity dielectric layer (high-electron affinity dielectric layer) at a lower electrode, as well as a method for forming the memory cell. The memory cell can be, for example, an RRAM cell or another suitable type of memory cell. The high-electron affinity dielectric layer is one of several different dielectric layers stacked vertically between the lower electrode and an upper electrode located above the lower electrode. Furthermore, the high-electron affinity dielectric layer is the one closest to the lower electrode among the various dielectric layers. The various dielectric layers differ with respect to their material systems and / or material compositions.Different material systems correspond to different sets of elements, while different material compositions correspond to different ratios of elements for the same set of elements.

[0009] It is evident that by arranging the dielectric HEA layer closest to the bottom electrode, the probability of the memory cell becoming stuck during a cyclic pass is reduced, at least if the memory cell is RRAM. Therefore, the probability of a hard reset / error bit is reduced. Since the probability of a hard reset / error bit is reduced, there is less chance that ECC capacity for a memory array to which the memory cell belongs will be used by hard reset / error bits. Since there is less chance that ECC capacity will be used by hard reset / error bits, there is less chance that ECC capacity for the memory array will be overloaded by hard reset / error bits. Therefore, there is less chance of memory array failure.Since the dielectric HEA layer reduces the probability of memory array failure, no additional ECC capacity is necessary. This, in turn, saves IC chip area that can be used for additional ECC capacity in other ways.

[0010] As will be shown below, the dielectric HEA layer can be integrated into storage processes with an additional deposition step. As such, the dielectric HEA layer adds little to no additional cost to the storage process. Furthermore, the integration is compatible with 40-nanometer process nodes and smaller.

[0011] With reference to Fig. Figure 1 shows a cross-sectional view of some embodiments of a memory cell 102, in which a dielectric HEA layer 104h is located at a lower electrode 106. The memory cell 102 can be, for example, an oxygen-ion type RRAM cell, a metal-ion type RRAM cell, or another suitable type of memory cell. It should be noted that a metal-ion type RRAM cell can also be referred to as a conductive bridging RAM (CBRAM).

[0012] The dielectric HEA layer 104h is one of several dielectric layers 104 stacked vertically above the lower electrode 106, separating the lower electrode 106 from an upper electrode 108 located above the lower electrode 106. Furthermore, the dielectric HEA layer 104h has the highest electron affinity and is the closest of the several dielectric layers 104 to the lower electrode 106. Thus, the dielectric HEA layer 104h has a "high" electron affinity relative to the rest of the several dielectric layers 104.

[0013] The electron affinity for a dielectric layer is an energy difference between a lower conductive band edge of the dielectric layer and the vacuum level. The vacuum level is the same for the multiple dielectric layers 104 and can be, for example, about 4.05 electron volts (eV). Since the vacuum level is the same for the multiple dielectric layers 104, lower conductive band edges of the multiple dielectric layers 104 each define electron affinities of the multiple dielectric layers 104. Furthermore, the lower conductive band edge of the dielectric HEA layer 104h is the lowest of the multiple dielectric layers 104.

[0014] It was found that by arranging the dielectric HEA layer 104h in close proximity to the lower electrode 106, the probability of memory cell 102 getting stuck during a cyclic cycle is reduced, at least when memory cell 102 is RRAM. For example, it is highly likely that memory cell 102 will get stuck during a reset operation when transitioning from an LRS to an HRS. Since the dielectric HEA layer 104h has the highest electron affinity of the multiple dielectric layers 104 and is located near the lower electrode 106, electrons can more easily pass through the multiple dielectric layers 104 during the reset operation. Therefore, the probability of memory cell 102 getting stuck during the cyclic cycle is reduced.

[0015] Since the probability of memory cell 102 becoming stuck during a cyclic pass is reduced, the probability of a hard reset / error bit is also reduced. Because the probability of a hard reset / error bit is reduced, the probability of the ECC capacity for a memory array (not shown) containing memory cell 102 being used by hard reset / error bits is lower. Thus, the probability of memory array failure is less likely. Because the probability of memory array failure is reduced by the dielectric HEA layer 104h, no additional ECC capacity, and therefore no additional IC chip area, is required.

[0016] With continued reference to Fig. In the embodiment 1, the multiple dielectric layers 104 are vertically stacked and define a dielectric structure extending from the lower electrode 106 to the upper electrode 108. Furthermore, the multiple dielectric layers 104 have two dielectric layers: 1) the HEA dielectric layer 104h; and 2) a low electron affinity dielectric layer (LEA dielectric layer) 104l. The LEA dielectric layer 104l lies above and adjacent to the HEA dielectric layer 104h and has a low electron affinity relative to the HEA dielectric layer 104h. In alternative embodiments, the multiple dielectric layers 104 have three or more different dielectric layers.

[0017] Each of the dielectric HEA and LEA layers 104h and 104l can be, for example, a metal oxide, a metal oxynitride, a component metal oxide, another suitable dielectric (or other suitable dielectrics), or any combination thereof. Furthermore, each of the dielectric HEA and LEA layers 104h and 104l can be, for example, titanium oxide (e.g., TiO2), hafnium oxide (e.g., HfO2), or hafnium aluminum oxide (e.g., Hf). x Al 1-x O2), tantalum oxide (e.g. Ta2O5), hafnium tantalum oxide (e.g. Hf x Ta 1-xThe dielectric may be tungsten oxide (e.g., WO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), sulfated tin oxide (e.g., STO), another suitable dielectric, or any combination thereof. In some embodiments, the HEA dielectric layer 104h is a high-k dielectric and / or the LEA dielectric layer 104l is a high-k dielectric. A high-k dielectric may, for example, be a dielectric with a dielectric constant k greater than approximately 3.9, 10.0, or another suitable value.

[0018] The dielectric HEA and LEA layers 104h and 104l have different material systems or different material compositions. Different material systems correspond to different sets of elements. Different material compositions correspond to different ratios of elements for the same set of elements (e.g., the same material systems).

[0019] In embodiments where the dielectric HEA and LEA layers 104h and 104l have different material systems, the dielectric HEA layer 104h consists of, or essentially consists of, a first set of elements, and the dielectric LEA layer 104l consists of, or essentially consists of, a second set of elements that differs from the first set of elements. For example, the dielectric HEA layer 104h can be aluminum oxide (e.g., Al₂O₃), and the dielectric LEA layer 104l can be silicon oxide (e.g., SiO₂). However, other suitable materials are possible.

[0020] In embodiments where the dielectric HEA and LEA layers 104h and 104l have different material compositions, the dielectric HEA layer 104h consists of, or essentially consists of, a set of elements. Furthermore, the dielectric LEA layer 104l consists of, or essentially consists of, the set of elements, but has a different ratio of elements compared to the dielectric HEA layer 104h. For example, the dielectric HEA layer 104h can be aluminum oxide (e.g., Al₂O₃), and the dielectric LEA layer 104l can be aluminum oxide with a different ratio of aluminum to oxide (e.g., Al₂O₃). x O y , where x ≠ 2 and y ≠ 3). However, other suitable materials are possible.

[0021] The dielectric HEA and LEA layers 104h and 104l have individual thicknesses T. d In some embodiments, the thicknesses T dapproximately 1-50 nanometers, approximately 1-25 nanometers, approximately 25-50 nanometers, or another suitable value. If the thickness T d If the dielectric thickness of the HEA or LEA layer 104h, 104l is too small (e.g., less than about 1 nanometer or another suitable value), the advantages of the material properties of the dielectric layer cannot be realized. For example, if the thickness T d If the thickness of the dielectric HEA layer 104h is too small, the dielectric HEA layer 104h cannot reduce the probability of the memory cell 102 becoming stuck. If the thickness T d If the diameter of the dielectric HEA or LEA layer 104h, 104l is too large (e.g., more than approximately 50 nanometers or another suitable value), the operating voltages of the memory cell 102 may be too high. These high voltages can, for example, increase power consumption, reduce the lifetime of the memory cell 102, and increase the risk of device failure.

[0022] The upper and lower electrodes 106, 108 are conductive and delimit the multiple dielectric layers 104. The lower electrode 106 can be, for example, a metal, a metal nitride, a metal oxide, doped polysilicon, another suitable conductive material, or any combination thereof. The upper electrode 108 can be, for example, a metal, a metal nitride, doped polysilicon, another suitable conductive material, or any combination thereof. The upper and lower electrodes 106, 108 can be, for example, aluminum (e.g., Al), titanium (e.g., Ti), tantalum (e.g., Ta), gold (e.g., Au), platinum (e.g., Pt), tungsten (e.g., W), nickel (e.g., Ni), iridium (e.g., Ir), titanium nitride (e.g., TiN), tantalum nitride (e.g., B2), or tungsten nitride (e.g., B2).TaN), N-doped polysilicon, P-doped polysilicon, another suitable conductive material (other suitable conductive materials) or any combination of the above.

[0023] With reference to Fig. Figure 2 is a graphic of 200 of some embodiments of electron affinities for the dielectric HEA and LEA layers 104h, 104l of Fig. 1 provided. The vertical axis corresponds to energy and the horizontal axis corresponds to a position along line A in Fig. 1. A first band gap 202 of the dielectric HEA layer 104h is from a vacuum energy level E vac A first Fermi level 204 of the lower electrode 106 is spaced and limited by a first electron affinity X1. A second band gap 206 of the dielectric LEA layer 104l is separated from the vacuum energy level E vacseparated by a second electron affinity X2, which is smaller than the first electron affinity X1. Furthermore, the second band gap 206 limits a second Fermi level 208 of the upper electrode 108. The first and second Fermi levels 204, 208 are the same, but can alternatively be different.

[0024] It should be noted that the upper edge of the first band gap 202 corresponds to a conductive lower band edge of the dielectric HEA layer 104h, while the upper edge of the second band gap 206 corresponds to a conductive lower band edge of the dielectric LEA layer 104l. Thus, the conductive lower band edge of the dielectric HEA layer 104h is lower than the conductive lower band edge of the dielectric LEA layer 104l.

[0025] As described above, it is evident that arranging the dielectric HEA layer 104h in close proximity to the lower electrode 106 reduces the probability of memory cell 102 becoming stuck during the cyclic pass, at least if the memory cell is RRAM. Thus, the probability of a hard reset / error bit is reduced. Since the probability of a hard reset / error bit is reduced, the probability of ECC capacity for a memory array (not shown) containing memory cell 102 being used by hard reset / error bits is lower. Therefore, the probability of memory array failure is less likely.

[0026] To determine the first and second electron affinities X1 and X2, respectively, of the dielectric HEA and LEA layers 104h and 104l, the first and second electron affinities X1 and X2 can be measured by X-ray photoelectron spectroscopy (XPS) or by other suitable methods. Alternatively, the materials of the dielectric HEA and LEA layers 104h and 104l can be found in the table of Fig. Reference 3 lists the materials and their corresponding electron affinities. For example, assuming that the dielectric HEA layer is 104h Al2O3 and the dielectric LEA layer is 104l SiO2, the following can be found by referring to the table in Fig. 3 shows that the first and second electron affinities X1, X2 are approximately 1.25 eV and approximately 0.55 eV respectively.

[0027] If a material of the dielectric HEA or LEA layer 104h, 104l is not in the table of Fig. 3 is found, but a mixture of two or more materials is found in the table of Fig. If the electron affinity of the material is found in the table below, it can be calculated from the electron affinities of the two or more materials. Specifically, the electron affinity of the material can be calculated as a weighted sum of the electron affinities of the two or more materials, using the atomic percent of each material as the respective weight for the electron affinities. For example, the dielectric HEA or LEA layer is assumed to be 104h, 104l ZrTiO4. ZrTiO4 is not found in the table below. Fig. 3 was found, but it is a mixture of TiO2 and ZrO2. TiO2 and ZrO2 each have an atomic percentage of approximately 50 in ZrTiO4. Further, as with reference to the table of Fig. As can be seen in Figure 3, the electron affinities for ZrO₂ and TiO₂ are approximately 2.65 eV and 2.85 eV, respectively. Therefore, the electron affinity of ZrTiO₄ is approximately equal to 2.65 eV * 0.5 + 2.85 eV * 0.5, which is approximately equal to 2.75 eV. Although the determination of electron affinity has been illustrated using ZrTiO₄, other suitable materials are possible.

[0028] With reference to Fig. 4A and Fig. 4B are cross-sectional views 400A, 400B of some embodiments of the memory cell 102 of Fig. 1 provided during a positioning operation and a reset operation. In Fig. At 4A, a control voltage (e.g., V+ to V- or GND) with a positive polarity is applied from the upper electrode 108 to the lower electrode 106 to form a conductive filament 402 within the multiple dielectric layers 104. The conductive filament 402 electrically couples the upper electrode 108 to the lower electrode 106, so that the memory cell 102 is in a linear resonant circuit (LRS). Fig. In step 4B, a reset voltage (e.g., V- to V+ or GND to V+) with a negative polarity is applied from the upper electrode 108 to the lower electrode 106 to at least partially dissolve the conductive filament 402. Since the conductive filament 402 is at least partially dissolved, the memory cell 102 is in a high-resolution state (HRS). Because a resistance of the memory cell 102 changes during the setting and resetting operation, this resistance can be used to represent a bit of data. For example, the low-resolution state (LRS) can represent a binary "1," while the high-resolution state (HRS) can represent a binary "0," or vice versa.

[0029] In some embodiments, the memory cell 102 is an oxygen-ion type RRAM cell. During the actuation phase for at least some embodiments of the oxygen-ion type RRAM cell, oxygen ions move from the multiple dielectric layers 104 to a reservoir region (not shown) between the multiple dielectric layers 104 and the upper electrode 108. Movement of the oxygen ions leaves oxygen vacancies that form the conductive filament 402 in the multiple dielectric layers 104. During the reset phase for at least some embodiments of the oxygen-ion type RRAM cell, oxygen ions move from the reservoir region to the multiple dielectric layers 104 to fill the oxygen vacancies and break the conductive filament 402.

[0030] In some embodiments, the memory cell 102 is a metal-ion RRAM cell. During the actuation phase of at least some embodiments of the metal-ion RRAM cell, the upper electrode 108 oxidizes to form metal ions. The metal ions then migrate to the multiple dielectric layers 104 and reduce into the conductive filament 402. During the reset phase of at least some embodiments of the metal-ion RRAM cell, the conductive filament 402 oxidizes to form metal ions. The metal ions then migrate to the upper electrode 108 and reduce into the upper electrode 108. This, in turn, breaks the conductive filament 402. In some embodiments where the memory cell 102 is the metal-ion RRAM cell, the conductive filament 402 is Fig. 4A and Fig. 4B is vertically inverted and extends from the lower electrode 106 into Fig. 4A and Fig. 4B.

[0031] With reference to Fig. Figure 5 is a cross-sectional view of 500 of some alternative embodiments of the memory cell 102 of Fig. 1 provided, in which the storage cell 102 further comprises a cap layer 502. The cap layer 502 is located between the upper electrode 108 and the several dielectric layers 104 and has a high affinity for oxygen compared to the lower and upper electrodes 106, 108. In other words, the cap layer 502 requires less energy to react with oxygen than the lower and upper electrodes 106, 108.

[0032] In at least some embodiments where the memory cell 102 is an oxygen-ion type RRAM cell, the reservoir region (not shown) is located between the multiple dielectric layers 104 and the cap layer 502. Furthermore, since the cap layer 502 has a high affinity for oxygen, it increases the size of the reservoir region. As such, more oxygen ions can be stored while the memory cell 102 is in standby mode and thus in LRS mode. Because more oxygen ions can be stored, the conductive filament 402 (see, for example, Figure 5) can be extended. Fig. 4A and Fig. 4B) have a higher density of oxygen vacancies, and therefore the LRS can have a lower resistance. This in turn can increase the difference between the resistances of memory cell 102 in the LRS and HRS, and thus can enlarge the switching windows.

[0033] In at least some embodiments where the memory cell 102 is a metal-ion RRAM cell, the cap layer 502 oxidizes during switching operation instead of the upper electrode 108. Furthermore, since the cap layer 502 has a high affinity for oxygen relative to the upper electrode 108, it oxidizes more readily than the upper electrode 108. As such, the switching operation can utilize a lower switching voltage, which can improve power efficiency and / or increase the lifetime of the memory cell 102. Additionally, the density of metal ions can be higher, and thus the density of metal in the conductive filament 402 can be higher. This, in turn, increases the difference between the resistances of the memory cell 102 in the LRS and HRS, and can therefore enlarge the switching window.

[0034] The cap layer 502 can be, for example, aluminum, titanium, tantalum, hafnium, titanium oxide, hafnium oxide, zirconium oxide, germanium oxide, cerium oxide, some other suitable material(s), or any combination thereof. In some embodiments, the cap layer 502 is conductive and / or metallic. For example, in embodiments where the memory cell 102 is a metal-ion RRAM cell, the cap layer 502 is conductive and metallic. In alternative embodiments, the cap layer 502 is dielectric. In embodiments where the cap layer 502 is dielectric, the cap layer 502 has a lower electron affinity and a higher conductive band edge than the dielectric HEA layer 104h.

[0035] With reference to Fig. Figure 6 is a cross-sectional view of 600 of some alternative embodiments of the memory cell 102 of Fig. 1 provided, in which the multiple dielectric layers 104 have three or more dielectric layers: 1) the dielectric HEA layer 104h; and 2) two or more dielectric LEA layers (labeled 104l1 to 104l n , where n is an integer greater than 1).

[0036] Each of the two or more dielectric LEA layers 104l1, ..., 104l n is, like the dielectric LEA layer 104l of Fig. 1 is described. Thus, each of the two or more dielectric LEA layers has 104l1, ..., 104l n a lower electron affinity than the dielectric HEA layer 104h. Furthermore, each of the two or more dielectric LEA layers 104l1, ..., 104l has a lower electron affinity than the dielectric HEA layer 104h. n a different material system or material composition than the dielectric HEA layer 104h. In some embodiments, each of the two or more dielectric LEA layers 104l1, ..., 104l differs. nfrom each adjacent dielectric LEA layer and / or each other dielectric LEA layer.

[0037] With reference to Fig. Figure 7 is a cross-sectional view of 700 of some embodiments of the memory cell 102 of Fig. 6 provided, in which the memory cell 102 is limited to two dielectric LEA layers: a first dielectric LEA layer 104l1; and a second dielectric LEA layer 104l2. In other words, the integer n in Fig. 6 equals 2.

[0038] With reference to Fig. 8A and Fig. Figures 8B are graphs 800A and 800B of different embodiments of electron affinities for the dielectric HEA layer 104h of Fig. 7 and the first and second and second dielectric LEA layer 104l1, 104l2 of Fig. 7 provided. The vertical axis corresponds to energy and the horizontal axis corresponds to the position along line B in Fig. 7.

[0039] A first band gap 802 of the dielectric HEA layer 104h is from a vacuum energy level E vac A first Fermi level 204 of the lower electrode 106 is spaced and limited by a first electron affinity X1. A second band gap 804 of the first dielectric LEA layer 104l1 is separated from the vacuum energy level E vac a second electron affinity X2 separates it. A third band gap 806 of the second dielectric LEA layer 104l2 is separated from the vacuum energy level E. vac A second Fermi level 208 of the upper electrode 108 is spaced apart and limited by a third electron affinity X3. As explained above, the second and third electron affinities X2, X3 are lower than the first electron affinity X1 to prevent the memory cell 102 from getting stuck during the cyclic pass, at least if the memory cell is RRAM.

[0040] It should be noted that the upper edge of the first band gap 802 corresponds to a conductive lower band edge of the dielectric HEA layer 104h, and the upper edges of the second and third band gaps 804, 806 correspond to conductive lower band edges of the first and second dielectric LEA layers 104l1, 104l2. Thus, the conductive lower band edge of the dielectric HEA layer 104h is lower than the conductive lower band edges of the first and second dielectric LEA layers 104l1, 104l2.

[0041] With reference in particular to Fig. 8A, the first electron affinity X1 is greater than the second electron affinity X2, which is greater than the third electron affinity X3. Thus, the electron affinity of a dielectric structure formed by the multiple dielectric layers 104 of Fig. 7 is defined, discretely from the lower electrode 106 to the upper electrode 108. Furthermore, the conductive lower edge of the dielectric structure has a stepped profile that rises in steps from the lower electrode 106 to the upper electrode 108.

[0042] With reference in particular to Fig. 8B, the first electron affinity X1 is greater than the second electron affinity X1, and the third electron affinity X3 is between the first and second electron affinities X1 and X2. Thus, the electron affinity of the dielectric structure formed by the multiple dielectric layers 104 of Fig. The conductive band edge of the dielectric structure, as defined in section 7, decreases discretely and then increases discretely from the lower electrode 106 to the upper electrode 108. Furthermore, the conductive band edge of the dielectric structure rises in steps and then increases in steps from the lower electrode 106 to the upper electrode 108. In alternative embodiments, the dielectric structure has other suitable electron affinity profiles and / or conductive band edge profiles.

[0043] With reference to Fig. Figure 9 is a cross-sectional view of 900 of some alternative embodiments of the memory cell 102 of Fig. 6 provided in which the memory cell 102 further comprises a cap layer 502. The cap layer 502 can, for example, be as described in relation to Fig. 5 described. Thus, the cap layer 502 can, for example, provide an enlarged switching window, reduced power consumption, other suitable advantages, or any combination of the above.

[0044] With reference to Fig. Figure 10 is a cross-sectional view of 1000 of some embodiments of the memory cell 102 of Fig. Figure 1 shows that the memory cell 102 is located in a connection structure 1002 of an IC chip. The memory cell 102 lies below an upper electrode wire 1004t and an upper electrode via 1006t. Furthermore, the memory cell 102 lies above a lower electrode wire 1004b and a lower electrode via 1008.

[0045] The upper electrode via 1006t extends downwards from the upper electrode wire 1004t to the upper electrode 108. The upper electrode via 1006t further extends through a hard mask 1010 on the upper surface of the upper electrode 108. In alternative embodiments, the hard mask 1010 is omitted. The hard mask 1010 can be, for example, silicon nitride and / or another suitable dielectric (or other suitable dielectrics). The upper electrode wire 1004t and the upper electrode via 1006t can be, for example, copper, aluminum, aluminum-copper alloy, some other suitable metal(s), or any combination thereof.

[0046] The lower electrode via 1008 extends upwards from the lower electrode wire 1004b to the lower electrode 106 and comprises a via connector 1008p and a via lining 1008l. In alternative embodiments, the via lining 1008l is omitted. The lower electrode wire 1004b can be, for example, copper, aluminum, aluminum-copper, some other suitable metal(s), or any combination thereof.

[0047] The via lining 1008l surrounds a bottom surface of the via connector 1008p to separate the via connector 1008p from the lower electrode wire 1004b. In some embodiments, the via lining 1008l is an adhesive layer to reinforce the deposition of a layer from which the via connector 1008p is formed. In some embodiments, the via lining 1008l is a diffusion barrier layer that prevents material from the lower electrode wire 1004b from diffusing upwards to the via connector 1008p and / or the lower electrode 106. The via lining 1008l may, for example, be or contain tantalum nitride and / or some other suitable conductive barrier material(s).The via connector 1008p can be, for example, titanium nitride, aluminum, titanium, tantalum, gold, platinum, tungsten, another suitable conductive material, or any combination thereof. In some embodiments, the via connector 1008p is integrated into the lower electrode 106 or is made of the same material, so that there is no boundary between the lower electrode 106 and the via connector 1008p.

[0048] A dielectric structure surrounds the memory cell 102 as well as the upper electrode wire 1004t, the upper electrode via 1006t, the lower electrode wire 1004b, and the lower electrode via 1008. The dielectric structure includes the hard mask 1010 and a sidewall spacer structure 1012 on the sidewall(s) of the upper electrode 108. The sidewall spacer structure 1012 can be, for example, silicon nitride and / or another suitable dielectric. Additionally, the dielectric structure includes several intermetal dielectric (IMD) layers 1014, a dielectric via layer 1016, and an etch stop layer 1018.

[0049] The IMD layers 1014 surround the lower electrode wire 1004b and the upper electrode wire 1004t, respectively. The IMD layers 1014 can be, for example, an extremely low k-dielectric and / or another suitable dielectric (or other suitable dielectrics).

[0050] The dielectric via layer 1016 and the etch stop layer 1018 are stacked between the IMD layers 1014. The dielectric via layer 1016 surrounds the lower electrode via 1008 between the memory cell 102 and the lower electrode wire 1004b. The dielectric via layer 1016 can be, for example, silicon carbide, silicon-rich oxide, another suitable dielectric (or other suitable dielectrics), or any combination thereof. The etch stop layer 1018 covers the dielectric via layer 1016 and wraps around a top surface of the memory cell 102. The etch stop layer 1018 can be, for example, silicon carbide and / or another suitable dielectric (or other suitable dielectrics).

[0051] With reference to Fig. 11A and Fig. 11B are cross-sectional views 1100A, 1100B of various alternative embodiments of the memory cell 102 of Fig. 10 provided. In Fig. 11A the memory cell 102 further has a cap layer 502, as in relation to Fig. 5 described. Furthermore, the side wall spacer structure 1012 is located on side walls of the cap layer 502. In Fig. In 11B, the memory cell 102 is located directly on the lower electrode wire 1004b, and each individual layer of the memory cell 102, with the exception of the upper electrode 108, has a U-shaped or V-shaped profile. However, other suitable profiles are possible in alternative embodiments. Furthermore, the relative positioning between features has been rearranged, and the lower electrode via 1008, the side wall spacer structure 1012, and the hard mask 1010 are omitted.

[0052] Memory cell 102 of Fig. Memory cell 102 can be formed using a single photolithography / etching process. For example, the dielectric via layer 1016 and an adjacent IMD layer 1014 can be deposited over the lower electrode wire 1004b. The dielectric via layer 1016 and the IMD layer can then be patterned to define a memory cell opening that exposes the lower electrode wire 1004b. Furthermore, the individual layers that make up memory cell 102 can be conformally deposited within the memory cell opening, covering the IMD layer. Once the layers are deposited, planarization can be performed to expose the IMD layer and pattern the layers to form memory cell 102. Since photolithography is expensive, forming memory cell 102 can be achieved using a single photolithography / etching process. Fig. 11B can achieve significant cost savings through a single photolithography / etching process.

[0053] With reference to Fig. Figure 12A is a cross-sectional view 1200A of some embodiments of an IC chip having multiple memory cells 102, in which the memory cells 102 are integrated into individual one-transistor-one-resistor (1T1R) cells 1202 and each as in Fig. 10 is configured. The 1T1R cells 1202 have individual drain areas 1204 and individual drain-side conductive paths 1206.

[0054] The drain regions 1204 are doped regions of a substrate 1208, and each has a doping type opposite to an adjacent region of the substrate 1208. Furthermore, the drain regions 1204 are electrically separated from one another by a trench isolation structure 1210 and partially define access transistors 1212 (partially shown) used for individually selecting the memory cells 102. The trench isolation structure 1210 extends into a top surface of the substrate 1208 and contains silicon oxide and / or some other suitable dielectric material. The trench isolation structure 1210 can, for example, be a shallow trench isolation (STI) structure or some other suitable trench isolation structure. The substrate 1208 can be, for example, a bulk silicon substrate, a silicon-on-insulator (SOI) substrate, or some other suitable semiconductor substrate.

[0055] The drain-side conductive paths 1206 electrically couple the drain regions 1204 to the memory cells 102 and are defined by the interconnection structure 1002. The interconnection structure 1002 has multiple wires 1004 and multiple vias 1006. The multiple wires 1004 have upper electrode wires 1004t and lower electrode wires 1004b. In some embodiments, the upper electrode wires 1004t correspond to bit lines BL. The multiple vias 1006 have the upper electrode via 1006t. One layer of the vias 1006 in close proximity to the substrate 1208 is an interlayer dielectric (ILD) layer 1214, while other layers of the vias 1006 and the wires 1004 are in IMD layers 1014.The wires 1004 and the vias 1006 are conductive and can be, for example, copper, aluminum, aluminum-copper, another suitable conductive material (other suitable conductive materials) or any combination of the above.

[0056] A peripheral region 1216 on one side of the 1T1R cells 1202 accommodates a peripheral device 1218 (only partially shown). The peripheral device 1218 has a pair of source / drain regions 1220 (only one of which is shown) in the substrate 1208 and further features a gate structure (not shown) between the source / drain regions 1220. The source / drain regions 1220 are doped regions of the substrate 1208, and each has a doping type opposite to an adjacent region of the substrate 1208. The peripheral device 1218 can be, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET) or some other suitable type of semiconductor device.In alternative embodiments, the peripheral device 1218 is a fin field-effect transistor (FinFET), a gate-all-around field-effect transistor (GAA FET), a nanowire field-effect transistor, a nanolayer field-effect transistor, or some other suitable type of semiconductor device.

[0057] With reference to Fig. 12B is a cross-sectional view 1200B of some embodiments of the IC chip of Fig. 12A provided along an axis orthogonal to an axis along which the cross-sectional view 1200A of Fig. 12A is taken. The 1T1R cells 1202 have individual memory cells 102, individual drain-side conductive paths 1206, individual access transistors 1212 and individual source-side conductive paths 1222.

[0058] The access transistors 1212 are located on the substrate 1208, between the substrate 1208 and the interconnect 1002. Furthermore, the access transistors 1212 are electrically separated from each other by the trench insulation structure 1210. The access transistors 1212 have individual drain regions 1204, individual source regions 1224, individual dielectric gate layers 1226, and individual gate electrodes 1228. The gate electrodes 1228 are located above the dielectric gate layers 1226 and, in some embodiments, define word lines WL. The drain and source regions 1204 and 1224 are doped regions of the substrate 1208, and each has an opposite doping type to an adjacent region (e.g., a bulk) of the substrate 1208. The drain regions 1204 define the drain sides of the gate electrodes 1228, and the source regions 1224 define the source sides of the gate electrodes 1228.The access transistors 1212 can be, for example, MOSFETs or some other suitable type of semiconductor device.

[0059] The drain-side conductive paths 1206 electrically couple the drain regions 1204 to the memory cells 102, and the source-side conductive paths 1222 electrically couple the source regions 1224 to source lines SL. The drain-side and source-side conductive paths 1206, 1222 are defined by the multiple wires 1004 and the multiple vias 1006.

[0060] With reference to Fig. 13 is an upper layout 1300 of some embodiments of the IC chip of Fig. 12A and Fig. 12B provided. The cross-sectional views 1200A, 1200B of Fig. 12A and Fig. 12B can, for example, be located along lines C or D, or at other suitable locations. The IC chip has multiple memory cells 102 in multiple rows and multiple columns, thus defining a memory array 1302. The memory cells 102 can, for example, be arranged as in a Fig. 1, 4A, 4B, 5-7, 9, 10, 11A, 11B, 12A or 12B.

[0061] Peripheral devices 1218 surround the memory array 1302 at a peripheral area 1216 of the IC chip. The peripheral devices 1218 can be, for example, transistors and / or other suitable semiconductor device(s). Furthermore, the peripheral devices 1218 can implement, for example, ECC circuits, read / write circuits, other suitable circuits for operating the memory cells 102, or any combination thereof.

[0062] As described above, the memory cells 102 have individual dielectric HEA layers located closest to individual lower electrodes to reduce the probability of the memory cells 102 getting stuck during cyclic traversal, at least when the memory cells 102 are RRAM cells. Thus, the probability of hard reset / error bits is reduced. Because the probability of hard reset / error bits is reduced, the probability of ECC capacity in the ECC circuit for the memory array 1302 being used by hard reset / error bits is lower. In some embodiments, the ECC circuit is fully or partially defined by a section 1304 of the peripheral region 1216. Because the probability of ECC capacity being used by hard reset / error bits is lower, the probability of failure of the memory array 1302 is lower.Since the probability of a failure of the memory array 1302 is lower due to the dielectric HEA layers, no additional ECC capacity and therefore no additional IC chip area is necessary.

[0063] With reference to Fig. Figure 14 is a schematic diagram of some embodiments of a 1T1R cell 1202 in Fig. 12A and Fig. 12B provided. The 1T1R cell 1202 is for any other 1T1R cell 1202 in Fig. 12A and Fig. Figure 12B is representative and features a memory cell 102 and an access transistor 1212, which are electrically coupled in series from a bit line BL to a source line SL. As described above, the memory cell 102 has a dielectric HEA layer 104h to prevent the memory cell 102 from becoming stuck during cyclic traversal, at least when the memory cell 102 is RRAM. The access transistor 1212 is gated by a word line WL and selectively couples the memory cell 102 to the source line SL, depending on a signal carried on the word line WL. The access transistor 1212 is illustrated as a MOSFET, but it could be any other suitable type of semiconductor device.

[0064] With reference to Fig. 15A-15C are schematic diagrams 1500A-1500C of some different alternative embodiments of the 1T1R cell 1202 from Fig. 14 provided, in which the access transistor 1212 is a different type of semiconductor device. In Fig. The access transistor 1212 in module 15A is a bipolar junction transistor (BJT). Fig. 15B, the access transistor 1212, is a HEMT with a Schottky gate contact. Fig. In 15C, the access transistor 1212 is a high-electron-mobility metal-oxide-semiconductor transistor (MOS transistor) (HEMT). In alternative embodiments, the access transistor 1212 is a suitable type of semiconductor device.

[0065] While the memory cells 102 of Fig. 10, 11A, 11B, 12A, 12B, 14 and 15A-15C with a single dielectric LEA layer 104l are illustrated, the memory cells 102 of Fig. 10, 11A, 11B, 12A, 12B, 14 and 15A-15C in alternative embodiments have two or more LEA dielectrics. Examples are given in Fig. 5 and Fig. Figure 6 illustrates this. While the memory cells 102 of Fig. 11B, 12A, 12B, 14 and 15A-15C without the cap layer 502 of Fig. As illustrated in point 5, the memory cells 102 of Fig. 11B, 12A, 12B, 14 and 15A-15C in alternative embodiments have the cap layer 502. While each memory cell 102 in the IC chip of Fig. 12A and Fig. 12B according to the embodiments of Fig. If configured as 10, alternatively the embodiments of Fig. 11A and Fig. 11B are used. While the 1T1R cells 1202 of Fig. 14 and 15A-15C, the memory cell 102 of Fig. If they exhibit 1, the 1T1R cells can 1202 of Fig. 14 and 15A-15C instead in alternative embodiments the memory cell 102 in one of Fig. 4A, 4B, 5-7, 9, 10, 11A, 11B, 12A or 12B.

[0066] With reference to Fig. Figures 16-23 provide a series of cross-sectional views 1600-2300 of some embodiments of a method for forming memory cells integrated with 1T1R cells and featuring individual dielectric HEA layers at corresponding lower electrodes. The cross-sectional views 1600-2300 can be seen, for example, along line C in Fig. 13 or at another suitable location in Fig. 13. Furthermore, the cross-sectional views 1600-2300 can, for example, show the formation of the IC chip. Fig. 12A and Fig. Illustrate 12B with the additional cap layer.

[0067] As seen in the cross-sectional view 1600 of Fig. As illustrated in Figure 16, a trench isolation structure 1210 is formed, extending into the top surface of a substrate 1208. The trench isolation structure 1210 individually surrounds and delimits the areas of the substrate 1208 where 1T1R cells 1202 are formed. Furthermore, the trench isolation structure 1210 surrounds and delimits a peripheral area 1216 of the IC chip.

[0068] As well as through the cross-sectional view 1600 of Fig. As illustrated in Figure 16, several semiconductor devices are formed on the substrate 1208. These semiconductor devices each have access transistors 1212 (partially shown), which are individually formed at and near the 1T1R cells 1202. Furthermore, the semiconductor devices each have a peripheral device 1218 (partially shown) at the peripheral region 1216 of the IC chip. The access transistors 1212 have individual drain regions 1204 and individual source regions (not shown) in the substrate 1208. The access transistors 1212 also have individual gate structures (not shown). The gate structures have individual drain faces, each delimiting the drain regions 1204, and individual source faces, each delimiting the source regions.The peripheral device 1218 has a pair of source / drain regions 1220 (of which only one is shown) in the substrate 1208 and further has a gate structure (not shown) between and limiting the source / drain regions 1220.

[0069] As seen in the cross-sectional view 1700 of Fig. As illustrated in Figure 17, a connection structure 1002 is partially formed over the semiconductor devices (e.g., the access transistors 1212 and the peripheral device 1218) and electrically coupled to them. The connection structure 1002 has several wires 1004 and several vias 1006 stacked in a dielectric structure. The dielectric structure has an ILD layer 1214 and several IMD layers 1014 over the ILD layer 1214. The several wires 1004 have several lower electrode wires 1004b along an upper surface of the connection structure 1002. The lower electrode wires 1004b are located individually at and near the 1T1R cells 1202 that are formed. Furthermore, the lower electrode wires 1004b are each electrically coupled to the drain areas 1204 of the access transistors 1212 by the wires 1004 and the vias 1006.

[0070] As well as through the cross-sectional view 1700 of Fig. Figure 17 illustrates that a dielectric through-hole layer 1016 is deposited on the interconnection structure 1002.

[0071] As seen in the cross-sectional view 1800 of Fig. As illustrated in Figure 18, lower electrode vias 1008 are formed in the dielectric via layer 1016. It should be noted that, for the sake of brevity, a lower section of the interconnect structure 1002 and the structure located beneath the lower section have been omitted here and in subsequent figures. The lower electrode vias 1008 are individual for the 1T1R cells 1202 that are formed and each extends through the dielectric via layer 1016 to the lower electrode wires 1004b. Furthermore, the lower electrode vias 1008 have individual via connectors 1008p and individual via linings 1008l. In alternative embodiments, the via linings 1008l are omitted.The via linings 1008l enclose the undersides of the via connectors 1008p to separate the via connectors 1008p from the lower electrode wires 1004b.

[0072] A process for forming the lower electrode vias 1008 may, for example, include: 1) structuring the dielectric via layer 1016 to form openings individually to the lower electrode wires 1004b to expose them; 2) depositing a lining layer and a plug layer that fills the openings and covers the dielectric via layer 1016; and 3) performing planarization into the plug and lining layers to expose the dielectric via layer 1016. However, other suitable processes are possible.

[0073] As well as through the cross-sectional view 1800 of Fig. As illustrated in Figure 18, a lower electrode layer 1802 is deposited, covering the dielectric via layer 1016 and the lower electrode vias 1008. The lower electrode layer 1802 is conductive and is electrically coupled to the lower electrode wires 1004b via the lower electrode vias 1008. The lower electrode layer 1802 can be, for example, a metal, a metal nitride, a metal oxide, doped polysilicon, another suitable conductive material, or any combination thereof. Furthermore, the lower electrode layer 1802 can be, for example, aluminum, titanium, tantalum, gold, platinum, tungsten, nickel, iridium, titanium nitride, tantalum nitride, N-doped polysilicon, P-doped polysilicon, some other suitable material, or any combination thereof.In some embodiments, the lower electrode layer 1802 is the same material as the via connectors 1008p.

[0074] While the lower electrode layer 1802 and the lower electrode vias 1008 are described as being formed separately, in alternative embodiments the lower electrode layer 1802 and the lower electrode vias 1008 can be formed together. In at least some of these alternative embodiments, the via connectors 1008p are part of the lower electrode layer 1802 and there is no boundary between the via connectors 1008p and the lower electrode layer 1802.

[0075] As seen in the cross-sectional view from 1900 Fig. As illustrated in Figure 19, several dielectric layers 104 are vertically stacked and deposited above the lower electrode layer 1802. Furthermore, a dielectric layer 104h with the highest electron affinity of the several dielectric layers 104 (i.e., a dielectric HEA layer 104h) is deposited first and thus in close proximity to the lower electrode layer 1802. As will be shown subsequently, the several dielectric layers 104 are divided into individual segments for the formed memory cells and serve as switching layers for the memory cells. It is also evident that by arranging the dielectric HEA layer 104h in close proximity to the lower electrode layer 1802, the probability of the memory cells getting stuck during cyclic operation is reduced, at least if the memory cells are RRAM cells.

[0076] The multiple dielectric layers 104 comprise the dielectric HEA layer 104h and further comprise a dielectric layer 104l with a low electron affinity (i.e., a dielectric LEA layer 104l) compared to the dielectric HEA layer 104h. The dielectric LEA layer 104l lies above the dielectric HEA layer 104h and is thus farther from the lower electrode layer 1802 than the dielectric HEA layer 104h. In alternative embodiments, the multiple dielectric layers 104 comprise two or more dielectric LEA layers stacked vertically above the dielectric HEA layer 104h, each being the dielectric LEA layer 104l as described.

[0077] The dielectric HEA layer 104h is a different dielectric material than the dielectric LEA layer 104l. Each of the dielectric HEA and LEA layers 104h and 104l can be, for example, a metal oxide, a metal oxynitride, a component metal oxide, another suitable dielectric, or any combination thereof. Furthermore, each of the dielectric HEA and LEA layers 104h and 104l can be, for example, titanium oxide (e.g., TiO2), hafnium oxide (e.g., HfO2), or hafnium aluminum oxide (e.g., Hf). x Al 1-x O2), tantalum oxide (e.g. Ta2O5), hafnium tantalum oxide (e.g. Hf x Ta 1-xO2), tungsten oxide (e.g., WO2), zirconium oxide (e.g., ZrO2), aluminum oxide (e.g., Al2O3), sulfated tin oxide (e.g., STO), another suitable dielectric (or other suitable dielectrics), or any combination thereof. In some embodiments, the HEA dielectric layer 104h is a high-k dielectric and / or the LEA dielectric layer 104l is a high-k dielectric.

[0078] The dielectric HEA and LEA layers 104h and 104l have different material systems or different material compositions. Different material systems correspond to different sets of elements. For example, the dielectric HEA layer 104h can be tantalum oxide (e.g., Ta₂O₃), while the dielectric LEA layer 104l can be aluminum oxide (e.g., Al₂O₃). Different material compositions correspond to different ratios of elements for the same set of elements (e.g., the same material systems). For example, the dielectric HEA layer 104h can be aluminum oxide (e.g., Al₂O₃), and the dielectric LEA layer 104l can be aluminum oxide with a different ratio of aluminum to oxide (e.g., Al₂O₃). x O y , where x ≠ 2 and y ≠ 3). While the preceding two examples provide specific materials, other suitable materials are possible.

[0079] The dielectric HEA and LEA layers 104h and 104l have individual thicknesses T. d In some embodiments, the thicknesses T d approximately 1-50 nanometers, approximately 1-25 nanometers, approximately 25-50 nanometers, or another suitable value. If the thickness T d If the thickness of the dielectric HEA or LEA layer 104h, 104l is too small (e.g., smaller than approximately 1 nanometer or another suitable value), the advantages of the material properties of the dielectric layer cannot be realized. For example, if the thickness T d If the dielectric HEA layer 104h is too small, it cannot prevent the formed memory cells from getting stuck during the cyclic cycle, at least if the memory cells are RRAM cells. If the thickness T dIf the diameter of the dielectric HEA or LEA layer 104h, 104l is too large (e.g., more than approximately 50 nanometers or another suitable value), the operating voltages of the resulting memory cells may be too high. These high voltages can, for example, increase power consumption, reduce the lifespan of the memory cell, and increase the risk of device failure.

[0080] A process for depositing the multiple dielectric layers 104 may, for example, comprise successive deposition of the multiple dielectric layers 104 by chemical vapor deposition (CVD), physical vapor deposition (PVD), some other suitable deposition process(s), or any combination thereof. In some embodiments, the dielectric HEA layer 104h is deposited by thermal oxidation of the lower electrode layer 1802, and then the dielectric LEA layer 104l is deposited by CVD, PVD, or some other suitable deposition process.

[0081] As noted above, the dielectric HEA and LEA layers 104h and 104l have different material systems or different material compositions. In some embodiments where the dielectric HEA and LEA layers 104h and 104l have different material systems, they are deposited by vapor deposition using different sets of precursors. In other embodiments where the dielectric HEA and LEA layers 104h and 104l have different material compositions, they are deposited by vapor deposition using the same set of precursors but different precursor ratios.Furthermore, in some embodiments in which the dielectric HEA and LEA layers 104h and 104l have different material compositions, the dielectric HEA and LEA layers 104h and 104l are deposited in situ in a common process chamber.

[0082] As well as through the cross-sectional view from 1900 Fig. As illustrated in Figure 19, a cap layer 502 and an upper electrode layer 1902 are vertically stacked and deposited over the several dielectric layers 104. In alternative embodiments, the cap layer 502 is omitted and therefore not deposited.

[0083] The cap layer 502 has a high affinity for oxygen compared to the lower and upper electrode layers 1802 and 1902. In other words, the cap layer 502 requires less energy to react with oxygen than the lower and upper electrode layers 1802 and 1902. At least when the resulting memory cells are metal-ion type RRAM cells and oxygen-ion type RRAM cells, the cap layer 502 can improve the performance of the memory cells. For example, the cap layer 502 can increase the switching windows and / or reduce operating voltages. The cap layer 502 can be, for example, aluminum, titanium, tantalum, hafnium, titanium oxide, hafnium oxide, zirconium oxide, germanium oxide, cerium oxide, some other suitable material, or any combination thereof. In some embodiments, the cap layer 502 is conductive and / or metallic.For example, in embodiments where the formed memory cells are RRAM cells of the metal ion type, the cap layer 502 is metal. In alternative embodiments, the cap layer 502 is dielectric. In embodiments where the cap layer 502 is dielectric, the cap layer 502 has a lower electron affinity than the dielectric HEA layer 104h.

[0084] The upper electrode layer 1902 can be, for example, a metal, a metal nitride, doped polysilicon, another suitable conductive material, or any combination thereof. Furthermore, the upper electrode layer 1902 can be, for example, aluminum, titanium, tantalum, gold, platinum, tungsten, nickel, iridium, titanium nitride, tantalum nitride, N-doped polysilicon, P-doped polysilicon, some other suitable material, or any combination thereof.

[0085] As seen in the cross-sectional view 2000 of Fig. As illustrated in Figure 20, individual hard masks 1010 are formed for and on each of the formed 1T1R cells 1202. As can be seen below, the hard masks 1010 have structures for memory cells of the 1T1R cells 1202. The hard masks 1010 can be formed, for example, by depositing a hard mask layer over the upper electrode layer 1902 (see, for example, Figure 20). Fig. 19) and subsequent structuring of the hard mask layer to form the hard masks 1010. The structuring can be achieved, for example, by a photolithography / etching process or some other suitable structuring process.

[0086] As well as through the cross-sectional view 2000 of Fig. Figure 20 illustrates that a first etching into the upper electrode layer was carried out in 1902 (see e.g. Fig. 19) and the cap layer 502 (see e.g. Fig. 19) with the hard masks 1010 in position. The first etching stops at the several dielectric layers 104 and transfers structures of the hard masks 1010 to the upper electrode layer 1902 and the cap layer 502. By transferring the structures to the upper electrode layer 1902, the first etching divides the upper electrode layer 1902 into individual upper electrodes 108 for the formed memory cells. By transferring the structures to the cap layer 502, the first etching divides the cap layer 502 into individual cap segments for the memory cells.

[0087] As shown in the cross-sectional view 2100 of Fig. As illustrated in Figure 21, sidewall spacer structures 1012 are formed on common sidewalls defined by the hard masks 1010, the upper electrodes 108, and the cap layer 502. The sidewall spacer structures 1012 can be, for example, silicon nitride and / or another suitable dielectric (other suitable dielectrics). A process for forming the sidewall spacer structures 1012 can, for example, include: 1) depositing a spacer layer having the structure of Fig. 20. Covered and conformally lined; and 2) etching back the spacer layer. However, other suitable processes are possible.

[0088] As well as through the cross-sectional view 2100 of Fig. As illustrated in Figure 21, a second etch is performed into the multiple dielectric layers 104 and the lower electrode layer 1802 with the hard masks 1010 and the sidewall spacer structures 1012 in position. The second etch stops at the dielectric via layer 1016 and transfers structures, jointly defined by the hard masks 1010 and the sidewall spacer structures 1012, to the dielectric layers 104 and the lower electrode layer 1802. By transferring the structures to the multiple dielectric layers 104, the second etch divides the multiple dielectric layers 104 into individual dielectric segments for the formed memory cells. By transferring the structures to the lower electrode layer 1802, the second etch divides the lower electrode layer 1802 into individual lower electrodes 106 for the memory cells.

[0089] After completion of the second etching, the memory cells 102 formed individually for the 1T1R cells 1202 remain. Individual lower electrodes 106 of the memory cells 102 each lie over the lower electrode vias 1008 and couple them electrically. Individual dielectric segments of the multiple dielectric layers 104 each lie over the lower electrodes 106. Individual cap segments of the cap layer 502 each lie over the dielectric segments. Individual upper electrodes 108 each lie over the cap segments. The memory cells 102 can be, for example, oxygen-ion type RRAM cells, metal-ion type RRAM cells, or some other suitable type of memory cell.

[0090] During operation of the memory cells 102, the individual dielectric segments serve as switching layers, alternating between HRSs and LRSs. Furthermore, since the dielectric HEA layer 104h is located in close proximity to the lower electrodes 106 of the multiple dielectric layers 104, the probability of the memory cells 102 getting stuck during cyclic operation is reduced, at least if the memory cells are RRAM cells. Thus, the probability of hard reset / error bits is reduced. Because the probability of hard reset / error bits is reduced, the probability that ECC capacity for a memory array (not shown) containing the memory cells 102 is used by hard reset / error bits is lower. Thus, the probability of memory array failure is less likely.Since the probability of memory array failure is reduced by the dielectric HEA layer 104h, no additional ECC capacity and therefore no additional IC chip area is necessary.

[0091] Since the probability of the memory cells 102 getting stuck during the cyclic pass is reduced by the dielectric HEA layer 104h, this probability can be further reduced by an additional deposition process during the procedure. As such, the dielectric HEA layer 104h adds little or no additional cost and is compatible with 40 nanometer process nodes and smaller.

[0092] As seen in the cross-sectional view 2200 of Fig. As illustrated in Figure 22, the interconnect structure 1002 is completed around the memory cells 102. This involves depositing an etch stop layer 1018 and an additional IMD layer 1014 covering the memory cells 102, and subsequently forming several additional wires 1004 and several additional vias 1006 in the etch stop layer 1018 and the additional IMD layer 1014. The several additional wires 1004 have top electrode wires 1004t, each located above the memory cells 102, and the several additional vias 1006 have top electrode vias 1006t extending from the top electrode wires 1004t to the top electrodes 108 of the memory cells 102.

[0093] As seen in the cross-sectional view 2300 of Fig. As illustrated in Figure 23, individual conductive filaments 402 for the memory cells 102 are formed in the multiple dielectric layers 104, each at the memory cells 102. Formation can, for example, involve applying a formation voltage across each of the memory cells 102. For instance, the lower electrodes 106 of the memory cells 102 can be grounded, while the upper electrodes 108 of the memory cells 102 are biased. However, other processes for forming the conductive filaments 402 are possible.

[0094] While Fig. 16-23, which are described with reference to a procedure, it is obvious that the in Fig. The structures shown in 16-23 are not limited to the procedure, but rather can stand on their own, separate from the procedure. While Fig. While sections 16-23 describe a series of operations, it is obvious that the sequence of operations may be changed in other embodiments. Fig. While sections 16-23 illustrate and describe a specific set of processes, in other embodiments some of the processes illustrated and / or described may be omitted. Further processes that are not illustrated and / or described may be included in other embodiments.

[0095] With reference to Fig. 24 is a block diagram 2400 of some embodiments of the method of Fig. 16-23 provided.

[0096] In the 2402, an access transistor is formed on a substrate. See, for example, Fig. 16.

[0097] In 2404, a connection structure is formed partially over the substrate and the access transistor, wherein the connection structure has a lower electrode wire that lies over the access transistor and is electrically coupled to it. See, for example, Fig. 17.

[0098] In 2406, a dielectric through-hole layer is formed over the interconnect structure. See, for example, Fig. 17.

[0099] In 2408, a lower electrode via is formed, extending through the dielectric via layer to the lower electrode wire. See, for example, Fig. 18.

[0100] In 2410, a lower electrode layer is deposited over the dielectric via layer and the lower electrode via. See, for example, Fig. 18.

[0101] In 2412, several dielectric layers are vertically stacked and deposited above the lower electrode layer, with the dielectric layer having the highest electron affinity being deposited first and being located closest to the lower electrode layer. See, for example, Fig. 19.

[0102] In 2414, a cap layer is deposited over the several dielectric layers. See, for example, Fig. 19.

[0103] In 2416, an upper electrode layer is deposited over the cap layer. See, for example, Fig. 19.

[0104] In 2418, the upper and lower electrode layers, the cap layer, and the multiple dielectric layers are structured to form a memory cell that lies above the lower electrode wire and is electrically coupled to it via the lower electrode via. See, for example, Fig. 20 and Fig. 21.

[0105] In 2420, the connection structure around the memory cell is completed. See, for example: Fig. 22.

[0106] In 2422, a formation voltage is applied to the memory cell to form a conductive filament in the multiple dielectric layers. See, for example, Fig. 23.

[0107] While the block diagram 2400 of Fig. 24. Where the processes and events illustrated and described here are a series, it is evident that the illustrated sequence of such processes and events is not to be interpreted in a restrictive sense. For example, some processes may occur in other sequences and / or concurrently with other processes and events, apart from those illustrated and / or described here. Furthermore, not all illustrated processes may be necessary to implement one or more aspects or embodiments of the present description, and one or more of the processes shown here may be carried out in one or more separate processes and / or in one or more separate phases.

[0108] With reference to Fig. Figures 25-29 are a series of cross-sectional views 2500-2900 of some alternative embodiments of the method of Fig. Figures 16-23 show which layers, from which the storage cells are formed, are structured using planarization. The cross-sectional views 2500-2900 can be seen, for example, along line C in Fig. 13 or at another suitable location in Fig. 13 can be taken. Furthermore, the cross-sectional views 2500-2900 can be used, for example, to show the formation of memory cell 102. Fig. 11B additionally illustrates with a cap layer.

[0109] As seen in the cross-sectional view 2500 of Fig. 25 illustrates the processes of Fig. 16 and Fig. 17. A trench isolation structure 1210 is formed, extending into the top of a substrate 1208, as described in relation to Fig. Figure 16 illustrates and describes several semiconductor devices on substrate 1208, as described in relation to Fig. Figure 16 illustrates and describes the multiple semiconductor devices, each featuring access transistors 1212 (partially shown) and a peripheral device 1218 (partially shown). A connection structure 1002 is partially formed over the semiconductor devices and electrically coupled to them, as shown in Figure 16. Fig. Figure 17 illustrates and describes. Furthermore, a dielectric through-hole layer 1016 is deposited on the interconnect structure 1002, as described in relation to Fig. 17 illustrated and described.

[0110] As well as through the cross-sectional view 2500 of Fig. As illustrated in Figure 25, an additional IMD layer 1014 is deposited, covering the dielectric via layer 1016.

[0111] As seen in the cross-sectional view 2600 of Fig. As illustrated in Figure 26, the dielectric via layer 1016 and the additional IMD layer 1014 on the top surface of the dielectric via layer 1016 are structured to form individual memory cell openings 2602 for and on each of the formed 1T1R cells 1202. It should be noted that, for the sake of brevity, the lower section of the interconnect structure 1002 and the structure located beneath the lower section are omitted here and in subsequent figures. The structuring can be carried out, for example, by a photolithography / etching process or some other suitable structuring process.

[0112] As can be seen from the cross-sectional view 2700 of Fig. As illustrated in Figure 27, a lower electrode layer 1802, several dielectric layers 104, a cap layer 502 and an upper electrode layer 1902 are deposited, lining and filling the storage cell openings 2602 (see e.g. Fig. 26). In alternative embodiments, the cap layer 502 is omitted and thus not formed. In alternative embodiments, the multiple dielectric layers 104 comprise three or more dielectric layers. The lower electrode layer 1802, the multiple dielectric layers 104, the cap layer 502, and the upper electrode layer 1902 are as described in relation to Fig. 18 and Fig. 19 described. Thus, a dielectric layer 104h with the highest electron affinity of the multiple dielectric layers 104 (i.e., a dielectric HEA layer 104h) is deposited first and is therefore in close proximity to the lower electrode layer 1802. It is evident that by arranging the dielectric HEA layer 104h in close proximity to the lower electrode layer 1802, the probability of memory cells getting stuck during the cyclic pass is reduced. The lower electrode layer 1802, the multiple dielectric layers 104, the cap layer 502, and the upper electrode layer 1902 are as described in relation to Fig. 18 and Fig. 19 described formed.

[0113] As seen in the cross-sectional view 2800 of Fig. Figure 28 illustrates planarization in the lower electrode layer 1802 (see e.g. Fig. 27), the several dielectric layers 104, the cap layer 502 and the upper electrode layer 1902 were carried out (see e.g. Fig. 27). The planarization stops at the additional IMD layer 1014 on a top side of the dielectric via layer 1016 and transfers a pattern of the memory cell openings 2602 (see e.g. Fig. 26) on the lower electrode layer 1802, the several dielectric layers 104, the cap layer 502 and the upper electrode layer 1902.

[0114] By transferring the structure, the planarization forms individual memory cells 102 at each of the 1T1R cells 1202. Transferring the structure to the lower and upper electrode layers 1802, 1902 divides the lower and upper electrode layers 1802, 1902 into individual lower electrodes 106 for the memory cells 102 and individual upper electrodes 108 for the memory cells 102, respectively. Transferring the structure to the multiple dielectric layers 104 divides the multiple dielectric layers 104 into individual dielectric segments for the memory cells 102. Transferring the structure to the cap layer 502 divides the cap layer 502 into individual cap segments for the memory cells 102. After completion of the structuring, the lower electrodes 106, the dielectric segments, and the cap segments have U-shaped profiles. V-shaped and other suitable profiles are also possible.

[0115] Since planarization is a structure derived from the structuring in Fig. Since the process is transferred to the different layers of the memory cells 102, the memory cells 102 can be formed by a single photolithography / etching process. This contrasts with the multiple photolithography / etching processes (e.g., in Fig. 18 or 20), which can be used to access memory cells 102 in Fig. 16-23 to form. Since photolithography is expensive, reducing the number of photolithography / etching processes can significantly reduce costs.

[0116] As seen in the cross-sectional view 2900 of Fig. 29 illustrates the processes in Fig. 22 and Fig. 23. The connection structure 1002 is completed around the memory cells 102, as described in relation to Fig. Figure 22 illustrates and describes individual conductive filaments 402 for the memory cells 102 are each formed in the multiple dielectric layers 104 in the memory cells 102, as shown in relation to Fig. 23 illustrated and described.

[0117] While Fig. 25-29, which are described with reference to a procedure, it is obvious that the in Fig. The structures shown in sections 25-29 are not limited to the procedure, but rather can stand on their own, separate from the procedure. While Fig. While sections 25-29 describe a series of operations, it is obvious that the sequence of operations may be changed in other embodiments. Fig. While sections 25-29 illustrate and describe a specific set of processes, in other embodiments some of the processes illustrated and / or described may be omitted. Further processes that are not illustrated and / or described may be included in other embodiments.

[0118] With reference to Fig. Figure 30 is a block diagram of 3000 of some embodiments of the method of Fig. 25-29 provided.

[0119] In the 3002, an access transistor is formed on a substrate. See, for example, Fig. 16 and Fig. 25.

[0120] In 3004, a connection structure is formed partially over the substrate and the access transistor, wherein the connection structure has a lower electrode wire that lies over the access transistor and is electrically coupled to it. See, for example, Fig. 17 and Fig. 25.

[0121] In 3006, a dielectric through-hole layer is formed over the interconnect structure. See, for example, Fig. 17 and Fig. 25.

[0122] In 3008, an IMD layer is formed over the dielectric via layer. See, for example, Fig. 25.

[0123] In 3010, the dielectric through-hole layer and the IMD layer are structured to form a memory cell opening that lies above and exposes the lower electrode wire. See, for example, Fig. 26.

[0124] In 3012, a lower electrode layer is deposited, covering the IMD layer and lining the memory cell opening. See, for example, Fig. 27.

[0125] In 3014, several dielectric layers are vertically stacked and deposited, covering the bottom electrode layer and lining the memory cell opening, with the dielectric layer having the highest electron affinity being deposited first and being located closest to the bottom electrode layer. See, for example, Fig. 27.

[0126] In 3016, a cap layer is deposited that covers the multiple dielectric layers and lines the storage cell opening. See, for example, Fig. 27.

[0127] In 3018, an upper electrode layer is deposited, covering the cap layer and lining the memory cell opening. See, for example, Fig. 27.

[0128] In 3020, planarization is performed in the upper and lower electrode layers, the cap layer, and the multiple dielectric layers to form a memory cell that lies above the wire in the memory cell opening and is electrically coupled to it. See, for example, Fig. 28.

[0129] In 3022, the connection structure around the memory cell is completed. See, for example, Fig. 29.

[0130] In 3024, a formation voltage is applied to the memory cell to form a conductive filament in the multiple dielectric layers. See, for example, Fig. 29.

[0131] While the block diagram 3000 of Fig.Since section 30 is illustrated and described here as a series of processes or events, it is obvious that the illustrated sequence of such processes and events is not to be interpreted in a restrictive sense. For example, some processes may occur in other sequences and / or concurrently with other processes and events, apart from those illustrated and / or described here. Furthermore, not all illustrated processes may be necessary to implement one or more aspects or embodiments of the present description, and one or more of the processes shown here may be carried out in one or more separate processes and / or in one or more separate phases.

[0132] The invention provides a storage cell comprising: a lower electrode; an upper electrode located above the lower electrode; and a dielectric stack comprising several dielectric layers stacked between the lower and upper electrodes; wherein the several dielectric layers comprise a first dielectric layer, the first dielectric layer being the one located in close proximity to the lower electrode and having the highest electron affinity of the dielectric layers; wherein the several dielectric layers comprise a second dielectric layer and a third dielectric layer, and wherein the second dielectric layer is located between the first and third dielectric layers.wherein the second dielectric layer has an electron affinity between that of the first dielectric layer and that of the third dielectric layer, or wherein the third dielectric layer has an electron affinity between that of the first dielectric layer and that of the second dielectric layer. In some embodiments, the multiple dielectric layers include a second dielectric layer located above the first dielectric layer, wherein the second dielectric layer has a different set of elements than the first dielectric layer. In some embodiments, the multiple dielectric layers include a second dielectric layer located above the first dielectric layer.wherein the second dielectric layer has the same set of elements as the first dielectric layer and furthermore has a different ratio of elements than the first dielectric layer. In some embodiments, the dielectric stack consists of two dielectric layers. In some embodiments, the memory cell further comprises a cap layer located above the dielectric stack, between the dielectric stack and the upper electrode, wherein the cap layer has a higher affinity for oxygen than the upper and lower electrodes. In some embodiments, the memory cell further comprises a conductive filament in the dielectric stack, wherein the conductive filament has oxygen vacancies. In some embodiments, the memory cell further comprises a conductive filament in the dielectric stack, wherein the conductive filament contains metal.

[0133] The invention further provides a storage device comprising a storage cell, wherein the storage cell comprises: a lower electrode; a dielectric structure located above the lower electrode, defined by several dielectric layers and comprising several different dielectric materials from top to bottom; and an upper electrode located above the dielectric structure; wherein the several dielectric layers comprise a first dielectric layer comprising a first dielectric material at the lower electrode, and the first dielectric material having a conductive lower edge of the band being the lowest of the several different dielectric materials; wherein the several dielectric layers comprise a second dielectric layer located above the first dielectric layer.and wherein the second dielectric layer has the same set of elements as the first dielectric layer, and furthermore, each of the elements has a different ratio than the respective element of the first dielectric layer. In some embodiments, a conductive lower edge of the dielectric structure rises stepwise from the lower electrode to an upper surface of the dielectric structure. In some embodiments, a conductive lower edge of the dielectric structure rises stepwise from the lower electrode to a midpoint between the lower electrode and an upper surface of the dielectric structure, and wherein the conductive lower edge of the dielectric structure descends stepwise from the midpoint to the upper surface. In some embodiments, the memory cell further comprises: a cap layer between and in direct contact with the upper electrode and the dielectric structure,wherein the cap layer has a higher affinity for oxygen than the upper electrode. In some embodiments, the storage device further comprises a conductive filament in the dielectric structure, wherein the conductive filament extends from an upper surface of the dielectric structure to a lower surface of the dielectric structure and terminates in front of the lower surface. In some embodiments, the multiple dielectric layers comprise a third dielectric layer, wherein the second dielectric layer is located between the first and the third dielectric layers, and wherein the second dielectric layer has an electron affinity between that of the first dielectric layer and that of the third dielectric layer. In some embodiments, the multiple dielectric layers comprise a third dielectric layer,wherein the second dielectric layer is located between the first and the third dielectric layer, wherein the third dielectric layer has an electron affinity between that of the first dielectric layer and that of the second dielectric layer.

[0134] The invention further provides a method comprising: depositing a lower electrode layer over a substrate; depositing a dielectric film over and directly onto the lower electrode layer, wherein the dielectric film comprises several different dielectric layers stacked vertically, wherein the several different dielectric layers have a first dielectric layer on the lower electrode layer, and wherein the first dielectric layer has the highest electron affinity of the several different dielectric layers, wherein the several different dielectric layers have a second dielectric layer lying over the first dielectric layer, and wherein the second dielectric layer has the same set of elements as the first dielectric layer, and furthermore, each of the elements has a different ratio than the respective element of the first dielectric layer;Depositing an upper electrode layer over the dielectric film; and structuring the lower electrode layer, the dielectric film, and the upper electrode layer into a storage cell. In some embodiments, the method further comprises depositing a cap layer over the dielectric film, wherein the upper electrode layer is deposited over the cap layer and has a lower affinity for oxygen than the cap layer. In some embodiments, the deposition of the dielectric film comprises: depositing the first dielectric layer by vapor phase deposition;and depositing the second dielectric layer over the first dielectric layer by vapor phase deposition, wherein the depositing of the first dielectric layer and the depositing of the second dielectric layer are carried out using the same set of precursors but different ratios of the precursors. In some embodiments, the dielectric film has a second dielectric layer, and wherein the deposition of the dielectric film comprises: depositing the first dielectric layer by vapor phase deposition with a first set of precursors;and deposition of the second dielectric layer over the first dielectric layer by vapor phase deposition using a second set of precursors that differs from the first set of precursors. In some embodiments, the method further comprises applying a formation voltage with a positive polarity from an upper electrode of the storage cell to a lower electrode of the storage cell to form a conductive filament in a dielectric structure that separates the upper and lower electrodes. In some embodiments, an electron affinity of the dielectric film decreases discretely and continuously from a lower surface of the dielectric film to an upper surface of the dielectric film.

Claims

[1] Memory cell (102), comprising: a lower electrode (106); an upper electrode (108) that lies above the lower electrode (106); and a dielectric stack (104) comprising several dielectric layers (104h, 104l1, 104l2) stacked between the lower and upper electrodes (106, 108); wherein the multiple dielectric layers (104h, 104l1 104l1, 104l2) have a first dielectric layer (104h) and the first dielectric layer (104h) those of the dielectric layers (104h, 104l) n 104l1, 104l2) is the one that is closest to the lower electrode (106) and has the highest electron affinity (X1) from the dielectric layers (104h, 104l1 104l1, 104l2), wherein the multiple dielectric layers (104h, 104l, 104l1, 104l2) have a second dielectric layer (104l1) and a third dielectric layer (10412), and wherein the second dielectric layer (104l1) is located between the first and the third dielectric layer (104h, 104l2), wherein the second dielectric layer (104l1) has an electron affinity (X2) between that of the first dielectric layer (104h) and that of the third dielectric layer (104l2), or wherein the third dielectric layer (10412) has an electron affinity (X3) between that of the first dielectric layer (104h) and that of the second dielectric layer (104l1). [2] Memory cell (102) according to claim 1, wherein the multiple dielectric layers (104h, 104l1, 104l2) have a second dielectric layer (104l, 10411) that lies above the first dielectric layer (104h), and wherein the second dielectric layer (104l, 104l1) has a different set of elements than the first dielectric layer (104h). [3] Storage cell (102) according to claim 1, wherein the multiple dielectric layers (104h, 104l1, 104l2) comprise a second dielectric layer (104l, 10411) that lies above the first dielectric layer (104h), and wherein the second dielectric layer (104l, 104l1) has the same set of elements as the first dielectric layer (104h) and furthermore has a different ratio of elements than the first dielectric layer (104h). [4] Memory cell (102) according to one of the preceding claims, further comprising: a cap layer (502) located above the dielectric stack (104), between the dielectric stack (104) and the upper electrode (108), wherein the cap layer (502) has a higher affinity for oxygen than the upper and lower electrodes (106). [5] Memory cell (102) according to one of the preceding claims, further comprising: a conductive filament (402) in the dielectric stack (104), wherein the conductive filament (402) has oxygen vacancies. [6] Memory cell (102) according to one of claims 1 to 4, further comprising: a conductive filament (402) in the dielectric stack (104), wherein the conductive filament (402) comprises metal. [7] Storage device comprising a memory cell (102), wherein the memory cell (102) comprises: a lower electrode (106); a dielectric structure located above the lower electrode (106), defined by several dielectric layers (104) and comprising several different dielectric materials; and an upper electrode (108) that lies above the dielectric structure; wherein the multiple dielectric layers have a first dielectric layer (104h) which has a first dielectric material at the lower electrode (106), and the first dielectric material has a conductive band lower edge that is the lowest of the several different dielectric materials (104h, 104l, 104l1, 104l2), wherein the multiple dielectric layers (104h, 104l1, 104l1, 104l2) have a second dielectric layer (104l, 10411) that lies above the first dielectric layer (104h), and wherein the second dielectric layer (104l, 104l1) has the same set of elements as the first dielectric layer (104h) and furthermore each of the elements has a different ratio than the respective element of the first dielectric layer (104h). [8] Storage device according to claim 7, wherein a conductive lower edge of the dielectric structure rises in steps from the lower electrode (106) to an upper surface of the dielectric structure. [9] Storage device according to claim 7, wherein a conductive lower edge of the dielectric structure rises from the lower electrode (106) to a central point between the lower electrode (106) and an upper surface of the dielectric structure; and wherein the conductive lower edge of the dielectric structure descends in steps from the central point to the upper surface. [10] Storage device according to any one of claims 7 to 9, wherein the storage cell (102) further comprises: a cap layer (502) between and in direct contact with the upper electrode (108) and the dielectric structure, wherein the cap layer (502) has a higher affinity for oxygen than the upper electrode (108). [11] Storage device according to any one of claims 7 to 10, further comprising: a conductive filament (402) in the dielectric structure, wherein the conductive filament (402) extends from an upper surface of the dielectric structure to a lower surface of the dielectric structure and terminates in front of the lower surface. [12] Storage device according to one of claims 7 to 11, wherein the multiple dielectric layers (104h, 104l, 104l1, 104l2) have a third dielectric layer (10412), and wherein the second dielectric layer (104l1) is located between the first and the third dielectric layer (104h, 10412), wherein the second dielectric layer (104l1) has an electron affinity (X2) between that of the first dielectric layer (104h) and that of the third dielectric layer (104l2). [13] Storage device according to one of claims 7 to 12, wherein the multiple dielectric layers (104h, 10411, 10412) comprise a second dielectric layer (104l1) and a third dielectric layer (104l2), and wherein the second dielectric layer (104l1) is located between the first and the third dielectric layer (104h, 10412), wherein the third dielectric layer (10412) has an electron affinity (X3) between that of the first dielectric layer (104h) and that of the second dielectric layer (10411). [14] Procedures, including: Deposition of a lower electrode layer (1802) over a substrate (1208); Deposition of a dielectric film (104) over and directly onto the lower electrode layer (1802), wherein the dielectric film comprises several different dielectric layers (104h, 104l1, 104l1, 104l2) stacked vertically, wherein the several different dielectric layers (104h, 104l1, 104l1, 104l2) have a first dielectric layer (104h) on the lower electrode layer (1802) and wherein the first dielectric layer (104h) has the highest electron affinity (X1) of the several different dielectric layers (104h, 104l1, 104l11, 104l12), wherein the several different dielectric layers (104h, 104l1, 104l11, 104l12) have a second dielectric layer (104l, 104l1) above the first dielectric layer (104h), and wherein the second dielectric layer (104l,10411) has the same set of elements as the first dielectric layer (104h) and furthermore each of the elements has a different ratio than the respective element of the first dielectric layer (104h);, Deposition of an upper electrode layer (1902) over the dielectric film; and Structuring the lower electrode layer (1802), the dielectric film and the upper electrode layer (1902) into a storage cell (102). [15] Method according to claim 14, further comprising: Depositing a cap layer (502) over the dielectric film, wherein the upper electrode layer (1902) is deposited over the cap layer (502) and has a lower affinity for oxygen than the cap layer (502). [16] Method according to claim 14 or 15, wherein the dielectric film comprises a second dielectric layer (104l, 104l1) and wherein the deposition of the dielectric film comprises: Deposition of the first dielectric layer (104h) by vapor phase deposition; and Deposition of the second dielectric layer (104l, 104l1) over the first dielectric layer (104h) by vapor phase deposition, wherein the deposition of the first dielectric layer (104h) and the deposition of the second dielectric layer (104l, 104l1) is carried out using the same set of precursors but different ratios of the precursors. [17] Method according to any one of claims 14 to 16, wherein the deposition of the dielectric film comprises: Deposition of the first dielectric layer (104h) by vapor phase deposition with a first set of precursors; and Deposition of the second dielectric layer (104l, 104l1) over the first dielectric layer (104h) by vapor phase deposition with a second set of precursors that differs from the first set of precursors. [18] Method according to any one of claims 14 to 17, further comprising: Applying a formation voltage with a positive polarity from an upper electrode (108) of the storage cell (102) to a lower electrode (106) of the storage cell (102) to form a conductive filament (402) in a dielectric structure that separates the upper electrode (108) and the lower electrode (106). [19] Method according to any one of claims 14 to 18, wherein an electron affinity of the dielectric film decreases discretely and continuously from a lower surface of the dielectric film to an upper surface of the dielectric film.

Images