Semiconductor device and method of manufacturing with passivation scheme design for wafer singulation

Abstract

A method of manufacturing a semiconductor device, the method comprising: Forming (1010) first electrical components (103) in a substrate (101) in a first device region (210) of the semiconductor device; Forming (1020) a first interconnect structure (106) over and electrically coupled to the first electrical components (103); Forming (1030) a first passivation layer (111) over the first interconnect structure (106), the first passivation layer (111) extending from the first device region (210) to a scribe line region (230) adjacent to the first device region; after forming the first passivation layer (111), removing (1040) the first passivation layer from the scribe line region (230) while maintaining a remaining portion of the first passivation layer (111) in the first device region (210), wherein only the first passivation layer (111) in the scribe line region (220) is removed; and Forming a conductive contact pad (115) through the first passivation layer (111) and electrically coupled to an electrically conductive feature of the first interconnect structure (106); Forming a second passivation layer (117) over the conductive pad (115) and over the first passivation layer (111), the second passivation layer (117) extending from the first device region (210) to the scribe line region (230); and Removing the second passivation layer (117) from the scribe line region (230) while maintaining a remaining portion of the second passivation layer (117) in the first device region (210); and Dicing (1050) along the scribe line region (230) after removing the first passivation layer.

Description

GENERAL STATE OF THE ART

[0001] Semiconductor devices are used in a wide variety of electronic applications such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconducting layers over a semiconductor substrate, and by patterning the various material layers using lithography to form circuit components and elements. Dozens or hundreds of integrated circuits are typically fabricated on a single semiconductor wafer. The individual dies are singulated by sawing the integrated circuits along a scribe line. The individual dies are then packaged separately, for example, in multi-chip modules or other types of packaging.

[0002] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. As feature sizes continue to shrink in advanced semiconductor manufacturing nodes, new challenges arise that must be addressed.

[0003] US 2012 / 0 211 748 A1 discloses a method for singulating a semiconductor wafer, wherein the substrate is irradiated with a laser beam to locally modify the substrate between a trench structure and a second main surface of the substrate opposite a first main surface. US 2010 / 0072635 A1 discloses a method for protecting sidewalls of semiconductor chips using insulating films. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration. The Fig. 1 to 6 illustrate cross-sectional views of a semiconductor device at various stages of manufacture according to one embodiment. The Fig. 7 and Fig. 8 illustrate cross-sectional views of a semiconductor device at various stages of manufacture according to another embodiment. The Fig. 9 and Fig. 10 illustrate cross-sectional views of a semiconductor device at various stages of manufacture according to another embodiment. The Fig. 11 and Fig. 12 illustrate cross-sectional views of a semiconductor device at various stages of manufacture according to another embodiment. The Fig. 13 and Fig. 14 illustrate sectional views of a semiconductor device at various stages of manufacture according to yet another embodiment. Fig. 15 illustrates a flowchart of a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and also embodiments where additional functions may be formed between the first and second features such that the first and second features may not be in direct contact.

[0006] Furthermore, for ease of discussion, spatially relative terms such as "beneath," "under," "lower," "over," "upper," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. The spatially relative terms are intended to encompass various orientations of the device during use or operation of the device, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.Unless otherwise indicated, the same or similar reference number in different figures throughout the specification refers to the same or similar components manufactured by the same or similar process using the same or similar materials.

[0007] In some embodiments, a method of manufacturing a semiconductor device comprises forming electrical components (e.g., transistors, resistors, capacitors, etc.) in a substrate in a device region of the semiconductor device; forming an interconnect structure over and electrically coupled to the electrical components; and forming a passivation layer over the interconnect structure, wherein the passivation layer extends from the device region to a scribe line region adjacent to the device region. The method further comprises, after forming the passivation layer, removing the passivation layer from the scribe line region while maintaining a remaining portion of the passivation layer in the device region; and singulating along the scribe line region after removing the passivation layer.In some embodiments, the passivation layer is a nitride-containing layer, and the dicing process is a plasma dicing process. The etch rate of the nitride-containing passivation layer may be too low for the plasma dicing process. By removing the nitride-containing passivation layer from the dicing region, the plasma etch process can easily etch through the semiconductor device without requiring a thick mask layer to protect other areas of the semiconductor device.

[0008] The Fig. 1 to 6 illustrate cross-sectional views of a semiconductor device 100 at various stages of manufacturing according to one embodiment. The semiconductor device 100 may, for example, be a wafer comprising a plurality of semiconductor dies, with the wafer later being singulated to form a plurality of individual semiconductor dies.

[0009] With reference to Fig. 1, the semiconductor device 100 includes a substrate 101, electrical components 103 formed in or on the substrate 101, and interconnect structures 106 formed over the substrate 101 and electrically coupled to the electrical components 103. As shown in Fig. 1, the semiconductor device 100 may include various regions, such as device regions 210, seal ring regions 220, and dicing regions 230 (which may also be referred to as scribe line regions). In some embodiments, functional circuits, such as integrated circuits, comprising electrical components 103 and the corresponding interconnect structures 106, are formed in the device regions 210. The seal rings 104 are formed in the seal ring regions 220 around the device regions 210. Each seal ring 104 may, for example, be formed in the seal ring regions 220 around the perimeter of a corresponding device region 210. Each of the dicing regions 230 is, for example, arranged between adjacent seal ring regions 220. During a subsequent dicing process, a seal ring 104 is formed along (e.g.,in) the dicing regions 230 to separate the wafer into a plurality of individual semiconductor dies. Note that . Fig. 1 can only show portions of the semiconductor device 100 for the sake of simplicity and not all details of the semiconductor device 100 are illustrated.

[0010] The substrate 101 may be a semiconductor substrate such as silicon, doped or undoped, or an active layer of a semiconductor-on-insulator (SOI) substrate. The semiconductor substrate may comprise other semiconductor materials, such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof. Other substrates such as multilayer or gradient substrates may also be used.

[0011] The electrical components 103, such as transistors, diodes, capacitors, resistors, etc., may be formed in and / or on the substrate 101 using any suitable formation method and interconnected by interconnect structures 106 to form functional circuits. The electrical components 103 in each device region 210 are interconnected, for example, by the corresponding (e.g., overlying) interconnect structure 106 in that device region 210 to form the functional circuits of the integrated circuit in the device region 210.

[0012] In some embodiments, each of the interconnect structures 106 includes metallization structures (e.g., electrically conductive features) formed in one or more dielectric layers over the semiconductor substrate 101. The interconnect structure 106 may, for example, include electrically conductive features, such as conductive traces 105 and vias 107, formed in a plurality of dielectric layers 109. In some embodiments, the dielectric layers 109 include a suitable dielectric, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, multiple layers thereof, or the like, and may be formed using a suitable formation method, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), lamination, or the like. The electrically conductive features (e.g.,105, 107) of the interconnect structure 106 may be formed from an electrically conductive material, such as copper, and using a suitable formation process, such as damascene, dual damascene, plating, or the like. Note that for the sake of simplicity, . Fig. 1 illustrates the dielectric layer 109 as a single layer, it being understood that the dielectric layer 109 of the interconnect structure 106 may include multiple dielectric layers.

[0013] Fig. 1 further illustrates sealing rings 104 formed in the sealing ring regions 220. As in Fig. 1, the sealing rings 104 may include layers of vias and conductive traces formed in the dielectric layers 109. The sealing rings 104 are, in some embodiments, manufactured in the same processing step(s) using the same material(s) as the conductive features 105 / 107. In a top view, each sealing ring 104 surrounds (e.g., encircles) a corresponding device region 210 in some embodiments. The sealing ring 104 may protect the functional circuitry in the device region 210 from mechanical stress and may also protect the functional circuitry from damage due to cracking or detachment during the singulation process. In some embodiments, the sealing rings 104 are electrically isolated and therefore do not perform any control or signal processing function.

[0014] In Fig. 1, a passivation layer 111 is next formed over the interconnect structures 106 to provide a degree of protection for the underlying structures. The passivation layer 111 may be formed from one or more suitable dielectrics such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, combinations thereof, or the like. The passivation layer 111 may be formed by a process such as CVD, although any suitable process may be used. In an exemplary embodiment, the passivation layer 111 is formed from a nitride-containing material (e.g., silicon nitride). The passivation layer 111 may be formed over the entire surface of the interconnect structures 106, and therefore, the deposited passivation layer 111 may extend continuously from a first device region 210 (e.g.,the device region 210 on the left side in . Fig. 1) to a second device region 210 (e.g., the device region 210 on the right side in Fig. 1) and therefore cover the top surface of the dielectric layers 109 in the device regions 210, the seal ring regions 220 and the singulation regions 230.

[0015] Then, a patterned mask 113, such as a patterned photoresist layer, is formed over the passivation layer 111. An anisotropic etching process, such as dry etching, may be performed using the patterned mask 113 as an etch mask to remove portions of the passivation layer 111. After the anisotropic etching process, openings 116 are formed in the passivation layer 111 in the device regions 210 to expose underlying conductive features of the interconnect structures 106. Additionally, openings 114 are formed in the passivation layer 111 in the singulation regions 230 to expose the underlying dielectric layer 109. Note that during subsequent processing, the openings 116 may be filled with one or more electrically conductive materials to form the via portions 115V (see Fig. 2) the subsequently formed conductive pads 115 so that they may have a suitable shape in a top view, such as a round, oval, rectangular shape, or the like. In contrast, the purpose of forming the openings 114 is to remove portions of the passivation layer 111 from the dicing region 230 so that it is easier to dicing the semiconductor device 100 in a subsequent plasma dicing process, which will be described in more detail below. Therefore, each of the openings 114, viewed from above (e.g., in a top view), is a trench extending along (e.g., into) the dicing region 230. For this reason, the openings 114 may also be referred to as trenches. After the openings 114 / 116 have been formed, the patterned mask 113 is removed by a suitable removal process, such as ashing.

[0016] With reference to Fig. 2, conductive pads 115 are formed in the device regions 210 over the passivation layer 111 and electrically coupled to underlying electrically conductive features of the interconnect structures 106. The conductive pads 115 may comprise aluminum, but alternatively, other materials such as copper may be used. The conductive pads 115 may be formed by depositing (e.g., using sputtering) a layer of electrically conductive material (e.g., aluminum) over the passivation layer 111 and in the openings 116 (see Fig. 1) the passivation layer 111 is deposited and then portions of the layer of electrically conductive material are removed by a suitable process (e.g., photolithography and etching techniques) to form the conductive contact pads 115. However, any other suitable method for forming the conductive contact pads 115 may be used. In the example of Fig. 2, the conductive pads 115 include via portions 115V extending into the passivation layer 111 to electrically couple to the conductive features of the interconnect structure 106. The conductive pads 115 can be used to test the functional circuits of the semiconductor device 100 to identify known good dies (KGDs).

[0017] Next, a passivation layer 117 is formed over the passivation layer 111, the conductive pads 115, and the interconnect structure 106 (e.g., conformally). The passivation layer 117 may be formed from one or more suitable dielectrics such as silicon oxide, silicon nitride, low-k dielectrics such as carbon-doped oxides, ultra-low-k dielectrics such as porous carbon-doped silicon dioxide, combinations thereof, or the like. The passivation layer 117 may be formed by a process such as CVD, although any suitable process may be used. In an exemplary embodiment, the passivation layer 117 is formed from a nitride-containing material (e.g., silicon nitride). The passivation layer 117 may be formed over a surface area, and therefore, when deposited, the passivation layer 117 may extend continuously from a first device region 210 (e.g.,the device region 210 on the left side in . Fig. 2) to a second device region 210 (e.g., the device region 210 on the right side in Fig. 2) and therefore cover the conductive contact pads 115, the passivation layer 111 and the top surface of the dielectric layers 109 in the singulation regions 230.

[0018] Then, a patterned mask, such as a patterned photoresist layer, is formed over the passivation layer 117, and an anisotropic etching process, such as dry etching, is performed to remove portions of the passivation layer 117. The patterned mask layer is then removed after the anisotropic etching process. After the anisotropic etching process, openings 118 are formed in the passivation layer 117 in the device regions 210 to expose the conductive contact pads 115. Furthermore, portions of the passivation layer 117 are removed from the singulation regions 230, and openings 119 (e.g., trenches) are formed to expose the underlying dielectric layer 109 in the singulation regions 230. In the example of Fig. 2, the sidewalls 117S of the passivation layer 117 facing the singulation region 230 and the corresponding sidewalls 111S of the passivation layer 111 facing the singulation region 230 are aligned (e.g., along the same vertical lines), and the openings 119 have the same dimensions as the openings 114. In other words, in a top view, each of the openings 119 is a trench that overlaps with a corresponding (e.g., underlying) opening 114.

[0019] Next, Fig. 3, a dielectric layer 121, such as silicon oxide, over the structure of Fig. 2 using a suitable formation process, such as CVD, PVD, or the like. A planarization process, such as chemical mechanical planarization (CMP), may be performed to achieve a flat top surface for the dielectric 121.

[0020] Next, Fig. 4, a dielectric layer 123, such as silicon oxide or silicon oxide, is formed over the dielectric layer 121 using a suitable formation process, such as CVD, PVD, or the like. Conductive pads 125 are formed in the dielectric layer 123, and vias 127 are formed that extend through the dielectric layer 121 and the passivation layers 117 / 111 to electrically couple the conductive pads 125 to conductive features of the interconnect structures 106. The vias 127 can also be formed to electrically couple the conductive pads 125 to the conductive pads 115.The conductive pads 125 and the vias 127 may be formed from a suitable conductive material, such as copper, gold, tungsten, cobalt, alloys thereof, combinations thereof, or the like, using any suitable method known or used in the art.

[0021] In the example of Fig. 4, a distance WPA2 measured between opposite sidewalls of the passivation layer 117 facing the singulation region 230 is equal to a distance WPA1 measured between opposite sidewalls of the passivation layer 111 facing the singulation region 230. The dashed lines in Fig. 4 further illustrates a singulation path in the singulation region 230 for a subsequent plasma singulation process. The width WPD of the singulation path is smaller than WPA1 or WPA2 in the illustrated embodiment. In some embodiments, the difference between the width WPD and the distances WPA1 and WPA2 is less than 2 µm (e.g., 0 < WPA1-WPD < 2 µm and WPA1 = WPA2). In the present description, the distance WPA1 may also be referred to as the width of the opening 114 in the passivation layer 111, and the distance WPA2 may also be referred to as the width of the opening 119 in the passivation layer 117.

[0022] In Fig. 5, a structured mask 129 such as a structured photoresist layer is next applied over the structure of Fig. 4. Next, a dicing process, such as a plasma dicing process, is performed along the dicing paths in the dicing regions 230 to form the recesses 131 (e.g., trenches in a top view). The plasma dicing process etches portions of the semiconductor device 100 exposed by the structures (e.g., openings) in the patterned mask 129. As shown in Fig. 5, the recess 131 extends through the dielectric layers 123 / 121 / 109 and into the substrate 101. A bottom surface of the recess 131 is located between a top surface and a bottom surface of the substrate 101. In other words, the recess 131 extends into the substrate 101 in Fig. 5, but not through it.

[0023] In some embodiments, plasma dicing is a dry plasma process such as deep reactive ion etching (DRIE), which can etch very narrow, deep vertical trenches into the substrate to separate individual dies. Problems with blade dicing, such as die chipping or cracking, can be avoided by the plasma dicing process, thereby improving the yield of the manufacturing process. Unlike blade dicing, plasma dicing avoids or reduces damage to the wafer face and / or sidewalls, resulting in higher die strengths, improved device reliability, and increased device lifetime. Due to the narrower dicing path of plasma dicing, the dicing regions can be made narrower, thus allowing more dies to be formed in the wafer to reduce the production cost per die.Furthermore, plasma dicing can be performed along multiple dicing paths simultaneously, increasing the throughput of the manufacturing process. Furthermore, by defining the shape of the openings in the patterned mask 129, non-rectangular die shapes can be easily achieved by plasma dicing.

[0024] In some embodiments, the passivation layers 111 / 117 are nitride-containing layers, and the etch rate of the passivation layers 111 / 117 using the plasma singulation process (e.g., a plasma etch process) is low. If the passivation layers 111 / 117 have not been removed from the singulation regions 230, a long plasma etch time may be required to etch through the passivation layers 111 / 117, which in turn requires a very thick patterned mask 129 (e.g., a thick patterned photoresist layer) to protect other areas of the wafer, such as the device regions 210. Due to the high etch rate of the photoresist layer, there may not be enough photoresist budget to achieve the required thickness of the patterned mask 129 (e.g., photoresist layer).By removing the passivation layers 111 / 117 from the singulation regions 230, the present disclosure enables the plasma singulation process to etch through the semiconductor device 100 at a faster rate, thereby eliminating the need for a very thick patterned mask 129 and increasing the throughput of the manufacturing process.

[0025] Then in Fig. 6 reduces the thickness of the substrate 101. A backside grinding process such as CMP may be performed from the backside of the substrate 101 (e.g., the side facing away from the interconnect structures 106) to reduce the thickness of the substrate 101. In some embodiments, the grinding process stops when the recesses 131 extend through the (thinned) substrate 101, thereby separating the semiconductor device 100 (e.g., a wafer) into a plurality of individual semiconductor dies 140 / 150. In the illustrated embodiment, each semiconductor die 140 / 150 includes electrical components 103 formed in the substrate 101, an overlying interconnect structure 106, passivation layers 111 / 117, dielectric layers 121 / 123, conductive pads 115 / 125, and vias 127. Note that Fig. 6 For the sake of simplicity, only sections of the semiconductor dies 140 / 150 (e.g. sections that are adjacent to the recess 131 in Fig. 6).

[0026] In the example of Fig. 6, the sidewall 117S of the passivation layer 117 and the corresponding sidewall 111S of the passivation layer 111 are aligned along a same vertical line, and there is a lateral distance (e.g., offset) between the sidewalls 117S / 111S and a corresponding (e.g., a nearest) sidewall 121S of the dielectric layers 121. The sidewall 121S is aligned along a same vertical line with a corresponding (e.g., a nearest) sidewall 101S of the substrate 101 and aligned along a same vertical line with a corresponding (e.g., a nearest) sidewall 109S of the dielectric layer 109 in the illustrated embodiment.

[0027] The Fig. 7 and Fig. 8 illustrate cross-sectional views of a semiconductor device 100A at various stages of fabrication according to another embodiment. The semiconductor device 100A of Fig. 7 is similar to the semiconductor device 100 of Fig. 4, but the passivation layer 111 is in the example of Fig. 7 omitted. Fig. 7 further illustrates the singulation path with a width WPD that is smaller than the width WPA2 of the opening (e.g., a trench in plan view) in the passivation layer 117 in the singulation region 230. Fig. 8 illustrates the semiconductor device 100A after the plasma dicing process and the backside thinning process, similar to Fig. 6. The semiconductor device 100A is singulated into a plurality of individual semiconductor dies 140A and 150A.

[0028] The Fig. 9 and Fig. 10 illustrate cross-sectional views of a semiconductor device 100B at various stages of fabrication according to another embodiment. The semiconductor device 100B of Fig. 9 is similar to the semiconductor device 100 of Fig. 4, but the width WPA2 of the opening in the passivation layer 117 is smaller than the width WPA1 of the opening in the passivation layer 111, so that the passivation layer 117 covers the sidewalls 111S of the passivation layer 111. In some embodiments, during the patterning process for forming openings 119 in the passivation layer 117 (see, e.g., Fig. 2) the size (e.g. width) of the openings 119 is formed smaller than that of the opening 114 of the passivation layer 111, which is in the Fig. 9 illustrated forms of the passivation layers 111 / 117. Fig. 9 further illustrates the simplification path with the width WPD being smaller than the width WPA2 and the width WPA1. In some embodiments, a difference between the widths WPA1 and WPA2 is less than 1 µm (e.g., 0 < WPA1-WPA2 < 1 µm), and the difference between the widths WPA2 and WPD is less than 2 µm (e.g., 0 < WPA2-WPD < 2 µm).

[0029] Fig. 10 illustrates the semiconductor device 100B after the plasma dicing process and the backside thinning process, similar to Fig. 6. The semiconductor device 100B is separated into a plurality of individual semiconductor dies 140B and 150B. In the example of Fig. 10, there is a lateral distance (e.g., offset) between the sidewall 117S of the passivation layer 117 and the corresponding sidewall 111S of the passivation layer 111. For example, the sidewall 1117S is closer to a corresponding (e.g., nearest) sidewall 121S of the dielectric layers 121 than to the sidewall 111S. The sidewall 121S, in the illustrated embodiment, is aligned along a same vertical line with the sidewall 101S of the substrate 101 and aligned along a same vertical line with a corresponding (e.g., nearest) sidewall 109S of the dielectric layer 109.

[0030] The Fig. 11 and Fig. 12 illustrate cross-sectional views of a semiconductor device 100C at various stages of fabrication according to another embodiment. The semiconductor device 100C in Fig. 11 is similar to the semiconductor device 100 in Fig. 4, but the width WPA2 of the opening in the passivation layer 117 is greater than the width WPA1 of the opening in the passivation layer 111, so that the sidewall 117S of the passivation layer 117 is further away from the singulation region 230 than the corresponding sidewall 111S of the passivation layer 111. In some embodiments, during the patterning process for forming openings 119 in the passivation layer 117 (see, e.g., Fig. 2) the size (e.g. width) of the openings 119 is formed larger than that of the opening 114 of the passivation layer 111, which is in the Fig. 11 illustrated forms of the passivation layers 111 / 117 results. Fig. 11 further illustrates the singulation path with width WPD being smaller than width WPA2 and width WPA1. In some embodiments, a difference between widths WPA1 and WPA2 is less than 1 µm (e.g., 0 < WPA2-WPA1 < 1 µm), and a difference between widths WPA1 and WPD is less than 2 µm (e.g., 0 < WPA1-WPD < 2 µm).

[0031] Fig. 12 illustrates the semiconductor device 100C after the plasma dicing process and the backside thinning process, similar to Fig. 6. The semiconductor device 100C is separated into several individual semiconductor dies 140C and 150C. In the example of Fig. 12, there is a lateral distance (e.g., offset) between the sidewall 117S of the passivation layer 117 and the corresponding sidewall 111S of the passivation layer 111. For example, the sidewall 117S is located farther from a corresponding (e.g., nearest) sidewall 121S of the dielectric layers 121 than at the sidewall 111S. The sidewall 121S, in the illustrated embodiment, is aligned along a same vertical line with the sidewall 101S of the substrate 101 and aligned along a same vertical line with a corresponding (e.g., nearest) sidewall 109S of the dielectric layer 109.

[0032] The Fig. 13 and Fig. 14 illustrate cross-sectional views of a semiconductor device 100D at various stages of fabrication according to yet another embodiment. The semiconductor device 100D of Fig. 13 is similar to the semiconductor device 100 of Fig. 4, but the passivation layer 111 is not removed from the dicing regions 230 (therefore remains therein) and the passivation layer 117 is removed from the dicing region 230. This embodiment can be used when the thickness of the passivation layer 111 is small (e.g., less than 8000 nm) and / or the passivation layer 111 is formed from a material with a high etch rate (e.g., an etch rate higher than 200 nm per minute (nm / min), such as between approximately 200 nm / min and approximately 1000 nm / min) for the plasma dicing process, in which case only the openings 119 (see notation in Fig. 2) in the passivation layer 117 with a width WPA2. Fig. 13 further illustrates the singulation path with a width WPD that is smaller than the width WPA2. In some embodiments, the difference between the widths WPA2 and WPD is less than 2 µm (e.g., 0 < WPA2 - WPD < 2 µm).

[0033] Fig. 14 illustrates the semiconductor device 100D after the plasma dicing process and the backside thinning process, similar to Fig. 6. The semiconductor device 100D is separated into several individual semiconductor dies 140D and 150D. In the example of Fig. 14, there is a lateral distance (e.g., offset) between the sidewall 117S of the passivation layer 117 and the sidewall 111S of the passivation layer 111. For example, the sidewall 117S is located farther from a corresponding (e.g., nearest) sidewall 121S of the dielectric layers 121 than at the sidewall 111S. The sidewall 111S of the passivation layer 111, the sidewall 121S of the dielectric layer 121, the sidewall 109S of the dielectric layers 109, and the sidewall 101S of the substrate 101 are aligned along a same vertical line in the illustrated embodiment.

[0034] Fig. 15 illustrates a flowchart of a method 1000 for manufacturing a semiconductor device according to some embodiments. It should be understood that the Fig. 15 is merely one example of many possible embodiments. One of ordinary skill in the art would recognize many variations, alternatives, and modifications. For example, various steps as illustrated in Fig. 15 may be added, removed, replaced, rearranged or repeated.

[0035] With reference to Fig.15, at block 1010, first electrical components are formed in a substrate in a first device region of the semiconductor device. In step 1020, a first interconnect structure is formed over the first electrical components and electrically coupled thereto. In step 1030, a first passivation layer is formed over the first interconnect structure, wherein the first passivation layer extends from the first device region to a scribe line region adjacent to the first device region. In step 1040, after forming the first passivation layer, the first passivation layer is removed from the scribe line region, while a remaining portion of the first passivation layer remains in the first device region. In step 1050, after removing the first passivation layer, a singulation process is performed along the scribe line region.

[0036] Embodiments may achieve advantages. For example, by removing the passivation layers 111 and / or 117 in the dicing region, it is easier for the plasma dicing process to etch through the dicing region of the wafer, eliminating the need to form a thick photoresist layer to protect other areas of the wafer. This enables the plasma dicing process to be used to dicing the wafer with difficult-to-etch (e.g., nitride-containing) passivation layers. The use of the plasma dicing process increases the throughput of the dicing process because multiple regions can be etched simultaneously by the plasma dicing process. By designing the shape of the openings in the patterned mask layer used in the plasma dicing process, non-rectangular-shaped dies can be easily formed.Furthermore, plasma dicing reduces or eliminates damage to the die, resulting in higher die strengths, improved device reliability, and longer device lifetime.

Claims

[1] A method of manufacturing a semiconductor device, the method comprising: Forming (1010) first electrical components (103) in a substrate (101) in a first device region (210) of the semiconductor device; Forming (1020) a first interconnect structure (106) over and electrically coupled to the first electrical components (103); Forming (1030) a first passivation layer (111) over the first interconnect structure (106), the first passivation layer (111) extending from the first device region (210) to a scribe line region (230) adjacent to the first device region; after forming the first passivation layer (111), removing (1040) the first passivation layer from the scribe line region (230) while maintaining a remaining portion of the first passivation layer (111) in the first device region (210), wherein only the first passivation layer (111) in the scribe line region (220) is removed; and Forming a conductive contact pad (115) through the first passivation layer (111) and electrically coupled to an electrically conductive feature of the first interconnect structure (106); Forming a second passivation layer (117) over the conductive pad (115) and over the first passivation layer (111), the second passivation layer (117) extending from the first device region (210) to the scribe line region (230); and Removing the second passivation layer (117) from the scribe line region (230) while maintaining a remaining portion of the second passivation layer (117) in the first device region (210); and Dicing (1050) along the scribe line region (230) after removing the first passivation layer. [2] The method of claim 1, further comprising, prior to forming the first passivation layer (111), forming a first seal ring (104) in a first seal ring region (220) between the first device region (210) and the scribe line region (230). [3] The method of claim 2, wherein after removing the first passivation layer (111) from the scribe line region (230), the first seal ring region (220) remains covered by the first passivation layer (111). [4] Method according to one of the preceding claims, wherein the singulation is carried out along a singulation path in the scribe line region (230), wherein a width of the singulation path is smaller than a width of the scribe line region (230). [5] Method according to one of the preceding claims, wherein the singulation forms a recess (131) in the substrate, wherein a bottom side of the recess is located between a first side of the substrate (101) facing the first interconnect structure (106) and a second side of the substrate (101) facing away from the first side of the substrate (101). [6] Method according to one of the preceding claims, wherein the singulation (1050) is carried out using a Plasma separation process is carried out. [7] The method of any preceding claim, further comprising, after dicing (1050), reducing a thickness of the substrate (101) from the second side of the substrate (101), wherein after reducing the thickness of the substrate (101), the recess (131) extends through the substrate (101). [8] A method according to any one of the preceding claims, wherein the first passivation layer (111) and the second passivation layer (117) in the scribe line region are removed by performing an anisotropic etching process. [9] The method of claim 8, wherein after removing the second passivation layer (117) from the scribe line region (230), a first sidewall (111S) of the first passivation layer (111) facing the scribe line region (230) and a second sidewall (117S) of the second passivation layer (117) facing the scribe line region (230) are aligned along a same line. [10] The method of claim 8, wherein after removing the second passivation layer (117) from the scribe line region (230), a first sidewall of the first passivation layer (111) facing the scribe line region (230) is closer to the scribe line region (230) than a second sidewall of the second passivation layer (117) facing the scribe line region (230). [11] The method of claim 8, wherein after removing the second passivation layer (117) from the scribe line region (230), a first sidewall of the first passivation layer (111) facing the scribe line region (230) is located farther from the scribe line region (230) than a second sidewall of the second passivation layer (117) facing the scribe line region (230). [12] A method according to any one of the preceding claims, further comprising: Forming second electrical components (103) in the substrate (101) in a second device region (210) of the semiconductor device, wherein the scribe line region (230) is located between the first device region (210) and the second device region (210); and Forming a second interconnect structure (106) over and electrically coupled to the second electrical components (103), wherein forming the first passivation layer (111) comprises forming the first passivation layer (111) such that it extends continuously from the first device region (210) to the second device region (210), wherein after removing the first passivation layer (111) from the scribe line region (230), the first passivation layer (111) covers an upper surface of the first interconnect structure (106) and covers an upper surface of the second interconnect structure (106). [13] A method of manufacturing a semiconductor device, the method comprising: Forming (1020) a first interconnect structure (106) and a second interconnect structure (106) over a substrate (101) respectively in a first device region (210) and a second device region (210) of the semiconductor device, wherein a scribe line region (230) of the semiconductor device is arranged between the first device region (210) and the second device region (210); Forming (1030) a first passivation layer (111) over the first interconnect structure (106) and over the second interconnect structure (106), wherein the first passivation layer (111) extends continuously from the first device region (210) to the second device region (210); Removing (1040) a first portion of only the first passivation layer (111) from the scribe line region (230); and, Forming a second passivation layer (117) over the first passivation layer (111), wherein the second passivation layer (117) extends continuously from the first device region (210) to the second device region (210); and Removing a second portion of the second passivation layer (117) from the scribe line region (230); and after removing the second portion of only the second passivation layer from the scribe line region, performing a plasma dicing process to form a trench (131) in the scribe line region (230) extending into the substrate (101) from a first side of the substrate (101) facing the first passivation layer (111). [14] The method of claim 13, wherein the first passivation layer (111) and the second passivation layer (117) are formed from a nitride-containing material. [15] The method of claim 13 or 14, wherein the depth of the trench (131) into the substrate (101) is less than the thickness of the substrate (101). [16] The method of claim 15, wherein the method further comprises, after performing (1050) the plasma dicing process, reducing the thickness of the substrate (101) from a second side of the substrate (101) facing away from the first passivation layer (111) such that the trench (131) extends through the substrate (101). [17] The method according to any one of claims 13 to 15, wherein the first passivation layer (111) and the second passivation layer (117) in the scribe line region are removed by performing an anisotropic etching process. [18] The method of claim 13, wherein after removing the second portion of the second passivation layer (117), a first sidewall of the first passivation layer (111) facing the scribe line region (230) has a first distance from the scribe line region (230) and a second sidewall of the second passivation layer (117) closest to the first sidewall has a second distance from the scribe line region (230), the first distance being different from the second distance. [19] Semiconductor device comprising: a substrate (101); electrical components (103) in the substrate (101); an interconnect structure (106) over the substrate (101) and electrically coupled to the electrical components (103); a sealing ring (104) around the interconnect structure (106); a first passivation layer (111) over the interconnect structure (106) and the sealing ring (104); and a dielectric layer (121) over the first passivation layer (111), wherein there is a first lateral distance between a first sidewall of the first passivation layer (111) closest to the sealing ring (104) and a sidewall of the dielectric layer (121) closest to the sealing ring (104); and a second passivation layer (117) between the first passivation layer (111) and the dielectric layer (121), wherein there is a second lateral distance between a second sidewall of the second passivation layer (117) closest to the sealing ring (104) and the sidewall of the dielectric layer (1 21 ) which is closest to the sealing ring (104), where the first lateral distance is equal to the second lateral distance. [20] The device of claim 19, wherein the first passivation layer (111) and the second passivation layer (117) are formed from a nitride-containing material.

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