semiconductor device

Abstract

Semiconductor device comprising: - a semiconductor element (3) mounted on one circuit pattern (2C) among a plurality of circuit patterns (2B) formed on at least one insulating substrate (2); - a plurality of terminal electrodes (5) formed on a housing (4) in which the at least one insulating substrate (2) and the semiconductor element (3) are formed; - an internal wiring (6) connecting the semiconductor element (3) and the plurality of terminal electrodes (5); and - a sealing material (10) which fills a space within the housing (4) and seals the at least one insulating substrate (2) and the semiconductor element (3), wherein: - the internal wiring (6) has: - the plurality of circuit patterns (2B), - a plurality of metal blocks (7, 17, 27) electrically connected to the respective circuit patterns (2B), and - at least one metal wire (9) connecting the plurality of metal blocks (7, 17, 27), - the plurality of metal blocks (7, 17, 27) are integrally attached to the housing (4), and - the at least one metal wire (9) is connected to the plurality of metal blocks (7, 17, 27) at positions which are closer to an upper surface (10A) of the sealing material (10) than surfaces of the plurality of circuit patterns (2B).

Description

Background of the InventionField of the InventionThe present invention relates to a semiconductor deviceDescription of the Prior Art

[0001] A semiconductor device has an overcurrent protection function to prevent an overcurrent caused by a malfunction of a semiconductor chip. However, if the overcurrent protection function fails and a downstream malfunction occurs, a large current flows through electrodes, wires, and a circuit pattern of a main circuit. As a technique for preventing such a situation and minimizing damage to the semiconductor device, a technique of providing a quick-disconnect part within the semiconductor device is known. The quick-disconnect part is formed, for example, in a wire bonding part. When an overcurrent occurs, the wire bonding part quickly burns out, and the overcurrent is interrupted.

[0002] Unexamined Japanese Patent Application Publication (PCT Application Translation) JP 2001-524735 A discloses a semiconductor structure in which a bonding wire connecting a semiconductor substrate and an external connection part functions as a quick-disconnect part. The bonding wire has a loop shape, and the apex of the loop is exposed on a surface of a molding compound that is a sealing material. When an overcurrent flows, the loop exposed on the surface of the molding compound melts.

[0003] To expose the wire on the surface of the sealing material, it is necessary to form a wire bonding part with a high curvature, that is, a wire bonding part with a high loop shape. In a structure where the height from the connecting portion of a metal wire to a surface of a sealing material is large, it is difficult to stably form a loop shape of the metal wire.

[0004] DE 10 2012 224 355 A1 describes a power module in which a power device chip is arranged within an outer housing, and an electrode of the power device chip is connected to an external electrode integrated in the outer housing. The power module includes a heat spreader mounted in the outer housing, the power device chip bonded to the heat spreader with solder, an insulating dam formed on the heat spreader to surround the power device chip, and an internal main electrode, one end of which is bonded to the electrode of the power device chip with solder and the other end of which is attached to an upper surface of the dam. The external electrode and the other end of the internal main electrode are electrically connected to each other by bonding wires. Summary

[0005] To solve the above problems, the present invention provides a semiconductor device in which a loop-shaped metal wire functioning as a quick-disconnect part is stably formed.

[0006] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1. Advantageous further developments are the subject of the respective dependent claims

[0007] A semiconductor device according to the present invention comprises a semiconductor element, a plurality of terminal electrodes, internal wiring, and a sealing material. The semiconductor element is mounted on a circuit pattern among a plurality of circuit patterns formed on the at least one insulating substrate. The plurality of terminal electrodes is formed on a case in which the at least one insulating substrate and the semiconductor element are formed. The internal wiring connects the semiconductor element and the plurality of terminal electrodes. The sealing material fills a space in the case and seals the at least one insulating substrate and the semiconductor element. The internal wiring includes the plurality of circuit patterns, a plurality of metal blocks, and at least one metal wire. The plurality of metal blocks are electrically connected to the respective circuit patterns.The at least one metal wire connects the plurality of metal blocks. The plurality of metal blocks are integrally attached to the housing. The at least one metal wire is connected to the plurality of metal blocks at positions closer to an upper surface of the sealing material than the plurality of circuit patterns.

[0008] According to the present invention, there is provided a semiconductor device in which a loop shape of a metal wire functioning as the quick-disconnect part is stably formed.

[0009] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. Short description of the characters Fig. 1 is a plan view illustrating a configuration of a semiconductor device according to a first preferred embodiment; Fig. 2 is a cross-sectional view illustrating the configuration of the semiconductor device according to the first embodiment; Fig. 3 is a plan view illustrating a configuration of the semiconductor device according to a second preferred embodiment; Fig. 4 is a cross-sectional view illustrating the configuration of the semiconductor device according to the second preferred embodiment; Fig. 5 is a plan view illustrating a configuration of the semiconductor device according to a third preferred embodiment; Fig. 6 is a cross-sectional view illustrating the configuration of the semiconductor device according to the third preferred embodiment; Fig. 7 is a plan view illustrating a configuration of a semiconductor device according to a fourth preferred embodiment; Fig. 8 is a circuit diagram illustrating a configuration of a semiconductor device according to a fifth preferred embodiment; Fig. 9 is a diagram illustrating a configuration of a semiconductor device provided with the Fig. 8 corresponds to the circuit diagram illustrated. Fig. 10 is a cross-sectional view illustrating a configuration of a semiconductor device according to a sixth preferred embodiment; and Fig. 11 is a cross-sectional view illustrating a configuration of a semiconductor device according to a seventh preferred embodiment. Description of the preferred embodiments<Erste bevorzugte Ausführungsform>

[0010] The Fig. 1 and Fig. 2 are a plan view and a cross-sectional view each illustrating a configuration of a semiconductor device according to the first preferred embodiment.

[0011] The semiconductor device comprises a base plate 1, an insulating substrate 2, a semiconductor element 3, a housing 4, a terminal electrode 5, an internal wiring 6, and a sealing material 10. In Fig. 1, the illustration of the sealing material 10 is omitted.

[0012] The insulating substrate 2 is bonded to the base plate 1. The insulating substrate 2 includes a plate-shaped insulating member 2A and at least one circuit pattern 2B provided on a surface of the plate-shaped insulating member 2A. The semiconductor device according to the first preferred embodiment includes two insulating substrates 2, and the semiconductor device includes a plurality of circuit patterns 2B.

[0013] The semiconductor element 3 is connected on a circuit pattern 2C among a plurality of circuit patterns 2B through an interconnection material. The semiconductor element 3 is formed of, for example, a semiconductor such as Si or a so-called wide band gap semiconductor such as SiC or GaN. The semiconductor element 3 is, for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a Schottky diode, or the like. The semiconductor element 3 is, for example, a power semiconductor element.

[0014] The housing 4 has a frame shape in a plan view. The housing 4 contains the insulating substrate 2 and the semiconductor element 3. The housing 4 is made of resin, for example.

[0015] The terminal electrode 5 is provided on the housing 4. Although only one terminal electrode 5 is provided in the Fig. 1 and Fig. 2, the semiconductor device comprises two terminal electrodes (see Fig. 7, which will be described later). One terminal electrode is connected to a P-side of the semiconductor element 3, and the other terminal electrode is connected to an N-side of the semiconductor element 3. A part of the terminal electrode 5 is inserted into the case 4. In other words, the terminal electrode 5 is integrally fixed to the case 4. The terminal electrode 5 is a terminal for connecting an external circuit.

[0016] The internal wiring 6 connects the semiconductor element 3 and the respective terminal electrodes 5. The internal wiring 6 includes the plurality of circuit patterns 2B, a plurality of metal blocks 7, a first metal wire 8, and a second metal wire 9 as circuit elements.

[0017] The plurality of metal blocks 7 are electrically connected to the respective circuit patterns 2B. In the first preferred embodiment, two metal blocks 7 are individually mounted on two circuit patterns 2B. For example, lower surfaces of the metal blocks 7 are connected to the circuit patterns 2B by a connecting material. A part of the respective metal blocks 7 is inserted into the housing 4. In other words, the metal blocks 7 are integrally fixed to the housing 4. The metal blocks 7 are made of aluminum, gold, silver, copper, or an alloy thereof. A shape of the metal blocks 7 is not limited to a cube or a rectangular parallelepiped, and may be a round shape or a triangle.

[0018] The first metal wire 8 connects the terminal electrode 5 and the circuit pattern 2c, connects the semiconductor element 3 and the circuit pattern 2B, and connects the two circuit patterns 2B. As shown in Fig. 1, a plurality of first metal wires 8 can connect two circuit elements.

[0019] The second metal wire 9 connects the two metal blocks 7. As in Fig. As illustrated in FIG. 1, a plurality of second metal wires 9 may connect the two metal blocks 7. The second metal wire 9 is connected to the metal blocks 7 at positions closer to an upper surface 10A of the sealing material 10 than a surface of the circuit pattern 2B. Both ends of the second metal wire 9 are connected to upper surfaces of the respective two metal blocks 7.

[0020] A degree to which the second metal wire 9 is curved is smaller than a degree to which the first metal wire 8 is curved. Alternatively, a height from the upper surface of the metal block 7 to the apex of the second metal wire 9 is lower than a height from a surface of a switching element to which the first metal wire 8 is connected to the apex of the first metal wire 8.

[0021] The limit load integral (I 2 t) of the second metal wire 9 is smaller than the limit load integral of the circuit pattern 2B and the first metal wire 8. Therefore, the second metal wire 9 burns out more easily than the first metal wire 8. That is, the second metal wire 9 forms a quick-disconnection part. Such a configuration is realized, for example, by adjusting the number of parallel connections, the wire diameters, the wire lengths, and the like of the first metal wire 8 and the second metal wire 9.

[0022] The sealing material 10 fills a space within the frame shape of the housing 4 and seals mounted components such as the insulating substrate 2 and the semiconductor element 3.

[0023] As described above, the semiconductor device includes at least one second metal wire 9 having a smaller limiting load integral than those of the first metal wire 8 and the circuit pattern 2B. In other words, the internal wiring 6 includes one or more parts whose limiting load integral is smaller than the limiting load integral of the first metal wire 8 and the circuit pattern 2B. When the overcurrent protection function fails and a downstream malfunction occurs, the second metal wire 9 quickly burns out, and thus the semiconductor device and a semiconductor module including the semiconductor device are prevented from being destroyed.

[0024] In summary, the semiconductor device according to the first preferred embodiment includes the semiconductor element 3, the plurality of terminal electrodes 5, the internal wiring 6, and the sealing material 10. The semiconductor element 3 is mounted on a circuit pattern 2C among a plurality of circuit patterns 2B provided on at least one insulating substrate 2. The plurality of terminal electrodes 5 are provided on the case 4, in which at least one insulating substrate 2 and the semiconductor element 3 are contained. The internal wiring 6 connects the semiconductor element 3 and the plurality of terminal electrodes 5. The sealing material 10 fills a space within the case 4 and seals at least one insulating substrate 2 and the semiconductor element 3.The internal wiring 6 includes the plurality of circuit patterns 2B, the plurality of metal blocks 7, and at least one metal wire (the second metal wire 9). The plurality of metal blocks 7 are electrically connected to the respective circuit patterns 2B. At least one second metal wire 9 connects the plurality of metal blocks 7. At least one second metal wire 9 is connected to the plurality of metal blocks 7 at positions closer to the upper surface 10A of the sealing material 10 than the plurality of circuit patterns 2B.

[0025] In such a semiconductor device, points where the second metal wire 9 is connected, that is, positions where the second metal wire 9 is connected to the metal block 7, are close to the upper surface 10A of the sealing material 10. Even in a case where a distance from the circuit pattern 2B to the surface of the sealing material 10 is large, the second metal wire 9 has a loop shape with a smooth curvature. It is easy to form such a smooth loop shape. In other words, the loop shape of the second metal wire 9, which functions as the quick-disconnect part, is stably formed. It also becomes easy to identify a part damaged due to an overcurrent.

[0026] Furthermore, the plurality of metal blocks 7 of the semiconductor device according to the first preferred embodiment are integrally fixed to the case 4 and mounted on the plurality of circuit patterns 2B, and thus, the plurality of metal blocks 7 are electrically connected to the plurality of circuit patterns 2B. Both ends of at least one second metal wire 9 are connected to the upper surfaces of the respective metal blocks 7.

[0027] By means of such a configuration, in a manufacturing process of the semiconductor device, positions of the metal block 7 with respect to the circuit patterns 2B are automatically determined by mounting the package 4 at a predetermined position with respect to the base plate 1 on which the insulating substrate 2 has been mounted. This facilitates the assembly of the semiconductor device. <Zweite bevorzugte Ausführungsform>

[0028] A semiconductor device according to the second preferred embodiment will be described below. The second preferred embodiment is a subordinate concept of the first preferred embodiment, and the semiconductor device according to the second preferred embodiment includes the constituent elements of the semiconductor device according to the first preferred embodiment. Note that a description of the configuration and operation similar to those of the first preferred embodiment will be omitted.

[0029] The Fig. 3 and Fig. 4 are a plan view and a cross-sectional view, each illustrating a configuration of the semiconductor device according to the second preferred embodiment. A shape of a metal block 17 of the semiconductor device according to the second preferred embodiment is different from the shape of the metal block 17 according to the first preferred embodiment. The metal block 17 has a cranked shape in a cross-sectional view. A part of the respective cranked-shaped metal blocks 17 is inserted into the case 4. In other words, the metal blocks 17 are integrally fixed to the case 4.

[0030] By means of such a configuration, a loop shape of the second metal wire 9, which functions as a quick-disconnect part, is stably formed. Furthermore, in a manufacturing process of the semiconductor device, positions of the metal blocks 17 with respect to the circuit patterns 2B are automatically determined by mounting the housing 4 at a predetermined position of the base plate 1 on which the insulating substrate 2 has been mounted. This facilitates the assembly of the semiconductor device. <Dritte bevorzugte Ausführungsform>

[0031] A semiconductor device according to the third preferred embodiment will be described below. The semiconductor device according to the third preferred embodiment includes the constituent elements of the semiconductor device according to the first preferred embodiment. Note that a description of the configuration and operation similar to those of the first and second preferred embodiments will be omitted.

[0032] The Fig. 5 and Fig. 6 are a plan view and a cross-sectional view, each illustrating a configuration of the semiconductor device according to the third preferred embodiment. A configuration of metal blocks of the semiconductor device according to the third preferred embodiment is different from that of the first preferred embodiment.

[0033] The plurality of metal blocks according to the third preferred embodiment is a plurality of terminal electrodes 15. That is, the terminal electrodes 15 have the functions of the metal blocks 7 in the first preferred embodiment. Specifically, two terminal electrodes 15 located on the right side in Fig. 5, the functions of the two metal blocks 7. The two terminal electrodes 15 are connected to one polarity of the semiconductor element 3. The terminal electrode 5, which is shown on the left side in Fig. 5 is connected to the other polarity of the semiconductor element 3 and does not have the functions of the metal blocks 7.

[0034] A part of each of the two terminal electrodes 15, which have the functions of the metal blocks 7, is inserted into the housing 4. In other words, the terminal electrodes 15 are integrally fixed to the housing 4. Lower parts 15A of the terminal electrodes 15 are connected to circuit patterns 2B by first metal wires 8. Upper surfaces 15B of the terminal electrodes 15 are higher than the upper surface 10A of the sealing material 10. The upper surfaces 15B of the terminal electrodes 15 are provided on an upper surface of the housing 4. Both ends of the second metal wire 9 are connected to the upper surfaces 15B of each of the two terminal electrodes 15.

[0035] By means of such a configuration, a loop shape of the second metal wire 9, which functions as a quick-disconnect part, is stably formed. Furthermore, in a manufacturing process of the semiconductor device, positions of the metal blocks 7, that is, positions of the terminal electrodes 15 with respect to the circuit patterns 2B, are automatically determined by mounting the package 4 at a predetermined position on the base plate 1 on which the insulating substrate 2 has been mounted. Moreover, the lower parts 15A of the terminal electrodes 15 and the circuit patterns 2B can be connected to each other by the first metal wires 8, and further, the two terminal electrodes 15 can be connected to each other by the second metal wire 9 even after filling the sealing material 10. This facilitates the assembly of the semiconductor device. <Vierte bevorzugte Ausführungsform>

[0036] A semiconductor device according to the fourth preferred embodiment will be described below. The semiconductor device according to the fourth preferred embodiment includes the constituent elements of the semiconductor device according to the first preferred embodiment. Note that a description of the configuration and operation similar to those of the first to third preferred embodiments will be omitted.

[0037] Fig. 7 is a plan view illustrating a configuration of the semiconductor device according to the fourth preferred embodiment.

[0038] The housing 4 has a rectangular flat shape and, in a plan view, specifically has a rectangular frame shape. A frame on a short side is wider than a frame on a long side.

[0039] The terminal electrodes 5 and the metal blocks 27 are provided on the short sides of the housing 4. A part of the respective terminal electrodes 5 and the metal blocks 27 is inserted into the housing 4. In other words, the terminal electrodes 5 and the metal blocks 27 are integrally fixed to the housing 4. A lower part of the respective terminal electrodes 5 and the metal blocks 27 is connected to the circuit pattern 2B by the first metal wires 8.

[0040] Upper surfaces of the metal blocks 27 are higher than the upper surface 10A of the sealing material 10. The upper surfaces of the metal blocks 27 are provided on the upper surface of the housing 4. Both ends of the second metal wire 9 are connected to the upper surfaces of the respective two metal blocks 27.

[0041] Such a configuration can reduce an entire shape of the package 4, thereby preventing an increase in size of the semiconductor device. <Fünfte bevorzugte Ausführungsform>

[0042] A semiconductor device according to a fifth preferred embodiment will be described below. The semiconductor device according to the fifth preferred embodiment includes the constituent elements of the semiconductor device according to the first preferred embodiment. Note that a description of the configuration and operation similar to those of the first to fourth preferred embodiments will be omitted.

[0043] Fig. 8 is a circuit diagram illustrating a configuration of a semiconductor device according to the fifth preferred embodiment. Fig. 9 illustrates a configuration of the semiconductor device used with the Fig. 8 corresponds to the circuit diagram illustrated.

[0044] The semiconductor device comprises two semiconductor elements 3, a first terminal electrode 25, and a second terminal electrode 35. The two semiconductor elements 3 are individually mounted on two circuit patterns 2C and are serially connected to each other by the first metal wire 8.

[0045] The first terminal electrode 25 is connected to a P-side of the semiconductor element 3, and the second terminal electrode 35 is connected to an N-side of the semiconductor element 3.

[0046] The plurality of metal blocks 7 includes a plurality of first metal blocks 37 provided between the first terminal electrode 25 and the semiconductor elements 3. The plurality of metal blocks 7 further includes a plurality of second metal blocks 47 provided between the second terminal electrode 35 and the semiconductor elements 3. In this example, two first metal blocks 37 and two second metal blocks 47 are provided. As described above, according to the fifth preferred embodiment, the plurality of metal blocks 7 are arranged on both the P-side and the N-side of the semiconductor elements 3.

[0047] The two first metal blocks 37 are connected to each other by a second metal wire 9, and the two second metal blocks 47 are connected to each other by a second metal wire 9.

[0048] By means of such a configuration, a short-circuit failure or a ground fault failure is prevented. Although an example was described above in which the plurality of metal blocks 7 are arranged on both the P-side and the N-side of the semiconductor element 3, a plurality of terminal electrodes 15 having the functions of the metal blocks 7 may be arranged on both the P-side and the N-side of the semiconductor element 3, as described in the third preferred embodiment. Similar effects are also produced in such a case. <Sechste bevorzugte Ausführungsform>

[0049] A semiconductor device according to the sixth preferred embodiment will be described below. The semiconductor device according to the sixth preferred embodiment includes the constituent elements of the semiconductor device according to the first preferred embodiment. Note that a description of the configuration and operation similar to those of the first to fifth preferred embodiments will be omitted.

[0050] Fig. 10 is a cross-sectional view illustrating a configuration of the semiconductor device according to the sixth preferred embodiment.

[0051] Upper surfaces 57A of metal blocks 57 protrude above the upper surface 10A of the sealing material 10. In other words, the metal blocks 57 have a height such that the upper surfaces 57A are higher than the upper surface 10A of the sealing material 10. Both ends of the second metal wire 9 are connected to the upper surfaces 57A of the metal block 57.

[0052] By means of such a configuration, a loop shape of the second metal wire 9, which functions as a quick-disconnect part, is stably formed. Furthermore, in a manufacturing process of the semiconductor device, a step of connecting the metal block 57 by the second metal wire 9 after filling the sealing material 10, that is, a post-wiring connecting step, can be realized. This facilitates the assembly of the semiconductor device. <Siebte bevorzugte Ausführungsform>

[0053] A semiconductor device according to the seventh preferred embodiment will be described below. The semiconductor device according to the seventh preferred embodiment includes the constituent elements of the semiconductor device according to the first preferred embodiment. Note that a description of the configuration and operation similar to those of the first to sixth preferred embodiments will be omitted.

[0054] Fig. 11 is a cross-sectional view illustrating a configuration of the semiconductor device according to the seventh preferred embodiment.

[0055] As in the sixth preferred embodiment, the upper surfaces 57A of the metal block 57 protrude above the upper surface 10A of the sealing material 10. In the seventh preferred embodiment, an insulating material 11 is further provided between the two metal blocks 57. The insulating material 11 connects the two metal blocks 57. Both ends of the second metal wire 9 are connected to the upper surfaces 57A of the metal block 57. In a manufacturing process, a component prepared in advance by coupling the two metal blocks 57 using the insulating material 11, that is, a coupled block 12, which is a semi-finished product, can be connected to the circuit pattern 2B. Moreover, the second metal wire 9 can be connected to the two metal blocks 57 before the coupled block 12 is connected to the circuit pattern 2B.

[0056] By means of such a configuration, a loop shape of a second metal wire 9, which functions as a quick-disconnect part, is stably formed. Furthermore, in the manufacturing process of the semiconductor device, a step of applying the sealing material 10 after connecting the coupled block 12 using the second metal wire 9, that is, a pre-wiring connection step, can be realized. This facilitates the assembly of the semiconductor device. Furthermore, in a case where the insulating material 11 is thin, a distance between the two metal blocks 57 becomes small, and a wiring inductance (Ls) becomes small. <Achte bevorzugte Ausführungsform>

[0057] A semiconductor device according to the eighth preferred embodiment will be described below. The semiconductor device according to the eighth preferred embodiment includes the constituent elements of the semiconductor device according to the first preferred embodiment. Note that a description of the configuration and operation similar to those of the first to seventh preferred embodiments will be omitted.

[0058] The semiconductor element 3 is a switching element or a diode element as described above. The semiconductor device 3 may be made of silicon (Si), but it may preferably be made of a wide-bandgap semiconductor having a wider bandgap than that of silicon. The wide-bandgap semiconductor is, for example, a material including silicon carbide (SiC) or gallium nitride (GaN). Alternatively, the wide-bandgap semiconductor is, for example, diamond.

[0059] The switching element and the diode element, which are formed of the wide band gap semiconductor, have high withstand voltage, high allowable current density, high heat resistance and low power loss.

[0060] The high dielectric strength and the high allowable current density enable a reduction in the size of the switching element and the diode element, thereby enabling a reduction in the size of the semiconductor module containing the switching element and the diode element.

[0061] The high thermal resistance allows a reduction in the size of a heat radiation fin or a heat sink, thereby enabling a further reduction in the size of the semiconductor module.

[0062] The low power loss enables an improvement in the efficiency of the switching element and the diode element, thereby enabling an improvement in the efficiency of the semiconductor module.

[0063] Both the switching element and the diode element are preferably formed from a wide band gap semiconductor, but either the switching element or the diode element may be formed from the wide band gap semiconductor. Even with such a configuration, the effects described in the above preferred embodiments can be obtained.

Claims

[1] A semiconductor device comprising: - a semiconductor element (3) mounted on one circuit pattern (2C) among a plurality of circuit patterns (2B) formed on at least one insulating substrate (2); - a plurality of terminal electrodes (5) formed on a housing (4) in which the at least one insulating substrate (2) and the semiconductor element (3) are formed; - an internal wiring (6) connecting the semiconductor element (3) and the plurality of terminal electrodes (5); and - a sealing material (10) which fills a space within the housing (4) and seals the at least one insulating substrate (2) and the semiconductor element (3), wherein: - the internal wiring (6) has: - the plurality of circuit patterns (2B), - a plurality of metal blocks (7, 17, 27) electrically connected to the respective circuit patterns (2B), and - at least one metal wire (9) connecting the plurality of metal blocks (7, 17, 27), - the plurality of metal blocks (7, 17, 27) are integrally attached to the housing (4), and - the at least one metal wire (9) is connected to the plurality of metal blocks (7, 17, 27) at positions which are closer to an upper surface (10A) of the sealing material (10) than surfaces of the plurality of circuit patterns (2B). [2] A semiconductor device according to claim 1, wherein: - the plurality of metal blocks (7, 17, 27) are mounted on a plurality of circuit patterns (2B) and are thus electrically connected to the plurality of circuit patterns (2B), and - both ends of the at least one metal wire (9) are connected to upper surfaces of the respective metal blocks (7, 17, 27). [3] A semiconductor device according to claim 2, wherein each of the plurality of metal blocks (7, 17) has a cranked shape. [4] A semiconductor device according to claim 1, wherein: - the plurality of connection electrodes (15) are integrally connected to the housing (4), - the plurality of metal blocks (7, 17, 27) is the plurality of terminal electrodes (15), and - both ends of the at least one metal wire (9) are connected to upper surfaces (15B) of the respective connection electrodes (15). [5] A semiconductor device according to any one of claims 1 to 4, wherein: - the housing (4) has a rectangular flat shape, and - the plurality of metal blocks (7, 17, 27) are formed on a short side of the housing (4). [6] A semiconductor device according to any one of claims 1 to 5, wherein: - the plurality of connection electrodes (5) comprises: - a first terminal electrode (25) which is connected to a P-side of the semiconductor element (3) and - a second terminal electrode (35) connected to an N-side of the semiconductor element (3), - the plurality of metal blocks (7, 17, 27) comprises: - a plurality of first metal blocks (37) formed between the first terminal electrode (25) and the semiconductor element (3) and - a plurality of second metal blocks (47) formed between the second terminal electrode (35) and the semiconductor element (3), and - the at least one metal wire (9) is a plurality of metal wires comprising a metal wire for connecting the plurality of first metal blocks (37) and a metal wire for connecting the plurality of second metal blocks (47). [7] A semiconductor device according to any one of claims 1 to 6, wherein upper surfaces (57A) of the plurality of metal blocks (57) to which the at least one metal wire (9) is connected each protrude above the upper surface (10A) of the sealing material (10). [8] A semiconductor device according to any one of claims 1 to 7, wherein the plurality of metal blocks (57) are coupled by an insulating material (11). [9] A semiconductor device according to any one of claims 1 to 8, wherein the semiconductor element (3) comprises SiC. [10] A semiconductor device according to any one of claims 1 to 9, wherein the limit load integral of the at least one metal wire (9) is smaller than the limit load integral of each of the plurality of circuit patterns (2B).

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