GATE-CONTROLLED LATERAL BIPOLAR / HETEROJUNCTION TRANSISTORS

Abstract

Structure, comprehensive: an emitter area (16b); a collector area (16a); Base regions on opposite sides of the emitter region (16b) and the collector region (16a); and a gate structure (18) composed of a body region (18b) and leg regions (18a), wherein the body region (18b) is located between the base regions on opposite sides of the emitter region (16b) and the collector region (16a), and the leg regions (18a) isolate the base regions from both the emitter region (16b) and the collector region (16a), wherein the base regions are extrinsic base regions (14a), the body region (18b) of the gate structure (18) is located above an intrinsic base region (19) between the collector region (16a) and the emitter region (16b), and further comprising an epitaxial material in the extrinsic base regions (14a) between the limb regions (18a).

Description

FIELD OF THE INVENTION

[0001] The present disclosure relates to semiconductor structures and, more particularly, to gate-controlled transistors and fabrication methods. BACKGROUND

[0002] A bipolar junction transistor (BJT) is a type of transistor that uses both electrons and holes as charge carriers. A heterojunction bipolar transistor (HBT) is an improvement on the BJT that can handle very high-frequency signals up to several hundred GHz. BJTs and HBTs can be used as amplifiers or switches in integrated semiconductor devices, giving them applicability in many types of electronic equipment, such as mobile devices, audio amplifiers, industrial control, radio transmitters, etc.

[0003] BJTs and HBTs have three differently doped semiconductor regions: the emitter region, the base region, and the collector region. These regions are p-type, n-type, and p-type, respectively, in a PNP transistor, and n-type, p-type, and n-type in an NPN transistor. For an HBT, different semiconductor elements are used for the transistor. For example, the emitter can be made of a material with a larger band gap than the base.

[0004] However, in any configuration, the base is located between the emitter and the collector. The base is lightly doped material, whereas the collector and emitter, for example, are highly doped. It is known that, due to the proximity between the base and the collector and emitter, a leakage current occurs between the base and collector or the base and emitter on each side base.

[0005] US Pat. No. 9,761,664 B1 discloses an integrated circuit with a lateral bipolar transistor. The bipolar transistor has an emitter, a base, and a collector formed in a semiconductor layer. An insulating material over the base insulates the bipolar transistor from the gate structures of the integrated circuit.

[0006] US 2007 / 0 105 310 A1 further discloses a lateral bipolar transistor having at least one emitter, a plurality of collectors, and a plurality of base contacts. The collectors are arranged adjacent to the sides of the at least one emitter, and none of the base contacts are arranged adjacent to the sides of the emitter. BRIEF SUMMARY

[0007] In one aspect of the disclosure, a structure comprises: an emitter region; a collector region; base regions on opposite sides of the emitter region and the collector region; and a gate structure composed of a body region and leg regions, wherein the body region is located between the base regions on opposite sides of the emitter region and the collector region, and the leg regions isolate the base regions from both the emitter region and the collector region, wherein the base regions are extrinsic base regions, the body region of the gate structure is located over an intrinsic base region between the collector region and the emitter region, and further comprising an epitaxial material in the extrinsic base regions between the leg regions.

[0008] In one aspect of the disclosure, a structure comprises: a semiconductor material comprising an emitter region; a collector region; and at least one base region; and a segmented gate structure comprising isolation regions in and / or above respective openings of the semiconductor material positioned between the at least one base region and both the emitter region and the collector region, and wherein the at least one base region is a first extrinsic base region at one end and a second extrinsic base region at another end, the first extrinsic base region is isolated from both the emitter region and the collector region by first and second isolation regions at the one end, and the second extrinsic base region is isolated from both the emitter region and the collector region by third and fourth isolation regions at the other end.

[0009] In one aspect of the disclosure, a structure comprises: a transistor formed using semiconductor-on-insulator (SOI) technology and composed of: an emitter region, a collector region, extrinsic base regions on opposite sides of the emitter region and the collector region; and an active body region of a gate structure composed of polysilicon material and extending between the extrinsic base regions;and isolation regions extending from the active body region of the gate structure, the isolation regions positioned to isolate the extrinsic base regions from both the emitter region and the collector region, the active body region of the gate structure being located over an intrinsic base region between the collector region and the emitter region, and further comprising an epitaxial material in the extrinsic base regions between the isolation regions of the gate structure.; BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The present disclosure is described in the following detailed description with reference to the aforementioned plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. Fig. 1A shows a top view of structured diffusion regions, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 1B shows a top view of a transistor on the structure diffusion regions and respective manufacturing processes according to aspects of the present disclosure. Fig. 2 shows a top view of a transistor and respective manufacturing processes according to additional aspects of the present disclosure. Fig. 3 shows a top view of a multi-finger transistor according to additional aspects of the present disclosure. Fig. 4 shows a top view of a transistor according to additional aspects of the present disclosure. Fig. 5 shows a top view of a multi-finger transistor according to additional aspects of the present disclosure. Fig. 6A and Fig. 6B show cross-sectional views of a transistor (ie, a lateral bipolar transistor) according to aspects of the present disclosure. Fig. 7A and Fig. 7B show cross-sectional views of a transistor (ie, a lateral heterojunction bipolar transistor) according to aspects of the present disclosure. DETAILED DESCRIPTION

[0011] The present disclosure relates to semiconductor structures, and more particularly, to gate-controlled transistors and fabrication methods. In embodiments, the gate-controlled transistors are gate-controlled lateral bipolar / heterojunction transistors. More particularly, the present disclosure relates to an "H"-body gate-controlled lateral bipolar junction transistor (LBJT) with double bases using fully depleted SOI (FDSOI) technology. In further embodiments, the present disclosure relates to an "H"-body gate-controlled lateral heterojunction bipolar transistor (LHBT) with double bases using semiconductor-on-insulator (SOI) technology.Advantageously, both the LBJT and the LHBT described herein reduce leakage current between junctions (base region and emitter / collector regions) to reduce power consumption in standby mode, among other advantages.

[0012] The LBJT and LHBT described herein provide excellent bipolar performance on FDSOI technology and SOI technology, respectively. For example, both the LBJT on FDSOI technology and the LHBT on SOI technology provide improved leakage prevention (e.g., reducing leakage) between base-to-collector or base-to-emitter by controlling gate bias between junctions using a unique segmented H-body gate design. The LBJT on FDSOI technology and the LHBT on SOI technology further improve base resistance with the segmented H-body gate design. The LBJT on FDSOI technology and the LHBT on SOI technology may also include additional epitaxial growth on the base junction to improve base resistance.Furthermore, in further embodiments, both LBJT-on-FDSOI technology and LHBT-on-SOI technology benefit from lower parasitic capacitances and demonstrate excellent bipolar performance for β, gm, and Ic. LHBT-on-SOI technology further improves fT and fMax.

[0013] Both the LBJT and the LHBT are applicable to high-frequency electronic circuits and a system on a chip (SoC). Those skilled in the art will understand that an SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume much less power and occupy much less area than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant force in mobile computing (such as smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0014] The transistors (e.g., LBJT and LHBT) of the present disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools used to form structures with dimensions in the micrometer and nanometer scale are used. The methodologies, i.e., technologies, used to fabricate the transistors of the present disclosure were adopted from integrated circuit (IC) technology. For example, the structures are built on wafers and realized in material films patterned onto the top of a wafer using photolithographic processes.In particular, the fabrication of transistors uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) application of a patterned mask on top of the films by photolithographic imaging, and (iii) etching the film selectively with respect to the mask.

[0015] Fig. Figure 1A shows a top view of a structured diffusion before gate (e.g. transistor) formation, whereas Fig. 1B shows a top view of a transistor formed on the patterned diffusion regions after gate formation. With reference to both Fig. 1A as well as Fig. 1B, structure 10 is an LBJT-on-FDSOI technology comprising a semiconductor material 12 and an insulator layer 17 in the FDSOI technology. Semiconductor material 12 may be any suitable fully depleted semiconductor material, including, but not limited to, Si, SiGe, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors.

[0016] The insulator layer 17 is provided between the semiconductor layer 12 and a wafer material (not shown). The insulator layer 17 comprises any suitable material including silicon oxide, sapphire, or other suitable insulating materials, and / or combinations thereof. An exemplary insulator layer 17 may be a buried oxide layer (BOX). The insulator layer 17 is formed on the wafer by any suitable process, e.g., separation by implantation of oxygen (SIMOX), oxidation, deposition, and / or other suitable processes.

[0017] Still referring to the Fig. 1A and Fig. 1B, the semiconductor material 12 includes structured diffusion regions 14, 16. In particular, the structured diffusion regions include P+ regions 14 and an N+ region 16. In embodiments, the diffusions 14, 16 may be provided by an ion implantation process or an epitaxial doping process (e.g., eSiGe with raised p+ or n+), as known to those skilled in the art, so no further explanation is required herein for a complete understanding of the disclosure. For example, the p+ diffusions 14 may be boron, and the n+ diffusions 16 may be arsenic.

[0018] In embodiments, an extrinsic base 14a of the LBJT is provided in the P+ regions 14 (e.g., forming a dual base region), whereas a collector region 16a and an emitter region 16b are provided in the N+ region 16. An intrinsic base 19 is provided between the collector region 16a and the emitter region 16b.

[0019] A space or opening 15 is provided between the diffusion regions 14, 16 to isolate the extrinsic base region 14a from the collector region 16a and the extrinsic base region 14a from the emitter region 16b. In embodiments, the opening 15 may be formed by conventional lithography and etching techniques known to those skilled in the art. For example, a resist formed over the semiconductor material 12 is exposed to energy (light) to create a structure (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to form one or more trenches (i.e., openings) 15 in the semiconductor material 12 through the openings of the resist. The formation of the openings 15 exposes the underlying insulator layer 17. The resist may be removed by a conventional oxygen ashing process or other known stripping means.

[0020] As further stated in the Fig. As shown in Figure 1B, a segmented H-body gate structure 18 is provided over the diffusion regions 14, 16 and within (and / or above) the opening 15. That is, the segmented H-body gate structure 18 is provided on the N+ diffusion region 16, e.g., between the collector region 16a and the emitter region 16b (above the intrinsic base region 19), and extending within the opening 15 between the diffusion regions 14, 16. It can be seen that the intrinsic base 19 is located between the collector region 16a and the emitter region 16b below the gate structure 18.

[0021] In embodiments, the segmented H-body gate structure 18 comprises segmented legs (e.g., isolation regions) 18a and a main body region 18b (e.g., active gate region), each composed of a poly material deposited as needed by a conventional deposition process, e.g., an epitaxial growth process, followed by a conventional patterning process (e.g., lithography and etching). In embodiments, the main body region 18b extends between the dual base regions 14a along the length of the collector region 16a and the emitter region 16b. The legs 18a of the segmented H-body gate structure 18, on the other hand, are provided within and / or above the openings 15, effectively isolating or separating the different diffusion regions 14, 16.

[0022] As will be appreciated by those of ordinary skill in the art, the segmented H-body gate structure 18, and in particular the legs 18a, effectively isolate or separate the diffusions 14, 16, i.e., isolate the base region 14a from the collector region 16a and the emitter region 16b. Also, in this configuration, by controlling the biasing of the segmented H-body gate structure 18, it is now possible to significantly reduce the leakage current between the junctions, e.g., to reduce the leakage between the base region 14a and the collector region 16a and between the base region 14a and the emitter region 16b.

[0023] As further stated in the Fig. As shown in Figure 1B, a plurality of contacts 20 are formed in the collector region 16a, emitter region 16b, extrinsic base region 14a, and on the body of the segmented H-body gate structure 18, i.e., including the legs 18a. The contacts 20 on the body of the segmented H-body gate structure 18, i.e., the legs 18a, can be used to provide a bias voltage for the gate structure 18. The contacts 20 can be any suitable conductive material. For example, the contacts 20 can be tungsten or aluminum formed by conventional deposition techniques followed by a planarization process.

[0024] Fig. Figure 2 is representative of manufacturing processes according to aspects of the present disclosure. In particular, Fig. 2 illustrates a process for fabricating the legs 18a of the segmented H-body gate structure 18 and the contacts 20, among other features. As a non-limiting example of the fabrication process for forming the legs 18a, a mask is deposited over portions of the epitaxial material (e.g., to protect portions of the soon-to-be-formed segmented H-body gate structure 18), followed by a dicing process (e.g., using a selective etch process) to remove epitaxial material proximate the base region 14a. In this way, the legs 18a are formed within (and / or over) the opening(s) 15. In embodiments, the legs 18a may overlap onto the semiconductor material 12 of the extrinsic base region 14a. Accordingly, the segmented H-body gate structure 18 can be formed over the base region 14, the collector region 16a and the emitter region 16b.

[0025] As previously noted, legs 18a are an epitaxial material (e.g., poly) grown over the cut portions (e.g., openings 15) of base regions 14a. Specifically, legs 18a are grown over openings 15 from the exposed semiconductor material 12 of base region 14a, collector region 16a, and emitter region 16b, resulting in a segmented portion (e.g., segmented legs 18a of gate structure 18) after the cutting process. In embodiments, gate structure 18 is intentionally cut out above the junction to improve extrinsic base-to-intrinsic base transitions. In optional embodiments, after the mask is removed, additional epitaxial material 22 is formed in extrinsic base region 14a between legs 18a to improve base resistance.

[0026] Still referring to the Fig. 2, the plurality of contacts 20 are formed in the collector region 16a, the emitter region 16b, and the extrinsic base region 14a, including on the segmented H-body gate structure 18, i.e., the legs 18a. To form the contacts 20, an interlevel dielectric material 24 may be deposited over the structure using a conventional chemical vapor deposition (CVD) process. The interlevel dielectric material 24 may, as one example, be an oxide-based material. A plurality of trenches are formed in the interlevel dielectric material 24 using conventional lithography and etching processes, exposing the underlying diffusion regions 14, 16 and the poly material of the legs 18a of the segmented H-body gate structure 18.A conductive material is deposited within the trenches, followed by a conventional chemical mechanical polishing (CMP) process to remove any excess material on the interlevel dielectric material.

[0027] Fig. 3 shows a multi-finger LBJT 10a according to aspects of the present disclosure. As shown in Fig. 3, the LBJT 10a includes a plurality of segmented H-body gate structures 18, each having contacts 20 on its legs 18a. As described with respect to the Fig. 1A and Fig. 1B, the segmented H-body gate structures 18 may be reverse biased to significantly reduce the interjunction leakage current, e.g., to reduce the leakage between the base region 14a and the collector region 16a and between the base region 14a and the emitter region 16b.

[0028] Fig. 4 shows a top view of a transistor according to additional aspects of the present disclosure. In this embodiment, structure 10b is LHBT-on-SOI technology with dual bases 14a. In LBHT 10b, a semiconductor material 26 is deposited over the SOI technology in the collector region 16a and partially over the intrinsic base 19 before forming the segmented H-body gate structure 18. In alternative embodiments, semiconductor material 26 is deposited over emitter region 16b and partially over the intrinsic base 19 before forming the segmented H-body gate structure 18. In any alternative, semiconductor material 26 may also extend into the extrinsic base region 14a (via openings 15).

[0029] To form the LBHT 10b, two different semiconductor materials 12, 26 are provided in the channel region of the gate structure 18. For example, as will be appreciated by those skilled in the art, for an LBHT, the semiconductor material 26 is partially beneath the gate structure 18 and is a different material from the semiconductor material 12 used to form the collector region 16a, the emitter region 16b, and the base regions (i.e., both the intrinsic base region 19 (beneath the gate structure) and the extrinsic base region 14). By way of non-limiting illustration, the semiconductor material 26 partially within the channel of the gate structure 18 may be SiGe, whereas the semiconductor material 12 in remaining portions of the channel of the gate structure may be Si (e.g., SOI technology), although other semiconductor materials are contemplated herein.The semiconductor material 26 can be deposited directly on the semiconductor material 12 by a conventional epitaxial growth process.

[0030] Still referring to the Fig. 4, after the formation of the semiconductor material 26, the segmented H-body gate structure 18 and contacts 20 can be arranged in the manner shown in relation to the Fig. 1B and Fig. 2. For example, the segmented H-body gate structure 18 may be fabricated over the semiconductor material 26 and semiconductor material 12 in a manner similarly described herein. The contacts 20 may be fabricated directly over the semiconductor material 26, in addition to the semiconductor material 12 of the emitter region 16, the base region 14a, and the body of the segmented H-body gate structure 18.

[0031] Fig. 5 shows a multi-finger LHBT 10c according to aspects of the present disclosure. As shown in Fig. 5, the LBHT comprises a plurality of segmented H-body gate structures 18 with double bases 14a, all of which have contacts 20. As described with respect to the Fig. As noted in Figure 4, the semiconductor material 26 is deposited over the collector region 16a and the emitter region 16b and partially over the intrinsic base 19 of adjacent segmented H-body gate structures 18. That is, the semiconductor material 26 may extend between adjacent devices.

[0032] Fig. 6A and Fig. 6B show cross-sectional views of a transistor (ie, lateral bipolar transistor) according to aspects of the present disclosure. In particular, Fig. 6A is a cross-sectional view of the transistor of Fig. 1B along a line “y”, whereas Fig. 6B is a cross-sectional view of the transistor of Fig. 1B along a line “x”. With reference to both the Fig. 6A as well as the Fig. 6B, the segmented H-body gate structures 18 include legs 18a provided above the diffusions 14a. In embodiments, the diffusions 14a may be raised semiconductor material, e.g., p+ eSiGe. The active body region 18b of the segmented H-body gate structures 18 includes a gate dielectric material 30 composed, for example, of a high-k dielectric material. The high-k dielectric material may be, for example, HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations including multilayers thereof. The segmented H-body gate structures 18 may also include sidewall spacers 32, e.g., nitride, formed by a conventional deposition process (e.g., CVD) followed by an anisotropic etching process. The sidewall spacers 32 isolate the gate structure from the source and drain regions 28 (shown in the Fig. 6B).

[0033] A silicide may also be provided on the raised source and drain regions 28 and segmented H-body gate structures 18 prior to contact formation. As will be appreciated by those skilled in the art, the silicide process begins with a deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over fully formed and patterned semiconductor devices (e.g., doped or ion-implanted source and drain regions and respective devices). After deposition of the material, the structure is heated, allowing the transition metal to react with exposed silicon (or another semiconductor material as described herein) in the active regions of the semiconductor device (e.g., source, drain, gate contact region), forming a low-resistance transition metal silicide.Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts in the active regions of the device.

[0034] As further stated in the Fig. 6B, in each of the embodiments described herein, the segmented H-body gate structures 18 include raised source and drain regions 28 adjacent to the active body region 18b. In embodiments, the raised source and drain regions 28 may be fabricated in the collector region 16a and the emitter region 16b by a doped epitaxial process, as is known in the art.

[0035] Fig. 7A and Fig. 7B show a cross-sectional view of a transistor (ie, a lateral heterojunction bipolar transistor) according to aspects of the present disclosure. In particular, the Fig. 7A is a cross-sectional view of the transistor of Fig. 4 along a line “y”, whereas Fig. 7B is a cross-sectional view of the transistor of Fig. 4 along a line “x”. With reference to the Fig. 7A, two different semiconductor materials 12, 26 are provided in the channel region of the segmented H-body gate structure 18. The semiconductor material 26 may be deposited using SOI technology in the collector region 16a and partially over the intrinsic base 19, or alternatively, the semiconductor material 26 may be deposited over the emitter region 16b and partially over the intrinsic base 19. In either alternative, the semiconductor material 26 may also extend into the extrinsic base region 14a (over the openings 15).

[0036] With reference to both the Fig. 7A as well as the Fig. 7B, the segmented H-body gate structures 18 include legs 18a provided above the diffusions 14a. In embodiments, the diffusions 14a may be a raised semiconductor material, e.g., p+ eSiGe. The active body region 18b of the segmented H-body gate structures 18 includes a gate dielectric material 30 composed, for example, of a high-k dielectric material. The high-k dielectric material may be, for example, HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations including multilayers thereof. The segmented H-body gate structures 18 may also include sidewall spacers 32, e.g., nitride, formed by a conventional deposition process (e.g., CVD) followed by an anisotropic etching process. The sidewall spacers 32 isolate the gate structure from the source and drain regions 28 (shown in Fig. 7B). A silicide may also be provided on the raised source and drain regions 28 and segmented H-body gate structures 18 prior to contact formation.

[0037] As further stated in the Fig. 7B, in each of the embodiments described herein, the segmented H-body gate structures 18 include raised source and drain regions 28 adjacent to the active body region 18b. In embodiments, the raised source and drain regions 28 may be fabricated in the collector region 16a and the emitter region 16b by a doped epitaxial process, as is known in the art.

[0038] The process(es) described above is(are) used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip assembly (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip assembly (such as a ceramic carrier containing one or both surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that include a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure, including: an emitter region (16b); a collector region (16a); Base regions on opposite sides of the emitter region (16b) and the collector region (16a); and a gate structure (18) composed of a body region (18b) and leg regions (18a), the body region (18b) being located between the base regions on opposite sides of the emitter region (16b) and the collector region (16a), and the leg regions (18a) isolating the base regions from both the emitter region (16b) and the collector region (16a), wherein the base regions are extrinsic base regions (14a), the body region (18b) of the gate structure (18) is located above an intrinsic base region (19) between the collector region (16a) and the emitter region (16b), and further comprising an epitaxial material in the extrinsic base regions (14a) between the leg regions (18a). [2] The structure of claim 1, wherein the body region (18b) of the gate structure (18) is an active gate portion over the intrinsic base region (19) located between the emitter region (16b) and the collector region (16a). [3] The structure of claim 1, wherein the leg regions (18a) are structured and arranged to prevent leakage between: a first base region and the emitter region (16b); the first base region and the collector region (16a); a second base region and the emitter region (16b); and the second base region and the collector region (16a). [4] The structure of claim 1, wherein the leg regions (18a) are structured and arranged to reduce a base resistance in the base regions. [5] The structure of claim 1, wherein the leg regions (18a) and the body region (18b) are formed as a segmented H-body gate structure (18). [6] The structure of claim 5, wherein the body region (18b) and the leg regions (18a) are composed of polysilicon. [7] The structure of claim 6, wherein the leg regions (18a) are provided over an opening (15) in a substrate adjacent to both the emitter region (16b) and the collector region (16a). [8] The structure of claim 1, further comprising an epitaxial material at least partially beneath the body region (18b) of the gate structure (18). [9] The structure of claim 8, wherein the emitter region (16b), the collector region (16a) and the base regions are formed on a semiconductor-on-insulator, SOI, technology. [10] The structure of claim 1, wherein the gate structure (18) is an H-shaped gate structure (18). [11] The structure of claim 1, wherein the emitter region (16b), the collector region (16a) and the base regions are formed on a fully depleted semiconductor-on-insulator, SOI, technology. [12] Structure comprising: a semiconductor material (12) composed of an emitter region (16b), a collector region (16a) and at least one base region; and a segmented gate structure (18) comprising insulation regions (18a) in and / or above respective openings (15) of the semiconductor material (12) positioned between the at least one base region and both the emitter region (16b) and the collector region (16a), and wherein the at least one base region is a first extrinsic base region (14a) at one end and a second extrinsic base region (14a) at another end, the first extrinsic base region (14a) being insulated from both the emitter region (16b) and the collector region (16a) by first and second isolation regions (18a) at one end, and the second extrinsic base region (14a) being insulated from both the emitter region (16b) and the collector region (16a) by third and fourth isolation regions (18a) at the other end. [13] The structure of claim 12, wherein the segmented gate structure (18) comprises an active body region (18b) over an intrinsic base region (19) between the emitter region (16b) and the collector region (16a), and the isolation regions (18a) are leg regions (18a) extending from the active body region (18b) and isolating the at least one base region (14a) from both the emitter region (16b) and the collector region (16a). [14] The structure of claim 13, wherein the leg regions (18a) and the active body region (18b) are a segmented H-shape body gate structure (18). [15] The structure of claim 12, wherein the segmented gate structure (18) is composed of polysilicon over a fully depleted substrate. [16] The structure of claim 12, wherein the segmented gate structure (18) is composed of polysilicon over silicon-on-insulator (SOI) technology. [17] The structure of claim 16, further comprising an epitaxial material at least partially beneath the active body region (18b) of the segmented gate structure (18). [18] Structure comprising: a transistor formed on a semiconductor-on-insulator (SOI) technology and composed of: an emitter region (16b), a collector area (16a), extrinsic base regions (14a) on opposite sides of the emitter region (16b) and the collector region (16a); and an active body region (18b) of a gate structure (18) composed of polysilicon material and extending between the extrinsic base regions (14a); and Isolation regions (18a) extending from the active body region (18b) of the gate structure (18), the isolation regions (18a) being positioned to isolate the extrinsic base regions (14a) from both the emitter region (16b) and the collector region (16a), wherein the active body region (18b) of the gate structure (18) is located above an intrinsic base region (19) between the collector region (16a) and the emitter region (16b), and further comprising an epitaxial material in the extrinsic base regions (14a) between the isolation regions of the gate structure (18).

Images