Finfet devices with rear busbar and rear self-aligning vias and methods for their manufacture

Abstract

Semiconductor structure which exhibits: a power rail on one back side of the semiconductor structure; a first interconnect structure on one front side of the semiconductor structure; a source feature, a drain feature, a first semiconductor fin and a gate structure located between the current rail and the first interconnect structure, wherein the first semiconductor fin connects the source feature and the drain feature, and the gate structure is arranged on a front face and two side faces of the first semiconductor fin; an insulation structure located between the busbar and the drain feature and between the busbar and the first semiconductor fin; a via that passes through the insulation structure and connects the source feature to the busbar; and a first dielectric fin and a second dielectric fin, which run longitudinally parallel to the first semiconductor fin and extend from the back of the semiconductor structure to the front of the semiconductor structure, wherein the first semiconductor fin is arranged between the first and the second dielectric fin, wherein the via fills a gap extending from the first dielectric fin to the second dielectric fin along a direction perpendicular to a longitudinal direction of the first semiconductor fin.

Description

BACKGROUND

[0001] Traditionally, integrated circuits (ICs) are built in a stacked manner, with transistors at the bottom layer and interconnects (vias and wires) on top of the transistors to provide connectivity. Power rails (for example, metal traces for voltage sources and ground planes) are also located above the transistors and may be part of the interconnect. As integrated circuits become smaller, so too do the power rails. This inevitably leads to an increased voltage drop across the power rails and increased power consumption by the integrated circuits. Therefore, while existing approaches in semiconductor manufacturing have generally been adequate for their intended purposes, they are not entirely satisfactory in every respect.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in US 2019 / 0378790A1.

[0003] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] The present disclosure is best understood with reference to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with common industry practice, various structural elements are not drawn to scale and are for illustrative purposes only. The dimensions of the various structural elements may, in fact, be enlarged or reduced as necessary for the sake of clarity in this discussion. Fig. 1A, Fig. 1B and Fig. Figure 1C shows a flowchart of a method for forming a semiconductor device with rear-side busbars and rear-side self-aligning vias according to various aspects of the present disclosure. Fig. 2 and Fig. Figure 3 illustrates cross-sectional views of a section of a semiconductor device according to some embodiments in intermediate steps of the manufacturing process according to one embodiment of the method. Fig. 1A-1C. Fig. 4A, Fig. 5A, Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A and Fig. Figure 20A illustrates top views of a section of a semiconductor device according to some embodiments. Fig. 4B, Fig. 5B, SC, 5D, 5E, 5F, 5G, 6B, 6C, 6D, 6E, 7B, 7C, 7D, 7E, 8B, 8C, 8D, 8E, 9B, 9C, 9D, 9E, 10B, 10C, 10D, 10E, 11B, 11C, 11D, 11E, 12B, 12C, 12D, 12E, 13B, 14B, 14C, 14D, 14E, 15B, 15C, 15D, 15E, 16B, 16C, 16D, 16E, 17B, 17C, 17D, 17E, 18B, 18C, 18D, Figures 18E, 19B, 19C, 19D, 19E and 20B illustrate cross-sectional views of a section of a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the subject matter discussed herein. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features are not necessarily in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not automatically create a relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," "upper," and the like, may be used in this text to simplify the description and to describe the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass other orientations of the device in use or operation besides the orientation shown in the figures. The device may also be oriented differently (rotated by 90 degrees, or in other orientations), and the spatially relative descriptors used in this text may be interpreted accordingly.Furthermore, when a number or range of numbers is described with "approximately", "about", or the like, the term includes numbers which—according to the knowledge of a person skilled in the art with regard to the specific technology disclosed in this text—lie within certain variations (such as ± 10% or other variations) of the described number, unless otherwise specified. For example, the term "approximately 5 nm" may encompass the dimensional range from 4.5 nm to 5.5 nm, 4.0 nm to 5.0 nm, etc.

[0007] This application relates generally to semiconductor structures and manufacturing processes, and specifically to FinFET devices with backside power rails and backside self-aligning vias. As discussed above, power rails in ICs require further improvement to achieve the necessary performance increase and reduce power consumption. One objective of the present disclosure is to provide power rails (or current routings) on the backside of a structure containing FinFET transistors, in addition to an interconnect structure (which may also contain power rails) on the frontside of the structure. This increases the number of metal traces available in the structure for direct connection to source / drain contacts and vias. It also increases the gate density for greater device integration than existing structures without the backside power rails.The rear busbars can be dimensioned wider than the first-level (M0) metal traces on the front of the structure, which advantageously reduces the busbar resistance. This disclosure also presents structures and methods for isolating the rear busbars from nearby conductors, such as metal gates. The details of the structure and the fabrication methods of this disclosure are described below in conjunction with the accompanying drawings, which illustrate a process for fabricating a FinFET device according to some embodiments. It is clear to the person skilled in the art that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or the same advantages as in the embodiments presented in this text.

[0008] Fig. 1A, Fig. 1B and Fig. Figure 1C is a flowchart of a process 100 for manufacturing a semiconductor device according to various aspects of the present disclosure. Further processing is also considered by the present disclosure. Additional operations may be provided before, during, and after the process 100, and some of the described operations may be postponed, replaced, or omitted to obtain additional embodiments of the process 100.

[0009] Procedure 100 is described below in conjunction with Fig. Figures 2 to 20B describe various top and cross-sectional views of a semiconductor device (or semiconductor structure) 200 at different manufacturing steps according to the method 100 according to some embodiments.In some embodiments, the device 200 is a section of an IC chip, a system-on-chip (SoC), or a section thereof, comprising various passive and active microelectronic components, such as resistors, capacitors, inductors, diodes, p-type field-effect transistors (PFETs), n-type field-effect transistors (NFETs), FinFETs, nanolayer FETs, nanowire FETs, other types of multi-gate FETs, metal-oxide-semiconductor field-effect transistors (MOSFETs), complementary metal-oxide-semiconductor transistors (CMOS transistors), bipolar transistors (BJTs), laterally diffused MOS transistors (LDMOS transistors), high-voltage transistors, high-frequency transistors, memory devices, other suitable components, or combinations thereof. Fig. Sections 2 to 20B have been simplified for the sake of clarity and to facilitate understanding of the inventive concepts of this disclosure. Additional features may be added to device 200, and some of the features described below may be replaced, modified, or omitted in other embodiments of device 200.

[0010] In operation 102, procedure 100 forms ( Fig. 1A) a semiconductor layer 210 and a semiconductor layer 215 over a substrate 201, as for example in the Fig. 2 and Fig. Figure 3 shows one embodiment. In particular, it illustrates Fig. 2 the substrate 201 in an embodiment, and Fig. Figure 3 illustrates that the semiconductor layer 210 is arranged above the substrate 201, and the semiconductor layer 215 is arranged above the semiconductor layer 210. In the illustrated embodiment, the substrate 201 is a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate. In the illustrated embodiment, the substrate 201 comprises a semiconductor layer 204, an insulator 203, and a support 202. In other embodiments, the semiconductor layer 204 may be silicon, silicon-germanium, germanium, or another suitable semiconductor. In the present embodiment, the semiconductor layer 204 comprises silicon. In some embodiments, the support 202 may be part of a silicon wafer or another suitable support wafer.In some embodiments, the insulator 203 can be silicon oxide or other types of insulating material. Semiconductor-on-insulator substrates can be fabricated using separation through implantation of oxygen (SIMOX), wafer bonding, and / or other suitable methods. In an alternative embodiment, the substrate 201 is a bulk silicon substrate (including, for example, single-crystal bulk silicon). In another alternative embodiment, the substrate 201 is a silicon substrate with a silicon-germanium layer (SiGe layer) that acts as a back-side barrier during silicon etching. The substrate 201 can, in various embodiments, include other semiconductor materials such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof.

[0011] In some embodiments, semiconductor layer 210 is epitaxially grown on semiconductor layer 204, and semiconductor layer 215 is epitaxially grown on semiconductor layer 210. In some embodiments, the epitaxial growth of semiconductor layers 210 and 215 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal-organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or combinations thereof. The composition of semiconductor layer 210 differs from the composition of semiconductor layer 215 to achieve etch selectivity in subsequent processing. In some embodiments, semiconductor layer 210 has a first etch rate with an etchant, and semiconductor layer 215 has a second etch rate with the same etchant, the second etch rate being lower than the first.In the illustrated embodiment, the semiconductor layers 210 and 215 contain different materials, atomic percentages of the components, weight percentages of the components, thicknesses, and / or properties to achieve the desired etch selectivity during an etching process. For example, if semiconductor layer 210 contains silicon-germanium and semiconductor layer 215 contains silicon, then a silicon etch rate of semiconductor layer 215 will be lower than a silicon-germanium etch rate of semiconductor layer 210. In some embodiments, the semiconductor layers 210 and 215 may contain the same material but with different atomic percentages of the components to achieve different etch selectivity and / or oxidation rates.For example, the semiconductor layers 210 and 215 can contain silicon-germanium, wherein the semiconductor layer 210 has a first silicon atom percentage and / or a first germanium atom percentage, and the semiconductor layer 215 has a second, different silicon atom percentage and / or a second, different germanium atom percentage. The present disclosure considers that the semiconductor layers 210 and 215 comprise any combination of semiconductor materials that can provide the desired etch selectivity, including any of the semiconductor materials disclosed herein. In the embodiment shown, the semiconductor layer 210 contains silicon-germanium, and the semiconductor layer 215 contains silicon.Furthermore, according to some embodiments, the semiconductor layer 210 can have a thickness in the range of about 20 nm to about 80 nm, and the semiconductor layer 215 can have a thickness in the range of about 30 nm to about 70 nm. As will be discussed later, the semiconductor layer 210 is replaced by a backside dielectric layer during wafer back-facing processing, and the backside dielectric layer serves to insulate the backside busbars from the frontside components, such as metal gates and transistor channels. Therefore, the semiconductor layer 210 is designed to have several suitable thicknesses.If the semiconductor layer 210 is too thin (for example, less than 20 nm), the backside dielectric layer may not provide sufficient insulation, or the coupling capacitance between the backside power rails and the frontside components may be unacceptably high in some cases. If the semiconductor layer 210 is too thick (for example, more than 80 nm), the backside vias connecting the backside power rails to the frontside S / D components may be long and narrow, which may result in unacceptably high resistance in some cases.

[0012] In the present embodiment, the semiconductor layer 215 is undoped. In the present embodiment, the “undoped” semiconductor layer 215 comprises embodiments in which the semiconductor layer 215 is unintentionally doped or otherwise doped with a very low doping concentration, such that it does not contain enough charge carriers (electrons or holes) to be conductive under a typical electric field. As will be discussed later, the method processes 100 layers on both sides of the substrate 201. In the present disclosure, the side of the substrate 201 on which the semiconductor layer 215 is located is referred to as the front side, and the side opposite the front side is referred to as the back side.

[0013] In Operation 104, the procedure 100 forms ( Fig. 1A) by structuring the semiconductor layers 215 and 210 and the substrate 201 fins 218. Fig. Figure 4A illustrates a top view of the device 200 with the fins 218 aligned along the “x” direction. Fig. Figure 4B illustrates a cross-sectional view of the device 200 in the section along line AA in Fig. 4A. As in Fig. As illustrated in Figure 4B, the fins 218 contain the structured semiconductor layers 210 and 215, the structured regions 204, and one or more structured hard mask layers 206. The fins 218 can be structured by any suitable method. For example, the fin 218 can be structured by one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacings than those obtainable by a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over the semiconductor layer 215 and structured by a photolithography process.Spacers are structured along the sacrificial layer using a self-aligning process. The sacrificial layer is then removed, and the remaining spacers, or mandrels, can be used as a masking element for structuring the fins 218. For example, the masking element (such as the structured hard mask 206) can be used to etch recesses into the semiconductor layers 215 and 210 and the substrate 201, leaving fins 218 embedded in the substrate 201. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes.For example, a dry etching process may implement an oxygen-containing gas, a fluorine-containing gas (for example, CF4, SF6, CH2F2, CHF3 and / or C2F6), a chlorine-containing gas (for example, Cl2, CHCl3, CCl4 and / or BCl3), a bromine-containing gas (for example, HBr and / or CHBR3), an iodine-containing gas, other suitable gases and / or plasmas and / or combinations thereof. The wet etching process may, for example, include etching in dilute hydrofluoric acid (DHF), potassium hydroxide solution (KOH solution), ammonia, a solution containing hydrofluoric acid (HF), nitric acid (HNO3) and / or acetic acid (CH3COOH), or another suitable wet etching agent. Numerous other embodiments of methods for forming the fins 218 may be suitable.

[0014] In Operation 106, the procedure 100 forms ( Fig. 1A) various insulation structures over the substrate 201 and insulates the fins 218, one embodiment of which is in the Fig. 5A-5G is illustrated. Fig. Figure 5A illustrates a top view of the device 200, and the Fig. Figures 5B-5G illustrate cross-sectional views of device 200 in sections along line AA. Fig. 5A at various steps of operation 106.

[0015] With reference to Fig. In 5B, an insulating feature 230 is deposited over the substrate 201 and the fins 218 to separate and isolate the fins 218 from each other. In the present embodiment, the insulating feature 230 fills dense fin areas (such as the two fins 218 on the right side of the substrate 201) with an insulating feature 230. Fig. 5B) - completely fills out the space between the adjacent fins 218; and for fins 218 in less dense fin areas (or isolated fin areas) (such as the two fins 218 on the left side of Fig. 5B) The insulating feature 230 partially fills the space between the adjacent fins 218. In various embodiments, the insulating feature 230 can be deposited in a thickness of about 5 nm to about 40 nm. In the present embodiment, the insulating feature 230 contains silicon oxide. The insulating feature 230 can alternatively or additionally contain silicon nitride, silicon oxynitride, another suitable insulating material (including, for example, silicon, oxygen, nitrogen, carbon, or another suitable insulating component), or combinations thereof. The insulating feature 230 can be deposited by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof.

[0016] With reference to Fig. In step 5C, a dielectric lining 232 is deposited over the insulating feature 230, a dielectric filler layer 233 is deposited over the dielectric lining 232 and fills the gaps between the fins 218 in the insulated fin regions, and the dielectric filler layer 233 is subsequently etched back to a level below the top surface of the semiconductor layer 215 in the fins 218. In one embodiment, the dielectric lining 232 contains a dielectric material with a low k-value, such as a dielectric material containing Si, O, N, and C. Examples of low k-value dielectric materials include fluoride-doped fused silica (FSG), carbon-doped silicon dioxide, and Black Diamond. ®(Applied Materials from Santa Clara, California), xerogel, aerogel, amorphous fluorinated carbon, parylene, BCB, SiLK (Dow Chemical, Midland, Michigan), polyimide, or combinations thereof. Low k-value dielectric material generally refers to dielectric materials with a low dielectric constant, for example, lower than about 6.0. The dielectric lining 232 can be deposited by CVD, PVD, ALD, HDPCVD, MOCVD, RPCVD, PECVD, LPCVD, ALCVD, APCVD, other suitable processes, or combinations thereof. In one embodiment, the dielectric filler layer 233 comprises silicon oxide, silicon nitride, silicon oxynitride, TEOS-formed oxide, PSG, BPSG, low k-value dielectric material, other suitable dielectric material, or combinations thereof.The dielectric filler layer 233 can be deposited using a flowable CVD (FCVD) process, which includes, for example, depositing a flowable material (e.g., a liquid compound) over the device 200 and converting the flowable material into a solid by a suitable technique, such as thermal annealing and / or treatment with ultraviolet radiation. The dielectric filler layer 233 can also be deposited using other types of processes discussed in this disclosure. Back-etching the dielectric filler layer 233 uses an etching process that is selective for the material of the dielectric filler layer 233 and with minimal etching of the dielectric lining 232.

[0017] With reference to Fig. In step 5D, the dielectric lining 232 is etched back (or trimmed) to the same height as the dielectric filler layer 233. The etching back of the dielectric lining 232 uses an etching process that is selective for the material of the dielectric lining 232 and with minimal etching of the dielectric filler layer 233 and the insulating feature 230.

[0018] With reference to Fig. In embodiment 5E, a dielectric cap 234 is applied over the dielectric layers 232 and 233 and between the insulating feature 230 on opposite side walls of the fins 218 in the insulated fin regions. In one embodiment, the dielectric cap 234 comprises a dielectric material with a high k-value, such as HfO₂, HfSiO₂, HfSiO₄, HfSiON₄, HfLaO₂, HfTaO₂, HfTiO₂, HfZrO₂, HfAlO₂ xZrO, ZrO₂, ZrSiO₂, AlO, AlSiO₂, Al₂O₃, TiO, TiO₂, LaO, LaSiO₂, Ta₂O₃, Ta₂O₅, Y₂O₃, SrTiO₃, BaZrO, BaTiO₃ (BTO), (Ba,Sr)TiO₃ (BST), Si₃N₄, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), other suitable high-k dielectric material, or combinations thereof. High-k dielectric material generally refers to dielectric materials with a high dielectric constant, for example, greater than that of silicon dioxide (k about 3.9), such as greater than 6.0. The dielectric cap 234 is formed by any of the processes described here, such as ALD, CVD, PVD, oxidation-based deposition processes, other suitable processes, or combinations thereof.

[0019] With reference to Fig. In operation 106, 5F deposits a sacrificial oxide layer (not shown) to fill the various gaps in the device 200 and subsequently performs a CMP process. The CMP process removes the sacrificial oxide layer and the hard mask layer 206 and planars the top surface of the device 200. The dielectric cap 234, the semiconductor layer 215, and the insulating feature 230 may be partially removed by the CMP process in some embodiments.

[0020] With reference to Fig. Operation 106, in 5G, etchs the insulation feature 230 to a level just above the semiconductor layer 210. Operation 106 can apply one or more etching processes that are selective for the insulation feature 230, with minimal etching of the dielectric cap 234, the semiconductor layer 215, and the dielectric lining 232. The selective etching processes can be dry etching, wet etching, reactive ion etching, or other suitable etching processes. As a result, the device 200 is provided with dielectric fins 219 arranged between the semiconductor fins 218 in the insulated fin regions. The dielectric fins 219 include the dielectric cap 234, the dielectric lining 232, and the dielectric filler layer 233. The insulation feature 230 is arranged between lower sections of the semiconductor fins 218 and the dielectric fins 219.

[0021] In operation 108, procedure 100 forms ( Fig. 1A) Gate stack 240 over the fins 218 and the insulation structures 230 and 219. The resulting structure is, according to one embodiment, in the Fig. 6A-6E shown. Fig. Figure 6A illustrates a top view of the device 200. Fig. 6B, Fig. 6C, Fig. 6D and Fig. Figure 6E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 6A. More precisely, line DD is cut into the source regions of the transistors and runs parallel to the gate stacks 240, and line EE is cut into the drain regions of the transistors and runs parallel to the gate stacks 240. The lines DD and EE in the Fig. 7A-12A and 14A-19A are similarly configured.

[0022] In the top view, the gate stacks 240 are generally oriented longitudinally along the “y” direction perpendicular to the “x” direction. In the present embodiment, the gate stacks 240 are dummy gate stacks (or sacrificial gate stacks) and are replaced in a later step by functional gate stacks 240'. In the present embodiment, the gate stacks 240 comprise a dummy gate dielectric layer 235, a dummy gate electrode layer 245 over the dummy gate dielectric layer 235, and one or more hard mask layers 246 over the dummy gate electrode layer 245.In some embodiments, the dummy gate dielectric 235 contains a dielectric material such as silicon oxide, a high k-value dielectric, another suitable dielectric material, or combinations thereof; the dummy gate electrode layer 245 contains polysilicon or another suitable material; and the one or more hard mask layers 246 contain silicon oxide, silicon nitride, or other suitable materials. The dummy gate stacks 240 can be formed by deposition processes, lithography processes, etching processes, other suitable processes, or combinations thereof.For example, the dielectric dummy gate layer 235, the dummy gate electrode layer 245 and the hard mask layers 246 can be deposited by various deposition processes such as CVD, physical evaporation (PVD), atomic layer deposition (ALD), high-density plasma-compressed cellular cetochemical (HDPCVD), metal-organic CVD (MOCVD), spatially separated plasma-compressed cetochemical (RPCVD), plasma-assisted CVD (PECVD), low-pressure CVD (LPCVD), atomic layer CVD (ALCVD), atmospheric pressure CVD (APCVD), other suitable methods, or combinations thereof. Subsequently, a lithographic structuring and etching process is carried out to structure the one or more hard mask layers 246, the dummy gate electrode layer 245 and the dielectric dummy gate electrode layer 235 to form dummy gate stacks 240, as shown in . Fig. Figure 6B shows the lithographic structuring processes. These include resist coating (e.g., spin coating), soft firing, mask alignment, exposure, post-exposure firing, resist development, rinsing, drying (e.g., hard firing), other suitable lithographic processes, or combinations thereof. Etching processes include dry etching, wet etching, other etching methods, or combinations thereof.

[0023] Operation 108 also forms gate spacers 247 on the side walls of the dummy gate stacks 240 (as, for example, in Fig. 6B) and fin sidewall spacers 248 on lower sections of the sidewalls of the fins 218 (as, for example, in the Fig. 6D and Fig. (6E shown). The gate spacers 247 and fin sidewall spacers 248 are formed by any suitable process and contain a dielectric material. The dielectric material can contain silicon, oxygen, carbon, nitrogen, another suitable material, or combinations thereof (for example, silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbide, silicon carbon nitride (SiCN), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN)). For example, a dielectric layer containing silicon and nitrogen, such as a silicon nitride layer, can be deposited over dummy gate stacks 240 and fins 218 and subsequently etched (for example, anisotropically etched) to form gate spacers 247 and fin sidewall spacers 248.In some embodiments, the gate spacers 247 and fin sidewall spacers 248 have a multilayer structure, such as a first dielectric layer containing silicon nitride and a second dielectric layer containing silicon oxide. In some embodiments, the fin sidewall spacers 248 are omitted (or removed) from the device 200.

[0024] In operation 110, the procedure forms 100 ( Fig. 1A) Source / drain (S / D) trenches 250 by etching the fins 218 next to the gate spacers 247. The resulting structure is described in one embodiment in the Fig. 7A-7E shown. Fig. Figure 7A illustrates a top view of the device 200, and Fig. 7B, Fig. 7C, Fig. 7D and Fig. Figure 7E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 7A.

[0025] In the illustrated embodiment, an etching process partially removes the semiconductor layer 215 in the source / drain regions of the fins 218, leaving only a portion of the semiconductor layer 215 in the source / drain grooves 250. The remaining portion of the semiconductor layer 215 is referred to as section 215' or semiconductor layer 215'. Section 215' has a thickness 'd1' along the 'z' direction. In one embodiment, the thickness d1 is in a range of approximately 5 nm to approximately 15 nm. As will be discussed later, section 215' provides some insulation between the drain region and the backside busbar. Therefore, the range of thickness d1 is designed to achieve this purpose. If d1 is too small (for example, less than 5 nm), the drain feature may be inadvertently etched during the formation of the backside insulation.If d1 is too large (for example, larger than 15 nm), then the source / drain trench 250 may be too shallow, and the source / drain features formed therein may be too small to achieve good device performance. As a result of the etching process, the source / drain trenches 250 have bottom and side walls defined by the semiconductor layer 215. The etching process may include a dry etching process, a wet etching process, another suitable etching process, or combinations thereof. In some embodiments, the parameters of the etching process are configured such that the semiconductor layer 215 is etched selectively, with minimal etching of the gate stack 240 (including the hard mask 246 on its top), the gate spacers 247, the dielectric fins 219, and the fin sidewall spacers 248, if present.

[0026] In operation 112, the procedure 100 ( Fig. 1A) an additional etching of the source region of the device 200. The resulting structure is described in one embodiment in the Fig. 8A-8E shown. Fig. Figure 8A illustrates a top view of the device 200, and Fig. 8B, Fig. 8C, Fig. 8D and Fig. Figure 8E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 8A.

[0027] In the illustrated embodiment, the operation 112 forms an etching mask 241, which includes a structured hard mask 236 and a structured resist 237. The etching mask 241 covers the device 200 except for the source regions, which are exposed through openings 238 in the etching mask 241. The operation 112 then etches the source regions through the semiconductor layer 210 and into the substrate 201 until only a thin layer 204 remains in the source trench 250, thereby extending the source trench 250 into the substrate 201. As a result of this etching process, a semiconductor fin 218 is divided into two fins or two fin segments (one fin segment to the left of the trench 250 in Fig. 8B and another fin segment to the right of trench 250 in Fig. 8B). The etching process can include dry etching, wet etching, reactive ion etching, or any other suitable etching method. In this embodiment, the etching process is essentially anisotropic (i.e., essentially vertical). Furthermore, the etching process can be selectively tailored to the material of the semiconductor layers 215 and 210, with minimal etching of the gate spacers 247 and gate hard mask layers 246. The etching process can first be selectively tailored to the material of the semiconductor layer 215 and then selectively tailored to the material of the semiconductor layer 210, with minimal etching of the gate spacers 247 and the gate hard mask layers 246. In the present embodiment, the fin sidewall spacers 248 are removed during operation 112.In some embodiments, although the fin sidewall spacers 248 and the gate spacers 247 contain the same material, the fin sidewall spacers 248 can be removed by operation 112 while the gate spacers 247 essentially remain, because the fin sidewall spacers 248 are much thinner along the "z" direction than the gate spacers 247. After the etching process is complete, operation 112 removes the structured resist 237, for example, by a peeling process.

[0028] In operation 114, the procedure forms 100 ( Fig. 1A) a semiconductor layer 239 in the source grooves 250. The resulting structure is, according to one embodiment, in the Fig. 9A-9E shown. Fig. Figure 9A illustrates a top view of the device 200, and Fig. 9B, Fig. 9C, Fig. 9D and Fig. Figure 9E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 9A.

[0029] Semiconductor layer 239 can be deposited by an epitaxial growth process or by other suitable processes. For example, semiconductor layer 239 can be epitaxially grown from the surfaces of layers 204, 210, and 215. In some embodiments, the epitaxial growth of semiconductor layer 239 is achieved by a molecular beam epitaxy (MBE) process, a chemical vapor deposition (CVD) process, a metal-organic chemical vapor deposition (MOCVD) process, other suitable epitaxial growth processes, or combinations thereof. Semiconductor layer 239 contains a semiconductor material that differs from the semiconductor material contained in semiconductor layer 210 in order to achieve etch selectivity during subsequent processing.For example, the semiconductor layers 239 and 210 can contain different materials, different atomic percentages of the components, different weight percentages of the components, and / or other properties to achieve the desired etch selectivity during an etching process. In one embodiment, the semiconductor layer 239 contains silicon, and the semiconductor layer 210 contains silicon-germanium. In another embodiment, both semiconductor layers 239 and 210 can contain silicon-germanium, but with different silicon atomic percentages. The present disclosure considers that the semiconductor layers 239 and 210 comprise any combination of semiconductor materials that can provide the desired etch selectivity, including any of the semiconductor materials disclosed herein.In another embodiment, the semiconductor layer 239 is undoped and contains, for example, undoped silicon (including unintentionally doped or otherwise doped with a very low doping concentration, such that it does not contain enough charge carriers (electrons or holes) to be conductive under a typical electric field). Since the drain regions ( Fig. 9E) are covered by the structured hard mask layer 236, the semiconductor layer 239 is deposited only in the source regions ( Fig. 9D). The semiconductor layer 239 is deposited to such a thickness that its top surface is above the semiconductor layer 210 by a thickness d2 ( Fig. 9B). In one embodiment, d2 is approximately equal to d1. In various embodiments, d2 lies in a range of approximately 5 nm to approximately 15 nm. Operation 114 may include an etching process that deposits the semiconductor layer 239 onto the substrate in Fig. The level shown in Figure 9B is omitted if the semiconductor layer 239 is initially grown to a greater thickness than this level. If the semiconductor layer 239 is too thick (for example, if d2 is greater than 15 nm), the source feature 260 formed on it (see Figure 9B) could be omitted. Fig. 10B) is too small to achieve good device performance. As will be discussed later, the semiconductor layer 239 is subsequently connected in a later step by a rear-side self-aligning contact 282 (see Fig. 19B). If the semiconductor layer 239 is too thin (for example, if d2 is less than 5 nm), there may not be enough space available to form the self-aligning backside contact. In dense fin areas (such as the source trench 250 on the right side in Fig. 9D) The semiconductor layer 239 grown from adjacent fins can fuse to form a larger epitaxial layer. Furthermore, in the present embodiment, an isotropic pre-cleaning process is carried out before the epitaxial growth of the semiconductor layer 239, and the pre-cleaning process spares the insulating feature 230 exposed by the source / drain grooves 250. Within the grooves 250, the insulating feature 230 can be partially or completely removed. In some embodiments, a void 239 can be formed between the fused semiconductor layer 239 and the spared insulating feature 230 within the groove 250, as shown in Fig. Figure 9D shows that after the semiconductor layer 239 has been deposited, operation 114 removes the structured hard mask layer 236 by one or more etching processes. As discussed further below, the additional etching in operation 112 and the growth of the semiconductor layer 239 in operation 114 need only be performed in source regions or only in drain regions, or in various embodiments, they can be performed in both source and drain regions.

[0030] In Operation 116, the procedure breeds 100 ( Fig. 1A) Semiconductor S / D features 260 epitaxial in the S / D trenches 250. The resulting structure is, according to one embodiment, in the Fig. 10A-10E shown. Fig. Figure 10A illustrates a top view of the device 200, and Fig. 10B, Fig. 10C, Fig. 10D and Fig. Figure 10E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 10A.

[0031] As in the Fig. 10B, Fig. 10D and Fig. As shown in Figure 10E, epitaxial S / D features 260 are grown from semiconductor layers 215 and 239 in the source trench 250 and from semiconductor layer 215 in the drain trench 250. An epitaxial growth process can employ CVD deposition techniques (for example, VPE and / or UHV-CVD), molecular beam epitaxy, other suitable epitaxial growth processes, or combinations thereof. The epitaxial growth process can utilize gaseous and / or liquid precursors that interact with the composition of semiconductor layers 239 and 215. The epitaxial S / D features 260 are doped with n-type dopants for n-type transistors or p-type dopants for p-type transistors.In some embodiments, the epitaxial S / D features 260 for n-transistors contain silicon and can be doped with carbon, phosphorus, arsenic, other n-dopeds, or combinations thereof (for example, by forming epitaxial Si:C source / drain features, epitaxial Si:P source / drain features, or epitaxial Si:C:P source / drain features). In some embodiments, the epitaxial S / D features 260 for p-transistors contain silicon-germanium or germanium and can be doped with boron, other p-dopeds, or combinations thereof (for example, by forming epitaxial Si:Ge:B source / drain features). In some embodiments, the epitaxial S / D features 260 comprise more than one epitaxial semiconductor layer, wherein the epitaxial semiconductor layers may contain the same or different materials and / or doping concentrations.Furthermore, in one embodiment, the S / D feature 260 (or at least its portion adjacent to the semiconductor layer 239) contains a different material composition than the semiconductor layer 239 in order to achieve etch selectivity during the back-side via formation process. For example, in one embodiment, the semiconductor layer 239 contains SiGe, and the S / D feature 260' contains Si (for an n-transistor). In another embodiment, for example, the semiconductor layer 239 contains SiGe with a first Ge atom percent, and the S / D feature 260' contains SiGe (for a p-transistor) with a second Ge atom percent, the first and second Ge atom percent being different. In some embodiments, the epitaxial S / D features 260 contain materials and / or dopants that achieve the desired tensile and / or compressive stress in the respective channel regions.In some embodiments, the epitaxial source / drain features 260 are doped during deposition by adding interfering atoms (i.e., in situ) to a starting material of the epitaxial process. In some embodiments, the epitaxial source / drain features 260 are doped by an ion implantation process following a deposition process. In some embodiments, annealing processes (for example, rapid thermal annealing (RTA) and / or laser annealing) are performed to activate dopants in epitaxial source / drain features 260.In some embodiments, the epitaxial source / drain features 260 are formed in separate processing sequences, which include, for example, masking p-transistor regions during the formation of epitaxial source / drain features 260 in n-transistor regions and masking n-transistor regions during the formation of epitaxial source / drain features 260 in p-transistor regions. As in . Fig. As shown in Figure 10D, the source features 260 are formed into rod-like shapes and completely fill the bottom of the source trenches 250. Due to the presence of the semiconductor layer 239, the bottom of the source features 260 is wider than the upper section of the source features 260. The sidewalls of the source features 260 touch the sidewalls of adjacent dielectric fins 219. The source features 260 in the dense fin regions (for example, the two source features 260 on the right side of Figure 10D) Fig. 10D) fuse to form a large piece of epitaxial semiconductor material. As in Fig. As shown in Figure 10E, the drain features 260 have a narrow lower section that is limited by the fin sidewall spacers 248. As the drain features 260 grow beyond the fin sidewall spacers 248, they expand laterally, forming a diamond-shaped upper section. The drain features 260 in the dense fin areas (for example, the two drain features 260 on the right side of Figure 10E) Fig. 10E) also merge, creating a void between the drain feature 260 and the fin sidewall spacer 248 in the present embodiment. In the illustrated embodiment, the source features 260 ( Fig. 10D) a larger volume than the drain characteristics 260 ( Fig. 10E), since the semiconductor layer 239 is present in the source region but not in the drain region. As will be shown later, the large source features ensure reduced contact resistance to both the front and back source contacts.

[0032] In operation 118, the procedure forms 100 ( Fig. 1B) a contact etch stop layer (CESL) 269 and an interlayer dielectric layer (ILD) 270. The resulting structure is described in one embodiment in the Fig. 11A-11E shown. Fig. Figure 11A illustrates a top view of the device 200, and Fig. 11B, Fig. 11C, Fig. 11D and Fig. Figure 11E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 11A.

[0033] As in the Fig. As shown in Figures 11B-11E, the CESL 269 is deposited over the S / D features 260, the dielectric fins 219, the dummy gate stack 240, and the gate spacer 247. The ILD layer 270 is deposited over the CESL 269 and fills the space between opposing gate spacers 247. The CESL 269 contains a material different from the ILD layer 270. In some embodiments, the CESL 269 contains a material different from the dielectric layer 234. CESL 269 can contain La2O3, Al2O3, SiOCN, SiOC, SiCN, SiO2, SiC, ZnO, ZrN, Zr2Al3O9, TiO2, TaO2, ZrO2, HfO2, Si3N4, Y2O3, AlON, TaCN, ZrSi or one or more other suitable materials and can be formed by CVD, PVD, ALD or other suitable processes.The ILD layer 270 can comprise tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass or doped silicon oxide, such as boron phosphosilicate glass (BPSG), fluoride-doped fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), a low k-value dielectric material, another suitable dielectric material, or combinations thereof. The ILD 270 can be formed by PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable methods.

[0034] In operation 120, procedure 100 replaces ( Fig. 1B) the dummy gate stack 240 by functional gate stack 240' (such as metal gates with a high k-value). The resulting structure is described in one embodiment in the Fig. 12A-12E shown. Fig. Figure 12A illustrates a top view of the device 200, and Fig. 12B, Fig. 12C, Fig. 12D and Fig. Figure 12E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 12A. This involves a large number of different processes, which are briefly described below.

[0035] First, operation 120 performs a CMP process and / or another planarization process on the ILD layer 270 and the CESL 269 until an upper section of the dummy gate stack 240 is exposed. In some embodiments, the planarization process removes hard mask layers 246 from dummy gate stacks 240 to expose underlying dummy gate electrodes 245, such as polysilicon gate electrode layers.

[0036] Then operation 120 removes the dummy gate stack 240 (the dummy gate electrodes 245 and the dielectric dummy gate layer 235, see Fig. 6B) using one or more etching processes. This creates a gate trench, and a channel region of the semiconductor layer 215 is exposed in the gate trench. The etching process can be a dry etching process, a wet etching process, another suitable etching process, or a combination thereof. In some embodiments, the etching process is a multi-stage etching process. For example, the etching process can alternately employ etchants to remove different layers of dummy gate stacks 240 separately. In some embodiments, the etching process is configured such that dummy gate stacks 240 are selectively etched, with other features of the device 200, such as the ILD layer 270, the gate spacers 247, the insulating features 230, the dielectric layers 232 and 234, and the semiconductor layer 215, being etched only minimally, if at all.

[0037] Next, Operation 120 forms a gate dielectric layer 349 on the top and side walls of the semiconductor layers 215 and forms a gate electrode 350 above the gate dielectric layer 349. The functional gate stack 240' comprises the gate dielectric layer 349 and the gate electrode 350. The gate dielectric layer 349 can contain a high k-value dielectric material, such as HfO₂, HfSiO₂, HfSiO₄, HfSiON, HfLaO, HfTaO, HfTiO₂, HfZrO₂, or HfAlO₂. xZrO, ZrO₂, ZrSiO₂, AlO, AlSiO₂, Al₂O₃, TiO, TiO₂, LaO, LaSiO₂, Ta₂O₃, Ta₂O₅, Y₂O₃, SrTiO₃, BaZrO, BaTiO₃ (BTO), (Ba,Sr)TiO₃ (BST), Si₃N₄, hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃ alloy), other suitable high-k dielectric material, or combinations thereof. "High-k dielectric material" generally refers to dielectric materials that have a high dielectric constant, for example, greater than that of silicon dioxide (k about 3.9). The gate dielectric layer 349 can be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable processes. In some embodiments, the gate stack 240' also has an interface layer between the gate dielectric layer 349 and the semiconductor layer 215. The interface layer may contain silicon dioxide, silicon oxynitride, or other suitable materials.In some embodiments, the gate electrode layer 350 comprises an n- or p-work function layer and a metal filler layer. For example, an n-work function layer may comprise a metal with a sufficiently low effective work function, such as titanium, aluminum, tantalum carbide, tantalum carbide nitride, tantalum silicon nitride, or combinations thereof. For example, a p-work function layer may comprise a metal with a sufficiently high effective work function, such as titanium nitride, tantalum nitride, ruthenium, molybdenum, tungsten, platinum, or combinations thereof. For example, a metal filler layer may comprise aluminum, tungsten, cobalt, copper, and / or other suitable materials. The gate electrode layer 350 may be formed by CVD, PVD, plating, and / or other suitable processes.Since the gate stack 240' contains a high k-value dielectric material and one or more metal layers, it is also referred to as a high k-value metal gate.

[0038] In operation 122, procedure 100 ( Fig. 1B) Various manufacturing processes are performed on the front face of the device 200, including mid-end-of-line (MEOL) and back-end-of-line (BEOL) processes. For example, the operation can form front-facing silicide features on the S / D features 260, form front-facing S / D contacts on the silicide features, form S / D contact vias connected to the S / D contacts, form gate vias connected to the gate stacks 240', and form one or more interconnect layers with wires and vias embedded in dielectric layers. The one or more interconnect layers connect the gate, source, and drain electrodes of various transistors, as well as other circuitry in the device 200, to form all or part of an integrated circuit. Operation 122 can also create passivation layers on the interconnect layers.In the in the . Fig. 13A and Fig. embodiment shown in 13B ( Fig. Figure 13 illustrates a cross-sectional view of the device 200 in a section along line BB in Fig. 13A) The reference number 271 refers to the various features on the front of the device 200, as described above.

[0039] In operation 124, the procedure rotates 100 ( Fig. 1B) the device 200 and attaches the front of the device 200 to a support 277, as for example in Fig. 14B shown. Fig. Figure 14A illustrates a top view of the device 200, and Fig. 14B, Fig. 14C, Fig. 14D and Fig. Figure 14E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 14A. This makes the device 200 accessible for further processing from the rear of the device 200. In operation 124, all suitable fastening processes, such as direct bonding, hybrid bonding, adhesive bonding, or other bonding processes, can be used. Operation 124 can further include alignment, annealing, and / or other processes. The carrier 277 can be a silicon wafer in a certain embodiment. In the Fig. Figures 14B-14E (as well as other figures described below) indicate the “z” direction from the back of the device 200 to the front of the device 200, while the “-z” direction indicates from the front of the device 200 to the back of the device 200.

[0040] In operation 126, the procedure thins 100 ( Fig. 1B) the device 200 from the rear of the device 200 until the insulation features 230, the semiconductor layer 210 and the semiconductor layer 239 are exposed from the rear of the device 200. The resulting structure is, according to one embodiment, in the Fig. 15A-15E shown. Fig. Figure 15A illustrates a top view of the device 200, and Fig. 15B, Fig. 15C, Fig. 15D and Fig. Figure 15E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 15A. The thinning process may include a mechanical grinding process and / or a chemical thinning process. A significant amount of substrate material may first be removed from the substrate 201 during a mechanical grinding process. Subsequently, a chemical thinning process may apply an etching chemical to the back of the substrate 201 to further thin the substrate 201.

[0041] In operation 128, the procedure etches 100 ( Fig. 1C) selectively processes the semiconductor layer 210 to form trenches 272 over the back side of the gate stack 240' and the drain features 260. The resulting structure is described in one embodiment in the Fig. 16A-16E shown. Fig. Figure 16A illustrates a top view of the device 200, and Fig. 16B, Fig. 16C, Fig. 16D and Fig. Figure 16E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 16A. In the present embodiment, operation 128 employs an etching process that is selective for the materials of the semiconductor layer 210 (such as SiGe in one embodiment) and performs minimal etching, if any, of the semiconductor layer 215 (such as Si in one embodiment), the semiconductor layer 239 (such as Si in one embodiment), and the insulation features 230. As a result, section 215' of the semiconductor layer 215, the semiconductor layer 239, and the insulation features 230 are exposed in the grooves 272. The etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. More specifically, in the present embodiment, the etching of the semiconductor layer 210 is self-adjusting.In other words, Operation 128 does not require the fabrication of an etching mask (for example, an etching mask formed by photolithography processes) to etch the semiconductor layer 210. Rather, it relies on the etching selectivity of the materials in the semiconductor layer 210 and the layers surrounding it.

[0042] In Operation 130, the procedure 100 forms ( Fig. 1C) one or more dielectric layers 276 to fill the trenches 272. The resulting structure is described in one embodiment in the Fig. 17A-17E shown. Fig. Figure 17A illustrates a top view of the device 200, and Fig. 17B, Fig. 17C, Fig. 17D and Fig. Figure 17E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 17A. In various embodiments, the one or more dielectric layers 276 can comprise silicon nitride (Si3N4), silicon oxide (SiO2), oxide formed from tetraethyl orthosilicate (TEOS), undoped silicate glass, or doped silicon oxide, such as boron phosphosilicate glass (BPSG), fluoride-doped fused silica (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The one or more dielectric layers 276 can be formed by ALD, CVD, PECVD (plasma-enhanced CVD), FCVD (flowable CVD), or other suitable processes. Operation 130 can further perform a CMP process on the one or more dielectric layers 276, which planars the back side of the device 200 and exposes the semiconductor layer 239 for further processing.

[0043] In operation 132, the procedure removes 100 ( Fig. 1C) the semiconductor layer 239 from the back of the device 200. The resulting structure is, according to one embodiment, in the Fig. 18A-18E shown. Fig. Figure 18A illustrates a top view of the device 200, and Fig. 18B, Fig. 18C, Fig. 18D and Fig. Figure 18E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 18A. In the present embodiment, the operation 132 employs an etching process that is selective for the materials of the semiconductor layer 239 (such as Si in one embodiment) and performs minimal etching, if any, of one or more dielectric layers 276, the insulating features 230, and the dielectric layer 232. The etching process can partially etch the source feature 260. Furthermore, the etching process is substantially vertical, so that it may also etch the semiconductor layer 215. The etching process creates a trench 278 that exposes the source feature 260 from the rear of the device 200. The etching process can be dry etching, wet etching, reactive ion etching, or other etching methods. More precisely, in the present embodiment, the etching of the semiconductor layer 239 is self-adjusting.In other words, operation 132 does not require the fabrication of an etching mask (for example, an etching mask formed by photolithography processes) to etch the semiconductor layer 239. Rather, it relies on the etching selectivity of the materials in the semiconductor layer 239 and the surrounding layers, in particular the one or more dielectric layers 276. This advantageously creates the grooves 278 in such a way that they are aligned with the underlying source feature 260 without misalignments, such as those caused, for example, by photolithographic overlay displacement. The use of this method results in a back-side source contact (or a back-side source via) that is ideally aligned with the source feature 260, as will be discussed further below.

[0044] In operation 134, procedure 100 forms ( Fig. 1C) a rear-side source silicide feature 280 and a rear-side source contact 282. The resulting structure is described in one embodiment in the Fig. Shown 19A-19E. Fig. Figure 19A illustrates a top view of the device 200, and Fig. 19B, Fig. 19C, Fig. 19D and Fig. Figure 19E illustrates cross-sectional views of the device 200 in sections along line BB, line CC, line DD and line EE respectively. Fig. 19A. As in the Fig. 19B and Fig. As illustrated in Figure 19D, the rear source contact 282 self-aligns with the source feature 260 as a result of the self-aligning etching processes described above. Fig. 18B and Fig. 18D were discussed. Therefore, it is isolated from the nearby gate stacks 240' by the dielectric layers 276. The self-adjusting rear contact 282 minimizes the risk of a short circuit between the source feature 260 and the nearby gate stacks 240'.

[0045] In some embodiments, operation 134 comprises depositing one or more metals in the holes 278, performing an annealing process on the device 200 to induce a reaction between the one or more metals and the source feature 260 to generate the silicide feature 280, and removing unreacted portions of the one or more metals, leaving the silicide feature 280 in the holes 278. The one or more metals may include titanium (Ti), tantalum (Ta), tungsten (W), nickel (Ni), platinum (Pt), ytterbium (Yb), iridium (Ir), erbium (Er), cobalt (Co), or a combination thereof (for example, an alloy of two or more metals) and may be deposited by CVD, PVD, ALD, or other suitable methods.The silicide feature 280 can comprise titanium silicide (TiSi), nickel silicide (NiSi), tungsten silicide (WSi), nickel-platinum silicide (NiPtSi), nickel-platinum-germanium silicide (NiPtGeSi), nickel-germanium silicide (NiGeSi), ytterbium silicide (YbSi), platinum silicide (PtSi), iridium silicide (IrSi), erbium silicide (ErSi), cobalt silicide (CoSi), or other suitable compounds. In the embodiment shown, the source contact 282 has a conductive barrier layer 281 and a metal filler layer 283 above the conductive barrier layer 281. The conductive barrier layer 281 is intended to prevent metallic materials from the metal filler layer 283 from diffusing into the layers adjacent to the source contacts 282, such as layers 215, 230 and 276.The conductive barrier layer 281 can contain titanium (Ti), tantalum (Ta), tungsten (W), cobalt (Co), ruthenium (Ru), or a conductive nitride such as titanium nitride (TiN), titanium aluminum nitride (TiAlN), tungsten nitride (WN), tantalum nitride (TaN), or combinations thereof, and can be formed by CVD, PVD, ALD, and / or other suitable processes. The metal filler layer 283 can contain tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals and can be formed by CVD, PVD, ALD, plating, or other suitable processes. In some embodiments, the conductive barrier layer 281 is omitted in the source contact 282. Operation 134 can perform a CMP process to remove excess material from the source contact 282. As described in the... Fig. 19C and Fig. As shown in Figure 19E, the gate stack 240' and the drain features 260 are protected from the various deposition and etching processes in Operation 134 by the isolation features 230 and 276.

[0046] In Operation 136, the procedure forms 100 ( Fig. 1C) rear busbars 284 and a rear interconnect connection 286. The resulting structure is described in one embodiment in the Fig. 20A-20B shown. Fig. Figure 20A illustrates a top view of device 200, and Fig. Figure 20B illustrates a cross-sectional view of the device 200 in a section along line BB in Figure 20A. As in Fig. As illustrated in Figure 20B, the rear busbars 284 are electrically connected to the rear source contact 282 and are insulated from the drain features 260 and the channel section of the semiconductor layer 215 by one or more dielectric layers 276 and the semiconductor layer 215'. As shown in Fig. As shown in Figure 20B, the source feature 260 is arranged between two segments of a semiconductor fin 218 (or is considered to be two semiconductor fins aligned along the “x” direction) and is directly connected to the semiconductor layer 215 in the semiconductor fin 218. A first section of the one or more dielectric layers 276 is arranged between the current rail 284 and the first segment of the semiconductor fin, and a second section of the one or more dielectric layers 276 is arranged between the current rail 284 and the second segment of the semiconductor fin. An upper section of the self-aligning contact 282 is included between the first and second sections of the one or more dielectric layers 276, and a lower section of the self-aligning contact 282 is included between the first and second segments of the semiconductor fin.In one embodiment, the rear busbars 284 can be formed using a damascus process, a double damascus process, a metal structuring process, or other suitable processes. The rear busbars 284 can contain tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), copper (Cu), aluminum (Al), titanium (Ti), tantalum (Ta), or other metals and can be deposited by CVD, PVD, ALD, plating, or other suitable processes. Although in . Fig. Not shown in Figure 20B, the rear busbars 284 are embedded in one or more dielectric layers, and the rear interconnect 286 contains wires and vias embedded in one or more dielectric layers. In some embodiments, the rear busbars 284 are considered part of the rear interconnect 286. The presence of the rear busbars 284 advantageously increases the number of metal tracks available in the device 200 for direct connection to source / drain contacts and vias. It also increases the gate density for higher device integration than other structures without the rear busbars 284. The rear busbars 284 can be wider than the first-level (M0) metal tracks on the front of the device 200, which advantageously reduces the resistance of the rear busbars.

[0047] In Operation 138, the procedure 100 ( Fig. 1C) further manufacturing processes on the device 200. For example, it can form passivation layers on the back of the device 200, remove the support 277 and perform further BEOL processes.

[0048] In the embodiments described above, the source feature 260 is configured with a backside silicide feature and a backside self-aligning contact, while the drain feature 260 is isolated from the backside busbars. Both the source and drain features 260 can be configured with a frontside silicide feature and a frontside contact. In an alternative embodiment, the drain feature 260 can be configured with a backside silicide feature and a backside self-aligning contact, while the source feature 260 is isolated from the backside busbars. This can be achieved by interchanging, in the embodiment described above, the processes specifically applied to the source region with those specifically applied to the drain region. For example, the semiconductor layer 239 can be located in the drain region, but need not be located in the source region.In another alternative embodiment, both the source feature 260 and the drain feature 260 can be configured with backside silicide features and backside self-aligning contacts. This can be achieved by applying the processes specifically applied to the source region in the above embodiment to both the source region and the drain region. For example, the semiconductor layer 239 can be arranged in both the source region and the drain region.

[0049] Without being limited thereto, embodiments of the present disclosure realize one or more of the following advantages. For example, embodiments of the present disclosure form backside silicide features and backside self-aligning contacts to source / drain features, which advantageously reduces the source / drain resistance and minimizes the risks of short-circuiting the source / drain features with nearby conductors that incorporate the gate stack. Embodiments of the present disclosure can be readily integrated into existing semiconductor manufacturing processes.

[0050] In one exemplary aspect, the present disclosure relates to a semiconductor structure comprising: a busbar on a rear side of the semiconductor structure; a first interconnect structure on a front side of the semiconductor structure; and a source feature, a drain feature, a first semiconductor fin, and a gate structure located between the busbar and the first interconnect structure, wherein the first semiconductor fin connects the source feature and the drain feature, and the gate structure is arranged on a front face and two side faces of the first semiconductor fin. The semiconductor structure further comprises an insulating structure located between the busbar and the drain feature and between the busbar and the first semiconductor fin, as well as a via extending through the insulating structure and connecting the source feature to the busbar.

[0051] In some embodiments, the semiconductor structure also includes a silicon layer between the drain feature and the isolation structure. In some embodiments, the semiconductor structure further includes a second semiconductor fin aligned with the first semiconductor fin along a longitudinal direction of the first semiconductor fin, wherein the source feature is directly connected to the first and second semiconductor fins, a first section of the isolation structure is arranged between the current rail and the first semiconductor fin, a second section of the isolation structure is arranged between the current rail and the second semiconductor fin, a first section of the via is included between the first and second sections of the isolation structure, and a second section of the via is included between the first and second semiconductor fins.

[0052] In one embodiment, the semiconductor structure also includes a silicide feature between the source feature and the via. In some embodiments, the semiconductor structure also includes a dielectric barrier layer between the first semiconductor fin and the via.

[0053] In one embodiment of the semiconductor structure, the through-hole comprises Cu, Al, Co, W, Ti, Ta, Mo, and Ru. In another embodiment, the semiconductor structure further includes a second interconnect structure on the back side of the semiconductor structure and above the busbar.

[0054] In another embodiment, the semiconductor structure further comprises a first dielectric fin and a second dielectric fin, which extend longitudinally parallel to the first semiconductor fin and from the back side of the semiconductor structure to the front side, with the first semiconductor fin being located between the first and second dielectric fins. In a further embodiment, the via fills a gap extending from the first dielectric fin to the second dielectric fin along a direction perpendicular to a longitudinal direction of the first semiconductor fin.

[0055] In a further exemplary aspect, the present disclosure relates to a method comprising: providing a structure having an insulator, a first semiconductor layer over the insulator, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer, wherein the first and third semiconductor layers contain a first semiconductor material, and wherein the second semiconductor layer contains a second semiconductor material different from the first semiconductor material. The method further comprises: structuring the structure to form fins, each fin having a section of the third semiconductor layer over a section of the second semiconductor layer over a section of the first semiconductor layer;Forming a sacrificial gate structure that engages a channel region of a first fin of the fins and gate spacers on opposite side walls of the sacrificial gate structure; etching a source trench and a drain trench into the first fin adjacent to the gate spacers, wherein the source and drain trenches do not reach the second semiconductor layer; forming an etch mask that covers the drain trench and exposes the source trench; etching the first fin through the etch mask, causing the source trench to extend through the second semiconductor layer and into the first semiconductor layer; and epitaxially growing a fourth semiconductor layer in the source trench and partially filling the source trench, wherein the fourth semiconductor layer extends from the first semiconductor layer to the third semiconductor layer, the fourth semiconductor layer encompassing the first semiconductor material.

[0056] In some embodiments of the method, the first semiconductor material is silicon, and the second semiconductor material is silicon-germanium. In another embodiment, the fourth semiconductor layer comprises undoped silicon.

[0057] In some embodiments, the method following epitaxial growth of the fourth semiconductor layer further comprises removing the etch mask and epitaxially growing a source feature in the source trench and a drain feature in the drain trench. In some further embodiments, the method further comprises: bonding a front face of the structure to a support wafer, the insulator being located on a back face of the structure; thinning the structure from the back face until the second semiconductor layer is exposed; and replacing the second semiconductor layer with a dielectric layer. In some embodiments, the method further comprises: removing the fourth semiconductor layer, thereby forming a hole that exposes the source feature from the back face of the structure, and forming a via in the hole.In some embodiments, the method further includes: forming a busbar on the back of the structure, directly on the dielectric layer, and connecting it to the via.

[0058] In a further exemplary aspect, the present disclosure relates to a method comprising providing a structure having an insulator, several fins on the insulator, a sacrificial gate structure engaging a channel region of a first fin of the fins, and gate spacers on opposite side walls of the sacrificial gate structure, wherein the first fin has a first silicon layer over the insulator, a silicon-germanium layer over the first silicon layer, and a second silicon layer over the silicon-germanium layer. The method further comprises etching a source trench and a drain trench into the first fin adjacent to the gate spacers, wherein the drain trench does not expose the silicon-germanium layer, and wherein the source trench extends through the second silicon layer and the silicon-germanium layer and into the first silicon layer.The process further comprises the epitaxial growth of a third silicon layer in the source trench and the partial filling of the source trench, with the third silicon layer extending from the first silicon layer to the second silicon layer. The process further comprises the epitaxial growth of a source feature from the second and third silicon layers in the source trench and a drain feature from the second silicon layer in the drain trench.

[0059] In some embodiments, the method further comprises replacing the sacrificial gate structure with a metal gate having a high k-value. In another embodiment, the method comprises: bonding a front face of the structure to a support wafer, wherein the insulator is located on a back face of the structure; thinning the structure from the back face until the silicon-germanium layer is exposed; and replacing the silicon-germanium layer with a dielectric layer. In a further embodiment, the method comprises: removing the third silicon layer, thereby forming a hole through the dielectric layer and exposing the source feature from the back face of the structure; forming a via in the hole; and forming a busbar on the back face of the structure and connecting it to the via.

Claims

[1] Semiconductor structure which exhibits: a power rail on one back side of the semiconductor structure; a first interconnect structure on one front side of the semiconductor structure; a source feature, a drain feature, a first semiconductor fin and a gate structure located between the current rail and the first interconnect structure, wherein the first semiconductor fin connects the source feature and the drain feature, and the gate structure is arranged on a front face and two side faces of the first semiconductor fin; an insulation structure located between the busbar and the drain feature and between the busbar and the first semiconductor fin; a via that passes through the insulation structure and connects the source feature to the busbar; and a first dielectric fin and a second dielectric fin, which run longitudinally parallel to the first semiconductor fin and extend from the back of the semiconductor structure to the front of the semiconductor structure, wherein the first semiconductor fin is arranged between the first and the second dielectric fin, wherein the via fills a gap extending from the first dielectric fin to the second dielectric fin along a direction perpendicular to a longitudinal direction of the first semiconductor fin. [2] Semiconductor structure of claim 1, further comprising: a silicon layer between the drain feature and the insulation structure. [3] Semiconductor structure according to claim 1 or 2, further comprising a second semiconductor fin which is aligned with the first semiconductor fin along a longitudinal direction of the first semiconductor fin, wherein the source feature is directly connected to the first and the second semiconductor fin, a first section of the insulation structure is arranged between the current rail and the first semiconductor fin, a second section of the insulation structure is arranged between the current rail and the second semiconductor fin, a first section of the via is accommodated between the first and the second section of the insulation structure, and a second section of the via is accommodated between the first and the second semiconductor fin. [4] Semiconductor structure according to one of the preceding claims, which further comprises a silicide feature between the source feature and the via. [5] Semiconductor structure according to one of the preceding claims, which further comprises a dielectric barrier layer between the first semiconductor fin and the via. [6] Semiconductor structure according to one of the preceding claims, wherein the through-hole comprises Cu, Al, Co, W, Ti, Ta, Mo and Ru. [7] Semiconductor structure according to one of the preceding claims, which further comprises a second interconnect structure on the back side of the semiconductor structure and above the busbar. [8] A method which features: Providing a structure comprising an insulator, a first semiconductor layer over the insulator, a second semiconductor layer over the first semiconductor layer, and a third semiconductor layer over the second semiconductor layer, wherein the first and third semiconductor layers contain a first semiconductor material, and wherein the second semiconductor layer contains a second semiconductor material that is different from the first semiconductor material; Structuring the structure to form fins, each fin having a section of the third semiconductor layer over a section of the second semiconductor layer over a section of the first semiconductor layer; Forming a sacrificial gate structure that engages a channel region of a first fin of the fins and gate spacers on opposite side walls of the sacrificial gate structure; Etching a source trench and a drain trench into the first fin next to the gate spacers, whereby the source and drain trenches do not reach the second semiconductor layer; Forming an etching mask that covers the drain trench and exposes the source trench; Etching of the first fin through the etching mask, causing the source trench to extend through the second semiconductor layer and into the first semiconductor layer; epitaxial growth of a fourth semiconductor layer in the source trench and partial filling of the source trench, wherein the fourth semiconductor layer extends from the first semiconductor layer to the third semiconductor layer, wherein the fourth semiconductor layer comprises the first semiconductor material; after epitaxial growth of the fourth semiconductor layer: Removing the etching mask; and epitaxial cultivation of a source trait in the source trench and a drain trait in the drain trench, the procedure further features: Bonding a front side of the structure to a support wafer, wherein the insulator is located on a back side of the structure; Thinning the structure from the back of the structure until the second semiconductor layer is exposed; Replacing the second semiconductor layer with a dielectric layer; Removal of the fourth semiconductor layer, creating a hole that exposes the source feature from the back of the structure; and Forming a via in the hole, wherein the structure further comprises a first dielectric fin and a second dielectric fin which extend longitudinally parallel to the first fin and from the back of the structure to the front of the structure, wherein the first fin is arranged between the first and the second dielectric fin, wherein the via fills a gap which extends from the first dielectric fin to the second dielectric fin along a direction perpendicular to a longitudinal direction of the first fin. [9] Method according to claim 8, wherein the first semiconductor material is silicon and the second semiconductor material is silicon germanium. [10] Method according to claim 9, wherein the fourth semiconductor layer comprises undoped silicon. [11] Method according to any one of the preceding claims 8 to 10, further comprising: Forming a busbar on the back of the structure, directly on the dielectric layer, and connecting it to the via. [12] A method which features: Providing a structure comprising an insulator, multiple fins on the insulator, a sacrificial gate structure engaging a channel region of a first fin of the fins, and gate spacers on opposite side walls of the sacrificial gate structure, wherein the first fin comprises a first silicon layer over the insulator, a silicon germanium layer over the first silicon layer, and a second silicon layer over the silicon germanium layer; Etching a source trench and a drain trench into the first fin next to the gate spacers, wherein the drain trench does not expose the silicon germanium layer, and wherein the source trench extends through the second silicon layer and the silicon germanium layer and into the first silicon layer; epitaxial growth of a third silicon layer in the source trench and partial filling of the source trench, with the third silicon layer extending from the first silicon layer to the second silicon layer; epitaxial growth of a source feature from the second and third silicon layers in the source trench and a drain feature from the second silicon layer in the drain trench; Replacing the sacrificial gate structure with a metal gate with a high k-value; Bonding a front side of the structure to a support wafer, wherein the insulator is located on a back side of the structure; Thinning the structure from the back of the structure until the silicon-germanium layer is exposed; Replacing the silicon-germanium layer with a dielectric layer; Removing the third silicon layer, thereby creating a hole through the dielectric layer and exposing the source feature from the back of the structure; Forming a via in the hole; and Forming a busbar on the back of the structure, and connecting it to the via, wherein the structure further comprises a first dielectric fin and a second dielectric fin which extend longitudinally parallel to the first fin and from the back of the structure to the front of the structure, wherein the first fin is arranged between the first and the second dielectric fin, the via fills a gap extending from the first dielectric fin to the second dielectric fin along a direction perpendicular to a longitudinal direction of the first fin.

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