Semiconductor device and its manufacturing process

Abstract

comprising a semiconductor device: a semiconductor layer (1830); a gate structure (1810, 1820) that is arranged on the semiconductor layer (1830); Source and drain terminals (1860) arranged on the semiconductor layer (1830); and a binary oxide layer (1840) that is positioned between and connects the semiconductor layer (1830) and the source and drain terminals (1860), wherein the source and drain terminals (1860) are arranged on two opposite sides of the gate structure (1810, 1820) and the gate structure (1810, 1820) and the source and drain terminals (1860) surround the semiconductor layer (1830), wherein the binary oxide layer (1840) extends over three sides of the semiconductor layer (1830) and the source and drain terminals (1860) are in contact with the binary oxide layer (1840).

Description

BACKGROUND

[0001] Developments in the decreasing size of semiconductor devices and electronic components enable the integration of more devices and components into a given volume, leading to a high integration density of various semiconductor devices and / or electronic components.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in publications US 2010 / 0 181 565 A1, US 2009 / 0 278 236 A1 and US 2019 / 0 245 090 A1.

[0003] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1 to Fig. Figure 6 shows schematic cross-sectional views of various stages in a manufacturing process of a semiconductor device according to some embodiments of the disclosure. Fig. 7 and Fig. Figure 8 are schematic cross-sectional views showing a semiconductor device according to some embodiments of the disclosure. Fig. Figure 9 is a schematic cross-sectional view showing a section of the structure and a semiconductor device therein according to some embodiments of the disclosure. Fig. 10 to Fig. Figure 15 are schematic cross-sectional views of various stages in a manufacturing process of a semiconductor device according to some embodiments of the disclosure. Fig. 16 and Fig. Figure 17 are schematic cross-sectional views showing a semiconductor device according to some embodiments of the disclosure. Fig. Figure 18 is a schematic three-dimensional view showing a semiconductor device according to some embodiments of the disclosure. Fig. 19 and Fig. Figure 20 are schematic cross-sectional views showing the semiconductor device according to some embodiments of the disclosure. Fig. Figure 21 is a schematic three-dimensional view showing a semiconductor device according to some embodiments of the disclosure. Fig. 22 and Fig. Figure 23 are schematic cross-sectional views showing the semiconductor device according to some embodiments of the disclosure. DETAILED DESCRIPTION

[0005] Embodiments of the present disclosure describe the exemplary fabrication process of integration structures formed with one or more semiconductor devices, such as transistors, and the integration structures fabricated therefrom. Certain embodiments of the present disclosure relate to the structures, including semiconductor transistors and other semiconductor devices. The substrates and / or wafers may include one or more types of integrated circuits or electronic components. The semiconductor device(s) may be formed on a basic semiconductor substrate or a silicon / germanium-on-insulator substrate.

[0006] Fig. 1 to Fig. Figure 6 shows schematic cross-sectional views of various stages in a manufacturing process for a semiconductor device according to some embodiments of the disclosure. Fig. Figures 1 to 6 show schematic cross-sectional views of a device area DR of the integration structure. Fig. Figure 9 is a schematic cross-sectional view showing part of the structure and a semiconductor device therein according to some embodiments of the disclosure.

[0007] Referring to Fig. In some embodiments, a substrate 100 is provided with one or more interconnect structures 102 therein. As in Fig. As shown in Figure 1, in some embodiments the interconnect structure 102 (only one is shown) is formed in the substrate 100 within the device area DR. It is understood that the number of interconnect structures 102 can be more than one and that the number or configuration of the interconnect structures 102 is not limited by the exemplary embodiments or drawings of this disclosure. Fig. 1 to Fig. Figure 6 shows only a portion of the device area DR of the substrate 100 for illustrative purposes. In some embodiments, the substrate 100 also includes one or more active components such as transistors, diodes, optoelectronic devices, and / or one or more passive components such as capacitors, inductors, and resistors. Referring to Fig. Figure 9 of the integration structure 90 comprises a substrate 900 and a semiconductor device 960 formed above the substrate 900. In some embodiments, the substrate 900 is adjacent to the substrate 100. Fig. 1 essentially similar.

[0008] Referring to Fig. 1 and Fig. In some embodiments, either substrate 100 or substrate 900 comprises a semiconductor substrate. In one embodiment, substrate 100 or 900 comprises a crystalline silicon substrate or a doped semiconductor substrate (e.g., a p-type or n-type semiconductor substrate). In certain embodiments, substrate 100 or 900 comprises one or more doped regions or different types of doped regions, depending on the design requirements. In some embodiments, the doped regions are doped with p-type and / or n-type dopants. For example, the p-type dopants are boron or BF₂, and the n-type dopants are phosphorus or arsenic. The doped regions can be configured for an n-type metal-oxide-semiconductor transistor (MOS transistor) or a p-type MOS transistor (PMOS transistor).In some alternative embodiments, the substrate 100 or 900 comprises a semiconductor substrate of another suitable elemental semiconductor such as diamond or germanium; a suitable compound semiconductor such as gallium arsenide, silicon carbide, indium arsenide or indium phosphide; or a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenic phosphide or gallium indium phosphide.

[0009] In some embodiments, such as in Fig. As shown in Figure 9, the substrate 900 has transistors such as an NMOS 902 and a PMOS 904 formed in the semiconductor substrate 901. In one embodiment, the NMOS 902 and / or the PMOS 904 are formed according to the complementary MOS processes (CMOS processes). As shown in Fig. As shown in Figure 9, in some embodiments more than one insulating structure 906 is formed in the semiconductor substrate 901. In certain embodiments, the insulating structures 906 are trench insulating structures. In other embodiments, the insulating structures 906 exhibit the local oxidation of silicon structures (LOCOS structures). In some embodiments, the insulating material of the insulating structures 906 comprises silicon oxide, silicon nitride, silicon oxynitride, a dielectric spin-on material, or a dielectric material with a low k-value. In one embodiment, the insulating material can be formed by CVD, such as by high-density plasma chemical vapor deposition (HDP-CVD), sub-atmospheric pressure CVD (SACVD), or spin deposition.In certain embodiments, the transistors such as the NMOS 902 and the PMOS 904 and the isolation structures 906 are formed in the substrate 900 during the front-end-of-line process (FEOL process).

[0010] In some embodiments, the substrate 900 has metallization structures 908 embedded in an insulating layer 910. As shown in Fig. As shown in Figure 9, the insulating layer 910 and the metallization structures 908 are located above the transistors formed in the semiconductor substrate 901. In some embodiments, the insulating layer 910 comprises one or more dielectric layers. In some embodiments, the insulating layer 910 material includes silicon oxide, a dielectric spin-on material, a low-k dielectric material, or a combination thereof. The formation of the insulating layer 910 involves performing one or more processes, such as chemical vapor deposition (CVD) or spin deposition. In some embodiments, the metallization structures 908 include interconnect structures, such as metal conductors, vias, and contact connectors. In certain embodiments, the metallization structures 908 materials include aluminum (Al), aluminum alloys, copper (Cu), copper alloys, tungsten (W), or combinations thereof.In exemplary embodiments, the transistors, such as the NMOS 902 and the PMOS 904, are electrically connected to the metallization structures 908, and some of the transistors are further electrically interconnected through the metallization structures 908. The metallization structures 908 shown here are for illustrative purposes only, and the metallization structures 908 may have other configurations and may include one or more vias and / or damascus structures.

[0011] With renewed reference to Fig. 1 In some embodiments, the interconnect structure 102 embedded in the substrate 100 can be part of metallization structures in the substrate 100 for electrical connection and interconnection, and the metallization structures in the substrate 100 are similar to the metallization structures 908 as shown in Fig. Figure 9 shows that in one embodiment, the interconnect structure 102 comprises a conductive via. Fig. In embodiment 1, a gate material layer 110 is formed covering the entire substrate 100, which covers the interconnect structure. In one embodiment, the gate material layer 110 is in direct contact with the interconnect structure 102. In some embodiments, the gate material layer 110 comprises one or more metallic material layers. In some embodiments, the formation of the gate material layer 110 involves one or more deposition processes, selected from chemical vapor deposition (CVD) (such as plasma-enhanced CVD (PECVD) and laser-enhanced CVD), atomic layer deposition (ALD), and physical vapor deposition (PVD) (such as sputtering and electron beam evaporation). In some embodiments, the formation of the gate material layer 110 includes a plating process. In some embodiments, the gate material layer 110 is formed with a thickness in the range of approximately 5 nm to approximately 100 nm.In some embodiments, the materials of the gate material layer 110 include aluminum (Al), titanium (Ti), tungsten (W), tantalum (Ta), nitrides thereof, combinations thereof, and / or alloys thereof. For example, the gate material layer 110 may comprise one or more stacked layers of TiN, TaN, W / TiN, TiN / TiAl / TiN, or TiN / TiAl / TaN.

[0012] In Fig. In some embodiments, a gate dielectric material layer 120 is formed globally above the gate material layer 110. In some embodiments, the gate dielectric material layer 120 comprises one or more high k-dielectric materials, such as ZrO2, Gd2O3, HfO2, BaTiO3, Al2O3, LaO2, TiO2, Ta2O5, Y2O3, STO, BTO, Ba-ZrO, HfZrO, HfLaO, HfTaO, HfTiO, or combinations thereof. In some embodiments, the gate dielectric material layer 120 contains one or more materials selected from aluminum oxide, hafnium oxide, tantalum oxide, and zirconium oxide. In some embodiments, the formation of the gate dielectric material layer 120 involves one or more deposition processes selected from CVD (such as PECVD and laser-assisted CVD), ALD, and PVD (such as sputtering and electron beam evaporation). In some embodiments, the gate dielectric material layer 120 is formed with a thickness in the range of approximately 1 nm to approximately 20 nm.In some embodiments, the materials of the gate dielectric material layer 120 contain aluminum oxide, hafnium oxide, or combinations thereof. For example, the gate dielectric material layer 120 can be formed by depositing a composite layer of HfO2 / Al2O3 by ALD.

[0013] In some embodiments, after the formation of the gate dielectric material layer 120, a semiconductor material layer 130 and a binary oxide material layer 140 are successively formed over the gate dielectric material layer 120 to form a stacked structure 10. In some embodiments, the materials of the semiconductor material layer 130 and the binary oxide material layer 140 comprise metal oxide materials. In some embodiments, the formation of the semiconductor material layer 130 and the binary oxide material layer 140 includes one or more deposition processes selected from CVD (such as PECVD and laser-assisted CVD), ALD, and PVD (such as sputtering, pulsed laser deposition (PLD), and electron beam evaporation). If the formation of the semiconductor material layer 130 includes a CVD process or an ALD process, an annealing process may optionally be included.In some embodiments, the semiconductor material layer 130 and the binary oxide material layer 140 are formed sequentially but continuously in the same PVD process or within the same reaction tool. In some embodiments, using the same deposition process, the semiconductor material layer 130 is deposited completely over the gate dielectric material layer 120, and then the binary oxide material layer 140 is formed completely over the top surface of the semiconductor material layer 130 as a cover layer. In one embodiment, the semiconductor material layer 130 is formed with a thickness in the range of approximately 1 nm to approximately 50 nm, and the binary oxide material layer 140 is formed with a thickness substantially equivalent to or less than approximately 5 nm. In some embodiments, the semiconductor material layer 130 has a thickness greater than that of the binary oxide material layer 140.In some embodiments, the semiconductor material layer 130 comprises indium gallium zinc oxide (IGZO) or a similar conductive oxide semiconductor material such as indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), or zinc tin oxide (ZTO), or combinations thereof. In some embodiments, the binary oxide material layer 140 comprises gallium oxide, indium oxide, zinc oxide, titanium oxide, aluminum oxide, mixtures thereof, or combinations thereof. In certain embodiments, the binary oxide material layer 140 comprises gallium oxide (such as Ga₂O₃), indium oxide (such as In₂O₃), zinc oxide, mixtures thereof, or combinations thereof.In one embodiment, the semiconductor material layer 130 and the binary oxide material layer 140 are formed sequentially and continuously in the same PVD process. The semiconductor material layer 130 is produced from IGZO, and then the binary oxide layer is formed from one or more materials selected from gallium oxide, indium oxide, and zinc oxide by adjusting the stoichiometry of the reactants to form IGZO. In other embodiments, the semiconductor material layer 130 is deposited by an ALD process, and the binary oxide material layer 140 is also formed by the ALD process. The reactants used in the ALD process can be adjusted or shifted. In certain embodiments, the material of the binary oxide material layer 140 contains titanium oxide and / or aluminum oxide.For example, the formation of the binary oxide material layer 140 (such as titanium oxide) can lead to more oxygen defects in the semiconductor material layer 130 (such as IGZO or other suitable materials).

[0014] In the embodiments mentioned above, the semiconductor material layer 130 and the binary oxide material layer 140 can be formed with similar reactants in varying stoichiometric ratios by the same forming process, and displacement regions (regions of composition gradients) can be formed at the interface between the semiconductor material layer 130 and the binary oxide material layer 140.

[0015] Referring to Fig. 1 and Fig. 2 In some embodiments, a structuring process is performed on the stacked structure 10 of the gate material layer 110, the gate dielectric material layer 120, the semiconductor material layer 130, and the binary oxide material layer 140, such that the stacked structure 10 is structured to form a stacked structure 12 with a gate layer 111, a gate dielectric layer 121, a semiconductor layer 131, and a binary oxide layer 141, which are stacked sequentially from bottom to top. In some embodiments, the stacked structure 10 of the gate material layer 110, the gate dielectric material layer 120, the semiconductor material layer 130, and the binary oxide material layer 140 is structured into the stacked structure 12 in a continuous structuring process.In some embodiments, the gate material layer 110, the gate dielectric material layer 120, the semiconductor material layer 130, and the binary oxide material layer 140 are structured successively by several structuring processes. As shown in . Fig. As shown in Figure 2, in exemplary embodiments the structured stacking structure 12 is arranged on the interconnecting structure 102, thereby exposing the substrate 100. The side walls of the stacking structure 12 in Fig. The two components can be shown to be vertically oriented or coplanar, and the stacked structure 12 can be shown to be structured in essentially the same structural design or configuration. It is understood, however, that the different layers of the stacked structure 12 may exhibit different patterns or configurations depending on the product designs. In some embodiments, the structuring and formation of the stacked structure 12 involves performing a photolithographic process and an anisotropic etching process. In some embodiments, a photoresist pattern (not shown) can be used as an etching mask, such that sections of the stacked structure 10 exposed by the photoresist pattern are removed during the etching process, and then the photoresist pattern is removed by a stripping process.

[0016] With reference to Fig. 3 is an interlayer dielectric layer (ILD layer) 150 formed between the layers, completely covering the substrate 100 and covering the stacked structure 12. In some embodiments, the ILD layer 150 material comprises silicon oxide, silicon nitride, silicon oxynitride, or one or more low-k dielectric materials. Examples of low-k dielectric materials include silicate glass such as fluorosilicate glass (FSG), phosphosilicate glass (PSG), and boron phosphosilicate glass (BPSG), BLACK DIAMOND®, SILK®, FLARE®, hydrogen silsesquioxane (HSQ), fluorinated silicon dioxide (SiOF), amorphous fluorinated carbon, parylene, BCB (bisbenzocyclobutene), or a combination thereof. It is understood that the ILD layer 150 may contain one or more dielectric materials or one or more dielectric layers.In some embodiments, the ILD layer 150 is formed to a suitable thickness by CVD (such as flowable CVD (FCVD), PECVD, high-density plasma-compressed CVD (HDPCVD), sub-atmospheric ACVD (SACVD), and low-pressure CVD (LPCVD)), spin-on coating, or other suitable methods. For example, a dielectric interlayer material (not shown) can be formed by PECVD to cover the exposed substrate 100 and the stacked structure 12 with the gate layer 111, the gate dielectric layer 121, the semiconductor layer 131, and the binary oxide layer 141. Optionally, an etching or polishing process can be performed to reduce the thickness of the dielectric interlayer material to a desired thickness for forming the ILD layer 150.

[0017] In Fig. 4. Contact openings 155 are formed in the ILD layer 150, thereby exposing the binary oxide layer 141. In some embodiments, the formation of the contact openings 155 includes forming a structured mask layer (not shown) over the ILD layer 150, anisotropic etching of the ILD layer 150 using the structured mask layer as a mask to form contact openings 155, thereby exposing the binary oxide layer 141. As in Fig. As can be seen in Figure 4, the contact openings 155 are shown with essentially vertical side walls. It goes without saying that, where feasible, the contact openings can be designed with sloping side walls.

[0018] Then in Fig. Five contact terminals 160 are formed in the contact openings 155. In some embodiments, a barrier layer 162 is deposited over the contact openings 155 and conformally covers the side walls and bottoms of the contact openings 155. In some embodiments, a nucleation layer 164 is formed over the contact openings 155 and on the barrier layer 162. In some embodiments, the barrier layer 162 is formed before the nucleation layer 164 forms to prevent diffusion of the nucleation layer 164 material. After the nucleation layer 164 has formed to cover the side walls and bottoms of the contact openings 155, metal contacts 166 are then formed on the nucleation layer 164 within the contact openings 155 and fill the contact openings 155.

[0019] In some embodiments, a barrier material (not shown) and a seed material are successively formed over the contact openings 155 and conformally cover the exposed surfaces of the contact openings 155, and a metallic material (not shown) is then filled into the contact openings 155 to form the metallic contacts 166. The barrier material, the seed material, and the metallic material may each comprise one or more materials selected from, for example, tungsten (W), ruthenium (Ru), molybdenum (Mo), tantalum (Ta), titanium (Ti), alloys thereof, and nitrides thereof. In some embodiments, the barrier material is formed by CVD or PVD. In some embodiments, the seed material is formed by CVD or PVD. In some embodiments, the metallic material is formed by CVD or PVD.In alternative embodiments, the formation of the metallic material may involve performing a plating process (such as electrochemical plating (ECP)). In some embodiments, the barrier material comprises titanium nitride (TiN) formed by the metal-organic CVD process (MOCVD process), the seed material contains tungsten formed by CVD, and the metallic material comprises tungsten formed by the CVD process (in particular, the tungsten CVD process). For example, the metal contact 166 comprises a tungsten contact, and the barrier layer 162 comprises a titanium nitride barrier layer.

[0020] In some embodiments, the additional barrier material, the additional nucleation material, and the additional metallic material can be removed by performing a planarization process, an etching process, or other suitable processes. In some embodiments, the planarization process may include performing a chemical-mechanical polishing (CMP) process. In some embodiments, the barrier layer 162, the nucleation layer 164, and the metal contact 166 form contact terminals 160. As in Fig. As can be seen in Figure 5, the upper surface 150t of the ILD layer 150 is essentially flush with and aligned with the upper surfaces 160t of the contact terminals 160. In some embodiments, the contact terminals 160 function as the source and drain terminals of the transistor. Fig. In this process, a transistor structure 50 is achieved. The transistor structure 50 has a stacked structure 12 with the gate layer 111, the gate dielectric layer 121, the semiconductor layer 131, and the binary oxide layer 141, which are stacked sequentially from bottom to top, and the contact terminals 160 located on the stacked structure. The semiconductor layer 131 acts as a channel layer, and the binary oxide layer 141 located between the contact terminals 160 and the semiconductor layer 131 helps to reduce the contact resistance of the source and drain terminals. In some embodiments, the transistor structure 50 is a bottom-gate transistor structure or a back-gate transistor structure.

[0021] Referring to Fig. In certain embodiments, an interconnect structure 170 is formed on the ILD layer 150 and over the contact terminals 160, and the semiconductor device structure 60 is formed. In one embodiment, the interconnect structure 170 is in direct contact with the contact terminals 160 and is electrically connected to the contact terminals 160 of the transistor structure 50, so that the transistor structure 50 is further electrically connected to other components or devices. In some embodiments, the interconnect structure 170 has first metal conductors 172 formed on first lining layers 174 and first metal vias 176 surrounded by the second lining layers 178.In some embodiments, a first lining material (not shown) is formed directly on the ILD layer 150 and on the upper surfaces 160t of the contact terminals 160. A first metal layer (not shown) is formed on the first lining material, and then the first lining material and the first metal layer are patterned into the first metal conductors 172 and the first lining layers 174 using photolithography and etching techniques. The first lining material can be formed, for example, by PVD (such as sputtering) or CVD or the like. In some embodiments, the first lining material comprises, for example, tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, combinations thereof, or other suitable materials.In some embodiments, the first lining layers 174 can prevent diffusion of the material of the first metal conductors 172 and / or improve the adhesion of the first metal conductors 172. In some embodiments, the first metal layer can be formed by performing a plating process such as electrochemical plating (ECP) or electroless plating, a PVD process, or a CVD process. In some embodiments, the first metal layer contains, for example, copper, copper-aluminum alloys, tantalum, titanium, tungsten, alloys thereof, or other suitable metallic materials.

[0022] In some embodiments, such as in Fig. As shown in Figure 6, the first metal conductors 172 are in direct contact with the contact terminals 160 and are electrically connected to them. For example, the first metal conductors 172 can contain copper or copper alloys and can be formed by performing a PVD process and a CVD process. In one embodiment, the thickness of the first metal conductors 172 can be adjusted according to the design requirements. As shown in Fig. As shown in Figure 6, in certain embodiments a further ILD layer 180 is formed above the ILD layer 150 and the first metal conductors 172. The materials and formation methods of the ILD layer 180 can be similar to those of the ILD layer 150, and detailed descriptions thereof are omitted here for the sake of simplicity. Subsequently, vias V are formed in the ILD layer 180 to partially expose the underlying first metal conductors 172. The method(s) for forming the vias V is / are similar to the method(s) for forming the contact openings 155. As shown in Fig. As can be seen in Figure 6, the vias V are shown with inclined sidewalls. It goes without saying that, where possible, the vias can be designed with essentially vertical sidewalls.

[0023] In some embodiments, in Fig. 6. The second lining layers 178 are formed in the through-holes V, covering the side walls and bottom of the through-holes V, and then the first metal vias 176 are formed on the second lining layers 178 and within the through-holes V. In some embodiments, a second lining material (not shown) is formed over the through-holes V, conformally covering the exposed surfaces of the through-holes V, and then a second metal layer (not shown) is formed over the ILD layer 180 and filled into the through-holes V. The formation methods and materials of the second lining layers 178 are similar to those of the first lining layers 174. The formation methods and materials of the first metal vias 176 are similar to those of the first metal traces 172. Detailed descriptions are omitted here for the sake of simplicity.However, it goes without saying that the material of the first metal conductors 172 may differ from that of the first metal vias 176, and that the material of the first lining layer 174 may differ from that of the second lining layer 178.

[0024] The number and configurations of the metal conductors and / or metal vias of the in Fig. The interconnect structure shown in Figure 6 (170) serves only for illustration; in some alternative embodiments, more than two metal conductors or metal vias can be formed according to actual design requirements. Furthermore, multiple levels of interconnect structures can be formed for electrical connection and wiring.

[0025] The semiconductor device structure 60 shows an integrated circuit or a section thereof. In some embodiments, the semiconductor device structure 60 includes active components such as oxide semiconductor thin-film transistors, high-voltage transistors, and / or other suitable components. In some embodiments, the semiconductor device structure 60 additionally includes passive components such as resistors, capacitors, inductors, and / or fuses. In some embodiments, additional steps may be performed before, during, and after the Fig. 1 to Fig. The process steps shown in the 6 diagrams are provided, and some of the steps described above can be replaced or omitted for additional embodiments of the process.

[0026] In the illustrated embodiments, the described methods and structures can be formed that are compatible with current semiconductor manufacturing processes. In exemplary embodiments, the described methods and structures are formed during back-end-of-line (BEOL) processes. In some embodiments, the described methods and structures can be formed during middle-of-line processes. In one embodiment, the transistor structure 50 comprises an IGZO thin-film transistor.

[0027] In the exemplary embodiments, the formation of the binary oxide layer between the channel layer (e.g., semiconductor layer) and the source and drain terminals leads to more oxygen vacancies and higher doping in the channel layer beneath the contact surfaces of the channel layer, as well as to lower contact resistance between the channel layer and the source and drain terminals. Overall, the performance of the semiconductor device is improved.

[0028] In the embodiments mentioned above, the binary oxide layer and the semiconductor channel layer can be formed in the same chamber in a self-aligned manner using the same deposition process, and the binary oxide layer can be formed as a cover layer on top. The surface of the semiconductor layer can be appropriately controlled. In some embodiments, the cover layer of the binary oxide formed over the semiconductor layer modulates the surface properties of the semiconductor layer and reduces the contact resistance between the semiconductor layer and the source and drain terminals.

[0029] Fig. Figure 7 is a schematic cross-sectional view showing a semiconductor device according to some embodiments of the disclosure. The exemplary structure shown in Fig. Figure 7 can be produced according to the process steps described in the previous embodiments, as shown in Fig. 1 to Fig. 6 shown. However, it is understood that other compatible process steps or procedures may be used and understandable modifications or adjustments may be made to form the exemplary structure of this disclosure. Referring to Fig. In some embodiments, the semiconductor device structure 70 comprises a stacked structure consisting of a gate layer 710, a gate dielectric layer 720, a semiconductor layer 730, and a binary oxide layer 740, stacked sequentially from bottom to top. In some embodiments, the semiconductor device structure 70 includes a source terminal 760A and a drain terminal 760B, which are directly located on the binary oxide layer 740 of the stacked structure. In some embodiments, the source terminal 760A and the drain terminal 760B are separated from each other by an interlayer dielectric layer (ILD layer) 750. In some embodiments, the source terminal 760A has a barrier layer 762A, and the drain terminal 760B also has a barrier layer 762B.In some embodiments, the binary oxide layer 740 extends onto and above the upper surface 730t of the semiconductor layer 730, and the binary oxide layer is in direct contact with the source terminal 760A and the drain terminal 760B. In some embodiments, the ILD layer 750, which is arranged interposed between the source terminal 760A and the drain terminal 760B, is located directly on the binary oxide layer 740. Fig. 7 The binary oxide layer 740 is arranged between the upper surface 730t of the semiconductor layer 730 and the lower surfaces 760p of the source terminal 760A and the drain terminal 760B, and between the upper surface 730t of the semiconductor layer 730 and the lower surface 750b of the ILD layer 750. Applicable materials for individual layers or elements are described in the preceding embodiments and are not repeated here.

[0030] Fig. Figure 8 is a schematic cross-sectional view showing a semiconductor device according to some embodiments of the disclosure. The in Fig. The structure shown in Figure 8 is similar, but also differs from the one in Figure 8. Fig. 7 structure shown, the main structural difference being that the location of the binary oxide layer 840 in the semiconductor device structure 80, as in Fig. As shown in point 8, it lies. With reference to Fig. In some embodiments, the semiconductor device structure 80 comprises a stacked structure of a gate layer 810, a gate dielectric layer 820, and a semiconductor layer 830, which are stacked sequentially from bottom to top. In some embodiments, the structure 80 has a source terminal 860A and a drain terminal 860B, which are arranged on the semiconductor layer 830 of the stacked structure. In some embodiments, the source terminal 860A and the drain terminal 860B are separated from each other by an interlayer dielectric layer (ILD layer) 850. Fig. In 8, each source terminal 860A and drain terminal 860B is surrounded by a binary oxide layer 840. In some embodiments, either the source terminal 860A or the drain terminal 860B is surrounded by the binary oxide layer 840, and the binary oxide layer 840 covers the side walls and bottom surfaces of the source terminal 860A and the drain terminal 860B. In some embodiments, the source terminal 860A and the drain terminal 860B are insulated from the underlying semiconductor layer 830 and the ILD layer 850 by the binary oxide layer 840. In some embodiments, the binary oxide layer 840 is located only directly under the source terminal and under the drain terminal 860A, 860B, and between the semiconductor layer 830 and the source and drain terminals 860A, 860B, and the ILD layer 850, which is located there in between, is in direct contact with the semiconductor layer 830. Fig. In section 8, the source terminal 860A has a barrier layer 862A, and the drain terminal 860B also has a barrier layer 862B. The exemplary structure shown in Fig. Figure 8 shows that it can be manufactured using similar process steps as described in the previous embodiments, as described by Fig. 1 to Fig. Figure 6 shows. In some embodiments, however, after the formation of the vias, the binary oxide layer 840 can be formed within the vias V before the formation of the barrier layer 862A, 862B. In some embodiments, the binary oxide layer 840 is deposited in the vias by at least one deposition process selected from CVD, ALD, and PVD, and the binary oxide layer 840 conformally covers the exposed surfaces of the vias. In some embodiments, the formation of the semiconductor layer 830 and the formation of the binary oxide layer 840 can undergo different deposition processes.

[0031] In the exemplary embodiments, the formation of the binary oxide layer located between the channel layer (e.g., semiconductor layer) and the source and drain terminals leads to a reduced contact resistance between the channel layer and the source and drain terminals. Therefore, the performance of the semiconductor device is increased.

[0032] Fig. 10 to Fig. Figure 15 are schematic cross-sectional views of various stages in a manufacturing process of a semiconductor device according to some embodiments of the disclosure.

[0033] Referring to Fig. In some embodiments, a substrate 300 is provided. Fig. Figures 10-15 show only a section of the device area DR of substrate 300 for illustrative purposes. In some embodiments, substrate 300 is similar to substrates 100 and 900 in the previous embodiments, and substrate 300 may include one or more active components such as transistors, diodes, and optoelectronic devices, and / or one or more passive components such as capacitors, inductors, and resistors. In some embodiments, as shown in Fig. As shown in Figure 10, a semiconductor material layer 330 and a binary oxide material layer 340 are successively formed over the substrate 300. In one embodiment, the semiconductor material layer 330 is formed with a thickness in the range of approximately 1 nm to approximately 50 nm, and the binary oxide material layer 340 is formed with a thickness that is substantially equal to or less than approximately 5 nm. In some embodiments, the semiconductor material layer 330 has a thickness greater than that of the binary oxide material layer 340.

[0034] In some embodiments, the semiconductor material layer 330 comprises indium gallium zinc oxide (IGZO) or a similar conductive oxide semiconductor material such as indium tin oxide (ITO), indium tungsten oxide (IWO), indium zinc oxide (IZO), or zinc tin oxide (ZTO), or combinations thereof. In some embodiments, the binary oxide material layer 340 comprises gallium oxide, indium oxide, zinc oxide, mixtures thereof, or combinations thereof. In some embodiments, the formation of the semiconductor material layer 330 and the binary oxide material layer 340 comprises one or more deposition processes selected from CVD, ALD, and PVD.In one embodiment, the semiconductor material layer 330 and the binary oxide material layer 340 are formed sequentially and continuously in the same PVD process, and the semiconductor material layer 330 consists of IGZO, and then the binary oxide layer 340 is formed from one or more materials selected from gallium oxide, indium oxide, and zinc oxide by adjusting the stoichiometry of the reactants to form IGZO. In certain embodiments, the material of the binary oxide material layer 340 comprises titanium oxide and / or aluminum oxide.

[0035] In some embodiments, using the same deposition process, the semiconductor material layer 330 is deposited completely over the substrate 300, and then the binary oxide material layer 340 is formed completely over the top surface of the semiconductor material layer 330 as a top layer. In some embodiments, the semiconductor material layer 330 and the binary oxide material layer 340 can be formed with similar reactants in different stoichiometric ratios using the same formation process, and displacement regions (regions of composition gradients) can be formed at the interface between the semiconductor material layer 330 and the binary oxide material layer 340.

[0036] Referring to Fig. 10 and Fig. 11 In some embodiments, the semiconductor material layer 330 and the binary oxide material layer 340 are structured to form a semiconductor layer 331 and a binary oxide layer 341 on the substrate 300, and an active region AR is defined by the structuring process. Subsequently, insulating structures 305 are formed in a non-active region NAR, which surrounds the active region AR for insulation. As in Fig. As shown in Figure 11, in some embodiments more than one insulation structure 305 is formed on the substrate 300. In certain embodiments, the insulation structures 305 are trench insulation structures, and the insulator material of the insulation structures 305 comprises silicon oxide, silicon nitride, silicon oxynitride, a spin-on dielectric material, or a dielectric material with a low k.

[0037] Referring to Fig. 11 A gate dielectric layer 321 and a gate layer 311 are formed on the binary oxide layer 341. In some embodiments, a gate dielectric material layer (not shown) and a gate material layer (not shown) are formed successively over the binary oxide layer 341 and the insulating structures 305 and are then structured into the stack of gate dielectric layer 321 and gate layer 311 by photolithographic and etching processes. As shown in Fig. As shown in Figure 11, in exemplary embodiments the stacked structure 310 of the gate dielectric layer 321 and the gate layer 311 is arranged on the stacked structure of the semiconductor layer 331 and the binary oxide layer 341. In some embodiments, the stacked structure of the gate dielectric layer 321 and the gate layer 311 partially covers the underlying stacked structure of the semiconductor layer 331 and the binary oxide layer 341, thereby exposing sections of the stacked structure of the semiconductor layer 331 and the binary oxide layer 341. In some embodiments, the stacked structure of the semiconductor layer 331 and the binary oxide layer 341 is located within the active region AR, and the gate structure 310 of the gate dielectric layer 321 and the gate layer 311 is located within the active region AR. The side walls of the stacked structure of the gate dielectric layer 321 and the gate layer 311 in Fig. Figure 11 can be shown as vertically oriented or coplanar, and the stacked structure of the gate dielectric layer 321 and the gate layer 311, and the stacked structure of the semiconductor layer 331 and the binary oxide layer 341, can be shown as structured in substantially different structural designs or configurations. It is understood, however, that the various layers of the stacked structure may exhibit different structures or configurations depending on the product design.

[0038] In Fig. In 12, an ILD layer 350 is formed over the substrate 300, which covers the stacked structure of the gate dielectric layer 321 and the gate layer 311, the exposed binary oxide layer 341, and the insulating structures 305. The materials and formation processes of the ILD layer 350 are similar to those of the ILD layer(s) described in the preceding paragraphs, and details are omitted here for the sake of simplicity.

[0039] Referring to Fig. 13 contact openings 355 are formed in the ILD layer 350 to expose parts of the binary oxide layer 341 and the gate layer 311, respectively. As in Fig. As can be seen in Figure 13, the contact openings 355 are shown with essentially vertical side walls. It goes without saying that, where feasible, the contact openings can be designed with sloping side walls.

[0040] Then in Fig. Fourteen contact terminals 360 are formed in the contact openings 355. In some embodiments, the contact terminals 360 are each connected to the gate layer 311 and the binary oxide layer 341. In certain embodiments, a barrier layer 362 is deposited over the contact openings. Similar materials and formation methods for forming the contact terminals 160 can be used for forming the contact terminals 360, and the contact terminals 360 can be formed with a nucleation layer and / or an adhesion layer, but the details will be omitted here for the sake of simplicity.

[0041] With reference to Fig. In some embodiments, a transistor structure 30 is achieved, and the contact terminals 360 function as the source and drain terminals of the transistor. Fig. 14 The transistor structure 30 comprises the gate structure 310 with the gate layer 311 stacked on the gate dielectric layer 321, the stacked structure of the binary oxide layer 341 stacked on the semiconductor layer 331, and the contact terminals 360 arranged on the gate structure and the binary oxide layer 341. The semiconductor layer 331 acts as a channel layer, and the binary oxide layer 341 located between the contact terminals 360 and the semiconductor layer 331 contributes to reducing the contact resistance of the source and drain terminals. In some embodiments, the transistor structure 30 is a top-gate transistor structure or a front-gate transistor structure.

[0042] With reference to Fig. 15 In certain embodiments, an interconnect structure 370 and a further ILD layer 380 are formed on the ILD layer 350, and the semiconductor device structure 40 is formed. In some embodiments, the interconnect structure 370 is formed on and in direct contact with the contact terminals 360 and is electrically connected to the contact terminals 360 of the transistor structure 30, so that the transistor structure 30 is further electrically connected to other components or devices. In some embodiments, the interconnect structure 370 comprises metal conductors 372 and metal vias 376 that are connected to the metal conductors 372.Similar materials and formation methods for forming the interconnect structure 170 can be used to form the interconnect structure 370, and the interconnect structure 370 can be formed with the lining layer(s), the nucleation layer and / or the barrier / adhesion layer, and multiple levels of interconnect structures can be formed for electrical connection and interconnection.

[0043] Although the steps of the process are presented and described as a series of actions or events, it is understood that the presented sequence of such actions or events is not to be interpreted in a restrictive sense. Furthermore, not all of the presented processes or steps are necessary to implement one or more embodiments of the present disclosure.

[0044] Fig. Figure 16 is a schematic cross-sectional view showing a semiconductor device according to some embodiments of the disclosure. Referring to Fig. In some embodiments, the semiconductor device structure 42 comprises a gate structure 1600 consisting of a gate layer 1610 and a gate dielectric layer 1620, which is stacked (from top to bottom) on a binary oxide layer 1640 and a semiconductor layer 1630. In some embodiments, the semiconductor device structure 42 has a source terminal 1660A and a drain terminal 1660B, which are located directly on the binary oxide layer 1640. In some embodiments, the source terminal 1660A and the drain terminal 1660B are located on two opposite sides of the gate structure 1600 and are separated from the gate structure 1600 by an interlayer dielectric layer (ILD layer) 1650. In some embodiments, the source port 1660A and the drain port 1660B may further comprise (a) nucleation layer(s) and / or adhesion / barrier layer(s).In some embodiments, the binary oxide layer 1640 extends onto and above the upper surface 1630t of the semiconductor layer 1630, and the binary oxide layer 1640 is in direct contact with the source terminal 1660A and the drain terminal 1660B. In some embodiments, the ILD layer 1650, which is arranged between the source terminal 1660A and the drain terminal 1660B, is located directly on the binary oxide layer 1640. Fig. 16 is the binary oxide layer 1640 located between the upper surface 1630t of the semiconductor layer 1630 and the lower surfaces 1660p of the source and drain terminals 1660A, 1660B and located between the upper surface 1630t of the semiconductor layer 1630 and the lower surface of the gate dielectric layer 1620.

[0045] Fig. Figure 17 is a schematic cross-sectional view showing a semiconductor device according to some embodiments of the disclosure. The structure shown in Fig. As shown in 17, this is the one in Fig. The structure shown in Figure 16 is similar, but differs from it, the main structural difference being that the location of the binary oxide layer 1740 in the semiconductor device structure 44 is different, as shown in Figure 16. Fig. As shown in 17, it lies. With reference to Fig. In some embodiments, the semiconductor device structure 44 comprises a gate structure 1700 consisting of a gate layer 1710 and a gate dielectric layer 1720, which are stacked on a semiconductor layer 1730. In some embodiments, the structure 44 has a source terminal 1760A and a drain terminal 1760B located on the semiconductor layer 1730 with an intervening binary oxide layer 1740. In some embodiments, the source terminal 1760A and the drain terminal 1760B are located on two opposite sides of the gate structure 1700 and are separated from the gate structure 1700 by an intervening dielectric layer (ILD layer) 1750. Fig. In embodiment 17, both the source terminal 1760A and the drain terminal 1760B are surrounded by a binary oxide layer 1740. In some embodiments, either the source terminal 1760A or the drain terminal 1760B is surrounded by the binary oxide layer 1740, and the binary oxide layer 1740 covers the side walls 1760s and the bottom surfaces 1760p of the source terminal 1760A and the drain terminal 1760B. In some embodiments, the source terminal 1760A and the drain terminal 1760B are insulated from the underlying semiconductor layer 1730 and the ILD layer 1750 by the binary oxide layer 1740. In some embodiments, the ILD layer 1750 and the gate dielectric layer 1720 are in direct contact with the semiconductor layer 1730. Fig. 17 the binary oxide layers 1740 are arranged between the upper surface 1730t of the semiconductor layer 1730 and the respective lower surfaces of the source and drain terminals 1760A, 1760B.

[0046] Fig. Figure 18 is a schematic three-dimensional view showing a semiconductor device according to some embodiments of the disclosure. Fig. 19 and Fig. Figure 20 shows schematic cross-sectional views along lines AA and BB, which depict the semiconductor device of Fig. 18 according to some embodiments of the disclosure.

[0047] With reference to Fig. In some embodiments, the semiconductor device structure 46 comprises a semiconductor layer 1830 and a binary oxide layer 1840, which are arranged on and around the semiconductor layer 1830. Fig. 18, Fig. 19 and Fig. 20 shows that the binary oxide layer 1840 surrounds and covers not only the upper surface 1830t, but also two opposite side faces 1830s of the semiconductor layer 1830. That is, the binary oxide layer 1840 covers at least three sides of the semiconductor layer 1830. With reference to Fig. 18 and Fig. 19 is a gate structure 1800 comprising a gate layer 1810 and a gate dielectric layer 1820 arranged on the top and two opposite sides of the stacked structure of the binary oxide layer 1840 and the semiconductor layer 1830, and surrounding it. In some embodiments, the gate structure 1800 can be shaped like an inverted U-shape that wraps around the binary oxide layer 1840 and the semiconductor layer 1830. In some embodiments, the semiconductor device structure 46 has source and drain terminals 1860 that are arranged directly on the binary oxide layer 1840, and the source and drain terminals 1860 can each be shaped like an inverted U-shape that wraps around the binary oxide layer 1840 and the semiconductor layer 1830.In some embodiments, the source and drain terminals 1860 are located on two opposite sides of the gate structure 1800 and are separated from the gate structure 1800 by an interlayer dielectric layer (ILD layer) (not shown). Fig. 18, Fig. 19 and Fig. For simplicity, the ILD layer is not shown in Figure 20. In some embodiments, the source and drain terminals 1860 may further comprise a seed layer and / or an adhesion / barrier layer. In some embodiments, the binary oxide layer 1840 is in direct contact with the source and drain terminals 1860 and in direct contact with the gate dielectric layer 1820. That is, the binary oxide layer 1840 is arranged between the semiconductor layer 1830 and the gate structure 1800 and the source and drain terminals 1860. In some embodiments, the semiconductor device structure 46 has a dual-gate transistor structure.

[0048] Fig. Figure 21 is a schematic three-dimensional view showing a semiconductor device according to some embodiments of the disclosure. Fig. 22 and Fig. Figure 23 shows schematic cross-sectional views along lines AA and BB, which depict the semiconductor device of Fig. 21 according to some embodiments of the disclosure.

[0049] The in Fig. The structure shown in Figure 21 is similar, but differs from the one in Figure 21. Fig. 18 structure shown, the main structural difference being that the location of the binary oxide layer 2040 in the semiconductor device structure 48, as in Fig. As shown in point 18, it lies. Referring to Fig. 21 and Fig. In some embodiments, the semiconductor device structure 48 comprises a gate structure 2000 consisting of a gate layer 2010 and a gate dielectric layer 2020, which are stacked on a semiconductor layer 2030. In some embodiments, as in Fig. As shown in Figure 21, the gate structure 2000 is arranged on the top and the two opposite sides of the semiconductor layer 2030 and surrounds it. Fig. Figure 21 shows that the gate structure 2000 can be shaped like an inverted U-shape that wraps around the semiconductor layer 2030. In some embodiments, the structure has 48 source and drain terminals 2060 arranged on the semiconductor layer 2030, with a binary oxide layer 2040 located between them. In some embodiments, the source and drain terminals 2060 are located on two opposite sides of the gate structure 2000 and are separated from the gate structure 2000 by an interlayer dielectric layer (ILD layer) (not shown). Fig. 21, Fig. 22 and Fig. Figure 23 does not show the ILD layer for the sake of simplicity. In some embodiments, the source and drain terminals 2060 can each be formed like an inverted U-shape, which wraps around the semiconductor layer 2030. Fig. 21, Fig. 22 and Fig. 23 Each of the source and drain terminals 2060 is surrounded by the binary oxide layer 2040. In some embodiments, either the source terminal or the drain terminal 2060 is encapsulated and surrounded by the binary oxide layer 2040, and the binary oxide layer 2040 covers the side walls and bottom surfaces of the source and drain terminals 2060 without covering the top surfaces 2060t of the source and drain terminals 2060. In some embodiments, the source and drain terminals 2060 are insulated from the semiconductor layer 2030 by the binary oxide layer 2040. In some embodiments, the gate dielectric layer 2020 is in direct contact with the semiconductor layer 2030. Fig. 23 the binary oxide layers 2040 are arranged between the semiconductor layer 2030 and the respective source and drain terminals 2060.

[0050] In the exemplary embodiments, the formation of the binary oxide layer between the channel layer (e.g., semiconductor layer) and the source and drain terminals leads to a lower contact resistance between the channel layer and the source and drain terminals. Overall, the performance of the semiconductor device is improved.

[0051] In these embodiments, the binary oxide layer and the semiconductor channel layer can be formed in the same chamber in a self-aligning manner, and the binary oxide layer, which forms as a cover layer over the entire outer surface of the semiconductor layer, can be adequately controlled. In some embodiments, the cover layer formed over the semiconductor layer modulates the surface properties of the semiconductor layer and reduces the contact resistance between the semiconductor layer and the source and drain terminals.

[0052] In other embodiments, the binary oxide layer and the semiconductor channel layer can be formed separately, and the binary oxide layer is formed between the contact surfaces of the source and drain terminals and the semiconductor layer, and the contact resistance between the semiconductor layer and the source and drain terminals can be reduced.

[0053] In some embodiments of the present disclosure, a semiconductor device is described. The semiconductor device comprises a semiconductor layer and a gate structure located on the semiconductor layer. The semiconductor device has source and drain terminals arranged on the semiconductor layer and a binary oxide layer arranged between the semiconductor layer and the source and drain terminals, connecting them together.

[0054] In some embodiments of the present disclosure, a semiconductor device is described. The semiconductor device comprises a semiconductor channel layer, a gate layer arranged above the semiconductor channel layer, and a gate dielectric layer arranged between the gate layer and the semiconductor channel layer. The semiconductor device has a source and a drain arranged on the semiconductor channel layer, and a binary oxide layer arranged between the semiconductor channel layer and the source, and between the semiconductor channel layer and the drain.

[0055] In some embodiments of the present disclosure, a method for forming a semiconductor device is described. A semiconductor material layer and a binary oxide material layer are formed on the semiconductor material layer. The semiconductor material layer and the binary material layer are structured into a semiconductor layer and a binary oxide layer. A gate structure is formed over the semiconductor layer and the binary oxide layer. An insulating layer is formed over the gate structure and the semiconductor layer and the binary oxide layer. Source and drain terminals are formed on the binary oxide layer.

Claims

[1] comprising a semiconductor device: a semiconductor layer (1830); a gate structure (1810, 1820) that is arranged on the semiconductor layer (1830); Source and drain terminals (1860) arranged on the semiconductor layer (1830); and a binary oxide layer (1840) that is positioned between and connects the semiconductor layer (1830) and the source and drain terminals (1860), wherein the source and drain terminals (1860) are arranged on two opposite sides of the gate structure (1810, 1820) and the gate structure (1810, 1820) and the source and drain terminals (1860) surround the semiconductor layer (1830), wherein the binary oxide layer (1840) extends over three sides of the semiconductor layer (1830) and the source and drain terminals (1860) are in contact with the binary oxide layer (1840). [2] Semiconductor device according to claim 1, wherein the gate structure (1810, 1820) is located on a first side of the semiconductor layer (1830), while the source and drain terminals (1860) are located on a second side of the semiconductor layer (1830) opposite the first side. [3] Semiconductor device according to claim 2, wherein the binary oxide layer (1840) extends on an upper surface of the semiconductor layer (1830) and the source and drain terminals (1860) are in contact with the binary oxide layer (1840). [4] Semiconductor device according to claim 2, wherein the binary oxide layer (1840) surrounds the source and drain terminals (1860) and contacts the lower surfaces and side walls of the source and drain terminals (1860). [5] Semiconductor device according to claim 1, wherein the gate structure (1810, 1820) and the source and drain terminals (1860) are located on the same side of the semiconductor layer (1830) and the source and drain terminals (1860) are located on two opposite sides of the gate structure (1810, 1820). [6] Semiconductor device according to claim 5, wherein the binary oxide layer (1840) extends on an upper surface of the semiconductor layer (1830) and the source and drain terminals (1860) are in contact with the binary oxide layer (1840). [7] Semiconductor device according to claim 5, wherein the binary oxide layer (1840) surrounds the source and drain terminals (1860) and contacts the lower surfaces and side walls of the source and drain terminals (1860). [8] Semiconductor device according to one of the preceding claims, wherein the binary oxide layer (1840) is wound around and contacts the lower surfaces and side walls of the source and drain terminals (1860) and exposes the upper surfaces of the source and drain terminals (1860). [9] comprising a semiconductor device: a semiconductor channel layer (1830); a gate layer (1810) arranged above the semiconductor channel layer (1830); a gate dielectric layer (1820) arranged between the gate layer (1810) and the semiconductor channel layer (1830); a source (1860) and a drain (1860) arranged on the semiconductor channel layer (1830); and a binary oxide layer (1840) that is positioned between the semiconductor channel layer (1830) and the source (1860) and the drain (1860), wherein a material of the binary oxide layer (1840) contains gallium oxide, indium oxide, zinc oxide, titanium oxide, aluminum oxide, a mixture thereof or a combination thereof, wherein the binary oxide layer (1840) extends over and touches three sides of the semiconductor channel layer (1830). [10] Semiconductor device according to claim 9, wherein the binary oxide layer (1840) extends on an upper surface of the semiconductor channel layer (1830). [11] Method for manufacturing a semiconductor device comprising: Forming a semiconductor material layer (330) and forming a binary oxide material layer (340) on the semiconductor material layer (330); Structuring the semiconductor material layer (330) and the binary oxide material layer (340) into a semiconductor layer (331) and a binary oxide layer (341); Forming a gate structure (310) over the semiconductor layer (331) and the binary oxide layer (341); Forming an insulating layer (350) over the gate structure (310) and the semiconductor layer (331) and the binary oxide layer (341); and Formation of source and drain terminals (360, 362) on the binary oxide layer (341). [12] The method of claim 11, further comprising: Forming contact openings in the insulating layer (350) that expose the binary oxide layer (341) before the source and drain terminals (360, 362) are formed. [13] Method according to claim 11 or 12, wherein the semiconductor material layer (330) and the binary oxide material layer (340) are continuously formed in the same deposition process. [14] Method according to any one of the preceding claims 11 to 13, wherein the binary oxide material layer (340) is formed covering the semiconductor material layer (330) and the binary oxide material layer (340) covers an upper surface of the semiconductor material layer (330). [15] Method according to any one of the preceding claims 11 to 13, wherein the binary oxide material layer (340) is formed covering the semiconductor material layer (330) and the binary oxide material layer (340) covers an upper surface and two opposite side walls of the semiconductor material layer (330).

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