Semiconductor devices with ferroelectric storage and their manufacturing processes

Abstract

comprising a semiconductor device: a gate stack over a semiconductor substrate; a capacitor (113a) across the gate stack, wherein the capacitor (113a) comprises: - a first electrode (106a) extending along an upper surface of the gate stack, wherein the first electrode is U-shaped; - a first ferroelectric layer (110a) over the first electrode; and - a second electrode (112a) above the first ferroelectric layer, wherein an upper surface of the second electrode is flush with an upper surface of the first ferroelectric layer, wherein the upper surface of the first ferroelectric layer and the upper surface of the second electrode are located further away from the semiconductor substrate than a top surface of the first electrode, wherein the first electrode has a first section extending along the gate structure and a second section extending along a side face of a first dielectric layer (104) extending along the upper surface of the gate stack, wherein the first section and the second section are discontinuous, wherein an upper surface of the first dielectric layer (104) is flush with the upper surface of the first ferroelectric layer and the upper surface of the second electrode.

Description

BACKGROUND

[0001] Semiconductor memory is used in integrated circuits for electronic applications, such as radios, televisions, mobile phones, and personal computers. Semiconductor memory includes two main categories: volatile memory and non-volatile memory. Volatile memory includes random-access memory (RAM), which can be further divided into two subcategories: static random-access memory (SRAM) and dynamic random-access memory (DRAM). Both SRAM and DRAM are volatile, meaning they lose stored information when power is removed.

[0002] On the other hand, non-volatile memories can retain the data stored on them. One type of non-volatile semiconductor memory is ferroelectric random access memory (FERAM or FRAM). The advantages of FERAM include fast read / write speeds and small size.

[0003] US 2020 / 0 013 871 A1 relates to a semiconductor device with a negative capacitance using a ferroelectric material. US 2018 / 0 006 129 A1 relates to a transistor with a ferroelectric material and a related manufacturing method. US 2018 / 0 151 745 A1 relates to manufacturing methods for integrated semiconductor circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced as desired for clarity of explanation. Fig. 1 shows an example of a FinFET in a three-dimensional view according to some embodiments. Fig. 2 to 32B are cross-sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments and examples of implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, but may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated throughout the various examples of the present disclosure.This repetition is for simplicity and clarity and does not necessarily prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0006] Furthermore, for ease of description, spatially relative terms such as "below," "below," "downward," "above," "above," "upward," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. These spatially relative terms are intended to encompass other orientations of the device during use or operation in addition to the orientation illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0007] Various embodiments provide a one-transistor-one-capacitor (1T-1C) memory cell having a capacitor formed over a gate of a transistor, and a method of fabricating the same. In some embodiments, the capacitor may include a ferroelectric (FE) material, and the memory cell may be a ferroelectric random access memory (FERAM) cell. The capacitor may be formed by forming a trench over the gate, forming spacers in the trench, depositing a bottom electrode layer in the trench, patterning the bottom electrode layer such that top surfaces of the bottom electrode layer are below top surfaces of the spacers, depositing a storage film (e.g., a ferroelectric material) over the bottom electrode layer, and depositing a top electrode layer over the storage film.A contact is then formed extending to the top electrode layer, with the storage film sandwiched between the bottom electrode layer and the contact. Patterning the bottom electrode layer before depositing the storage film and the top electrode layer over the bottom electrode layer isolates the bottom electrode from the contact, preventing a shunt between the contact and the bottom electrode layer. This reduces defects and improves device performance.

[0008] Fig. 1 shows a three-dimensional view of an example of fin field-effect transistors (FinFETs) according to some embodiments. The FinFETs include fins 55 on a substrate 50 (e.g., a semiconductor substrate). Shallow trench isolation regions (STI) 58 are disposed in the substrate 50, and the fins 55 protrude above and between adjacent STI regions 58. Although the STI regions 58 are described and illustrated as being separate from the substrate 50, the term "substrate" as used herein may refer only to the semiconductor substrate or to a semiconductor substrate including the STI regions. Furthermore, although the fins 55 are illustrated as being discrete materials continuous with the substrate 50, the fins 55 and / or the substrate 50 may include a single material or multiple materials.In this context, the fins 55 refer to the section extending between the adjacent STI areas 58.

[0009] The gate dielectric layers 100 lie along sidewalls and over top surfaces of the fins 55, and the gate electrodes 102 lie over the gate dielectric layers 100. Epitaxial source / drain regions 92 are arranged on opposite sides of the fins 55 with respect to the gate dielectric layers 100 and the gate electrodes 102. Fig. 1 further shows reference cross-sections used in later drawings. Cross-section AA' runs along a longitudinal axis of a gate electrode 102 and, for example, in a direction perpendicular to the direction of current flow between the source / drain regions 92 of the FinFETs. Cross-section BB' runs perpendicular to cross-section AA' and runs along a longitudinal axis of a fin 55 and, for example, in a direction perpendicular to current flow between the epitaxial source / drain regions 92 of the FinFETs. Cross-section CC' is parallel to cross-section AA' and extends through the source / drain regions 92 of the FinFETs. Subsequent drawings refer to these reference cross-sections for the sake of clarity.

[0010] Some of the embodiments discussed herein are discussed in the context of FinFETs fabricated using a gate-last process. In other embodiments, a gate-first process may be used. Furthermore, some embodiments contemplate aspects used in planar devices such as planar FETs, nanostructured field-effect transistors (e.g., nanosheets, nanowires, gate-all-around, or the like), or the like.

[0011] Fig. 2 to 32B are cross-sectional views of intermediate stages in the fabrication of memory devices according to some embodiments. Fig. 2 to 5 are along the reference cross section AA' as in Fig. 1 shown in an N-type region 50N and a P-type region 50P. Fig. 6A, Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A, Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A, Fig. 26A, Fig. 27A, Fig. 28A, Fig. 29A, Fig. 30A, Fig. 31A and Fig. 32A are along the reference cross-section AA' from Fig. 1 either in the N-type region 50N or the P-type region 50P. Fig. 6B, Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 14C, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 21B, Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B, Fig. 26B, Fig. 27B, Fig. 28B, Fig. 29B, Fig. 30B, Fig. 31B and Fig. 32B are along the reference cross section BB' as in Fig. 1 shown. Fig. 7C, Fig. 8C, Fig. 9C, Fig. 10C and Fig. 10D are along the reference cross section CC' as in Fig. 1 shown.

[0012] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate such as a bulk semiconductor, an SOI (silicon on insulator substrate), or the like, which may be doped (e.g., with a P-type or an N-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates such as a multilayer substrate or a gradient substrate may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon, germanium, a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide, or combinations thereof.

[0013] The substrate 50 includes an N-type region 50N and a P-type region 50P. The N-type region 50N can be used to form N-type devices such as NMOS transistors, e.g., N-type FinFETs. The P-type region 50P can be used to form P-type devices such as PMOS transistors, e.g., P-type FinFETs. The N-type region 50N can be physically separated from the P-type region 50P (as illustrated by separation line 51), and any number of devices (e.g., other active devices, doped regions, isolation structures, etc.) can be disposed between the N-type region 50N and the P-type region 50P.

[0014] In Fig. 3, fins 55 are formed in the substrate 50. The fins 55 are semiconductor strips. In some embodiments, the fins 55 may be formed in the substrate 50 by etching trenches into the substrate 50. The etching may be any acceptable etching process, such as a reactive ion etch (RIE), a neutral beam etch (NBE), or a combination thereof. The etching may be anisotropic.

[0015] The fins 55 can be patterned by any suitable method. For example, the fins 55 can be patterned by one or more photolithography processes, including double patterning or multiple patterning processes. In general, double patterning or multiple patterning processes combine photolithography with self-aligned processes, which can create structures that have, for example, smaller pitches than those that can be achieved by a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned by a photolithography process. Spacers are formed by a self-aligned process along the patterned sacrificial layer. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 55.In some embodiments, the mask (or other layer) may remain on the fins 55.

[0016] In Fig. 4, STI regions 58 (shallow trench isolation regions) are formed adjacent to the fins 55. The STI regions 58 may be formed by depositing an isolation material (not separately shown) over the substrate 50 and between adjacent fins 55. The isolation material may be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by HDP-CVD (high density plasma chemical vapor deposition), FCVD (flowable chemical vapor deposition) (e.g., CVD-based material deposition in a remote plasma system followed by annealing to convert the deposited material into another material, such as an oxide), or the like, or a combination thereof. Other isolation materials produced by any acceptable process may also be used.In the illustrated embodiment, the insulating material is silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process may be performed. In some embodiments, the insulating material is formed such that excess insulating material covers the fins 55. The insulating material may comprise a single layer or utilize multiple layers. For example, in some embodiments, a liner (not separately shown) may first be formed along surfaces of the substrate 50 and the fins 55. Thereafter, a fill material may be formed over the liner as described above.

[0017] Subsequently, a removal process is applied to the insulation material to remove excess insulation material over the fins 55. In some embodiments, a planarization process, such as a chemical mechanical polishing (CMP) process, an etch-back process, combinations thereof, or the like, may be used. The planarization process may planarize the insulation material and the fins 55. The planarization process exposes the fins 55 so that top surfaces of the fins 55 and the insulation material are flat after completion of the planarization process.

[0018] The insulating material is then cut out to form the STI areas 58 as shown in Fig. 4. The insulating material is recessed so that upper portions of the fins 55 and the substrate 50 protrude between adjacent STI regions 58. Further, the upper surfaces of the STI regions 58 may include flat surfaces as shown, convex surfaces, concave surfaces (e.g., bevels), or a combination thereof. The upper surfaces of the STI regions 58 may be shaped to be flat, convex, and / or concave by a suitable etch. The STI regions 58 may be recessed by a suitable etching process, for example, one that is selective for the material of the insulating material (e.g., the material of the insulating material etches faster than the material of the fins 55 and the substrate 50). For example, oxide removal with, for example, dilute hydrofluoric acid (dHF) may be used.

[0019] The process as with reference to Fig. 2 to 4 is merely exemplary of how the fins 55 may be formed. In some embodiments, the fins 55 may be formed by an epitaxial growth process. For example, a dielectric layer may be formed over a top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the homoepitaxial structures protrude from the dielectric layer and form fins. Furthermore, in some embodiments, heteroepitaxial structures may be used for the fins 55. For example, the fins 55 may Fig. 4, and a material other than fins 55 may be epitaxially grown over recessed fins 55. In such embodiments, fins 55 include both the recessed material and the epitaxially grown material disposed over the recessed material. In some embodiments, a dielectric layer may be formed over a top surface of substrate 50, and trenches may be etched through the dielectric layer. Heteroepitaxial structures may then be epitaxially grown in the trenches using a material other than substrate 50, and the dielectric layer may be recessed such that the heteroepitaxial structures protrude from the dielectric layer and form fins 55.In some embodiments where homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be doped in-situ during growth, which may eliminate the need for prior and subsequent implants, although in-situ and implant doping may be used in combination.

[0020] Furthermore, it may be advantageous to epitaxially grow a material in the N-type region 50N (e.g., an NMOS region) that is different from the material in the P-type region 50P (e.g., a PMOS region). In some embodiments, upper portions of the fins 55 may be formed from silicon germanium (SixGe1-x, where x may range from 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. Available materials for forming III-V compound semiconductors include, for example, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0021] Furthermore, Fig. 4 Suitable wells (not separately shown) may be formed in the fins 55 and / or the substrate 50. In some embodiments, a P-well may be formed in the N-type region 50N and an N-well in the P-type region 50P. In some embodiments, a P-well or an N-well is formed in both the N-type region 50N and the P-type region 50P.

[0022] In embodiments with different well types, the various implantation steps for the N-type region 50N and the P-type region 50P can be achieved using photoresist or other masks (not separately shown). For example, a photoresist can be formed over the fins 55 and the STI regions 58 in the N-type region 50N. The photoresist is patterned to expose the P-type region 50P of the substrate 50, e.g., a PMOS region. The photoresist can be formed using a spin-on technique and patterned using acceptable photolithography techniques. After the photoresist is patterned, an N-type impurity is implanted into the P-type region 50P, and the photoresist can serve as a mask to substantially prevent N-type impurities from being implanted into the N-type region 50N, such as an NMOS region.The N-type impurities may be phosphorus, arsenic, antimony or the like, which range to a concentration equal to or less than 1 10. 18 atoms / cm 3 implanted, such as between about 1·10 16 atoms / cm 3 and about 1·10 18 atoms / cm 3 After implantation, the photoresist is removed, e.g., by an acceptable ashing process.

[0023] After implanting the P-type region 50P, a photoresist is formed over the fins 55 and the STI regions 58 in the P-type region 50P. The photoresist is patterned to expose the N-type region 50N of the substrate 50, e.g., the NMOS region. The photoresist may be formed by a spin-on technique and patterned by acceptable photolithography techniques. After the photoresist is patterned, an implantation of P-type impurities may be performed into the N-type region 50N, and the photoresist may serve as a mask to substantially prevent P-type impurities from being implanted into the P-type region 50P, such as the PMOS region. The P-type impurities may be boron, boron fluoride, indium, or the like, which may be introduced into the region to a concentration of equal to or less than 1 10 18 atoms / cm 3 implanted, such as between about 1·10 16 atoms / cm 3and about 1·10 18 atoms / cm 3 After implantation, the photoresist can be removed, e.g., by an acceptable ashing process.

[0024] After the implantation of the N-type region 50N and the P-type region 50P, an annealing process may be performed to repair implant damage and activate the implanted P-type and / or N-type impurities. In some embodiments, the grown materials of the epitaxial fins may be doped in-situ during growth, which may eliminate the need for implantation, although in-situ and implant doping may be used in combination.

[0025] In Fig. 5, dummy dielectric layers 60 are formed on the fins 55. The dummy dielectric layers 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown by acceptable techniques. A dummy gate layer 62 is formed over the dummy dielectric layers 60, and a mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 may be deposited over the dummy dielectric layers 60 and then planarized, e.g., by a CMP. The mask layer 64 may be deposited over the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material and may be selected from a group including: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals.The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material. The dummy gate layer 62 may be formed from other materials that have high etch selectivity toward etching isolation regions, e.g., toward the STI regions 58 and / or the dummy dielectric layers 60. The mask layer 64 may include one or more layers of, e.g., silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over the N-type region 50N and the P-type region 50P. Note that the dummy dielectric layers 60 are shown covering only the fins 55 for illustrative purposes only.In some embodiments, the dummy dielectric layers 60 may be deposited such that the dummy dielectric layers 60 cover the STI regions 58 and extend over the STI regions 58 and between the dummy gate layer 62 and the STI regions 58.

[0026] Fig. 6A to 37B illustrate various additional steps in fabricating devices according to embodiments. Fig. 8A to 37B show features in the N-type region 50N or in the P-type region 50P. For example, the features shown in Fig. The structures shown in Figures 6A to 37B may be applicable to both the N-type region 50N and the P-type region 50P. Differences (if any) in the structures of the N-type region 50N and the P-type region 50P will be described in the specification with reference to the respective drawings.

[0027] In Fig. 6A and Fig. 6B, the mask layer 64 (see Fig. 5) be patterned using acceptable photolithography and etching techniques to form masks 74. An acceptable etching process may be used to transfer the pattern of the masks 74 to the dummy gate layer 62 to form dummy gates 72. In some embodiments, the pattern of the masks 74 may also be transferred to the dummy dielectric layers 60. The dummy gates 72 cover the respective channel regions 68 of the fins 55. The pattern of the masks 74 may be used to physically separate each of the dummy gates 72 from adjacent dummy gates 72. The dummy gates 72 may further have a longitudinal direction substantially perpendicular to the longitudinal direction of the respective fins 55. The dummy dielectric layers 60, the dummy gates 72, and the masks 74 may collectively be referred to as a dummy gate stack.

[0028] In Fig. 7A to 7C, a first spacer layer 80 and a second spacer layer 82 are formed over the Fig. 6A and Fig. 6B shown structures are formed. In Fig. 7A to 7C, the first spacer layer 80 is formed on top surfaces of the STI regions 58, top surfaces and sidewalls of the fins 55 and the masks 74, and sidewalls of the dummy gates 72 and the dummy dielectric layers 60. The second spacer layer 82 is deposited over the first spacer layer 80. The first spacer layer 80 may be formed by thermal oxidation or deposited by CVD, ALD, or the like. The first spacer layer 80 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like. The second spacer layer 82 may be deposited by CVD, ALD, or the like. The second spacer layer 82 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0029] In Fig. 8A to 8C, the first spacer layer 80 and the second spacer layer 82 are etched to form first spacers 81 and second spacers 83. The first spacer layer 80 and the second spacer layer 82 may be etched by a suitable etching process, such as an anisotropic etching process (e.g., a dry etching process) or the like. The first spacers 81 and the second spacers 83 may be arranged on sidewalls of the fins 55, the dummy dielectric layers 60, the dummy gates 72, and the masks 74. Due to the etching processes for etching the first spacer layer 80 and the second spacer layer 82 and due to the different heights between the fins 55 and the dummy gate stacks, the first spacers 81 and the second spacers 83 may have different heights adjacent to the fins 55 and the dummy gate stacks. In particular, as in Fig. 8A to 8C, in some embodiments, the first spacers 81 and the second spacers 83 partially extend to the sidewalls of the fins 55 and the dummy gate stacks. In some embodiments, the first spacers 81 and the second spacers 83 may extend to upper surfaces of the dummy gate stacks.

[0030] After the first spacers 81 and the second spacers 83 are formed, implantations for lightly doped source / drain regions (not separately shown) may be performed. In embodiments with different device types, similar to the implantations described above with reference to Fig. 4, a mask, such as a photoresist, may be formed over the N-type region 50N while exposing the P-type region 50P, and impurities of the appropriate type (e.g., P-type) may be implanted into the exposed fins 55 and into the substrate 50 in the P-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the P-type region 50P while exposing the N-type region 50N, and impurities of the appropriate type (e.g., N-type) may be implanted into the exposed fins 55 and into the substrate 50 in the N-type region 50N. The mask may then be removed. The N-type impurities may be any of the aforementioned N-type impurities, and the P-type impurities may be any of the aforementioned P-type impurities. The lightly doped source / drain regions may have an impurity concentration of about 1 10 15 atoms / cm3 up to about 1·10 19 atoms / cm 3 An annealing process can be used to repair implantation damage and activate the implanted impurities.

[0031] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. However, other processes and sequences may be used. For example, fewer or additional spacers may be used, a different sequence of steps may be used (e.g., the first spacers 81 may be formed before the formation of the second spacers 83, additional spacers may be formed and removed, and / or the like). Furthermore, N-type and P-type devices may be formed with different structures and by different steps.

[0032] In Fig. 9A to 9C, first recesses 86 are formed in the fins 55 and the substrate 50. As in Fig. 9C, upper surfaces of the STI regions 58 may be flush with upper surfaces of the substrate 50. The substrate 50 may be etched so that lower surfaces of the first recesses 86 are disposed above or below the upper surfaces of the STI regions 58. The first recesses 86 may be formed by etching the fins 55 and the substrate 50 using an anisotropic etching process such as RIE, NBE, or the like. The first spacers 81, the second spacers 83, and the masks 74 mask portions of the fins 55 and the substrate 50 during the etching processes used to form the first recesses 86. A single etch process or multiple etch processes may be used to form the first recesses 86. Timed etch processes may be used to stop the etching of the first recesses 86 after the first recesses 86 reach a desired depth.

[0033] In Fig. 10A-10D, epitaxial source / drain regions 92 are formed in the first recesses 86 to apply stress to the channel regions 68 of the fins 55, thereby improving performance. As shown in Fig. 10B, the epitaxial source / drain regions 92 are formed in the first recesses 86 such that each dummy gate 72 is disposed between adjacent pairs of the epitaxial source / drain regions 92. In some embodiments, the first spacers 81 are used to separate the epitaxial source / drain regions 92 from the dummy gates 72 by an appropriate lateral distance such that the epitaxial source / drain regions 92 do not short to the subsequently formed gates of the resulting FinFETs.

[0034] The epitaxial source / drain regions 92 in the N-type region 50N, e.g., the NMOS region, may be formed by masking the P-type region 50P, e.g., the PMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86. The epitaxial source / drain regions 92 may include any acceptable material suitable for N-type FinFETs. For example, if the fins 55 include silicon, the epitaxial source / drain regions 92 may include materials that exert tensile stress on the fins 55, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 92 may have surfaces raised from corresponding surfaces of the fins 55 and may have facets.

[0035] The epitaxial source / drain regions 92 in the P-type region 50P, e.g., the PMOS region, may be formed by masking the N-type region 50N, e.g., the NMOS region. Then, the epitaxial source / drain regions 92 are epitaxially grown in the first recesses 86. The epitaxial source / drain regions 92 may include any acceptable material suitable for P-type NSFETs. For example, if the fins 55 include silicon, the epitaxial source / drain regions 92 may include materials that exert compressive stress on the fins 55, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 92 may also include surfaces raised from corresponding surfaces of the fins 55 and facets.

[0036] The epitaxial source / drain regions 92, the fins 55, and / or the substrate 50 may be implanted with dopants to form source / drain regions, similar to the method discussed above for forming lightly doped source / drain regions, followed by an annealing process. The source / drain regions may have an impurity concentration of approximately 1 10 19 atoms / cm 3 up to about 1·10 21 atoms / cm 3 The N-type and / or P-type impurities for the source / drain regions may be any of the aforementioned impurities. In some embodiments, the epitaxial source / drain regions 92 may be doped in-situ during growth.

[0037] As a result of the epitaxial processes used to form the epitaxial source / drain regions 92 in the N-type region 50N and in the P-type region 50P, upper surfaces of the epitaxial source / drain regions 92 have facets that extend laterally outward beyond the sidewalls of the fins 55. In some embodiments, these facets cause adjacent epitaxial source / drain regions 92 of the same FinFET to join together, as shown in Fig. 10C. In some embodiments, adjacent epitaxial source / drain regions 92 remain separated from each other after the epitaxial process is completed, as shown in Fig. 10D. In the embodiments as shown in Fig. 10C and Fig. As shown in Figure 10D, the first spacers 81 may be formed to cover portions of the sidewalls of the fins 55 that extend above the STI regions 58, thereby blocking epitaxial growth. In some embodiments, the spacer etch used to form the first spacers 81 may be configured to remove the spacer material to allow the epitaxially grown region to extend to the surface of the STI region 58.

[0038] The epitaxial source / drain regions 92 may include one or more semiconductor material layers. For example, the epitaxial source / drain regions 92 may include a first semiconductor material layer 92A, a second semiconductor material layer 92B, and a third semiconductor material layer 92C. Any number of semiconductor material layers may be used for the epitaxial source / drain regions 92. Each of the first semiconductor material layer 92A, the second semiconductor material layer 92B, and the third semiconductor material layer 92C may be formed from different semiconductor materials and / or doped with different dopant concentrations. In some embodiments, the first semiconductor material layer 92A may have a lower dopant concentration than the second semiconductor material layer 92B and a higher dopant concentration than the third semiconductor material layer 92C.In embodiments where the epitaxial source / drain regions 92 comprise three semiconductor material layers, the first semiconductor material layer 92A may be deposited, the second semiconductor material layer 92B may be deposited over the first semiconductor material layer 92A, and the third semiconductor material layer 92C may be deposited over the second semiconductor material layer 92B.

[0039] In Fig. 11A and Fig. 11B, a first interlayer dielectric (ILD) 96 is formed over the Fig. 10A and Fig. 10B. The first ILD 96 may be formed from a dielectric material and deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials, fabricated by any acceptable method, may be used. In some embodiments, a contact etch stop layer (CESL) 94 is disposed between the first ILD 96 and the epitaxial source / drain regions 92, the masks 74, and the first spacers 81. The CESL 94 may comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a different etch rate than the material of the overlying first ILD 96.

[0040] In Fig. 12A and Fig. 12B, a planarization process, such as CMP, may be performed to level the top surface of the first ILD 96 with the top surfaces of the dummy gates 72 or the masks 74. The planarization process may also remove the masks 74 on the dummy gates 72 and portions of the first spacers 81 along the sidewalls of the masks 74. After the planarization process, the top surfaces of the dummy gates 72, the first spacers 81, and the first ILD 96 are planar. Thus, the top surfaces of the dummy gates 72 are exposed through the first ILD 96. In some embodiments, the masks 74 may remain. In this case, the planarization process levels the top surface of the first ILD 96 with the top surfaces of the masks 74 and the first spacers 81.

[0041] In Fig. 13A and Fig. 13B, the dummy gates 72 and the masks 74, if present, are removed by one or more etching steps to form second recesses 98. Portions of the dummy dielectric layers 60 in the second recesses 98 may also be removed. In some embodiments, only the dummy gates 72 are removed, and the dummy dielectric layers 60 remain and are exposed through the second recesses 98. In some embodiments, the dummy dielectric layers 60 are removed from the second recesses 98 in a first region of a die (e.g., a core logic region) and remain in the second recesses 98 in a second region of the die (e.g., an I / O region). In some embodiments, the dummy gates 72 are removed by an anisotropic dry etch process.For example, the etching process may comprise a dry etching process using reactant gas(es) that selectively etch the dummy gates 72 at a faster rate than the first ILD 96 or the first spacers 81. Each second recess 98 exposes and / or overlies a channel region 68 of a respective fin 55. Each channel region 68 is disposed between respective adjacent pairs of the epitaxial source / drain regions 92. During removal, the dummy dielectric layer 60 may be used as an etch stop layer when the dummy gates 72 are etched. Optionally, the dummy dielectric layer 60 may then be removed after the dummy gates 72 are removed.

[0042] In Fig. 14A to 14C, gate dielectric layers 100 and gate electrodes 102 for replacement gates are formed. Fig. Figure 14C shows a detailed view of area 101 of Fig. 14B. The gate dielectric layers 100 may comprise one or more layers deposited in the second recesses 98, e.g., on top surfaces and sidewalls of the fins 55, on top surfaces and sidewalls of the first spacers 81, and on top surfaces of the second spacers 83. The gate dielectric layers 100 may also be formed on top surfaces of the first ILD 96, the CESL 94, and the STI regions 58. In some embodiments, the gate dielectric layers 100 comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. In some embodiments, the gate dielectric layers 100 comprise an interfacial layer of silicon oxide formed by thermal or chemical oxidation, and an overlying high-k dielectric material, such asa metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layers 100 may include a dielectric layer having a k-value greater than about 7.0. The fabrication processes of the gate dielectric layers 100 may include molecular beam deposition (MBD), ALD, PECVD, and the like. In embodiments in which portions of the dummy dielectric layers 60 remain in the second recesses 98, the gate dielectric layers 100 may include a material of the dummy dielectric layers 60 (e.g., silicon oxide).

[0043] The gate electrodes 102 are deposited over the gate dielectric layers 100 and fill the remaining portions of the second recesses 98. The gate electrodes 102 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although in Fig. 14B, a single-layer gate electrode 102 is shown, the gate electrode 102 may include any number of liner layers 102A, any number of work function matching layers 102B, and a fill material 102C, as shown in Fig. 14C.

[0044] After filling the second recesses 98, a planarization process, such as CMP, may be performed to remove the excess portions of the gate dielectric layers 100 and the gate electrodes 102, wherein the excess portions lie above upper surfaces of the first ILD 96. The remaining portions of the gate electrodes 102 and the gate dielectric layers 100 form replacement gates of the resulting FinFETs. The gate electrodes 102 and the gate dielectric layers 100 may collectively be referred to as gate stacks. The gate stacks may extend along the sidewalls of the channel regions 68 of the fins 55.

[0045] The formation of the gate dielectric layers 100 in the N-type region 50N and in the P-type region 50P may occur simultaneously, such that the gate dielectric layers 100 in each region are formed from the same materials. The formation of the gate electrodes 102 may occur simultaneously, such that the gate electrodes 102 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 100 in each region may be formed by different processes, such that the gate dielectric layers 100 in the N-type region 50N and in the P-type region 50P may be made of different materials. In some embodiments, the gate electrodes 102 in each region may be formed by different processes, such that the gate electrodes 102 in the N-type region 50N and in the P-type region 50P may be made of different materials.Different masking steps can be used to mask and expose appropriate areas when using the different processes.

[0046] The epitaxial source / drain regions 92, the channel regions 68 of the fins 55, and the gate stacks (including the gate dielectric layers 100 and the gate electrodes 102) may be collectively referred to as transistor structures 109. As described below with reference to Fig. As explained in Figures 15A through 32B, portions of the gate stacks may be replaced with capacitors to form 1T-1C memory cells (e.g., FERAM memory cells). Although the transistor structures 109 are described as including FinFETs, other embodiments may include transistor structures 109 that include other types of transistors (e.g., planar FETs, nano-FETs, thin-film transistors (TFTs), or the like).

[0047] In Fig. 15A and Fig. 15B, the gate stacks (including the gate dielectric layers 100 and the gate electrodes 102) are recessed such that third recesses 103 are formed directly above the gate stack and between opposing portions of the first spacers 81. The gate stacks may be recessed by an etching process, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), multiple processes or combinations thereof, or the like. The etching process may be an etching process that is selective to the material of the gate dielectric layers 100 and the gate electrodes 102 (e.g., the materials of the gate dielectric layers 100 and the gate electrodes 102 are etched at a faster rate than the materials of the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83).Thus, the gate dielectric layers 100 and the gate electrodes 102 may be etched to form the third recesses 103, while the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 remain relatively unetched. The third recesses 103 may have heights H1 of about 5 nm to about 50 nm.

[0048] In Fig. 16A and Fig. 16B, a first dielectric layer 104 is formed in the third recesses 103 above the gate stacks. The first dielectric layer 104 may be deposited by any suitable method, such as CVD, ALD, or the like. The first dielectric layer 104 may include silicon oxide, silicon nitride, or the like. After filling the third recesses 103, a planarization process, such as CMP, may be performed to remove excess portions of the first dielectric layer 104, which excess portions overlie upper surfaces of the first ILD 96. Thus, the upper surfaces of the first dielectric layer 104, the first spacers 81, the second spacers 83, the CESL 94, and the first ILD 96 may be planar with each other. The first dielectric layer 104 may have heights H1 of about 5 nm to about 50 nm.

[0049] In Fig. 17A and Fig. 17B, ​​fourth recesses 105 are patterned through the first dielectric layer 104. The fourth recesses 105 may be patterned in the first dielectric layer 104 by a combination of photolithography and etching. The etching may be any acceptable etching process, such as wet or dry etching, RIE, NBE, or a combination thereof. The etching may be anisotropic. The fourth recesses 105 may be arranged between opposing sidewalls of the first dielectric layer 104. The fourth recesses 105 may expose upper surfaces of the gate electrodes 102. In some embodiments, the fourth recesses 105 may also expose upper surfaces of the gate dielectric layers 100.

[0050] In Fig. 18A and Fig. 18B, a first electrode layer 106 and a first hard mask layer 108 are formed in the fourth recesses 105 and extend over the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The first electrode layer 106 may be deposited by a conformal deposition process, such as CVD, ALD, or the like. The first electrode layer 106 may be a conductive material, such as titanium nitride (TiN), ruthenium (Ru), tantalum (Ta), titanium (Ti), aluminum (Al), tungsten (W), combinations thereof, or the like. The first electrode layer 106 may have a thickness of about 1 nm to about 15 nm. The first hard mask layer 108 may be deposited by spin-on coating or the like. The first hard mask layer 108 may include a polymer material such as poly(methyl)acrylate, poly(maleimide), novolacs, poly(ether), combinations thereof, or the like.In some embodiments, the first hard mask layer 108 may be a BARC (bottom anti-reflective coating material).

[0051] In Fig. 19A and Fig. 19B, the first hard mask layer 108 and the first electrode layer 106 are etched. The first hard mask layer 108 and the first electrode layer 106 may be etched by one or more etching processes, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), combinations thereof, or the like. In some embodiments, the first hard mask layer 108 may be etched by a first etching process to expose top portions and sidewall portions of the first electrode layer 106. The first electrode layer 106 may then be etched by a second etching process using the first hard mask layer 108 as a mask. In some embodiments, the first etching process and the second etching process may be isotropic etching processes. In some embodiments, the first electrode layer 106 and the first hard mask layer 108 may be etched simultaneously.

[0052] After etching the first hard mask layer 108 and the first electrode layer 106, upper surfaces of the first hard mask layer 108 and the first electrode layer 106 are arranged below the upper surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81 and the second spacers 83, as shown in Fig. 19A and Fig. 19B. Furthermore, the upper surfaces of the first electrode layer 106 may be arranged below the upper surfaces of the first hard mask layer 108. The upper surfaces of the first electrode layer 106 may be straight and inclined, as shown in Fig. 19A and Fig. 19B; in some embodiments, the upper surfaces of the first electrode layer 106 may also be horizontal, curved, or the like. Etching the first electrode layer 106 such that the upper surfaces of the first electrode layer 106 are below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 helps to isolate the first electrode layer 106 from subsequently formed contacts (such as the contacts 116 as described below with reference to Fig. 23A and Fig. 23B), which prevents shunting, reduces device defects, and improves device performance. Furthermore, the first hard mask layer 108 protects sidewall portions and bottom portions of the first electrode layer 106 from etching, so that the first electrode layer 106 can be used as a bottom electrode in a later-finished FE capacitor. As shown in Fig. 19A and Fig. 19B, the first electrode layer 106 may be U-shaped, which may increase the capacitance (e.g., the capacitor area) of a subsequently formed capacitor.

[0053] In Fig. 20A and Fig. 20B, the first hard mask layer 108 is removed, and a storage film 110 and a second electrode layer 112 are formed over the first electrode layer 106, the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The first hard mask layer 108 may be removed by plasma ashing, an etching process, such as an isotropic or anisotropic etching process, or the like.

[0054] The storage film 110 can be deposited by CVD, ALD, or the like. The storage film 110 can contain a material that can switch between two different polarization directions by applying a suitable voltage difference to the storage film 110. The storage film 110 can be a high-k dielectric material. In some embodiments, the memory film 110 includes a ferroelectric material (FE material), such as a metal oxide (e.g., hafnium oxide (HfxOy) or the like), a component metal oxide (e.g., hafnium silicon oxide (HfxSiyOz), hafnium aluminum oxide (HfxAlyOz), hafnium gadolinium oxide (HfxGdyOz), hafnium zirconium oxide (HfxZryOz), hafnium lanthanum oxide (HfxLayOz), hafnium strontium oxide (HfxSryOz), hafnium yttrium oxide (HfxYyOz), strontium titanate (SrTiO3) or the like), a metal oxynitride (e.g., Hafnium oxynitride (HfxOyNz) or the like), multiple layers or combinations thereof or the like.In some embodiments, the memory film 110 may include various ferroelectric materials or different types of memory materials. In some embodiments, the memory film 110 may be a multilayer memory structure comprising a layer of SiNx between two SiOx layers (e.g., an ONO structure). The memory film 110 may have a thickness of about 1 nm to about 20 nm.

[0055] The second electrode layer 112 may be deposited by CVD, ALD, or the like. The second electrode layer 112 may be a conductive material, e.g., titanium nitride (TiN), ruthenium (Ru), tantalum (Ta), titanium (Ti), aluminum (Al), tungsten (W), combinations thereof, or the like. The second electrode layer 112 may have a thickness of about 1 nm to about 15 nm.

[0056] The memory film 110 can be polarized in one of two different directions. The polarization direction can be changed by applying a suitable voltage difference across the memory film 110 and generating a suitable electric field. Depending on a polarization direction of the memory film 110, a threshold voltage of a corresponding FinFET varies, and a digital value (e.g., a 0 or a 1) can be stored. For example, if the memory film 110 has a first electrical polarization direction, the associated transistor can have a relatively low threshold voltage, and if the memory film 110 has a second electrical polarization direction, the associated transistor can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g.,less error-prone) to read the digital value stored in the respective memory cell.

[0057] As in Fig. 20A and Fig. 20B, the storage film 110 may be deposited in contact with top surfaces and sidewalls of the first electrode layer 106, top surfaces and sidewalls of the first dielectric layer 104, and top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. Forming the storage film 110 along top surfaces of the sidewall portions of the first electrode layer 106 separates and insulates the first electrode layer 106 from subsequently formed contacts (such as the contacts 116 as described below with reference to Fig. 23A and Fig. 23B), thus preventing shunting, reducing device errors, and improving device performance.

[0058] In Fig. 21A and Fig. 21B, a planarization process, such as CMP, is performed to level top surfaces of the memory film 110 and the second electrode layer 112 with top surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The planarization process may form capacitors 113 including the first electrode layer 106, the memory film 110, and the second electrode layer 112. After the planarization process, top surfaces of the memory film 110, the second electrode layer 112, the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 become level with each other. The combination of the first electrode layer 106, the storage film 110 and the second electrode layer 112 can act as the capacitors 113 (e.g., FE capacitors) in the finished device.Each of the capacitors 113, including the first electrode layer 106, the memory film 110, and the second electrode layer 112, may be electrically coupled to the metal gate structure (e.g., the gate electrode 102) of an underlying FinFET to form a 1T-1C memory cell (e.g., a FERAM memory cell).

[0059] In Fig. 22A and Fig. 22B, a second ILD 114 is deposited over the first ILD 96, and contacts 116 and contacts 118 are formed in the second ILD 114. In some embodiments, the second ILD 114 is a flowable film formed by FCVD. In some embodiments, the second ILD 114 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method such as CVD, PECVD, or the like.

[0060] Furthermore, Fig. 22A and Fig. 22B Contacts 116 and contacts 118 are formed by the second ILD 114 and the first ILD 96. Openings for the contacts 118 are formed by the first ILD 96 and the second ILD 114, and openings for the contacts 116 are formed by the second ILD 114. The openings may be formed by acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD 114. The remaining lining and conductive material form the contacts 116 and the contacts 118 in the openings.An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain regions 92 and the contacts 118. The contacts 118 are physically and electrically coupled to the epitaxial source / drain regions 92 and may be referred to as source / drain contacts. The contacts 116 are physically and electrically coupled to the second electrode layer 112 and may be referred to as capacitor contacts. The contacts 116 and the contacts 118 may be formed in different processes or formed in the same process. Although the contacts 116 and the contacts 118 are shown in the same cross-sections, it is conceivable that they may be formed in different cross-sections, which may prevent the contacts from shorting out.

[0061] As in Fig. 22A and Fig. 22B, the storage film 110 formed over the first electrode layer 106 can separate the contacts 116 from the first electrode layer 106, even in cases where the contacts 116 are misaligned (as in Fig. 22A and Fig. 22B by the dashed outlines of the contacts 116). For example, the storage film 110 covers the first electrode layer 106 and physically separates it from the contacts 116. This prevents shunting of the contacts 116 through the first electrode layer 106, preventing device failures and improving device performance.

[0062] Fig. 23A to 27B show an embodiment in which a first electrode layer 106a is formed by PVD, rather than by CVD or ALD, as in the embodiment in Fig. 18A to 22B. The steps as in Fig. 2 to 17B can be carried out and discussed before the steps described in Fig. 23A and Fig. 23B. In Fig. 23A and Fig. 23B, the first electrode layer 106a and a first hard mask layer 108a are formed in the fourth recesses 105 (see Fig. 17A and Fig. 17B) and extend over the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81 and the second spacers 83. The first electrode layer 106a may be formed by a less conformal process than that used in the embodiment of Fig. 18A to 22B, such as PVD or the like. The first electrode layer 106a may be a conductive material such as titanium nitride (TiN), ruthenium (Ru), tantalum (Ta), titanium (Ti), aluminum (Al), tungsten (W), combinations thereof, or the like. The first electrode layer 106a may have a thickness of about 1 nm to about 15 nm. The first hard mask layer 108a may be deposited by spin coating or the like. The first hard mask layer 108a may include a polymeric material such as poly(methyl)acrylate, poly(maleimide), novolaks, poly(ethers), combinations thereof, or the like. In some embodiments, the first hard mask layer 108a may be a bottom anti-reflective coating material (BARC).

[0063] As in Fig. 23A and Fig. 23B, the first electrode layer 106a may be non-conformal. For example, a lower portion of the first electrode layer 106a may have a curved surface, sidewall portions of the first electrode layer 106a may have inclined surfaces, and a thickness of the first electrode layer 106a may vary. However, in some embodiments, the lower portion and sidewall portions of the first electrode layer 106a may also have curved or inclined surfaces. Depositing the first electrode layer 106a by PVD may cause inner sidewalls of the first electrode layer 106a to have thicknesses that taper toward the substrate 50, and a lower portion of the first electrode layer 106a extending along the gate electrode 102 to have a greater thickness in the center that decreases toward the edges of the first electrode layer 106a.The portions of the first electrode layer 106a disposed on sidewalls of the first dielectric layer 104 are discontinuous with the portions of the first electrode layer 106a disposed on the top surfaces of the gate stack. Forming the first electrode layer 106a as a discontinuous layer can be used to adjust the capacitance (e.g., the capacitor area) of a subsequently formed capacitor comprising the first electrode layer 106a. This provides greater flexibility for finished devices.

[0064] In Fig. 24A and Fig. 24B, the first hard mask layer 108a and the first electrode layer 106a are etched. The first hard mask layer 108a and the first electrode layer 106a may be etched by one or more etching processes, such as isotropic etching processes (e.g., wet etching processes), anisotropic etching processes (e.g., dry etching processes), combinations thereof, or the like. In some embodiments, the first hard mask layer 108a may be etched by a first etching process to expose top portions and sidewall portions of the first electrode layer 106a. The first electrode layer 106a may then be etched by a second etching process using the first hard mask layer 108a as a mask. In some embodiments, the first etching process and the second etching process may be isotropic etching processes. In some embodiments, the first electrode layer 106a and the first hard mask layer 108a may be etched simultaneously.

[0065] After etching the first hard mask layer 108a and the first electrode layer 106a, upper surfaces of the first hard mask layer 108a and the first electrode layer 106a are arranged under upper surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81 and the second spacers 83, as shown in Fig. 24A and Fig. 24B. Furthermore, the upper surfaces of the first electrode layer 106a may be arranged below the upper surfaces of the first hard mask layer 108a. The upper surfaces of the first electrode layer 106a may be straight and inclined, as shown in Fig. 24A and Fig. 24B; however, in some embodiments, the upper surfaces of the first electrode layer 106a may be horizontal, curved, or the like. Etching the first electrode layer 106a such that the upper surfaces of the first electrode layer 106a are below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 helps to isolate the first electrode layer 106a from subsequently formed contacts (such as the contacts 116a as described below with reference to Fig. 27A and Fig. 27B), which prevents shunting, reduces device defects, and improves device performance. Furthermore, the first hard mask layer 108a protects sidewall portions and bottom portions of the first electrode layer 106a, allowing the first electrode layer 106a to be used as a bottom electrode in a later-completed FE capacitor.

[0066] In Fig. 25A and Fig. 25B, the first hard mask layer 108a is removed, and a storage film 110a and a second electrode layer 112a are formed over the first electrode layer 106a, the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The first hard mask layer 108a may be removed by plasma ashing, an etching process such as an isotropic or anisotropic etching process, or the like.

[0067] The storage film 110a can be deposited by CVD, ALD, or the like. The storage film 110a can contain a material that can switch between two different polarization directions by applying a suitable voltage difference to the storage film 110a. The storage film 110a can be a high-k dielectric material. In some embodiments, the storage film 110a includes a ferroelectric (FE) material, such as a metal oxide (e.g., hafnium oxide (HfxOy) or the like), a component metal oxide (e.g., hafnium silicon oxide (HfxSiyOz), hafnium aluminum oxide (HfxAlYOz), hafnium gadolinium oxide (HfxGdyOz), hafnium zirconium oxide (HfxZryOz), hafnium lanthanum oxide (HfxLayOz), hafnium strontium oxide (HfxSryOz), hafnium yttrium oxide (HfxYyOz), strontium titanate (SrTiO3) or the like), a metal oxynitride (e.g., Hafnium oxynitride (HfxOyNz) or the like), multiple layers or combinations thereof or the like.In some embodiments, the memory film 110a may include various ferroelectric materials or different types of memory materials. In some embodiments, the memory film 110a may be a multilayer memory structure comprising a layer of SiNx between two SiOx layers (e.g., an ONO structure). The memory film 110a may have a thickness of about 1 nm to about 20 nm.

[0068] The second electrode layer 112a may be deposited by CVD, ALD, or the like. The second electrode layer 112a may be a conductive material, e.g., titanium nitride (TiN), ruthenium (Ru), tantalum (Ta), titanium (Ti), aluminum (Al), tungsten (W), combinations thereof, or the like. The second electrode layer 112a may have a thickness of about 1 nm to about 15 nm.

[0069] As in Fig. 25A and Fig. 25B, the storage film 110a may be deposited in contact with top surfaces and sidewalls of the first electrode layer 106a, top surfaces and sidewalls of the first dielectric layer 104, and top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The formation of the storage film 110a along the top surfaces of the sidewall portions of the first electrode layer 106a separates and insulates the first electrode layer 106a from the subsequently formed contacts (such as the contacts 116 as described below with reference to Fig. 27A and Fig. 27B), thereby preventing shunting, reducing device defects, and improving device performance. Furthermore, in embodiments where the first electrode layer 106a is discontinuous, the storage film 110a may be formed in contact with the first dielectric layer 104 between the discontinuous side portions and the bottom portion of the first electrode layer 106a. Forming the storage film 110a between the discontinuous portions of the first electrode layer 106a may isolate the side portions of the first electrode layer 106a from the bottom portions of the first electrode layer 106a, preventing a short circuit between the portions of the first electrode layer 106a.

[0070] In Fig. 26A and Fig. 26B, a planarization process, such as CMP, is performed to level top surfaces of the memory film 110a and the second electrode layer 112a with top surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The planarization process may form capacitors 113a including the first electrode layer 106a, the memory film 110a, and the second electrode layer 112a. After the planarization process, top surfaces of the memory film 110a, the second electrode layer 112a, the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 are level with each other. The combination of the first electrode layer 106a, the memory film 110a and the second electrode layer 112a can act as the capacitors 113a (e.g., FE capacitors) in the finished device.Each of the capacitors 113a including the first electrode layer 106a, the memory film 110a, and the second electrode layer 112a may be electrically coupled to the metal gate structure (e.g., the gate electrode 102) of an underlying FinFET to form a 1T-1C memory cell (e.g., a FERAM memory cell).

[0071] In Fig. 27A and Fig. 27B, a second ILD 114 is deposited over the first ILD 96, and contacts 116 and contacts 118 are formed in the second ILD 114. In some embodiments, the second ILD 114 is a flowable film formed by FCVD. In some embodiments, the second ILD 114 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method, such as CVD, PECVD, or the like.

[0072] In Fig. 27A and Fig. 27B, contacts 116 and contacts 118 are further formed by the second ILD 114 and the first ILD 96. Openings for the contacts 118 are formed by the first ILD 96 and the second ILD 114, and openings for the contacts 116 are formed by the second ILD 114. The openings may be formed by acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD 114.The remaining liner and conductive material form contacts 116 and contacts 118 in the openings. An annealing process may be performed to form a silicide at the interface between epitaxial source / drain regions 92 and contacts 118. Contacts 118 are physically and electrically coupled to epitaxial source / drain regions 92 and may be referred to as source / drain contacts. Contacts 116 are physically and electrically coupled to second electrode layer 112a and may be referred to as capacitor contacts. Contacts 116 and contacts 118 may be formed in different processes or in the same process. Although shown as formed in the same cross-sections, each of contacts 116 and contacts 118 may be formed in different cross-sections, which may prevent the contacts from shorting out.

[0073] As in Fig. 27A and Fig. As shown in Figure 27B, the storage film 110a formed over the first electrode layer 106a can separate the contacts 116 from the first electrode layer 106a. This prevents shunting of the contacts 116 through the first electrode layer 106a, thereby preventing device failures and improving device performance. Furthermore, the sidewall and bottom portions of the first electrode layer 106a are discontinuous, allowing additional control over the capacitance and capacitor size of the capacitors including the first electrode layer 106a, the storage film 110a, and the second electrode layer 112a.

[0074] Fig. 28A to 32B show an embodiment in which a first electrode layer 106b and a first hard mask layer 108b are planarized prior to etching the first electrode layer 106b. The steps as described with reference to Fig. 2 to 18B can be carried out and discussed before the steps as with reference to Fig. 28A and Fig. 28B. In Fig. 28A and Fig. 28B, a planarization process, such as CMP, is performed to level the top surfaces of the first electrode layer 106b and the first hard mask layer 108b with the top surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. After the planarization process, the top surfaces of the first electrode layer 106b, the first hard mask layer 108b, the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 are level with each other.

[0075] In Fig. 29A and Fig. 29B, the first electrode layer 106b is etched. The first electrode layer 106b may be etched by one or more etching processes, such as an isotropic etching process (e.g., a wet etching process), an anisotropic etching process (e.g., a dry etching process), a combination thereof, or the like. The first electrode layer 106b may be etched by an acceptable etching process that is, for example, selective for the material of the first electrode layer 106b (e.g., that etches the material of the first electrode layer 106b at a faster rate than the material of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, the second spacers 83, and the first hard mask layer 108b). As shown in Fig. 29A and Fig. As illustrated in Figure 29B, a portion of the material of the first hard mask layer 108b may be removed by etching the first electrode layer 106b. In some embodiments, the first electrode layer may be etched using an isotropic etch process.

[0076] As in Fig. 29A and Fig. 29B, after etching the first electrode layer, upper surfaces of the first hard mask layer 108b and the first electrode layer 106b may be disposed below the upper surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. In some embodiments, the upper surfaces of the first hard mask layer 108b may be flush with the upper surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The upper surfaces of the first electrode layer 106b may be disposed below the upper surfaces of the first hard mask layer 108b. The upper surfaces of the first electrode layer 106b may be straight and horizontal, as shown in Fig. 29A and Fig. 29B; however, in some embodiments, the upper surfaces of the first electrode layer 106a may be sloped, curved, or the like. Etching the first electrode layer 106b such that the upper surfaces of the first electrode layer 106b are below the upper surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 helps to isolate the first electrode layer 106b from subsequently formed contacts (such as the contacts 116 as described below with reference to Fig. 32A and Fig. 32B), which prevents shunting, reduces device defects, and improves device performance. Furthermore, the first hard mask layer 108b protects sidewall portions and bottom portions of the first electrode layer 106b, allowing the first electrode layer 106b to be used as a bottom electrode in a subsequently completed FE capacitor.

[0077] In Fig. 30A and Fig. 30B, the first hard mask layer 108b is removed, and a storage film 110b and a second electrode layer 112b are formed over the first electrode layer 106b, the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The first hard mask layer 108b may be removed by plasma ashing, an etching process such as an isotropic or anisotropic etching process, or the like. As shown in Fig. 30A and Fig. As shown in Figure 30B, the process used to remove the first hard mask layer 108b may etch the first electrode layer 106b such that the top surfaces of the first electrode layer 106b are straight and sloped. However, in some embodiments, the first hard mask layer 108b may be removed without etching the first electrode layer 106b, such that the top surfaces of the first electrode layer 106b remain straight and horizontal.

[0078] The storage film 110b can be deposited by CVD, ALD, or the like. The storage film 110b can contain a material that can switch between two different polarization directions by applying a suitable voltage difference across the storage film 110b. The storage film 110b can be a high-k dielectric material. In some embodiments, the memory film 110b includes a ferroelectric material (FE material) such as a metal oxide (e.g., hafnium oxide (HfxOy) or the like), a component metal oxide (e.g., hafnium silicon oxide (HfxSiyOz), hafnium aluminum oxide (HfxAlYOz), hafnium gadolinium oxide (HfxGdyOz), hafnium zirconium oxide (HfxZryOz), hafnium lanthanum oxide (HfxLayOz), hafnium strontium oxide (HfxSryOz), hafnium yttrium oxide (HfxYyOz), strontium titanate (SrTiO3) or the like), a metal oxynitride (e.g., Hafnium oxynitride (HfxOyNz) or the like), multiple layers or combinations thereof or the like.In some embodiments, the memory film 110b may include various ferroelectric materials or different types of memory materials. In some embodiments, the memory film 110b may be a multilayer memory structure comprising a layer of SiNx between two SiOx layers (e.g., an ONO structure). The memory film 110b may have a thickness of about 1 nm to about 20 nm.

[0079] The second electrode layer 112b may be deposited by CVD, ALD, or the like. The second electrode layer 112b may be a conductive material, e.g., titanium nitride (TiN), ruthenium (Ru), tantalum (Ta), titanium (Ti), aluminum (Al), tungsten (W), combinations thereof, or the like. The second electrode layer 112b may have a thickness of about 1 nm to about 15 nm.

[0080] As in Fig. 30A and Fig. 30B, the storage film 110b may be deposited in contact with top surfaces and sidewalls of the first electrode layer 106b, top surfaces and sidewalls of the first dielectric layer 104, and top surfaces of the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The formation of the storage film 110b along the top surfaces of the sidewall portions of the first electrode layer 106b separates and insulates the first electrode layer 106b from subsequently formed contacts (such as the contacts 116 as described below with reference to Fig. 32A and Fig. 32B), thus preventing shunting, reducing device errors, and improving device performance.

[0081] In Fig. 31A and Fig. 31B, a planarization process, such as CMP, is performed to level top surfaces of the memory film 110b and the second electrode layer 112b with top surfaces of the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83. The planarization process may form capacitors 113b including the first electrode layer 106b, the memory film 110b, and the second electrode layer 112b. After the planarization process, the top surfaces of the memory film 110b, the second electrode layer 112b, the first dielectric layer 104, the first ILD 96, the CESL 94, the first spacers 81, and the second spacers 83 are level with each other. The combination of the first electrode layer 106b, the memory film 110b and the second electrode layer 112b can act as the capacitors 113b (e.g., FE capacitors) in the finished device.Each of the capacitors 113b, including the first electrode layer 106b, the memory film 110b, and the second electrode layer 112b, may be electrically coupled to the metal gate structure (e.g., the gate electrode 102) of an underlying FinFET to form a 1T-1C memory cell (e.g., a FERAM memory cell).

[0082] In Fig. 32A and Fig. 32B, a second ILD 114 is deposited over the first ILD 96, and contacts 116 and contacts 118 are formed in the second ILD 114. In some embodiments, the second ILD 114 is a flowable film formed by FCVD. In some embodiments, the second ILD 114 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable method such as CVD, PECVD, or the like.

[0083] In Fig. 32A and Fig. 32B, contacts 116 and contacts 118 are further formed by the second ILD 114 and the first ILD 96. Openings for the contacts 118 are formed by the first ILD 96 and the second ILD 114, and openings for the contacts 116 are formed by the second ILD 114. The openings may be formed by acceptable photolithography and etching techniques. A liner, such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD 114.The remaining liner and conductive material form contacts 116 and contacts 118 in the openings. An annealing process may be performed to form a silicide at the interface between epitaxial source / drain regions 92 and contacts 118. Contacts 118 are physically and electrically coupled to epitaxial source / drain regions 92 and may be referred to as source / drain contacts. Contacts 116 are physically and electrically coupled to second electrode layer 112b and may be referred to as capacitor contacts. Contacts 116 and contacts 118 may be formed in different processes or in the same process. Although illustrated as being formed in the same cross-sections, it is conceivable that each of contacts 116 and contacts 118 may be formed in different cross-sections, which may prevent the contacts from shorting out. As shown in FIG. Fig. 32A and Fig.As shown in Figure 32B, the storage film 110b formed over the first electrode layer 106b can separate the contacts 116 from the first electrode layer 106b. This prevents shunting of the contacts 116 by the first electrode layer 106b, preventing device failures and improving device performance.

[0084] Embodiments can achieve various advantages. For example, the first electrode layer is isolated from subsequently formed contacts by forming a first electrode layer in a first dielectric layer over a gate stack, etching back the first electrode layer such that upper surfaces of the first electrode layer lie below upper surfaces of the first dielectric layer, and forming a memory film over the upper surfaces of the first electrode layer. This prevents shunting between the contacts and the first electrode layer, reduces defects, and improves device performance.

[0085] The disclosed embodiments of a FinFET could also be applied to nanostructured devices such as nanostructured field-effect transistors (NSFETs, e.g., nanosheets, nanowires, gate-all-around, or the like). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack of alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to the embodiments described above. After the dummy gate stacks are removed, the sacrificial layers in the channel regions can be partially or completely removed.The replacement gate structures are formed in a manner similar to the embodiments described above. The replacement gate structures may partially or completely fill openings created by removing the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source / drain regions may be formed in a manner similar to the embodiments described above. A nanostructure device may be formed as disclosed in US 2016 / 0 365 414 A1, which is incorporated herein by reference in its entirety.

[0086] According to one embodiment, a semiconductor device comprises: a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor having a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, wherein a top surface of the second electrode is flush with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode are located farther from the semiconductor substrate than a top surface of the first electrode.In one embodiment, the semiconductor device further comprises a first dielectric layer extending along the top surface of the gate stack, wherein a top surface of the first dielectric layer is planar with the top surface of the first ferroelectric layer and the top surface of the second electrode. In one embodiment, a combined width of the first dielectric layer and the first electrode is equal to a width of the gate stack. In one embodiment, the semiconductor device further comprises a gate contact electrically coupled to the second electrode, wherein the first ferroelectric layer separates the gate contact from the first electrode. In one embodiment, the first ferroelectric layer completely covers the top surfaces of the first electrode.In one embodiment, the first ferroelectric layer is U-shaped, and a lower surface of the first ferroelectric layer is disposed below the upper surface of the first electrode. In one embodiment, a thickness of a sidewall of the first electrode layer tapers toward the semiconductor substrate.

[0087] According to another embodiment, a semiconductor device comprises a transistor structure over a semiconductor substrate; a first spacer extending along a sidewall of a gate structure of the transistor structure; a first dielectric layer over the gate structure, the first dielectric layer extending along a sidewall of the first spacer; and a capacitor over the gate structure, the capacitor extending through the first dielectric layer, the capacitor having a first electrode over the gate structure, a memory film over the first electrode, the memory film extending along a topmost surface of the first electrode, the topmost surface of the first electrode being over a bottommost surface of the memory film, and a second electrode over the memory film.In one embodiment, the first electrode comprises a first portion extending along the gate structure and a second portion extending along a side surface of the first dielectric layer, the first portion and the second portion being discontinuous. In one embodiment, a thickness of the second portion tapers toward the semiconductor substrate, and the memory film insulates the first portion from the second portion. In one embodiment, the memory film comprises a ferroelectric material. In one embodiment, a top surface of the memory film is planar with a top surface of the second electrode, and the top surface of the memory film and the top surface of the second electrode are planar with a top surface of the first spacer and a top surface of the first dielectric layer.In one embodiment, the semiconductor device further comprises a gate contact electrically coupled to the second electrode, wherein the memory film separates the gate contact from the first electrode.

[0088] According to another embodiment, a method comprises: forming a gate stack over a substrate, the gate stack being adjacent to a gate spacer; etching the gate stack to form a first recess; depositing a first electrode layer in the first recess; etching the first electrode layer such that upper surfaces of the first electrode layer are below an upper surface of the gate spacer; depositing a memory film over the first electrode layer; depositing a second electrode layer over the memory film; and planarizing the memory film and the second electrode layer such that an upper surface of the memory film, an upper surface of the second electrode layer, and an upper surface of the gate spacer are planar with each other.In one embodiment, the method further comprises forming a hard mask layer over the first electrode layer, wherein the hard mask layer masks portions of the first electrode layer while the first electrode layer is etched. In one embodiment, the method further comprises planarizing the hard mask layer and the first electrode layer prior to etching the first electrode layer. In one embodiment, the first electrode layer is deposited by atomic layer deposition (ALD) as a conformal layer. In one embodiment, the method further comprises depositing a first dielectric layer in the first recess; and etching the first dielectric layer to expose the gate stack, wherein the first electrode layer is deposited after etching the first dielectric layer.In one embodiment, the first electrode layer is deposited by physical vapor deposition (PVD), and the first electrode layer is deposited with a first portion extending along the gate stack and a second portion extending along the first dielectric layer, wherein the first portion is discontinuous from the second portion.

Claims

[1] Semiconductor device comprising: a gate stack over a semiconductor substrate; a capacitor (113a) over the gate stack, the capacitor (113a) comprising: - a first electrode (106a) extending along a top surface of the gate stack, the first electrode being U-shaped; - a first ferroelectric layer (110a) over the first electrode; and - a second electrode (112a) above the first ferroelectric layer, wherein an upper surface of the second electrode is flat with an upper surface of the first ferroelectric layer, wherein the upper surface of the first ferroelectric layer and the upper surface of the second electrode are arranged farther from the semiconductor substrate than an uppermost surface of the first electrode, wherein the first electrode has a first portion extending along the gate structure and a second portion extending along a side surface of a first dielectric layer (104) extending along the upper surface of the gate stack, wherein the first portion and the second portion are discontinuous, wherein an upper surface of the first dielectric layer (104) is flat with the upper surface of the first ferroelectric layer and the upper surface of the second electrode. [2] The semiconductor device of claim 1, wherein a combined width of the first dielectric layer (104) and the first electrode is equal to a width of the gate stack. [3] A semiconductor device according to any one of the preceding claims, further comprising: a gate contact (116) electrically coupled to the second electrode, wherein the first ferroelectric layer separates the gate contact from the first electrode. [4] A semiconductor device according to any one of the preceding claims, wherein the first ferroelectric layer completely covers upper surfaces of the first electrode. [5] A semiconductor device according to any one of the preceding claims, wherein the first ferroelectric layer is U-shaped and wherein a lower surface of the first ferroelectric layer is disposed below the upper surface of the first electrode. [6] A semiconductor device according to any one of the preceding claims, wherein a thickness of a sidewall of the first electrode layer (106a) tapers toward the semiconductor substrate. [7] Semiconductor device comprising: a transistor structure over a semiconductor substrate; a first spacer (81) extending along a sidewall of a gate structure of the transistor structure; a first dielectric layer (104) over the gate structure, the first dielectric layer (104) extending along a sidewall of the first spacer (81); and a capacitor (113a) over the gate structure, the capacitor (113a) extending through the first dielectric layer (104), the capacitor (113a) comprising: - a first electrode (106a) over the gate structure; - a storage film (110a) over the first electrode, the storage film (110a) extending along a top surface of the first electrode, the top surface of the first electrode being above a bottom surface of the storage film (110a); and - a second electrode (112a) over the memory film (110a), the first electrode having a first portion extending along the gate structure and a second portion extending along a side surface of the first dielectric layer (104), the first portion and the second portion being discontinuous. [8] The semiconductor device according to claim 7, wherein a thickness of the second portion tapers toward the semiconductor substrate, wherein the memory film (110a) isolates the first portion from the second portion. [9] The semiconductor device according to claim 7 or 8, wherein the first electrode has a first portion extending along the gate structure and a second portion extending along a side surface of the first dielectric layer (104), the second portion including the top surface of the first electrode. [10] A semiconductor device according to any one of claims 7 to 9, wherein the memory film (110a) contains a ferroelectric material. [11] A semiconductor device according to any one of claims 7 to 10, wherein a top surface of the memory film (110a) is flat with a top surface of the second electrode, and wherein the top surface of the memory film (110a) and the top surface of the second electrode are flat with a top surface of the first spacer (81) and a top surface of the first dielectric layer (104). [12] A semiconductor device according to any one of claims 7 to 11, further comprising: a gate contact (116) electrically coupled to the second electrode, wherein the storage film (110a) separates the gate contact from the first electrode. [13] Procedure comprising: Forming a gate stack over a substrate (50), the gate stack being adjacent to a gate spacer; etching the gate stack to form a first recess (86); Depositing a first dielectric layer (104) in the first recess (86); and etching the first dielectric layer (104) to expose the gate stack; Depositing a first electrode layer (106a) in the first recess (86), wherein the first electrode layer (106a) is deposited after etching the first dielectric layer (104); Etching the first electrode layer (106a) such that upper surfaces of the first electrode layer (106a) are below an upper surface of the gate spacer; Depositing a storage film (110a) over the first electrode layer (106a); Depositing a second electrode layer (112) over the storage film (110a); and Planarizing the storage film (110a) and the second electrode layer such that a top surface of the storage film (110a), a top surface of the second electrode layer (112), and a top surface of the gate spacer are planar, wherein the first electrode layer (106a) is deposited with a first portion extending along the gate stack and a second portion extending along the first dielectric layer (104), the first portion being discontinuous with the second portion. [14] The method of claim 13, further comprising: Forming a hard mask layer (108a) over the first electrode layer (106a), wherein the hard mask layer (108a) masks portions of the first electrode layer (106a) while the first electrode layer (106a) is etched. [15] The method of claim 14, further comprising: Planarizing the hard mask layer (108a) and the first electrode layer (106a) before etching the first electrode layer (106a). [16] The method according to any one of claims 13 to 15, wherein the first electrode layer (106a) is deposited as a conformal layer by atomic layer deposition. [17] The method according to any one of claims 13 to 16, wherein the first electrode layer (106a) is deposited by physical vapor deposition.

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