STORAGE ARRAY CONTACT STRUCTURES

Abstract

Having memory cell (202): a semiconductor substrate (50); and a transistor (204) above the semiconductor substrate (50), wherein the transistor (204) comprises: - a storage film (90) extending along a word line (72), wherein the storage film (90) contacts the word line (72); - a channel layer (92) extending along the storage film (90), the storage film (90) being located between the channel layer (92) and the word line (72); - a source line (108) extending along the memory film (90), the memory film (90) being located between the source line (108) and the word line (72); - a first contact layer (96) on the source line (108), wherein the first contact layer (96) contacts the channel layer (92) and the storage film (90), wherein the first contact layer (96) contains a first material and the source line (108) establishes an electrical contact with the channel layer (92) via the first contact layer (96); - a bit line (106) extending along the storage film (90), the storage film (90) being located between the bit line (106) and the word line (72); - a second contact layer (96) on the bit line (106), wherein the second contact layer (96) contacts the channel layer (92) and the storage film (90), wherein the second contact layer (96) contains the first material and the bit line (106) establishes an electrical contact with the channel layer (92) via the second contact layer (96); and - an isolation area (98) between the source line (108) and the bit line (106), wherein the source line (108) and the bit line (106) contain a conductive material that is different from the first material, and where: the isolation area (98) contacts the source line (108) and the bit line (106); and / or the first contact layer (96) extends between the source line (108) and the isolation area (98) and the second contact layer (96) extends between the bit line (106) and the isolation area (98).

Description

BACKGROUND

[0001] Semiconductor memory is used in integrated circuits for electronic applications, such as radios, televisions, mobile phones, and personal computers. Semiconductor memory includes two main categories: volatile memory and non-volatile memory. Volatile memory includes random-access memory (RAM), which can be further divided into two subcategories: static random-access memory (SRAM) and dynamic random-access memory (DRAM). Both SRAM and DRAM are volatile because they lose stored information when power is removed.

[0002] On the other hand, non-volatile memory can retain stored data. One type of non-volatile semiconductor memory is ferroelectric random access memory (FeRAM or FRAM). The advantages of FeRAM include its fast read / write speed and small size.

[0003] Ferroelectric memory cells are known, for example, from PARK, JH [et al.]: A hybrid ferroelectric-flash memory cells. In: Journal of Applied Physics, Vol. 116, 2014, Issue 12, 124512. Other semiconductor memory cells are known from US 2016 / 0 086 970 A1, WO 2019 / 152 226 A1, US 2019 / 0 295 626 A1, and US 2017 / 0 301 684 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be exaggerated or reduced arbitrarily for the sake of clarity of explanation. Fig. 1A, Fig. 1B and Fig. 1C show a perspective view, a circuit diagram, and a top-down view of a memory array according to some embodiments. Fig. 2, Fig. 3A, Fig. 3B, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14A, Fig. 14B, Fig. 15, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27, Fig. 28A, Fig. 28B, Fig. 28C and Fig. 28D show various views of intermediate steps in the fabrication of a memory array according to some embodiments. Fig. 29, Fig. 30, Fig. 31 and Fig. 32 show various views of intermediate steps in the fabrication of a memory array according to some embodiments. Fig. 33, Fig. 34, Fig. 35 and Fig. 36 show various views of intermediate steps in the fabrication of a memory array according to some embodiments. DETAILED DESCRIPTION

[0005] The present invention provides a memory cell having the features of claim 1, a memory device having the features of claim 6, and a method having the features of claim 13. Exemplary embodiments are specified in the dependent claims.

[0006] The following disclosure provides many different embodiments and examples of implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments where the first and second features are formed in direct contact, but may also include embodiments where additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Further, reference numerals may be repeated throughout the various examples of the present disclosure.This repetition is for simplicity and clarity and does not necessarily prescribe any relationship between the various embodiments and / or configurations discussed herein.

[0007] Furthermore, for ease of description, spatially relative terms such as "below," "below," "downward," "above," "above," "upward," and the like may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the drawings. These spatially relative terms are intended to encompass other orientations of the device during use or operation in addition to the orientation illustrated in the drawings. The device may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0008] Various embodiments provide a 3D memory array with a plurality of vertically stacked memory cells. Each memory cell includes a transistor having a wordline region serving as a gate electrode, a bitline region serving as a first source / drain electrode, and a sourceline region serving as a second source / drain electrode. Each transistor further includes an insulating memory film (e.g., as a gate dielectric) and an oxide semiconductor channel region (OSR). In some embodiments, trenches are etched in which the source / drain electrodes of each transistor are formed. In some cases, the etching for the trenches may also etch a portion of the OSR channel material. Etching the OSR channel regions may degrade device performance and reduce device efficiency.For example, this etching of the OS material may reduce the contact area between each source / drain electrode and the OS channel region, which may increase the contact resistance between the source / drain electrodes and the OS channel region. In some embodiments of the present disclosure, a refill layer of OS material is deposited within the trenches before the source / drain electrodes are formed. This refill layer compensates for possible etching of the OS channel regions during trench formation and increases the contact area between the source / drain electrodes and the OS channel regions. In some cases, the refill layer may be a different material than the OS channel region, and the material of the refill layer may be a material that reduces the contact resistance between the OS channel region and the source / drain electrodes.Thus, the resistance between the source / drain electrodes and the OS channel regions can be improved, which can improve the performance and efficiency of the device.

[0009] Fig. 1A, Fig. 1B and Fig. 1C show examples of a memory array according to some embodiments. Fig. 1A shows an example of a portion of the memory array 200 in a three-dimensional view; Fig. 1B shows a circuit diagram of the memory array 200; and Fig. 1C shows a top view of the memory array 200 according to some embodiments. The memory array 200 includes a plurality of memory cells 202, which may be arranged in a grid of rows and columns. The memory cells 202 may be further stacked vertically to provide a three-dimensional memory array, thereby increasing device density. The memory array 200 may be arranged in the BEOL (Back End of Line) of a semiconductor chip. For example, the memory array may be arranged in the interconnect layers of the semiconductor chip, such as above one or more active devices (e.g., transistors or the like) formed on a semiconductor substrate.

[0010] In some embodiments, the memory array 200 is a memory array, such as a NOR memory array, a NAND memory array, or the like. Other types of memory arrays are possible. Each memory cell 202 may include a transistor 204 with an insulating memory film 90 as a gate dielectric. The transistor 204 may be, for example, a thin-film transistor (TFT) or another transistor type. In some embodiments, a gate of each transistor 204 is electrically coupled to a respective word line (e.g., a conductive line 72), a first source / drain region of each transistor 204 is electrically coupled to a respective bit line (e.g., a conductive line 106), and a second source / drain region of each transistor 204 is electrically coupled to a respective source line (e.g., a conductive line 108) that electrically connects the second source / drain region to ground.The memory cells 202 in a same horizontal row of the memory array 200 may share a word line (e.g., 72), while the memory cells 202 in a same vertical column of the memory array 200 may share a source line (e.g., 108) and a bit line (e.g., 106).

[0011] The memory array 200 includes a plurality of vertically stacked conductive lines 72 (e.g., word lines) with dielectric layers 52 disposed between adjacent conductive lines 72. The conductive lines 72 extend in a direction parallel to a main surface of an underlying substrate (in Fig. 1A and Fig. 1B not shown separately). The conductive lines 72 may have a stepped configuration such that the lower conductive lines 72 are longer than the endpoints of the upper conductive lines 72 and extend laterally beyond them. For example, as in Fig. 1A, multiple superimposed layers of conductive lines 72 are shown, with the topmost conductive lines 72 being the shortest and the bottommost conductive lines 72 being the longest. The respective lengths of the conductive lines 72 may increase toward the underlying substrate. Thus, a portion of each of the conductive lines 72 may be accessible from above the memory array 200, and conductive contacts may be made to an exposed portion of each of the conductive lines 72 (see, for example, Fig. 28A-D).

[0012] The memory array 200 further includes a plurality of conductive lines 106 (e.g., bit lines) and conductive lines 108 (e.g., source lines). The conductive lines 106 and 108 may each extend in a direction perpendicular to the conductive lines 72. A dielectric material 98 is disposed between and insulates adjacent conductive lines 106 and 108. Pairs of the conductive lines 106 and 108, together with an intersecting conductive line 72, define boundaries of each memory cell 202, and a dielectric material 102 is disposed between and insulates adjacent pairs of the conductive lines 106 and 108. In some embodiments, the conductive lines 108 are electrically coupled to ground. Although Fig. 1A shows a particular arrangement of the conductive lines 106 relative to the conductive lines 108, it should be noted that the arrangement of the conductive lines 106 and 108 may be reversed in other embodiments.

[0013] As described above, the memory array 200 may also include an OS semiconductor (oxide semiconductor) layer 92. The OS layer 92 may provide channel regions for the transistors 204 of the memory cells 202. For example, when a suitable voltage (e.g., higher than a respective threshold voltage (Vth) of a corresponding transistor 204) is applied across a respective conductive line 72, a region of the OS layer 92 that intersects the conductive line 72 may allow current to flow from the conductive lines 106 to the conductive lines 108 (e.g., in the direction indicated by arrow 207). Thus, in some cases, the OS layer 92 may be considered a channel layer.

[0014] In some embodiments, a refill layer 96 at least partially surrounds the conductive lines 106 and the conductive lines 108. The refill layer 96 may include the same material as the material of the OS layer 92 or may include one or more materials that are different from the material of the OS layer 92. The refill layer 96 may extend between the conductive lines 106 / 108 and surfaces of the OS layer 92. Thus, the refill layer 96 may provide contacts between the conductive lines 106 / 108 and the channel regions for the transistors 204. Thus, in some cases, the refill layer 96 may be considered a "contact layer" or a "contact interface layer." In some cases, a combination of the OS layer 92 and the refill layer 96 may provide the channel regions for the transistors 204. The refill layer 96 will be described further below with reference to Fig. 23A-C are described in detail.

[0015] A memory film 90 is disposed between the conductive lines 72 and the OS layer 92, and the memory film 90 may provide gate dielectrics for the transistors 204. In some embodiments, the memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Thus, the memory array 200 may also be referred to as a FeRAM (Ferroelectric Random Access Memory Array) array. Alternatively, the memory film 90 may be a multilayer structure comprising a layer of SiNx between two SiOx layers (e.g., an ONO structure), another ferroelectric material, another type of memory layer (e.g., capable of storing one bit), or the like.

[0016] In embodiments where the memory film 90 comprises a ferroelectric material, the memory film 90 may be polarized in one of two different directions, and the polarization direction may be changed by applying a suitable voltage difference across the memory film 90 and generating a suitable electric field. The polarization may be relatively localized (e.g., generally contained within each boundary of the memory cells 202), and a continuous region of the memory film 90 may extend across multiple memory cells 202. Depending on a polarization direction of a particular region of the memory film 90, a threshold voltage of an associated transistor 204 varies, and a digital value (e.g., 0 or 1) may be stored.For example, if a region of the memory film 90 has a first electrical polarization direction, the associated transistor 204 may have a relatively low threshold voltage, and if the region of the memory film 90 has a second electrical polarization direction, the associated transistor 204 may have a relatively high threshold voltage. The difference between the two threshold voltages may be referred to as a threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error-prone) to read the digital value stored in the associated memory cell 202.

[0017] To perform a write operation on a memory cell 202 in such embodiments, a write voltage is applied across a portion of the memory film 90 corresponding to the memory cell 202. The write voltage can be applied, for example, by applying suitable voltages to a respective conductive line 72 (e.g., the word line) and the respective conductive lines 106 / 108 (e.g., the bit line / source line). By applying the write voltage to the region of the memory film 90, a polarization direction of the region of the memory film 90 can be changed. This can also switch the corresponding threshold voltage of the associated transistor 204 from a low threshold voltage to a high threshold voltage or vice versa, and a digital value can be stored in the memory cell 202.Since the conductive lines 72 cross the conductive lines 106 and 108, individual memory cells 202 can be selected for the write operation.

[0018] In such embodiments, to perform a read operation on memory cell 202, a read voltage (a voltage between the low and high threshold voltages) is applied to the respective conductive line 72 (e.g., the word line). Depending on the polarization direction of the corresponding region of memory film 90, transistor 204 of memory cell 202 may or may not be turned on. Consequently, conductive line 106 may or may not be discharged via conductive line 108 (e.g., a source line coupled to ground), and the digital value stored in memory cell 202 may be determined. Because conductive lines 72 cross conductive lines 106 and 108, individual memory cells 202 can be selected for the read operation.

[0019] In Fig. 1A illustrates further reference cross-sections of the memory array 200 used in subsequent drawings. The reference cross-section BB' runs along a longitudinal axis of the conductive lines 72 and in a direction, for example, parallel to the current flow direction of the transistors 204. The reference cross-section CC' runs perpendicular to the cross-section BB' and perpendicular to a longitudinal axis of the conductive lines 72. The reference cross-section CC' runs through the conductive lines 106 and / or the conductive lines 108. The reference cross-section DD' is parallel to the reference cross-section CC' and runs through the dielectric material 102. In the following drawings, reference is made to these reference cross-sections for clarity.

[0020] In Fig. 2, a substrate 50 is shown. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, an SOI (semiconductor-on-insulator) substrate, or the like, which may be doped (e.g., with a p-type or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may, for example, be a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may include silicon, germanium, a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide, or combinations thereof.

[0021] Fig. 2 further shows circuits that may be formed over the substrate 50. The circuits include active devices (e.g., transistors) on a top surface of the substrate 50. The transistors may include gate dielectric layers 203 over top surfaces of the substrate 50 and gate electrodes 205 over the gate dielectric layers 203. Source / drain regions 206 are disposed in the substrate 50 on opposite sides of the gate dielectric layers 203 and the gate electrodes 205. Gate spacers 208 are formed along the sidewalls of the gate dielectric layers 203 and separate the source / drain regions 206 from the gate electrodes 205 by suitable lateral distances. In some embodiments, the transistors may be planar field-effect transistors (FETs), fin field-effect transistors (FinFETs), nano-field-effect transistors (nanoFETs), or the like.

[0022] A first ILD 210 surrounds and insulates the source / drain regions 206, the gate dielectric layers 203, and the gate electrodes 205, and a second ILD 212 overlies the first ILD 210. Source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 206, and gate contacts 216 extend through the second ILD 212 and are electrically coupled to the gate electrodes 205. An interconnect structure 220 comprising one or more stacked dielectric layers 224 and conductive features 222 formed in the one or more dielectric layers 224 overlies the second ILD 212, the source / drain contacts 214, and the gate contacts 216. Although in Fig. 2 illustrates two stacked dielectric layers 224, the interconnect structure 220 may include any number of dielectric layers 224 with conductive features 222 disposed therein. The interconnect structure 220 may be electrically connected to the gate contacts 216 and the source / drain contacts 214 to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure 220 may include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, and the like, or combinations thereof. Although in Fig. 2 transistors formed over the substrate 50, other active components (e.g., diodes or the like) and / or passive components (e.g., capacitors, resistors, or the like) may also be formed as part of the functional circuits.

[0023] In Fig. 3A and Fig. 3B, a multilayer stack 58 is placed over the structure of Fig. 2. For simplicity and clarity, the substrate 50, the transistors, the ILDs, and the interconnect structure 220 may be omitted from the following drawings. Although the multilayer stack 58 is illustrated in contact with the dielectric layers 224 of the interconnect structure 220, any number of intermediate layers may be disposed between the substrate 50 and the multilayer stack 58. For example, one or more additional interconnect layers comprising conductive features in insulating layers (e.g., low-k dielectric layers) may be disposed between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features may be patterned to provide power, ground, and / or signal lines for the active devices on the substrate 50 and / or the memory array 200 (see Fig. 1A and Fig. 1B).

[0024] The multilayer stack 58 includes alternating layers of conductive lines 72A-D (collectively referred to as conductive layers 54) and dielectric layers 52A-C (collectively referred to as dielectric layers 52). The conductive layers 54 may be patterned in subsequent steps to define the conductive lines 72 (e.g., wordlines). The conductive layers 54 may include a conductive material, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and the dielectric layers 52 may include an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like. The conductive layers 54 and the dielectric layers 52 may each include, for example,by chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), or the like. While in . Fig. 3A and Fig. 3B illustrates a particular number of conductive layers 54 and dielectric layers 52, other embodiments may include a different number of conductive layers 54 and dielectric layers 52.

[0025] Fig. 4 to 12B are views of intermediate stages in the fabrication of a staircase structure of the memory array 200 according to some embodiments. Fig. 4 to 11 and 12B are along the reference cross section BB' as in Fig. 1 shown. Fig. 12A is shown in a three-dimensional view.

[0026] In Fig. 4, a photoresist 56 is formed over the multilayer stack 58. As described above, the multilayer stack 58 may include alternating layers of the conductive layers 54 (referenced 54A, 54B, 54C, and 54D) and the dielectric layers 52 (referenced 52A, 52B, and 52C). The photoresist 56 may be formed using a spin-on technique.

[0027] In Fig. 5, the photoresist 56 is patterned such that the multilayer stack 58 is exposed in the regions 60, while the remaining portions of the multilayer stack 58 are masked. For example, a topmost layer of the multilayer stack 58 (e.g., the conductive layer 54D) may be exposed in the regions 60. The photoresist 56 may be patterned using acceptable photolithographic techniques.

[0028] In Fig. 6, the exposed portions of the multilayer stack 58 in the regions 60 are etched using the photoresist 56 as a mask. The etching may be any acceptable etching process, e.g., wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. The etching may remove portions of the conductive layer 54D and the dielectric layer 52C in the regions 60 and define openings 61. Because the conductive layer 54D and the dielectric layer 52C have different material compositions from one another, the etchants used to remove the exposed portions of these layers may be different from one another.In some embodiments, dielectric layer 52C serves as an etch stop layer during the etching of conductive layer 54D, and conductive layer 54C serves as an etch stop layer during the etching of dielectric layer 52C. This allows portions of conductive layer 54E and conductive layer 54D to be selectively removed without removing the remaining layers of multilayer stack 58, and openings 61 can be extended to a desired depth. Alternatively, a timed etch process can be used to stop the etching of openings 61 after openings 61 have reached a desired depth. In the resulting structure, conductive layer 54C is exposed in regions 60.

[0029] In Fig. 7, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist may be trimmed using acceptable photolithographic techniques. As a result of trimming, the width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60 and 62 may be exposed. For example, a top surface of the conductive layer 54C may be exposed in regions 60, and a top surface of the conductive layer 54D may be exposed in regions 62.

[0030] In Fig. 8, portions of the conductive layer 54D, the dielectric layer 52C, the conductive layer 54C, and the dielectric layer 52B in the regions 60 and 62 are removed by acceptable etching processes using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching may be anisotropic. The etching may extend the openings 61 further into the multilayer stack 58. Because the conductive layers 54D / 54C and the dielectric layers 52C / 52B have different material compositions from one another, the etchants used to remove the exposed portions of these layers may be different from one another.In some embodiments, dielectric layer 52C serves as an etch stop layer during the etching of conductive layer 54D; conductive layer 54C serves as an etch stop layer during the etching of dielectric layer 52C; dielectric layer 52B serves as an etch stop layer during the etching of conductive layer 54C; and conductive layer 54B serves as an etch stop layer during the etching of dielectric layer 52B. This allows portions of conductive layers 54D / 54C and dielectric layer 52C / 52B to be selectively removed without removing the remaining layers of multilayer stack 58, and openings 61 can be extended to a desired depth. Furthermore, unetched portions of the conductive layers 54 and the dielectric layers 52 serve as a mask for underlying layers during the etching processes, so that a previous pattern of the conductive layer 54D and the dielectric layer 52C (see . Fig. 7) can be transferred to the underlying conductive layer 54C and the dielectric layer 52B. In the resulting structure, the conductive layer 54B is exposed in the regions 60 and the conductive layer 54C is exposed in the regions 62.

[0031] In Fig. 9, the photoresist 56 is trimmed to expose additional portions of the multilayer stack 58. The photoresist may be trimmed using acceptable photolithographic techniques. As a result of trimming, the width of the photoresist 56 is reduced, and portions of the multilayer stack 58 in regions 60, 62, and 64 may be exposed. For example, a top surface of the conductive layer 54B may be exposed in regions 60; a top surface of the conductive layer 54C may be exposed in regions 62; and a top surface of the conductive layer 54D may be exposed in regions 64.

[0032] In Fig. 10, portions of the conductive layers 54D, 54C, and 54B in the regions 60, 62, and 64 are removed by acceptable etching processes using the photoresist 56 as a mask. The etching may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching may be anisotropic. The etching may extend the openings 61 further into the multilayer stack 58. In some embodiments, the dielectric layer 52C serves as an etch stop layer during the etching of the conductive layer 54D; the dielectric layer 52B serves as an etch stop layer during the etching of the conductive layer 54C; and the dielectric layer 52A serves as an etch stop layer during the etching of the conductive layer 54B.Consequently, portions of the conductive layers 54D, 54C, and 54B can be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 can be extended to a desired depth. Furthermore, each of the dielectric layers 52 serves as a mask for underlying layers during the etching processes, thereby preserving a prior pattern of the dielectric layers 52C / 52B (see FIG. Fig. 9) can be transferred to the underlying conductive layers 54C / 54B. In the resulting structure, the dielectric layer 52A is exposed in regions 60; the dielectric layer 52B is exposed in regions 62; and the dielectric layer 52C is exposed in regions 64.

[0033] In Fig. 11, the photoresist 56 can be removed, e.g., by an acceptable ashing or wet stripping process. Thus, a stair structure 68 is formed. The stair structure comprises a stack of alternately arranged conductive layers 54 and dielectric layers 52. The lower conductive layers 54 are wider and extend laterally beyond the upper conductive layers 54, and a width of each of the conductive layers 54 increases toward the substrate 50. For example, the conductive layer 54A can be longer than the conductive layer 54B; the conductive layer 54B can be longer than the conductive layer 54C; and the conductive layer 54C can be longer than the conductive layer 54D. This allows conductive contacts to each of the conductive layers 54 to be made from above the stair structure 68 in subsequent processing steps.

[0034] In Fig. 12A and Fig. 12B, an intermetallic dielectric (IMD) 70 is deposited over the multilayer stack 58. The IMD 70 may include a dielectric material and may be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may be phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials fabricated by any acceptable process may be used. The IMD 70 extends along both the sidewalls of the conductive layers 54 and the sidewalls of the dielectric layers 52. Further, the IMD 70 may contact top surfaces of each of the dielectric layers 52.

[0035] As in Fig. 12A and Fig. 12B, a removal process is then applied to the IMD 70 to remove excess dielectric material over the multilayer stack 58. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like, may be used. The planarization process exposes the multilayer stack 58 so that top surfaces of the multilayer stack 58 and the IMD 70 are flat after completion of the planarization process.

[0036] Fig. 13 to 17B are views of intermediate stages in the fabrication of the memory array 200 according to some embodiments. Fig. 13 to 17B, the multilayer stack 58 is formed, and trenches are formed in the multilayer stack 58, thereby defining the conductive lines 72. The conductive lines 72 may correspond to word lines in the memory array 200, and the conductive lines 72 may further provide gate electrodes for the resulting transistors of the memory array 200. Fig. 17A is shown in a three-dimensional view. Fig. 13 to 16 and 17B are along the reference cross section CC' as in Fig. 1A.

[0037] In Fig. 13, a hard mask 80 and a photoresist 82 are deposited over the multilayer stack 58. The hard mask 80 may, for example, contain silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist 82 may, for example, be formed by a spin-on technique.

[0038] In Fig. 14A and Fig. 14B, the photoresist 82 is patterned to form trenches 86. Photoresists can be patterned using acceptable photolithographic techniques. For example, the photoresist 82 can be exposed for patterning. After the exposure process, the photoresist 82 can be developed to remove exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, thereby defining the structure of the trenches 86.

[0039] In Fig. 15, a pattern of photoresist 82 is transferred to hard mask 80 by an acceptable etching process, e.g., wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching may be anisotropic. This forms trenches 86 that extend through hard mask 80. Photoresist 82 may be removed, e.g., by an ashing process.

[0040] In Fig. 16, a pattern of the hard mask 80 is transferred to the multilayer stack 58 by one or more acceptable etching processes, e.g., by wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or the like, or a combination thereof. The etching processes may be anisotropic. Thus, the trenches 86 extend through the multilayer stack 58, and the conductive lines 72 (e.g., word lines) are formed from the conductive layers 54. By etching the trenches 86 through the conductive layers 54, adjacent conductive lines 72 may be separated from each other. Subsequently, the hard mask 80 may be Fig. 17A and Fig. 17B by an acceptable method, such as a wet etching method, a dry etching method, a planarization method, combinations thereof, or the like. Due to the stair-step shape of the multilayer stack 58 (see, for example, Fig. 12), the conductive lines 72 may have different lengths that increase toward the substrate 50. For example, the conductive lines 72A may be longer than the conductive lines 72B; the conductive lines 72B may be longer than the conductive lines 72C; and the conductive lines 72C may be longer than the conductive lines 72D. In some embodiments, the trenches 86 may be formed with a width W1 that is about 50 nm to about 100 nm, although other widths are also possible.

[0041] Fig. 18A to 20 show the fabrication and patterning of channel regions for the transistors 204 (see Fig. 1A) in trenches 86. Fig. 18A and Fig. 19A are shown in a three-dimensional view. Fig. 18B, Fig. 19B and Fig. 20 show cross-sectional views along the reference cross-section CC' of Fig. 1A.

[0042] In Fig. 18A and Fig. 18B, a memory film 90 is conformally deposited in the trenches 86. The memory film 90 may comprise a material capable of storing a bit, such as a material capable of switching between two different polarization directions by applying a suitable voltage difference to the memory film 90. For example, the polarization of the memory film 90 may change due to an electric field resulting from the application of the voltage difference.

[0043] For example, the memory film 90 may be a high-k dielectric material, such as a hafnium-based dielectric material or the like. In some embodiments, the memory film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. In other embodiments, the memory film 90 may be a multilayer structure comprising a layer of SiNx between two SiOx layers (e.g., an ONO structure). In further embodiments, the memory film 90 may include a different ferroelectric material or a different type of memory material. The memory film 90 may be deposited by CVD, PVD, ALD, PECVD, or the like to extend along the sidewalls and a bottom surface of the trenches 86. In some embodiments, an annealing step may be performed after the deposition of the memory film 90.In some embodiments, the storage film 90 may be deposited with a thickness of about 5 nm to about 15 nm, although other thicknesses are also possible. In some embodiments, the trenches 86 may have a width W2 of about 40 nm to about 70 nm after the storage layer 90 is deposited, although other widths are also possible.

[0044] In Fig. 19A and Fig. 19B, the OS layer 92 is conformally deposited in the trenches 86 over the memory film 90. The OS layer 92 contains a material suitable for forming a channel region for a transistor (e.g., transistors 204, see Fig. 1A). In some embodiments, the OS layer 92 includes an indium-containing material, such as indium oxide, indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, indium tin oxide, or the like, or combinations thereof. In other embodiments, a different semiconductor material than these examples may be used for the OS layer 92. In other embodiments, the OS layer 92 may include, for example, zinc oxide or another type of oxide. The OS layer 92 may be deposited by CVD, PVD, ALD, PECVD, or the like. The OS layer 92 may extend along the sidewalls and a bottom surface of the trenches 86 above the memory film 90. In some embodiments, an annealing step (e.g., in a temperature range of about 300°C to about 450°C) may be performed after the deposition of the OS layer 92 in an oxygen-containing environment to activate the charge carriers of the OS layer 92.In some embodiments, the OS layer 92 may be deposited to a thickness of about 1 nm to about 15 nm, although other thicknesses are also possible. In some embodiments, the trenches 86 may have a width W3 of about 20 nm to about 70 nm after deposition of the OS layer 92, although other widths are also possible.

[0045] In Fig. 20, a dielectric material 98 is deposited on the sidewalls and a bottom surface of the trenches 86 and over the OS layer 92. The dielectric material 98 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. As shown in Fig. 20, the dielectric material 98 may fill the trenches 86 and cover the multilayer stack 58.

[0046] In Fig. 21A to 21C, a removal process is then applied to the dielectric material 98, the OS layer 92, and the storage film 90 to remove excess material over the multilayer stack 58. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), a grinding process, an etch-back process, combinations thereof, or the like may be used. The planarization process may expose the multilayer stack 58 so that the top surfaces of the multilayer stack 58 are flat after completion of the planarization process. Fig. 21A shows a three-dimensional view, Fig. 21B shows a corresponding plan view of the Fig. 21A shown structure and Fig. Figure 21C shows a cross-sectional view through the Fig. 1A and Fig. Reference cross-section C-C' shown in Figure 21B.

[0047] Fig. 22A to 26C show intermediate steps in the fabrication of conductive lines 106 and 108 (e.g., source lines and bit lines) in the memory array 200. The conductive lines 106 and 108 may extend along a direction perpendicular to the conductive lines 72 so that individual cells of the memory array 200 may be selected for read and write operations. Fig. 22A, Fig. 23A, Fig. 24A, Fig. 25A and Fig. 26A shows a three-dimensional view. Fig. 22B, Fig. 23B, Fig. 24B, Fig. 25B and Fig. 26B show a top-down view. Fig. 22C, Fig. 23C and Fig. 24C show cross-sectional views along the Fig. 1A and e.g. in Fig. 22B shown reference cross section C-C'. Fig. 25C and Fig. 26C show cross-sectional views along the reference cross section DD' as in Fig. 1A and e.g. in Fig. 25B.

[0048] In Fig. 22A, Fig. 22B and Fig. 22C, trenches 100 are patterned through the dielectric material 98. The trenches 100 may be disposed between opposing sidewalls of the storage film 90 and define regions in which the conductive lines 106 / 108 are subsequently formed. Patterning the trenches 100 may, in some embodiments, be performed by a combination of photolithography and etching. For example, a photoresist 101 may be deposited over the multilayer stack 58, the dielectric material 98, the OS layer 92, and the storage film 90. The photoresist 101 may be formed by a suitable technique, such as a spin-on technique. The photoresist 101 is then patterned to define openings 100. Each of the openings 100 exposes a region of the dielectric material 98 and may expose regions of the OS layer 92. The photoresists may be patterned by acceptable photolithographic techniques.For example, the photoresist 101 can be exposed for patterning. After the exposure process, the photoresist 101 can be developed to remove exposed or unexposed portions of the photoresist, depending on whether a negative or positive resist is used, thereby defining the structure of the openings 100.

[0049] Portions of the dielectric material 98 exposed by the openings 100 may be removed by etching, thereby forming trenches 100 in the dielectric material 98. The etching may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching may be anisotropic. In some embodiments, the trenches 100 may have a width W4 of about 40 nm to about 70 nm or a length L1 of about 80 nm to about 150 nm, although other dimensions are also possible. In some embodiments, the trenches 100 are separated by a distance L2 of about 30 nm to about 120 nm, although other distances are also possible. In some embodiments, the trenches 100 may have a depth of about 1000 nm to about 2000 nm, although other depths are also possible.After the trenches 100 are patterned, the photoresist 101 can be removed, e.g. by ashing.

[0050] The etching may leave portions of the OS layer 92 within the trenches 100 covering the storage film 90, or the etching may remove the OS layer 92 from the storage film 90 to expose the storage film 90 within the trenches 100. Fig. For example, Fig. 22A shows an embodiment in which portions of the OS layer 92 remain after the formation of the trenches 100 and cover sidewalls of the storage film 90. Fig. 22B-C illustrate embodiments in which the OS layer 92 is removed, exposing sidewalls of the storage film 90. In some embodiments in which portions of the OS layer 92 remain on the storage film 90 after the formation of the trenches 100, the remaining OS layer 92 may have a thickness of about 0 nm to about 15 nm, although other thicknesses are also possible.

[0051] In Fig. 23A, Fig. 23B and Fig. 23C, according to some embodiments, a refill layer 96 is deposited in the trenches 100. As in Fig. 23A, the refill layer 96 may be conformally deposited on surfaces of the dielectric material 98, the OS layer 92, and / or the memory film 90 within the trenches 100. Fig. 23A-C show an embodiment in which the OS layer 92 covering the storage film 90 has been removed and thus the refill layer 96 is deposited on surfaces of the storage film 90 within the trenches 100. The refill layer 96 may extend along the sidewalls and a bottom surface of the trenches 100 above the storage film 90. In other embodiments, the refill layer 96 may be deposited on the remaining portions of the OS layer 92 within the trenches 100 that cover the storage film 90. The refill layer 96 may provide an increased effective contact area between the subsequently formed conductive lines 106 / 108 (see Fig. 25A-26C) and the OS layer 92, particularly in cases where the OS layer 92 is removed within the trenches 100. In some embodiments, the refill layer 96 may be formed from a material that provides a less resistive contact to the conductive lines 106 / 108 than the material of the OS layer 92. Thus, as described herein, the refill layer 96 may reduce resistance and provide improved performance for transistors (e.g., transistors 204, see Fig. 1A).

[0052] The refill layer 96 may be deposited using similar techniques as the OS layer 92, e.g., CVD, PVD, ALD, PECVD, or the like. The refill layer 96 may, in some embodiments, contain the same or a similar material as the material of the OS layer 92. In some embodiments, the refill layer 96 contains, for example, an indium-containing material such as indium oxide, indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, indium tin oxide, or the like, or combinations thereof. In other embodiments, a different semiconductor material than these examples or the OS layer 92 may also be used for the refill layer 96. In other embodiments, the refill layer 96 may, for example, contain zinc oxide or another type of oxide.

[0053] In some embodiments, the refill layer 96 may include a material having a higher concentration of charge carriers than the material of the OS layer 92. Thus, the refill layer 96 may establish a less resistive contact between the conductive lines 106 / 108 and the OS layer 92. In some embodiments, the OS layer 92 may be formed from a material such as indium gallium zinc oxide, indium titanium oxide, indium tungsten oxide, zinc oxide, or indium oxide, for example; the refill layer 96 may be formed from a material with a relatively higher charge carrier concentration such as indium titanium oxide, indium tungsten oxide, zinc oxide, or indium oxide. In some embodiments, the OS layer 92 may have a charge carrier concentration of about 1015 cm -3 up to about 10 17 cm -3 and the refill layer 96 may have a charge carrier concentration of about 10 19 cm -3 up to about 10 22 cm -3have.

[0054] In some embodiments, the refill layer 96 may be deposited to a thickness of about 1 nm to about 15 nm, although other thicknesses are also possible. The refill layer 96 may have a thickness that is less than, approximately equal to, or greater than the thickness of the OS layer 92. For example, in some embodiments, the refill layer 96 extending on the storage film 90 may have a different thickness than the OS layer 92 extending on the storage film 90. In some embodiments, the trenches 100 after deposition of the refill layer 96 may have a width W5 of about 20 nm to about 70 nm or a length L3 of about 50 nm to about 80 nm, although other dimensions are also possible. In some embodiments, the trenches 100 may have a depth D1 after deposition of the refill layer 96 that is about 1000 nm to about 2000 nm, although other depths are also possible.In some embodiments, a planarization process is performed after the deposition of the refill layer 96.

[0055] In Fig. 24A, Fig. 24B and Fig. 24C, the trenches 100 are filled with a conductive material 104 according to some embodiments. The conductive lines 106 / 108 are subsequently formed from the conductive material 104 (see Fig. 25A-26C). The conductive material 104 may include one or more materials such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, molybdenum, combinations thereof, or the like, each of which may be formed, for example, by CVD, ALD, PVD, PECVD, or the like. After the conductive material 104 is deposited, a planarization process may be performed to remove excess portions of the conductive material 104. In some embodiments, the planarization process may also remove excess portions of the refill layer 96. In the resulting structure, the top surfaces of the multilayer stack 58, the memory film 90, the OS layer 92, the refill layer 96, and the conductive material 104 may be substantially planar (e.g., coplanar within process-related variations).

[0056] In Fig. 25A, Fig. 25B and Fig. 25C, trenches 120 are patterned in the conductive material 104, forming conductive lines 106 and conductive lines 108, according to some embodiments. Fig. Figure 25C shows a cross-sectional view of line DD' in Fig. 25B. The trenches 120 are patterned by patterning the conductive material 104 using a combination of photolithography and etching. For example, a photoresist 119 may be deposited over the multilayer stack 58, the dielectric material 98, the OS layer 92, the refill layer 96, the storage film 90, and the conductive material 104. The photoresist 119 may be formed, for example, using a spin-on technique. The photoresist 119 is patterned to define openings 120. Each of the openings 120 may overlap respective portions of the conductive material 104 and the refill layer 96. The openings 120 do not completely overlap the conductive material 104, and the portions of the conductive material 104 that are not overlapped by the openings 120 define the portions of the conductive material 104 that form the conductive lines 106 / 108.The photoresist 119 can be patterned using acceptable photolithographic techniques. For example, the photoresist 119 can be exposed for patterning. After the exposure process, the photoresist 119 can be developed to remove exposed or unexposed portions of the photoresist 119, depending on whether a negative or positive resist is used, thereby defining the openings 120.

[0057] Portions of the conductive material 104 and the fill layer 96 exposed by the openings 120 may be removed by etching, thereby forming trenches 120. The etching may be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching may be anisotropic. Thus, each of the trenches 120 may define a structure of a conductive line 106 of the conductive material 104 and an adjacent conductive line 108 of the conductive material 104 separated from each other by that trench 120. The conductive lines 106 may correspond to bit lines in the memory array, and the conductive lines 108 may correspond to source lines in the memory array 200. Although Fig. While Figure 25C shows a cross-sectional view showing only the conductive lines 106, a cross-sectional view of the conductive lines 108 may be similar. After the trenches 120 are patterned, the photoresist 119 may be removed, for example, by ashing.

[0058] In some embodiments, the trenches 120 may have a length L4 that is about 30 nm to about 100 nm, although other dimensions are also possible. After etching the trenches 120, the remaining portions of the conductive material 104 forming the conductive lines 106 / 108 may have a length L5 that is about 20 nm to about 50 nm, although other dimensions are also possible. In some cases, a conductive line 106 and a conductive line 108 adjacent to the same trench 120 may have different lengths (e.g., lengths L5). In some embodiments, the length L5 of the conductive lines 106 / 108 may be controlled by controlling the length L4 of the trenches 120 (e.g., by controlling the patterning of the trenches 120). Thus, by controlling the size of the trenches 120, the size of the conductive lines 106 / 108 can be controlled.In addition, by controlling the length L4 of the trenches 120, the area of ​​contact between the conductive lines 106 / 108 and the fill layer 96 can also be controlled. An example of a contact region 105 between a conductive line 106 and a refill layer 96 is shown in FIG. Fig. 25B. The size of the contact area between the conductive lines 106 / 108 and the refill layer 96 (e.g., contact area 105) is described below with reference to Fig. 26A-C and Fig. 27 discussed in detail.

[0059] In Fig. 26A, Fig. 26B and Fig. 26C, a dielectric material 102 is deposited in and fills the trenches 120, according to some embodiments. Fig. Figure 26C shows a cross-sectional view of line DD' in Fig. 26B. The dielectric material 102 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, or the like, or combinations thereof. The material of the dielectric material 102 may be the same as or different from the material of the dielectric material 98. The dielectric material 102 may be deposited by any suitable technique, such as CVD, PVD, ALD, PECVD, or the like. The dielectric material 102 may extend along the sidewalls and a bottom surface of the trenches 120 above the memory film 90. After deposition, a planarization process (e.g., CMP, etch-back, or the like) may be performed to remove excess portions of the dielectric material 102.In the resulting structure, the top surfaces of the multilayer stack 58, the storage film 90, the conductive lines 106 / 108, the refill layer 96, the OS layer 92, and the dielectric material 102 may be substantially planar. Thus, adjacent conductive lines 106 and conductive lines 108 are separated from each other by an isolation region formed from the dielectric material 102. The adjacent conductive lines 106 / 108 are separated from each other by a length L4, which can be controlled by controlling the corresponding length L4 of the trenches 120.

[0060] An example of a contact area 105 between a conductive line 106 and a refill layer 96 is shown in Fig. 26B. In some cases, the formation of a refill layer 96 between the conductive lines 106 / 108 and the OS layer 92, as described herein, may improve the conduction between the conductive lines 106 / 108 and the OS layer 92. For example, in embodiments in which the OS layer 92 is removed from the storage film 90 during the etching of the trenches 100 (see Fig. 22A-C) and the refill layer 96 is not present, the contact area between the conductive lines 106 / 108 and the OS layer 92 can be limited by the thickness of the OS layer 92, as in Fig. 26B by the exemplary contact area 103. By partially surrounding the conductive lines 106 / 108 by the refill layer 96, the effective contact area between the conductive lines 106 / 108 and the OS layer 92 can be increased, as shown in Fig. 26B by the contact region 105. The area of ​​a contact region 105 may be approximately defined by the depth D1, the width W5, and the length L5 of the conductive lines 106 / 108. In some embodiments, the area of ​​a contact region 105 may be approximately 1800 nm 2 up to about 8500 nm 2, although other contact areas are also possible. In some embodiments, the use of a refill layer 96 can increase the effective contact area between the conductive lines 106 / 108 and the OS layer 92 by about 33% to about 500%, although other percentages are also possible. By forming contact regions 105 with a larger area, the contact resistance between the conductive lines 106 / 108 and the OS layer 92 can be reduced. In addition, as previously described, the material of the refill layer 96 can be selected to further reduce the contact resistance. In some cases, the contact resistance when using a refill layer 96 is between about 30% and about 100% of the contact resistance when no refill layer 96 is present.

[0061] Since the area of ​​the contact regions 105 can be approximately defined by the depth D1, the width W5 and the length L5 of the conductive lines 106 / 108, controlling the dimensions D1, W5 and / or L5 of the conductive lines 106 / 108 can also control the size of the contact regions 105. An example is shown in Fig. 27, in which the trenches 120 (see Fig. 25A-C) with a length L4 which is smaller than the length L4 of the trenches 120 as in Fig. 26A-C. By forming trenches 120 with a smaller length L4, the size of the conductive lines 106 / 108 and the area of ​​the contact regions 105 can be increased. This is also shown in Fig. 27, in which the conductive lines 106 / 108 have a greater length L5 than the conductive lines in Fig. 26A-C. Thus, a smaller length L4 of the trenches 120 may result in a longer length L5 of the conductive lines 106 / 108, resulting in a correspondingly larger area of ​​the contact regions 105. Forming larger conductive lines 106 / 108 or a larger area of ​​the contact regions 105 may reduce resistance, which may improve device performance, e.g., by improving power efficiency or reducing heating.

[0062] With reference again to Fig. 26A-C, stacked transistors 204 may be formed in the memory array 200. Each transistor 204 includes a gate electrode (e.g., a portion of a respective conductive line 72), a gate dielectric (e.g., a portion of a respective memory film 90), a channel region (e.g., a portion of a respective OS layer 92 and refill layer 96), and source and drain electrodes (e.g., portions of respective conductive lines 106 and 108). The dielectric material 102 isolates adjacent transistors 204 in a same column and on a same vertical plane. The transistors 204 may be arranged in an array of vertically stacked rows and columns.

[0063] In Fig. 28A, Fig. 28B, Fig. 28C and Fig. 28D, the contacts 110 are connected to the conductive lines 72, the conductive lines 106 and the conductive lines 108. Fig. 28A shows a perspective view of the memory array 200; Fig. 28B shows a top-down view of the memory array 200; and Fig. Figure 28C shows a cross-sectional view of the device and the underlying substrate along line 30C'-30C' of Fig. 28A; and Fig. Figure 28D shows a cross-sectional view of the device along the reference cross section BB' of Fig. 1A. In some embodiments, the stair-step shape of the conductive lines 72 may provide a surface on each of the conductive lines 72 upon which the conductive contacts 110 may land. Formation of the contacts 110 may include patterning openings in the IMD 70 and the dielectric layers 52 to expose portions of the conductive layers 54, e.g., through a combination of photolithography and etching. A liner (not shown), such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the IMD 70.The remaining lining and the conductive material form the contacts 110 in the openings.

[0064] As in the perspective view of Fig. 28A, conductive contacts 112 and 114 may also be connected to conductive lines 106 and conductive lines 108. Conductive contacts 110, 112, and 114 may be electrically connected to conductive lines 116A, 116B, and 116C, which connect the memory array to underlying / overlying circuitry (e.g., control circuitry) and / or signal, power, and ground lines in the semiconductor die. For example, conductive vias 118 may extend through the IMD 70 to electrically connect conductive lines 116C to the underlying circuitry of the interconnect structure 220 and the active devices on the substrate 50, as shown in Fig. 28C. Other conductive vias may be formed through the IMD 70 to electrically connect the conductive lines 116A and 116B to the underlying circuitry of the interconnect structure 220. In alternative embodiments, routing and / or power lines to and from the memory array may be provided by an interconnect structure formed above the memory array 200 in addition to or instead of the interconnect structure 220. Thus, the memory array 200 may be completed.

[0065] Although the embodiments of Fig. While Figures 2 through 28B depict a particular structure for the conductive lines 106 and 108, other configurations are also possible. In these embodiments, the conductive lines 106 / 108 have, for example, a staggered structure. In some embodiments, the conductive lines 106 / 108 that are in a same row of the array are all aligned with each other. The refill layers 96 may be formed on the conductive lines 106 / 108 in any suitable manner using the techniques described herein.

[0066] Fig. 29, Fig. 30, Fig. 31 and Fig. 32 show top views of intermediate steps in forming a memory array 200 according to some embodiments. The process as in Fig. 29-32 shows the process as with reference to Fig. 22A to 26C, except that the OS layer 92 remains partially on the storage film 90 after etching the trenches 100. This incomplete etching of the OS layer 92 may produce trenches 100 having a round shape, an example of which is shown in Fig. 29. The storage film 90 is exposed through the trenches 100, but remaining portions of the OS layer 92 cover larger portions of the storage film 90 than in the trenches 100 as in Fig. 22B. In some embodiments, the incomplete etching of the OS layer 92 exposes a larger area of ​​the OS layer 92 within the trenches, which may increase the contact area between the subsequently formed refill layer 96 (see Fig. 30) and the OS layer 92. In some cases, increasing the contact area between the OS layer 92 and the refill layer 96 can reduce the resistance. The trenches 100 as in Fig. 22B and Fig. 29 are examples and trenches 100 with other shapes are possible.

[0067] In Fig. 30, the refill layer 96 is deposited within the trenches 100 according to some embodiments. The refill layer 96 may be similar to the refill layer 96 as described above with reference to Fig. 23A-C and can be formed in a similar manner. In Fig. 31, the conductive material 104 is deposited within the trenches 100 and on the refill layer 96. The conductive material 104 may be similar to the conductive material 104 as described above with reference to Fig. 24A-C and can be formed in a similar manner. In Fig. 32, trenches are formed in the conductive material 104 and the fill layer 96, and a dielectric material 102 is deposited in the trenches. The trenches may correspond to the trenches 120 as described above with reference to Fig. 25A-C and may be formed in a similar manner. The dielectric material 102 may be similar to the dielectric material 102 described above with reference to Fig. 26A-C and may be formed in a similar manner. Thus, conductive lines 106 and conductive lines 108 are formed. The conductive lines 106 / 108 make electrical contact with the OS layer 92 via the refill layer 96, which may reduce the contact resistance as described above.

[0068] Fig. 33, Fig. 34, Fig. 35 and Fig. 36 show top views of intermediate steps in forming a memory array 200 according to some embodiments. The process as in Fig. 33-36 shows the process as with reference to Fig. 22A to 26C, except that the refill layer 96 is selectively deposited on the storage film 90. Selectively depositing the refill layer 96 in this way can increase the size (e.g., the length L5) of the conductive lines 106 / 108 while simultaneously improving the contact resistance between the conductive lines 106 / 108 and the OS layer 92. Increasing the size of the conductive lines 106 / 108 can improve the conductivity of the conductive lines 106 / 108 and increase device performance.

[0069] Fig. 33 shows a plan view after the trenches 100 have been formed, similar to the plan view in Fig. 22B. In Fig. 34, according to some embodiments, the refill layer 96 is deposited in the trenches 100. As in Fig. 34, the refill layer 96 is formed using a selective deposition process such that the refill layer 96 is formed on exposed portions of the storage film 90 and not on the dielectric material 98. In some embodiments, the selectively deposited refill layer 96 is a material such as ITO, IWO, ZnO, In2O3, or the like, or combinations thereof, although other materials are also possible. The refill layer 96 may be formed by a selective deposition process such as selective ALD, CVD, or the like, or other selective deposition processes. For example, the refill layer 96 may include In2O3 deposited by ALD using In(CH3)3 and H2O at a temperature of about 200°C. In this example process, the refill layer 96 is deposited on the storage film 90 but not on the dielectric material 98, although other materials or processes are also possible.The refill layer 96 may be a material similar to that described above with reference to FIG. Fig. 23A-C, or it may be another material.

[0070] In Fig. 35, the conductive material 104 is deposited in the trenches 100 and on the refill layer 96. The conductive material 104 may be similar to the conductive material 104 as described above with reference to Fig. 24A-C and may be formed in a similar manner. Since the refill layer 96 does not cover the dielectric material 98, the conductive material 104 is deposited on portions of the dielectric material 98 in the trenches 100. In Fig. 36, trenches are formed in the conductive material 104 and the refill layer 96, and a dielectric material 102 is deposited in the trenches. The trenches may correspond to the trenches 120 as described above with reference to Fig. 25A-C and may be formed in a similar manner. The dielectric material 102 may be similar to the dielectric material 102 described above with reference to Fig. 26A-C and may be formed in a similar manner. Thus, conductive lines 106 and conductive lines 108 are formed. The conductive lines 106 / 108 make electrical contact with the OS layer 92 via the refill layer 96, which may reduce the contact resistance, as explained above.

[0071] Various embodiments provide a 3D memory array with vertically stacked memory cells. The memory cells each comprise a transistor with a memory film, gate dielectric, and an oxide semiconductor channel region. The transistor includes source / drain electrodes, which are also source lines and bit lines in the memory array. A dielectric material is disposed between and insulates adjacent source / drain electrodes. In some embodiments, during the etching of the trenches in which the source / drain electrodes are formed, a refill layer is deposited on the surfaces of the trenches to establish improved contact between the source / drain electrodes and the oxide semiconductor channel regions. For example, in some cases, oxide semiconductor channel material is removed during the trench etch process, which may reduce the possible contact area between the oxide semiconductor channel material and the source / drain electrodes.By depositing a refill material in the trenches, the removed oxide semiconductor channel material may be replaced. In addition, the refill material may provide an increased effective contact area between the oxide semiconductor channel material and the source / drain electrodes. By increasing the effective contact area, the contact resistance between the oxide semiconductor channel material and the source / drain electrodes may be reduced. In some embodiments, the refill material may be formed from a material that provides improved contact, such as a material with a higher charge carrier concentration than the oxide semiconductor channel material. By reducing the contact resistance in this way, the performance of the device may be improved. For example, the techniques described herein may provide an improved turn-on current (I on) of a memory cell, improved power efficiency and other benefits.

Claims

[1] Memory cell (202) comprising: a semiconductor substrate (50); and a transistor (204) over the semiconductor substrate (50), the transistor (204) comprising: - a memory film (90) extending along a word line (72), the memory film (90) contacting the word line (72); - a channel layer (92) extending along the memory film (90), the memory film (90) being located between the channel layer (92) and the word line (72); - a source line (108) extending along the memory film (90), the memory film (90) being located between the source line (108) and the word line (72); - a first contact layer (96) on the source line (108), the first contact layer (96) contacting the channel layer (92) and the storage film (90), the first contact layer (96) containing a first material and the source line (108) making electrical contact with the channel layer (92) via the first contact layer (96); - a bit line (106) extending along the memory film (90), the memory film (90) being located between the bit line (106) and the word line (72); - a second contact layer (96) on the bit line (106), wherein the second contact layer (96) contacts the channel layer (92) and the memory film (90), wherein the second contact layer (96) contains the first material and the bit line (106) makes electrical contact with the channel layer (92) via the second contact layer (96); and - an isolation region (98) between the source line (108) and the bit line (106), wherein the source line (108) and the bit line (106) contain a conductive material different from the first material, and where: the isolation region (98) contacts the source line (108) and the bit line (106); and / or the first contact layer (96) extends between the source line (108) and the isolation region (98) and the second contact layer (96) extends between the bit line (106) and the isolation region (98). [2] The memory cell (202) of claim 1, wherein the channel layer (92) contains the first material. [3] The memory cell (202) of claim 1 or 2, wherein the first material has a higher charge carrier concentration than the channel layer (92). [4] The memory cell (202) of any preceding claim, wherein the first material comprises an oxide. [5] The memory cell (202) of any preceding claim, wherein the channel layer (92) has a first thickness, the first contact layer (96) has a second thickness, and the second contact layer (96) has the second thickness, the first thickness being different from the second thickness. [6] Device (200) comprising: a semiconductor substrate (50); a first memory cell (202) over the semiconductor substrate (50), the first memory cell (202) comprising a first transistor (204), the first transistor (204) comprising: - a gate electrode comprising a portion of a first word line (72); - a first portion of a ferroelectric material (90), wherein the first portion of the ferroelectric material (90) is located on a sidewall of the first word line (72); and - a first channel region (92) on a sidewall of the first portion of the ferroelectric material (90); a source line (108), wherein a first portion of the source line (108) provides a first source / drain electrode for the first transistor (204); a first contact layer (96) on the source line (108), the source line (108) making electrical contact with the first channel region (92) via the first contact layer (96); a bit line (106), wherein a first portion of the bit line (106) provides a second source / drain electrode for the first transistor (204); a second contact layer (96) on the bit line (106), wherein the bit line (106) makes electrical contact with the first channel region (92) via the second contact layer (96); a first dielectric material (98) separating the source line (108) and the bit line (106) from each other; and a second memory cell (202) above the first memory cell (202), wherein the first contact layer (96) and the second contact layer (96) contain a first material and the source line (108) and the bit line (106) contain a conductive material that is different from the first material, wherein the first portion of the ferroelectric material (90) physically contacts the first contact layer (96) and the second contact layer (96), where: the first dielectric material (98) physically contacts the first channel region (92), the first contact layer (96) and the second contact layer (96); and / or the first dielectric material (98) physically contacts the first channel region (92), the source line (108) and the bit line (106). [7] The device (200) of claim 6, wherein the second memory cell (202) comprises a second transistor, wherein a second portion of the source line (108) provides a first source / drain electrode for the second transistor, and wherein a second portion of the bit line (106) provides a second source / drain electrode for the second transistor. [8] The device (200) of claim 7, further comprising: a second word line (72) below the first word line (72), wherein a gate electrode of the second transistor (204) comprises a portion of the second word line (72), and wherein the first word line (72) is longer than the second word line (72). [9] The device (200) of any one of claims 6 to 8, wherein the first channel region (92) includes a second material different from the first material. [10] The device (200) of any one of claims 6 to 9, wherein the contact area between the source line (108) and the first contact layer (96) is larger than the contact area between the first contact layer (96) and the first channel region (92). [11] The device (200) of any one of claims 6 to 10, wherein the first channel region (92) extends between a portion of the first contact layer (96) and the first portion of the ferroelectric material (90). [12] The device (200) of any one of claims 6 to 11, wherein a sidewall of the source line (108) is free of the first contact layer (96). [13] Procedure comprising: Structuring a first trench (86) extending through a first conductive line (72); depositing a storage film (90) along sidewalls and a bottom surface of the first trench (86); Depositing an oxide semiconductor layer, OS layer (92), over the memory film (90), the OS layer (92) extending along the sidewalls and the bottom surface of the first trench (86); Depositing a first dielectric material (98) on the OS layer (92), wherein the first dielectric material (98) fills the remaining portion of the first trench (86); Patterning a second trench (100) in the first dielectric material (98) and the OS layer (92), wherein patterning the second trench (100) exposes a sidewall surface of the memory film (90) and a sidewall surface of the OS layer (92); Depositing a refill layer (96) along sidewalls and a bottom surface of the second trench (100), the refill layer (96) physically contacting the sidewall surface of the OS layer (92); Depositing a conductive material (104) on the refill layer (96), wherein the conductive material (104) fills the remaining portion of the second trench (100); Structuring a third trench (120) in the conductive material (104) and the refill layer (96), wherein the structuring of the third trench (120) exposes the sidewall surface of the storage film (90) and a sidewall surface of the refill layer (96); and Depositing a second dielectric material (102) in the third trench (120), wherein the second dielectric material (102) fills the third trench (120). [14] The method of claim 13, wherein depositing the refill layer (96) comprises: Performing a selective deposition process that deposits the refill layer (96) selectively on surfaces of the storage film (90) and on surfaces of the OS layer (92) more than on surfaces of the first dielectric material (98). [15] The method of claim 13 or 14, wherein the refill layer (96) has a different composition than the OS layer (92). [16] The method of any one of claims 13 to 15, wherein the refill layer (96) is deposited with a different thickness than the OS layer (92).

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