METHOD FOR PRODUCING FINFETS WITH EPITAXIC AREAS WITH MIXED WAVE-SHAPED AND NON-WAVE-SHAPED SECTIONS

Abstract

Procedure comprehensive: Recessing of insulating areas (22) on opposite sides of a first semiconductor strip (24), a second semiconductor strip (24) and a third semiconductor strip (24) to form a first semiconductor fin (24A'), a second semiconductor fin (24A') and a third semiconductor fin (24A'); Forming a gate stack (30) on the first semiconductor fin (24A'), the second semiconductor fin (24A') and the third semiconductor fin (24A'); Forming gate spacers (38) on side walls of the gate stack (30); Forming fin spacers (39) on side walls of the first semiconductor strip (24), the second semiconductor strip (24) and the third semiconductor strip (24); Performing a recession process to recess the first semiconductor strip (24), the second semiconductor strip (24), and the third semiconductor strip (24) to form a first recess (40A), a second recess (40A), and a third recess (40A); and Performing an epitaxy process to form an epitaxy area (48A) starting from the first recess (40A), the second recess (40A) and the third recess (40A), wherein the epitaxial area (48A) has an upper surface which has: - a convex section (45A) that is higher than the first semiconductor fin (24A') and the second semiconductor fin (24A') and lies laterally between them; and - a concave section (46C) that is higher than the second semiconductor fin (24A') and the third semiconductor fin (24A') and is located laterally between them; wherein the epitaxial area (48A) has a first epitaxial layer (48-1), a second epitaxial layer (48-2) and a third epitaxial layer (48-3), wherein the third epitaxial layer has a first part with the convex section (45A) of the upper surface and a second part with the concave section (46C) of the upper surface, and the procedure further includes: Etching through the first part of the third epitaxial layer (48-3) to expose a concave upper surface of the second epitaxial layer (48-2).

Description

BACKGROUND

[0001] In the fabrication of fin field-effect transistors, source / drain regions are typically formed by creating semiconductor fins, removing sections from these fins to form recesses, and growing epitaxial regions from these recesses. The epitaxial regions grown from the recesses of adjacent semiconductor fins can merge, and the resulting epitaxial regions may have flat top surfaces. Source / drain contact plugs are formed to provide an electrical connection to the source / drain regions.

[0002] US 2019 / 0378901 A1 describes a semiconductor device with a plurality of active structures on a substrate. The semiconductor device may include a device insulating layer that defines the multiple active structures, a gate electrode that extends across the multiple active structures, and a source / drain structure on the active structures. The plurality of active structures may include a first active structure and a second active structure. The source / drain structure comprises a first part on the first active structure, a second part on the second active structure, and a third part that extends from the first part and along an upper portion of the first active structure. The device insulating layer comprises a first outer segment on a sidewall of the first active structure below the source / drain structure.The lowest level of a lower surface of the third part can be lower than the highest level of an upper surface of the first outer segment.

[0003] US 2019 / 0288065 A1 describes a semiconductor device with fin structures on a substrate, at least one gate electrode that intersects the fin structures, source / drain regions on upper surfaces of the fin structures, and at least one barrier layer on a side wall of a first fin structure of the fin structures, wherein the at least one barrier layer extends over an upper surface of the first fin structure of the fin structures, and wherein a first source / drain region of the source / drain regions, located on the upper surface of the first fin structure, has an asymmetric shape and is in direct contact with the at least one barrier layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be understood that, in accordance with industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1, 2A, 2B, 3A, 3B, 3C, 4A, 4B, 4C, 5-7, 8A, 8B, 9, 10, 11A, 11B and 11C show perspective views and cross-sectional views of intermediate stages in the fabrication of fin field-effect transistors (FinFETs) according to some embodiments. Fig. Figure 12 shows a process flow for the fabrication of an n-type FinFET and a p-type FinFET according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments and examples of the implementation of various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples. For instance, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, but may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features may not be in direct contact. Furthermore, reference numerals may be repeated in the various examples of the present disclosure.This repetition serves for simplicity and clarity and does not fundamentally prescribe a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, to simplify the description, spatially relative terms such as "below," "down," "downward," "above," "above," "upward," and the like may be used to describe the relationship of one element or feature to another, as illustrated in the drawings. These spatially relative terms are intended to encompass not only the orientation shown in the drawings but also other orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative terms used here may be interpreted accordingly.

[0007] Fin-based field-effect transistors (FinFETs) and the method for their fabrication are provided. According to some embodiments of the present disclosure, a fused epitaxial region, which may be a source / drain region of a FinFET, is formed based on several semiconductor fins forming a fin group. The fused epitaxial region comprises at least one wavy section and one non-wavy section, the term "wavy" referring to the fact that a central section of an upper surface is lower than the upper surfaces of opposing sections grown from semiconductor fins. The non-wavy section serves to prevent bending of the fins for the entire fin group, while the wavy section has a larger contact area than if the section were non-wavy, thereby reducing the contact resistance.Thus, since the fused epitaxial region has both the non-wavy and the wavy sections, problems of reliability such as contact resistance are solved. The embodiments discussed herein are intended to serve as examples to facilitate the manufacture or use of the subject matter of this disclosure, and the person skilled in the art will readily recognize that modifications can be made while remaining within the scope of the various embodiments under consideration. The same reference numerals are used in the different views and illustrative embodiments to designate the same elements. Although the method implementations are described in a specific order, other method implementations can be carried out in any logical sequence.

[0008] Fig. Figures 1, 2A, 2B, 3A, 3B, 3C, 4A, 4B, 4C, 5-7, 8A, 8B, 9, 10, 11A, 11B, and 11C illustrate cross-sectional views of intermediate stages in the formation of FinFETs and the corresponding source / drain regions according to some embodiments of the present disclosure. The corresponding processes are also schematically shown in the process flow in Fig. 12 reproduced.

[0009] Fig. Figure 1 shows a perspective view of a starting structure. The starting structure comprises a wafer 10, which further comprises a substrate 20. The substrate 20 can be a semiconductor substrate, which may be a silicon substrate, a silicon-germanium substrate, or a substrate formed from other semiconductor materials. The top surface of the substrate 20 may have a surface plane. The substrate 20 may be doped with a p-type or an n-type impurity. Isolation regions 22, such as shallow trench isolation regions (STI), may be formed to extend from a top surface of the substrate 20 into the substrate 20. The associated process is referred to as process 202 in the process flow in Fig. Figure 12 shows the sections of substrate 20 between adjacent STI regions 22, which are referred to as semiconductor strips 24. According to some embodiments, the upper surfaces of the semiconductor strips 24 and the upper surfaces of the STI regions 22 can be substantially planar.

[0010] STI regions 22 can include a lining oxide (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The lining oxide can also be a deposited silicon oxide layer formed, for example, by ALD (Atomic Layer Deposition), HDPCVD (High-Density Plasma Chemical Vapor Deposition), or CVD (Chemical Vapor Deposition). STI regions 22 can also include a dielectric material over the lining oxide, the dielectric material being formed using FCVD (Flowable Chemical Vapor Deposition), spin-on deposition, or the like. According to some embodiments, the STI regions 22 can include STI regions 220 located on the outer surfaces of the fin groups, as explained below, and STI regions 221 formed in inner-group gaps in fin groups.STI areas 220 can have a greater height than STI areas 221.

[0011] According to some embodiments, the upper sections 24T of the semiconductor strips 24 are formed from a material different from the material of the main part of the semiconductor substrate 20. For example, the upper sections 24T can be formed from silicon-germanium, which may have a germanium atom content of about 15 percent to about 30 percent. According to some embodiments, the upper sections 24T are formed prior to the formation of the STI regions 22 and are formed by an epitaxial process for the deposition of silicon-germanium onto the substrate 20. The upper sections 24T can also have a lower section formed from the same material as the underlying bulk section of the semiconductor substrate 20. The STI regions 22 are then formed by etching certain sections of the epitaxial silicon-germanium layer and the underlying substrate 20, and by depositing dielectric materials.According to alternative embodiments, the upper sections 24T are formed after the formation of the STI areas 22 by etching the sections of the substrate 20 between the STI areas 22 and subsequently performing an epitaxy process to grow a semiconductor material such as silicon germanium into the resulting recesses.

[0012] With reference to Fig. 2A and Fig. 2B excludes the STI areas 22. Fig. Figure 2B shows a cross-sectional view of the reference cross-section BB in Fig. 2A. Fig. 2A, however, shows the left part of the Fig. 2B structure shown. The upper sections of the semiconductor strips 24 protrude higher than the upper surfaces 22A of the STI areas 22 to form protruding fins 24', the protruding fins 24A' in the device area 100A ( Fig. 2B) and protruding fins 24B' ( Fig. 2B) in the device area 100B. The associated process is designated as process 204 in the process flow in Fig. Figure 12 shows the sections of the semiconductor strips 24 in the STI areas 22, which are still referred to as semiconductor strips.

[0013] With reference to Fig. In 2B, the protruding fins 24A' are collectively referred to as a fin group 25A, and the protruding fins 24B' are collectively referred to as a fin group 25B. According to some embodiments, the inner distance S1 between adjacent fins in an identical fin group 25A and 25B is smaller than the intergroup distance S2, e.g., to a ratio S2 / S1 greater than approximately 2 or greater than approximately 5. The etching of the STI regions 22 can be carried out using a dry etching process, wherein a mixture of HF and NH3 can be used as the etching gas. The etching can also be carried out using a mixture of NF3 and NH3 as the etching gas. A plasma can be generated during the etching process. Furthermore, argon can be included. According to alternative embodiments of the present disclosure, the etching of the STI regions 22 is carried out by a wet etching process. The etching chemical can, for example, contain HF solution.

[0014] According to some embodiments, the fins for forming the FinFETs can be formed / structured by any suitable method. For example, the fins can be structured by one or more photolithography processes, including dual-structuring or multiple-structuring processes. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes so that structures can be produced that, for example, have smaller pitches than can otherwise be achieved by a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured by a photolithography process. Spacers are formed along the structured sacrificial layer by a self-aligning process.The sacrificial layer is then removed and the remaining spacers or spikes can then be used to structure the fins.

[0015] As in Fig. As shown in Figure 2B, wafer 10 contains a first device area 100A and a second device area 100B, each for forming a FinFET. The FinFET formed in the first device area 100A can be a p-type FinFET, while the FinFET formed in the second device area 100B can be an n-type or a p-type FinFET. To distinguish the features in device area 100A and device area 100B, a feature formed in device area 100A can be designated with a reference numeral ending in A, and a feature formed in device area 100B can be designated with a reference numeral ending in B.For example, the semiconductor strips 24 in the device area 100A are marked 24A, which together are referred to as a strip group 25A, and the semiconductor strips 24 in the device area 100B are marked 24B, which together are referred to as a strip group 25B.

[0016] According to some embodiments, the upper surfaces 22A of the STI areas 22 can be higher, lower, or at the same level as the lower surfaces of the upper sections 24T (see Fig. 1) Thus, the entirety of the protruding fins 24A' after the recess of the STI regions 22 may be formed from silicon germanium and may or may not extend downwards into the spaces between the remaining STI regions 22. Alternatively, the lower sections of the protruding fins 24A' may be formed from silicon, while the upper sections of the protruding fins 24A' may be formed from silicon germanium.

[0017] With reference to Fig. 3A, Fig. 3B and Fig. 3C Dummy gate stacks 30 are formed on the upper surfaces and side walls of the protruding fins 24A' and 24B'. The associated process is designated as process 206 in the process flow in Fig. 12 shown. The in Fig. 3B and Fig. The cross-sections shown in 3C result along the reference cross-sections BB and CC in Fig. 3A. In Fig. 3C and the following Fig. 11C can determine the level of the upper surfaces 22A of the STI areas 22 (see also Fig. 3A) is shown and the semiconductor fins 24A' and 24B' are higher than the upper surfaces 22A. Lower surfaces 22B (see also Fig. 3A) of the STI areas 221 are also shown in the cross-sectional views. The STI areas 22I lie in the planes between 22A and 22B and are shown in Fig. 3C and Fig. 11C is not shown because it lies in different planes than those shown there.

[0018] Dummy gate stack 30 can dummy gate dielectrics 32 ( Fig. 3C) and dummy gate electrodes 34 over the dummy gate dielectrics 32. The dummy gate electrodes 34 can be made of, for example, amorphous silicon or polysilicon, although other materials may also be used. Each of the dummy gate stacks 30 can also have one (or more) hard mask layers 36 over the dummy gate electrode 34. The hard mask layers 36 can be made of silicon nitride, silicon carbon nitride, or the like. The dummy gate stacks 30 also have longitudinal directions that are perpendicular to the longitudinal directions of the projecting fins 24A' and 24B'. According to some embodiments, the dummy gate stacks 30 on the projecting fins 24A' and the dummy gate stacks 30 on the projecting fins 24B' are discrete dummy gate stacks that are physically separated from one another.According to alternative embodiments, one and the same dummy gate stack 30 can extend to both the protruding fins 24A' and the protruding fins 24B'.

[0019] Next, gate spacers 38 ( Fig. 3A and Fig. 3C) formed on the side walls of the dummy gate stack 30. The associated process is designated as process 208 in the process flow in Fig. Figure 12 illustrates this. According to some embodiments of the present disclosure, the gate spacers 38 are formed from dielectric materials such as silicon carbon oxynitride (SiCN), silicon nitride, silicon oxycarbon oxynitride (SiOCN), or the like, and can have a single-layer structure or a multi-layer structure with multiple dielectric layers. The fabrication processes include the deposition of conformal spacer layers and the subsequent performance of anisotropic etching processes to form the gate spacers 38 (and fin spacers 39). According to some embodiments of the present disclosure, the gate spacers 38 are multi-layer gate spacers. For example, each of the gate spacers 38 can have a SiN layer and a SiOCN layer over the SiN layer. Fig. 3A and Fig. Figure 3C further shows fin spacers 39 formed on the side walls of the projecting fins 24'. The associated process is also referred to as process 208 in the process flow in Fig. 12 shown.

[0020] According to some embodiments of the present disclosure, the fin spacers 39 (including 39A, 39B, 39C, 39D, 39E, 39F, 39A', 39B', 39C' and 39D' ( Fig. 3B)) by the same methods for forming gate spacers 38. For example, in the method for forming gate spacers 38, the area-covering dielectric layer (or such layers) deposited to form gate spacers 38 may, when etched, leave some sections on the sidewalls of the protruding fins 24A' and 24B', thereby forming fin spacers 39. According to some embodiments, the fin spacers 39 comprise outer fin spacers such as fin spacers 39A, 39F, 39A' and 39D' ( Fig. 3B), which are located on the outer sides of the outermost fins in the fin group. The fin spacers 39 further comprise inner fin spacers such as fin spacers 39B, 39C, 39D, 39E, 39B' and 39C', wherein the inner fin spacers 39B, 39C, 39D, 39E are arranged between the fins 24A' and the inner fin spacers 39B' and 39C' are arranged between the fins 24B'.

[0021] With reference to Fig. 4A, Fig. 4B and Fig. 4C the sections of the protruding fins 24A' and 24B' that are not covered by the dummy gate stacks 30 and the gate spacers 38 are recessed, forming recesses 40A and 40B ( Fig. 4B). The associated process is designated as process 210 in the process flow in Fig. 12 shown. Fig. 4B and Fig. Figures 4C show the cross-sectional views derived from the reference cross-sections BB and CC in Fig. 4A. The recess can be anisotropic, and therefore the sections of the fins 24' that lie directly beneath the dummy gate stacks 30 and the gate spacers 38 are protected and not etched. According to some embodiments, the upper surfaces of the recessed semiconductor fins 24' can be higher than the upper surfaces 22A of the STI areas 22 and can be higher than the remaining fin spacers 39.

[0022] According to some embodiments, during the etching of the protruding fins 24', the fin spacers 39 are also etched, thus reducing their height. The fin spacers 39A, 39B, 39C, 39D, 39E, 39F each have heights H1, H2, H3, H4, H5 and H6 ( Fig. 4B). The etching of the fin spacers 39 can be carried out simultaneously with the recessing of the fins 24', whereby one or more etching gases for etching the fin spacers 39 are added to the etching gas for recessing the protruding fins 24'.

[0023] According to some embodiments of the present disclosure, the recessing of the protruding fins 24' is carried out by a dry etching step. The dry etching can be carried out using process gases such as C2F6, CF4, SO2, a mixture of HBr, Cl2 and O2, a mixture of HBr, Cl2, O2 and CF2, or the like. The etching can be anisotropic. According to some embodiments of the present disclosure, as in Fig. As shown in Figure 4C, the side walls of the projecting fins 24' facing the recess 40 are substantially vertical and are substantially flush with the outer side walls of the gate spacers 38. The side walls of the projecting fins 24A' and 24'B facing the recess 40 may lie on (110) surface planes of the respective projecting fins 24A' and 24B'. With reference to Fig. 4B is the position of the recesses 40A and 40B, which are also the removed sections of the protruding fins 24', shown by dashed lines. The dashed lines also represent the protruding fins 24', which are located directly below the dummy gate stacks 30 ( Fig. 4C) lie in a plane other than the one shown.

[0024] When removing the protruding fins 24', a process gas is also added for etching the fin spacers 39 in order to remove the fin spacers 39. According to some embodiments, the process gases and process conditions for etching the fin spacers 39 (during the recessing of the protruding fins 24') are adjusted to achieve the following relationships: (H1 > H6), (H1 > (H2 & H3) > (H4 & H5)), and ((H6 > (H2 & H3) > (H4 & H5)). Heights H2 and H3 may also be equal to or close to heights H4 and H5. Alternatively, the left outer fin 39A has a height H1 greater than the height H6 of the right outer fin 39F, and heights H1 and H6 of both outer fins are greater than heights H2, H3, and H4 of the inner fins. Heights H2 and H3 of the left inner fins may also be greater than or equal to heights H4 and H5 of the right inner fins.The etching of the fin spacers 39 can be carried out using a fluorinated gas such as a mixture of CF4, O2, and N2, a mixture of NF3 and O2, SF6, a mixture of SF6 and O2, or the like, and can include a gas such as argon for bombarding the outer spacers 39A. The adapted process conditions for achieving the desired fin spacer heights include, among other things, the partial pressures of the etching and bombardment gases, the preload, and / or the like. Furthermore, the loading effect can be used to achieve the desired fin spacer heights. For example, the ratio S2 / S1, which is the ratio of the intergroup spacing S2 to the ingroup spacing S1, can be adjusted to control the loading effect, allowing the heights H1, H2, H3, H4, H5, and H6 to be set.

[0025] According to some embodiments, after etching the protruding fins 24', in which the fin spacers 39 are also recessed, an additional etching process is carried out to further etch the fin spacers 39 and adjust the heights of the protruding fins 39. In this process, the protruding fins 24' are not recessed. According to alternative embodiments, the additional etching process is omitted. The additional etching process (if carried out) can also be performed by an anisotropic etching process, in which, for example, similar process gases are used as in the manufacture of the fin spacers. According to some embodiments, the preceding processes may not achieve the relationships (H1 > H6), (H1 > (H2 & H3) > (H4 & H5)), and ((H6 > (H2 & H3) > (H4 & H5)). For example, in the preceding manufacturing of fin spacers 39, the height H1 may unfortunately be smaller than the height H6.The etching process therefore adjusts the heights of the fin spacers so that height H1 is greater than H6. Alternatively, the aforementioned ratios can already be achieved through the prior production of the fin spacers 39, but the ratios between the fin spacer heights H1, H2, H3, H4, H5, and H6 may not be satisfactory. Therefore, the additional etching process can be carried out to adjust the ratios to the desired values.

[0026] In the above described procedures, the height H1', ​​H2', H3' and H4' of the respective fin spacers 39A', 39B', 39C' and 9D' can also be set so that the height H1' is greater than H4' and the two heights H1' and H4' are greater than the heights H2' and H3'.

[0027] With reference to Fig. 5. The epitaxial layers 48-1 (also referred to as epitaxial layers L1, comprising 48-11, 48-12, and 48-13) are deposited by an epitaxial process. The associated process is designated as process 212 in the process flow diagram in Fig. 12. According to some embodiments, the deposition is carried out by a non-conforming deposition process, so that the lower section ( Fig. 11C) of the first layer 48-1 is thicker than the sidewall sections. Deposition can be carried out by RPCVD, PECVD, or the like. According to some embodiments, the epitaxial layers 48-1 are formed from or contain SiGeB. The process gas for deposition of the epitaxial layer 48-1 can contain a silicon-containing gas such as silane, disilane (Si₂H₆), dicholorosilane (DCS), or the like; a germanium-containing gas such as germanium (GeH₄), digermane (Ge₂H₆), or the like; and a dopant-containing process gas such as B₂H₆ or the like, depending on the desired composition of the epitaxial layer 48-1. Additionally, an etching gas such as HCl can be added to achieve selective deposition on the semiconductor but not on the dielectric. The epitaxial layer 48-1 can have a boron concentration of about 5–10 19 / cm 3 and about 8 · 10 20 / cm 3The germanium atom content can range from approximately 15 percent to approximately 45 percent. The germanium atom percentage can exhibit a gradient, with higher percentages in the higher ranges than in the corresponding lower ranges.

[0028] As in Fig. As shown in Figure 5, the epitaxial layers 48-1 extend laterally and grow towards each other. On the other hand, the epitaxial layers 48-1, which have grown from different protruding fins 24A' and 24B', are still separate from each other and not fused together. The upper ends of the epitaxial layers 48-1 are controlled to be lower than the upper surfaces of the original, uncut, protruding fins 24', for example, by a difference of about 5 nm to about 10 nm. According to some embodiments, the upper end of the epitaxial layer 48-11 is higher than the upper end of the epitaxial layer 48-13 due to the aforementioned relationship between the heights H1 to H6. Furthermore, the upper end of the epitaxial layer 48-11 can be at the same level as, or higher than, the upper end of the epitaxial layer 48-12.

[0029] With reference to Fig. 6. The epitaxial layers 48-2 (also referred to as epitaxial layer L2) are deposited. The associated process is described as process 214 in the Fig. The process sequence is illustrated in Figure 12. The deposition process can be carried out by RPCVD, PECVD, or the like. According to some embodiments, the epitaxial layer 48-2 contains SiGeB, wherein the boron has a second boron concentration that is higher than the boron concentration in the epitaxial layer 48-1. For example, according to some embodiments, the boron concentration in the epitaxial layer 48-2 can be approximately 5 × 10⁻⁶. 2 / cm 3 and about 3 · 10 21 / cm 3Furthermore, the germanium atom content in epitaxial layer 48-2 is higher than the germanium atom content in epitaxial layers 48-1. For example, according to some embodiments, the germanium atom percentage in epitaxial layer 48-2 can be approximately 40 percent to approximately 65 percent. The process gas for the formation of epitaxial layers 48-2 can be similar to the process gas for the formation of epitaxial layers 48-1, except that the flow rates of the process gases for the formation of epitaxial layers 48-2 can differ from the flow rates of the corresponding process gases for the formation of epitaxial layers 48-1.

[0030] Following the epitaxial process for the deposition of the epitaxial layers 48-2, a (re-)etching process is carried out. According to some embodiments of the present disclosure, the re-etching process is isotropic. According to some embodiments, the etching process is carried out using an etching gas such as HCl and a carrier gas(es) such as H₂ and / or N₂. Additionally, a germanium-containing gas such as German (GeH₄) may be added to the etching gas. A silicon-containing gas such as silane (SiH₄) may be added to the etching gas, but this is not required. The addition of the germanium-containing gas (and the possible silicon-containing gas) leads to a deposition effect that occurs simultaneously with the etching effect. However, the etching rate is greater than the deposition rate, so the net effect is the re-etching of the epitaxial layer 48-2.The addition of the germanium- and silicon-containing gas reduces the net etch rate, so that the thickness of the epitaxial layer 48-2 is not significantly reduced when the surface profile of the epitaxial layers 48-2 is reshaped. The deposition and etching are optimized so that the epitaxial layers 48-2 have a desirable thickness. As in . Fig. As shown in Figure 6, the upper surfaces of the epitaxial layer 48-2 are reshaped to produce (111)-facets, particularly on the section of the epitaxial layer 48-2 which has grown from the protruding fin located furthest to the right in fin group 25A and the protruding fin located furthest to the left in fin group 25B.

[0031] The upper ends of the epitaxial layer 48-2 are controlled so that they are flush with the upper ends of the original, non-recessed, protruding fins 24A' or at least close to them (e.g. with a difference of less than about 5 nm or less than about 3 nm). Fig. Figure 11C illustrates the cross-sectional views of the reference cross-sections CC in Fig. 6 and shows that the opposite ends of the epitaxial layer 48-2 are flush with the upper surfaces of the protruding fins 24A', with the middle section of the upper surface of the epitaxial layer 48-2 being flush with the upper surfaces of the respective protruding fins 24A' and 24B' or slightly lower.

[0032] Referring back to Fig. 6. The epitaxial layers 48-2, which grow from adjacent recesses, fuse together, enclosing the air gap 44 beneath the epitaxial layer 48-2. The upper surface of the fused epitaxial layer 48-2 may have a non-planar profile (also described as wavy), with the central section, located laterally between adjacent fins 24A', being lower than the sections on its opposite sides. The non-recessed sections may lie directly above the protruding fins 24A'. Due to the different heights of the fin spacers H1, H2, H3, H4, H5, and H6, recesses 46A and 46B are formed. Recess 46A lies laterally between the two left protruding fins 24A' (and is higher than them), while recess 46B lies laterally between the two right protruding fins 24A' (and is higher than them).According to some embodiments, the recess depth D1 of recess 46A is smaller than the recess depth D2 of recess 46B, e.g. to a ratio D2 / D1 that is greater than about 1.5, greater than about 2 or is about 1.5 to about 5.

[0033] Fig. Figure 7 shows the epitaxial process for the deposition of epitaxial layer 48-3 (also referred to as epitaxial layer L3 or as a cover layer). The associated process is designated as process 216 in the Fig. The process sequence is illustrated in Figure 12. The deposition process can be carried out by RPCVD, PECVD, or the like. According to some embodiments, the epitaxial layer 48-3 contains SiGeB. The boron concentration in the epitaxial regions 48-3 can be approximately 5 × 10 20 / cm 3 up to about 1 x 10 21 / cm 3Furthermore, the germanium atom fraction in epitaxial layer 48-3 can be greater, equal to, or less than the germanium atom fraction in epitaxial layers 48-2. For example, according to some embodiments, the germanium atom fraction in epitaxial layers 48-3 can be approximately 45 percent to approximately 55 percent.

[0034] Following the epitaxial process for the deposition of the epitaxial layers 48-3, a (re-)etching process is carried out. According to some embodiments of the present disclosure, the re-etching process is isotropic. According to some embodiments, the etching process is carried out using an etching gas such as HCl and a carrier gas(es) such as H₂ and / or N₂. Additionally, a germanium-containing gas such as German (GeH₄) may be added to the etching gas. A silicon-containing gas such as silane (SiH₄) may be added to the etching gas, but this is not necessary. The addition of the germanium-containing gas leads to a deposition effect that occurs simultaneously with the etching effect. However, the etching rate is greater than the deposition rate, so that the net effect results in the re-etching of the epitaxial layer 48-3.The addition of the germanium-containing gas reduces the net etch rate, so that the thickness of the epitaxial layer 48-3 is not significantly reduced when the surface profile of the epitaxial layers 48-3 is reshaped. The deposition and etching are optimized so that the epitaxial layers 48-3 have a desirable thickness. As in . Fig. As shown in Figure 7, the upper surfaces and the sidewall surfaces of epitaxial layer 48-3 are reshaped to generate more (111) facets, particularly the portion of epitaxial layer 48-3 that grows from the protruding fin located furthest to the right in fin group 25A and the protruding fin located furthest to the left in fin group 25B. Furthermore, the formation of more and better (111) facets results in sharper corners. Throughout this description, epitaxial layers 48-1, 48-2, and 48-3 are referred to collectively and individually as epitaxial layers (epitaxial regions) 48, which are hereinafter collectively referred to as source / drain regions 48A and 48B.

[0035] According to some embodiments, the epitaxial region 48A has raised sections that are higher than the upper surface 24'TS of the projecting fins 24A'. The raised height RH1 directly above the leftmost projecting fin 24A' is greater than the raised height RH3 directly above the rightmost projecting fin 24A' and may be equal to or slightly greater (e.g., with a difference of less than about 2 nm) than the raised height RH2.

[0036] The epitaxial layer 48-3 has an upper surface 48-3TS, which is also the upper surface of the source / drain region 48. According to some embodiments, the section 45A of the source / drain region 48, formed on the basis of the two leftmost protruding fins 24A', has a conical shape, and the upper surface of section 45A is generally flat and may have a convex upper surface. For example, the upper surface of the epitaxial layer 48-3 may be flat from the right edge of the first protruding fin (counting from the left) to the right edge of the second protruding fin 24' (counting from the left). Alternatively, this section of the upper surface may be round (as indicated by the dashed line 47) and have a convex shape, with the highest point (in the middle) located between the first and second protruding fins.Alternatively, the increased height RH4 is greater than the increased heights RH1, RH2, and RH3. Furthermore, the upper surface of the right-hand section of the source / drain region 48, formed on the basis of the two right-hand protruding fins 24A', is corrugated (concave), with this right-hand section encompassing section 45B and the right-hand portion of section 45A, forming a significant recess 46C. According to some embodiments, the depth D3 of the recess 46C is greater than approximately 3 nm and can range from approximately 3 nm to approximately 15 nm. Thus, overall, the left side of the upper surface of the source / drain region 48 is flatter and higher than the right side, with the left side being the side farther from the adjacent fin group 25B, while the right side is the side closer to the adjacent fin group 25B.

[0037] The epitaxial region 48B can comprise layers 48-1, 48-2, and 48-3. According to some embodiments, the epitaxial region 48B is p-type and can be formed in the same process as the epitaxial region 48A. According to alternative embodiments, the epitaxial region 48B is n-type and belongs to an n-type FinFET and is therefore formed in a different process than the epitaxial region 48A. The epitaxial region 48B can have a conical shape (with a convex upper surface) if, for example, the epitaxial region 48B is p-type. Alternatively, the epitaxial region 48B can have a corrugated upper surface, as indicated by the dashed line 50, which can occur if the epitaxial region 48B is n-type.According to some embodiments, the upper surface of the epitaxial area 48B may be flat or slightly inclined, with the section closer to the fin group 25A being lower than the section farther from the fin group 25A.

[0038] With reference to Fig. 8A and Fig. 8B, the contact etch stop layer (CESL) 66 and the interlayer dielectric (ILD) 68 are formed over the epitaxial regions 48A and 48B. The associated process is designated as process 218 in the process flow diagram in Fig. 12 shown. A planarization process, such as a CMP (Chemical Mechanical Polish) or a mechanical grinding process, is carried out to remove excess sections of the CESL 66 and the ILD 68 until dummy gate stack 30 ( Fig. 4A and Fig. 4C) will be exposed.

[0039] The dummy gate stacks 30 ( Fig. 4A and Fig. 4C) are then removed in an etching process and replaced by replacement gate stack 56, as in Fig. 8A shows the corresponding process. The associated process is shown as processes 220 and 222 in the process flow in Fig. Figure 12 shows that the replacement gate stacks 56 comprise gate dielectrics 58, which also include interface layers on the upper surfaces and sidewalls of the projecting fins 24' and high-k dielectrics over the interface layers. The replacement gate stacks 56 further include gate electrodes 60 over the gate dielectrics 58. After the formation of the replacement gate stacks 56, recesses are made in the stacks to form trenches between the gate spacers 38. A dielectric material such as silicon nitride, silicon oxynitride, or the like is filled into the resulting trenches to form dielectric hard masks 62. The associated process is shown as process 224 in the process flow in Figure 12. Fig. 12 shown.

[0040] As in Fig. As shown in Figure 9, the ILD 68 and the CESL 66 are etched next to form the source / drain contact opening 70. The associated process is shown as process 226 in the process flow in Fig. Figure 12 illustrates this. The epitaxial layers 48-3 are also etched through, and the upper surfaces of the epitaxial layers 48-2 are exposed. The opening 70 can extend into the epitaxial regions 48A and 48B to a depth of approximately 5 nm to approximately 10 nm. The etching can be controlled to stop at the epitaxial layers 48-2, except for a small over-etch (e.g., less than approximately 2 nm) on the epitaxial layers 48-2. The exposed upper surface of the epitaxial layers 48-2 is wavy, and the recesses 46A and 46B can be exposed such that the exposed upper surface of the epitaxial layers 48-2 exhibits V-shaped sections in cross-sectional view.It is conceivable that the overall structure, including the CESL 66 and the ILD 68, will prevent the bending of the protruding fins at this stage of the manufacturing process, although the left section of the epitaxial area is no longer non-wavy and also exhibits the wavy upper surface.

[0041] Since the flat sections of epitaxial layers 48-2 are etched more slowly than the sections with corners, the right-hand sections 48-2R, which have more corners than the left-hand sections, are etched more than the sections 48-2L, which have a flatter surface. Thus, the top of section 48-2R is lower than the top of section 48-2L, with their upper surfaces exhibiting a height difference ΔH1 of more than approximately 3 nm, ranging from approximately 2 nm to approximately 10 nm. Overall, the side of epitaxial region 48A facing epitaxial region 48B is lower than the side facing away from epitaxial region 48B. The exposed upper surface of epitaxial layers 48-2 exhibits recesses (round cavities) 46A' and 46B'.

[0042] As in Fig. As shown in Figure 10, source / drain silicide zones 72A and 72B are formed next. The associated process is shown as process 228 in the process flow diagram in Figure 10. Fig. Figure 12 illustrates this. According to some embodiments of the present disclosure, the formation of the source / drain silicide regions 72A and 72B comprises the deposition of a metal layer, such as a titanium layer, a cobalt layer, or the like, extending into the opening 70, and subsequently performing an annealing process such that lower portions of the metal layer react with the epitaxial layers 48-2 to form the silicide regions 72A and 72B. The remaining, unreacted metal layer can be removed.

[0043] Fig. 11A, Fig. 11B and Fig. Figure 11C shows the formation of the contact plug(s) 74. The respective process is designated as process 230 in the process flow in Fig. 12 shown. As in Fig. As shown in Figure 11B, the source / drain contact plug 74 is formed such that it fills the opening 70 and electrically connects the source / drain silicide areas 72A and 72B. Thus, FinFET 76A and FinFET 76B ( Fig. 11B) is formed and the source / drain areas 48A and 48B are electrically connected to each other by the contact plug 74. Fig. Figure 11B shows the reference cross-section BB in Fig. 11A and Fig. 11C shows the reference cross-section CC in Fig. 11A. As in Fig.As shown in Figure 11B, the upper surface of the epitaxial regions 48A is asymmetrical and inclined, with the inner sections, which are closer to the epitaxial region 48B, being lower than the outer sections, which are farther from the epitaxial region 48B. The silicide regions 72A and 72B are inclined accordingly. According to some embodiments, the upper surface of the inner sections of the silicide region 72A is lower than the corresponding outer sections by a height difference ΔH2, which may be greater than about 2 nm and may range from about 2 nm to about 10 nm. The silicide region 72A may have recesses (circular cavities) 46A'' and 46B''. Furthermore, the silicide areas 72A and 72B extend to the side wall of the epitaxial areas 48A and 48B, thus increasing the contact areas between the silicide areas 72A and 72B and the respective epitaxial areas 48A and 48B and reducing the contact resistance.

[0044] The embodiments of the present disclosure exhibit several advantageous features. By forming a first section of the epitaxial region such that it is non-wavy (has a conical shape), the bending of all semiconductor fins in a fin group on which the epitaxial region is formed can be reduced, since the non-wavy section acts as an anchor to prevent bending of the remaining semiconductor fins. By producing a second section of the epitaxial region with a wavy upper surface, the contact area is reduced. Furthermore, the epitaxial regions with the wavy shape have more sharp corners, which are etched during the formation of the source / drain silicide region and the contact plug, so that the corresponding silicide region extends to the side wall of the epitaxial region and the contact resistance is further reduced.

[0045] The invention is defined by the main claim and the dependent claims. The subclaims describe further embodiments of the invention.

Claims

[1] Procedure encompassing: Recessing of insulating areas (22) on opposite sides of a first semiconductor strip (24), a second semiconductor strip (24) and a third semiconductor strip (24) to form a first semiconductor fin (24A'), a second semiconductor fin (24A') and a third semiconductor fin (24A'); Forming a gate stack (30) on the first semiconductor fin (24A'), the second semiconductor fin (24A') and the third semiconductor fin (24A'); Forming gate spacers (38) on side walls of the gate stack (30); Forming fin spacers (39) on side walls of the first semiconductor strip (24), the second semiconductor strip (24) and the third semiconductor strip (24); Performing a recession process to recess the first semiconductor strip (24), the second semiconductor strip (24), and the third semiconductor strip (24) to form a first recess (40A), a second recess (40A), and a third recess (40A); and Performing an epitaxy process to form an epitaxy area (48A) starting from the first recess (40A), the second recess (40A) and the third recess (40A), wherein the epitaxial area (48A) has an upper surface which has: - a convex section (45A) that is higher than the first semiconductor fin (24A') and the second semiconductor fin (24A') and lies laterally between them; and - a concave section (46C) that is higher than the second semiconductor fin (24A') and the third semiconductor fin (24A') and is located laterally between them; wherein the epitaxial area (48A) has a first epitaxial layer (48-1), a second epitaxial layer (48-2) and a third epitaxial layer (48-3), wherein the third epitaxial layer has a first part with the convex section (45A) of the upper surface and a second part with the concave section (46C) of the upper surface, and the procedure further includes: Etching through the first part of the third epitaxial layer (48-3) to expose a concave upper surface of the second epitaxial layer (48-2). [2] Method according to claim 1, wherein the fin spacers (39) further comprise: a first outer fin spacer (39A) with a first height (H1); a second outer fin spacer (39F) with a second height (H6) that is smaller than the first height; and inner spacers (39B, ..., 39E) between the first outer fin spacer (39A) and the second outer fin spacer (39F), wherein the inner spacers have heights (H2, ..., H5) that are less than the first height (H1) and the second height (H6). [3] Method according to claim 1 or 2, wherein the fin spacers (39) are etched simultaneously during the recessing process, the method further comprising: after the recession process, further recession of the fin spacers (39). [4] Method according to claim 2, wherein the first semiconductor fin (24A'), the second semiconductor fin (24A') and the third semiconductor fin (24A') form a first fin group (25A), wherein the first fin group is adjacent to a second fin group (25B), and the second outer fin spacer (39F) faces the second fin group and the first outer fin spacer (39A) faces away from the second fin group. [5] Method according to any of the preceding claims, wherein, after the recession of the first semiconductor fin (24A'), the second semiconductor fin (24A') and the third semiconductor fin (24A'), the upper surfaces of the first semiconductor fin, the second semiconductor fin and the third semiconductor fin are higher than the upper ends of the fin spacers (39). [6] Method according to any of the preceding claims, further comprising forming a silicide region (72A) on the second epitaxial layer (48-2), wherein the silicide region comprises: a first section (46A') directly on the concave upper surface of the second epitaxial layer (48-2); and a second section directly above the third semiconductor fin (24A'), with the first section of the silicide area (72A) being higher than the second section of the silicide area. [7] Method according to any of the preceding claims, wherein the third epitaxial layer (48-3) has a lower boron concentration than the second epitaxial layer (48-2). [8] Method according to any of the preceding claims, wherein the epitaxy process comprises: deposition of silicon germanium boron. [9] Method according to claim 8, wherein the second epitaxial layer (48-2) has a higher boron concentration than the first epitaxial layer (48-1). [10] Procedure encompassing: Forming a first fin group (25A) and a second fin group (25B), wherein the first fin group has several semiconductor fins (24A') with inner group distances (S1), wherein the first fin group and the second fin group have an intergroup distance (S2) that is larger than the inner group distances, which feature multiple semiconductor fins (24A'): - a first semiconductor fin (24A') wherein, in the first fin group (25A), the first semiconductor fin is furthest away from the second fin group (25B); - a second semiconductor fin (24A'); and - a third semiconductor fin (24A'), wherein, in the first fin group (25A), the third semiconductor fin is closest to the second fin group (25B); and performing an epitaxy process to form an epitaxy region (48A) based on the multiple semiconductor fins (24A'), the epitaxial area (48A) exhibits: - a first section in the middle between the first semiconductor fin (24A') and the second semiconductor fin (24A'), wherein the first section has a first upper surface; and - a second section in the middle between the second semiconductor fin (24A') and the third semiconductor fin (24A'), wherein the second section has a second upper surface which is lower than the first upper surface; wherein a section of the epitaxial region (48A) between the first semiconductor fin (24A') and the second semiconductor fin (24A') has a convex upper surface (47); and the procedure further includes: Forming a silicide area (72A), wherein forming the silicide area comprises: removing the portion of the epitaxial area (48A) with the convex upper surface (47) to form a concave upper surface (46A) of the epitaxial area, and forming the silicide area (72A) on the concave upper surface (46A) of the epitaxial area (48A). [11] Method according to claim 10, wherein the first section has a first highest point laterally between the first semiconductor fin (24A') and the second semiconductor fin (24A'), wherein the epitaxial region (48A) further has a third section directly above the third semiconductor fin (24A'), wherein the third section has a second highest point, wherein the first highest point is higher than the second highest point. [12] Method according to claim 10 or 11, wherein an upper surface of the epitaxial region (48A) has a recess (46C) laterally between the second semiconductor fin (24A') and the third semiconductor fin (24A'). [13] Method according to claim 12, wherein the recess has a depth of about 3 nm to about 15 nm. [14] Method according to any one of claims 10 to 13, wherein the epitaxy process comprises: Deposition of silicon germanium boron. [15] Method according to claim 14, wherein the second epitaxial layer (48-2) has a higher boron concentration than the first epitaxial layer (48-1). [16] Procedures, including: Forming a first fin group (25A) and a second fin group (25B), wherein the first fin group has several semiconductor fins (24A') with in-group spacings (S1), wherein the first fin group has a first semiconductor fin (24A') that is furthest away from the second fin group, a second semiconductor fin (24A') and a third semiconductor fin (24A') that is closest to the second fin group; Forming a gate stack (30) on the first fin group (25A); Forming gate spacers (38) on side walls of the gate stack (30); Forming fin spacers (39), comprising: - a first outer fin spacer (39F) facing the second fin group (25B), wherein the first outer fin spacer has a first height (H6); - a second outer fin spacer (39A) facing away from the second fin group (25A), wherein the second outer fin spacer has a second height (H1) that is greater than the first height (H6); and - inner spacers (39B, ..., 39E) between the first outer fin spacer (39F) and the second outer fin spacer (39A); Performing epitaxial processes to form a first epitaxial area (48A) based on the first group of fins (25A) and a second epitaxial area (48B) based on the second group of fins (25B); and Forming a source / drain contact plug (74) that electrically connects the first epitaxy area (48A) and the second epitaxy area (48B); wherein the first epitaxial area (48A) has an upper surface, and the upper surface has: a first section (45A) that lies laterally between the first semiconductor fin (24A') and the second semiconductor fin (24A') and higher than the latter, wherein the first section has a convex upper surface; and a second section (46C) laterally between the second semiconductor fin (24A') and the third semiconductor fin (24A'), wherein the second section has a concave upper surface. [17] Method according to claim 16, wherein the fin spacers (39) are formed such that the inner spacers (39B, ..., 39E) have a height (H2, ..., H5) that is smaller than the first height (H6) and the second height (H1). [18] Method according to claim 16 or 17, wherein the first fin group (25A) and the second fin group (25B) have an intergroup distance (S2) which is larger than the ingroup distances (S1). [19] Method according to claim 16, 17 or 18, wherein the source / drain contact plug (74) has a bottom surface with a section that overlaps the first epitaxy area (48A), wherein the bottom surface is inclined, wherein sections of the bottom surface that are closer to the second fin group (25B) are lower than sections of the bottom surface that are farther away from the second fin group.

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