Magnetic tunnel transition structures with protective outer layers

Abstract

Integrated circuit, including: a vertical magnetic tunnel transition stack (124) comprising a first magnetic layer (206), a second magnetic layer (210) and a barrier layer (208) between the first magnetic layer (206) and the second magnetic layer (210); a first electrode (128) below the vertical magnetic tunnel junction stack (124); a second electrode (132) above the vertical magnetic tunnel transition stack (124); a first dielectric layer (144) that laterally envelops the vertical magnetic tunnel junction stack (124); and a second dielectric layer (142) that laterally surrounds the first dielectric layer (144); wherein the first dielectric layer (144) and the second dielectric layer (142) exhibit etch selectivity towards each other; wherein the first dielectric layer (144) contains aluminium oxide and / or aluminium nitride, wherein the vertical magnetic tunnel junction stack (124) is arranged in an interlayer dielectric layer (123) and above an etch stop layer (125), wherein the etch stop layer (125) is arranged below the interlayer dielectric layer (123), wherein the second dielectric layer (142) contains a dielectric material which is designed to be etched out using the same etchant as the etch stop layer (125), and wherein in a region (120) of the integrated circuit, which is located laterally next to the vertical magnetic tunnel junction stack (124), the etch stop layer (125) borders the interlayer dielectric layer (123) from below.

Description

BACKGROUND

[0001] Magnetoresistive random-access memory (MRAM) is a promising technology for non-volatile data storage. The heart of an MRAM memory cell (or "bit") is a magnetic tunnel junction (MTJ), in which a dielectric layer is sandwiched between a magnetically fixed layer (reference layer) and a magnetically free layer (free layer), whose magnetization orientation can be changed. Due to the tunneling magnetoresistance effect, the resistance value between the reference layer and the free layer changes with the change in the magnetization orientation in the free layer. Parallel magnetizations (P-state) result in lower electrical resistance, while antiparallel magnetizations (AP-state) result in higher electrical resistance.The two states of the resistance values are considered as two logical states “1” or “0” which are stored in the MRAM cell.

[0002] In a spin-transfer torque MRAM (STT-MRAM) cell, the write current is applied such that the write current flows through the entire MTJ—that is, the reference layer, the dielectric layer, and the free layer—thus adjusting the magnetization orientation of the free layer through the spin-transfer torque effect. That is, the write current flows through the same path as the read path of the MRAM. In a spin-orbit torque MRAM (SOT-MRAM) cell, an MTJ structure is arranged on a heavy metal layer with a large spin-orbit interaction. The free layer is in direct contact with the heavy metal layer. A spin torque is induced by the in-plane current injected through the heavy metal layer via the spin-orbit coupling effect, which generally includes the Rashba effect and / or the spin Hall effect (SHE effect).The write current does not flow through the vertical MTJ. Instead, the write current flows through the heavy metal layer. The magnetization orientation in the free layer is tuned by the spin-orbit torque effect. Specifically, when an in-plane current is injected into the heavy metal layer, the spin-orbit coupling results in an orthogonal spin current, which generates a spin torque and induces a magnetization reversal in the free layer.

[0003] US 2019 / 0 164 584 A1 describes an MRAM structure comprising an array region and a logic region adjacent to the array region. The array region includes an MTJ structure between a bottom electrode via and a top electrode, a conformal oxide layer over the MTJ structure and the top electrode, and a silicon oxide layer over the conformal oxide layer. The conformal oxide layer and the silicon oxide layer extend from the array region into the logic region.

[0004] US 2019 / 0 165 258 A1 describes a method of manufacturing a memory device, comprising forming a top electrode over an MTJ structure, forming a first spacer covering a sidewall of the MTJ structure, forming a second spacer surrounding the first spacer and exposing the top electrode, and forming a metallization pattern connected to the top electrode and the second spacer.

[0005] DE 10 2019 116 882 A1 describes a method for forming spacer stacks with metal interconnect layers. The method comprises forming MTJ structures on an interconnect layer and depositing a first spacer layer over the MTJ structures and the interconnect layer. The method further comprises disposing a second spacer layer—comprising a metal interconnect—over the first spacer material, the MTJ structures, and the interconnect layer, such that the second spacer layer is thinner than the first spacer layer. The method further comprises depositing a third spacer layer over the second spacer layer and between the MTJ structures. The third spacer is thicker than the second spacer.

[0006] DE 10 2018 108 545 A1 describes a method for manufacturing a semiconductor device with an MRAM cell structure. The MRAM cell structure has a bottom electrode, an MTJ stack, and a top electrode. A first insulating cover layer is formed over the MRAM cell structure. A second insulating cover layer is formed over the first insulating cover layer. The second insulating cover layer has oxygen scavenging capacity.

[0007] US 2017 / 0 053 967 A1 also concerns the production of MRAM structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Aspects of the present invention can best be understood from the following detailed description when considered in combination with the accompanying figures. Throughout the drawings, identical reference numerals indicate similar elements or steps unless the context requires otherwise. The sizes and relative positions of elements in the drawings are not necessarily drawn to scale. Rather, the dimensions of various structures may be arbitrarily exaggerated or reduced for illustrative purposes. Fig. 1 is an exemplary MRAM structure according to exemplary embodiments of the invention. Fig. 2 is an exemplary MRAM cell according to exemplary embodiments of the invention. Fig. 3A to 3D show a wafer at various stages of a first manufacturing process according to exemplary embodiments of the invention. Fig. 4A to 4J show a wafer at various stages of a second manufacturing process according to exemplary embodiments of the invention. Fig. 5A-5D show a wafer at various stages of a third manufacturing process according to exemplary embodiments of the invention. DETAILED DESCRIPTION

[0009] The following disclosure provides many different embodiments or examples of implementing various features of the described subject matter. To simplify the present description, specific examples of components and arrangements are described below. For example, the formation of a first element over or on top of a second element in the following description may include embodiments where the first and second elements are formed in direct contact, and may also include embodiments where additional elements may be formed between the first and second elements such that the first and second elements may not be in direct contact. Furthermore, reference numerals may be repeated throughout the various examples in the present disclosure.This repetition is for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations described.

[0010] Furthermore, for ease of description, relative spatial terms such as "beneath," "beneath," "lower," "above," "upper," and the like may be used herein to describe the relationship of one element or structure to one or more other elements or structures as illustrated in the figures. The relative spatial terms encompass other orientations of the device during use or operation in addition to the orientation illustrated in the figures. The device may be oriented differently (rotated 90 degrees or in other orientations), and the relative spatial terms used herein may also be interpreted accordingly.

[0011] In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the invention. However, one skilled in the art will understand that the invention may be implemented without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques are not described in detail in order not to unnecessarily obscure the descriptions of embodiments of the present invention.

[0012] Unless the context requires otherwise, throughout the specification and claims below, the word "comprise" and variations thereof, such as "comprises" and "comprising", are to be construed in an open, inclusive sense, that is, as "including, but not limited to".

[0013] The use of enumerations such as “first”, “second”, and “third” does not necessarily imply a rank order, but rather can simply distinguish between multiple instances of a step or structure.

[0014] Reference in this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the phrase "in one embodiment" in various places in this specification does not necessarily refer to the same embodiment. Moreover, the individual features, structures, or characteristics may be combined in one or more embodiments in any suitable manner.

[0015] The use of the singular forms "a" and "an" in this specification and the appended claims includes the plural form unless the context clearly dictates otherwise. It should also be noted that the term "or" is generally used to include "and / or" unless the context clearly dictates otherwise.

[0016] The application relates to a method for forming interconnect structures to a magnetic tunnel junction structure (MTJ structure) and to an interconnect element of a logic device in an integrated process. The MTJ structure is formed above a metallization level to which the interconnect element belongs. Therefore, a first interconnect structure to the MTJ structure is shorter than a second interconnect structure to the interconnect element of the logic device and is generally wider than the second interconnect structure to the interconnect element of the logic device. In an integrated opening etch process, in which, for example, the opening to the MTJ structure and the opening to the interconnect element are etched together, the MTJ structure is exposed to a larger dose of etchant.

[0017] Two layers of dielectric materials are formed over the MTJ structure. The two layers of dielectric materials prevent the high dosage of etchant from damaging the MTJ structure. In some embodiments, the outer / top layer of the two layers of dielectric materials comprises the same dielectric material as an etch stop layer disposed between inter-level dielectric layers, e.g., over the interconnect element of the logic device. Thus, the same etch process can remove the outer layer of dielectric material in the opening to the MTJ and the etch stop layer in the opening to the interconnect element. The inner / bottom layer of the two layers of dielectric materials has a high etch selectivity compared to the outer / top layer. Therefore, the etch process at least does not completely remove the inner layer of dielectric material.This means that after the etching process that creates openings to the MTJ structure and the logic device interconnect element, the MTJ structure is still covered by the inner layer. The inner layer of dielectric material is sensitive to an acid solution used for wet cleaning of the interconnect element opening and the MTJ structure opening. The wet cleaning process thus removes the inner / bottom layer of dielectric material exposed in the MTJ structure opening and exposes the MTJ structure in the corresponding opening.

[0018] After wet cleaning, conductive materials are formed in the opening to the MTJ structure and in the opening to the interconnect element in the same metal deposition process.

[0019] In an integrated circuit (IC), an MTJ structure is formed as part of a back-end-of-line process. The MTJ structure comprises a vertical MTJ stack with a free magnetic layer, a fixed magnetic layer, and a barrier layer between the free magnetic layer and the fixed magnetic layer. A spacer, e.g., made of SiN, laterally encloses the MTJ stack. A top electrode and a bottom electrode contact the MTJ stack from a top surface and a bottom surface of the MTJ stack, respectively. Two protective layers of dielectric materials are arranged outside the spacer. A bottom electrode via (BEVA) contacts the bottom electrode from below the bottom electrode. A top electrode via (TEVA) contacts the top electrode from above the top electrode.

[0020] In some embodiments, the two protective layers also at least partially enclose the side walls of the lower electrode and the upper electrode laterally.

[0021] The MTJ stack is in an interlayer dielectric (ILD) layer ILD X arranged vertically above a metallization layer in an ILD X-1 -Layer below the ILD X -layer. In some embodiments, the ILD X -shift from the ILD X-1 -layer separated by an etch stop layer, e.g., SiC, and an oxygen-rich silicon oxide layer SRO. In the logic area of the IC, the connecting elements of logic devices are in the ILD X-1 -layer. The connecting elements may comprise wiring and / or intermediate connecting elements, e.g., a connecting island and / or a jumper structure.

[0022] In some embodiments, the outer of the two protective layers, the outer protective layer, contains the same dielectric material as the etch stop layer, e.g., SiC. The inner of the two protective layers, the inner protective layer, contains a dielectric material that has high selectivity toward the outer protective layer and etch selectivity toward a material of the interconnect element, which may include copper, tungsten, and / or cobalt. The inner and outer protective layers are not present in the logic region.

[0023] Fig. 1 shows a portion of an exemplary integrated circuit (IC) 100 over a substrate 102. The IC 100 includes a first region 110 having a plurality of MRAM cells, with MRAM cells 112, 114 shown for illustration. The IC 100 also includes a second region 120 containing other circuit elements (in Fig. 1 not shown) than MRAM cells, e.g. logic circuit elements. Fig. 1 shows the BEOL layers and structures of the IC circuit 100. The MRAM cells 112, 114 are formed in the BEOL process over one or more ILD layers 122, with one ILD layer 122 shown for illustration. In some embodiments, metallization elements 116, 118, such as metal interconnect structures or metal wire structures, are formed in or between the one or more ILD layers 122. In one example, the metallization elements 116 are disposed in the first region 110 and beneath the MRAM cells 112, 114, and the metallization element 118 is disposed in the second portion 120. For illustration, the metallization elements 116 and the metallization element 118 are disposed in the same ILD layer 122.

[0024] The MRAM cells 112, 114 each have an MTJ structure 124 and 126, respectively. The MTJ structures 124, 126 are each vertically adjacent to a bottom electrode (BE) 128 and 130, respectively, and a top electrode (TE) 132 and 134, respectively. Interconnection structures, e.g., interconnect vias (BEVA) 136, 138, connect the BE 128 and 130, respectively, to the respective metallization elements 116 below. In some embodiments, the MTJ structures 124, 126 and the respective bottom electrode (BE) 128, 130 and top electrode (TE) 132, 134 are formed in an ILD layer 123 containing the same dielectric material as the ILD layer 122 beneath the MTJ structures 124, 126. The ILD layers 122, 123 are made of silicon oxide or a low-k dielectric material or another suitable dielectric material. A composite etch stop layer 125 is disposed between the ILD layer 122 and the ILD layer 123.In some embodiments, the composite etch stop layer 125 includes a laminate of two dielectric layers 127, 129 that have etch selectivity toward each other. In some embodiments, the lower 129 of the two layers 127, 129 has etch selectivity toward the ILD layer 123 and functions as an etch stop layer. In some embodiments, the composite etch stop layer 125 includes an etch stop layer 129 made of SiC and a silicon-rich oxide SRO layer 127 over the SiC layer 129. The layer 127 may also include a TEOS material.

[0025] In some embodiments, the BEs 128, 130 are formed above the composite etch stop layer 125, and the BEVAs 136, 138 are formed in the composite etch stop layer 125. Other embodiments are also possible. For example, the BEs 128, 130 may be formed in the composite etch stop layer 125.

[0026] A laminate 140 of two protective layers 142, 144 encloses sidewalls 143, 145 of the MTJ structures 124, 126. The two protective layers 142, 144 contain materials that exhibit etch selectivity toward each other. In some embodiments, the outer 142 of the two protective layers 142, 144 contains the same material as the etch stop layer 129 or a material that exhibits similar etch selectivity properties as the etch stop layer 129. For example, if the etch stop layer 129 is made of SiC, the outer protective layer 142 is made of SiC, SiOC, other dielectric materials formed using a plasma-enhanced atomic layer deposition (PEALD) process, or other suitable materials that exhibit similar etching properties to SiC with respect to an etchant. In some embodiments, the inner protective layer 144 is made of aluminum oxide (AlO x) or other suitable material having etch selectivity to the outer layer 142.

[0027] In some embodiments, the outer protective layer 142 has a thickness in the range of about 5 nm to about 50 nm. The inner protective layer 144 has a thickness between about 0.2 nm and about 5 nm. The different values of the thickness of the outer protective layer 142 and the inner protective layer 144 are chosen to facilitate the formation of a recess in the outer protective layer 142 and the inner protective layer 144 to expose the upper electrodes 132, 134. As will be described in detail herein, a recess is formed in the inner protective layer 144 by wet etching to expose the upper electrode 132, 134. It is generally difficult to etch out aluminum oxide from aluminum nitride during wet etching. Therefore, the value of the thickness of the inner protective layer 144 of aluminum oxide or aluminum nitride is chosen to be relatively small. In some embodiments, the outer protective layer 142 is made of SiC or SiOC, just like layer 129.As described here, the same etching process forms recesses in outer protective layer 142 and layer 129. In the SiC etching process, outer protective layer 142 is exposed to a larger load of etchants than layer 129 because outer protective layer 142 is close to the etchant source. Therefore, the thickness of outer protective layer 142 is chosen to be relatively large.

[0028] In some embodiments, spacer layers 146, 148 surround the sidewalls 143, 145, respectively, of the MTJ structures 124, 126, respectively. The spacer layers 146, 148 are disposed laterally between the sidewalls 143, 145, and the laminate 140. In some embodiments, the spacer layers 146, 148 are disposed over the BEs 128, 130, respectively. The spacer layers 146, 148 are made of SiN or another suitable dielectric material.

[0029] In some embodiments, the laminate 140 also at least partially encloses the sidewalls 133, 135 of the upper electrodes 132, 134. Upper portions of the upper electrodes 132, 134, e.g., including the upper surfaces 137, 139 of the upper electrodes 132, 134 and, in some embodiments, the upper portions of the sidewalls 133, 135, are not covered by the laminate 140. Metal interconnect structures 152, 154 are formed over the upper electrodes 132, 134 and contact the upper portions of the upper electrodes 132, 134 that are not covered by the laminate 140. In some embodiments, the laminate 140 extends over the entire surface of the first region 110, except for the upper portions of the upper electrodes 132, 134 that are not covered by the laminate 140. The laminate does not extend over the second region 120.

[0030] In some embodiments, a metal interconnect structure 156 is formed in the second region 120 and contacts the metallization element 118. In particular, the metal interconnect structure 156 extends through the ILD 123 and the composite etch stop layer 125 and contacts the metallization element 118. The metal interconnect structures 152, 154, 156 are formed in the same process and each extend downward from a top surface 158 of the ILD 123. The metal interconnect structures 152, 154, 156 are coplanar with each other with respect to the top surface 158 of the ILD 123.

[0031] In one embodiment, BEs 128, 130 include a conductive nitride having a magnetic property suitable for the operation of the respective MTJ structures 124, 126. For example, the conductive nitride material of BEs 128, 130 does not interfere with the pinning of the magnetic polarization of a fixed layer of MTJ structures 124, 126. In one embodiment, BEs 128, 130 are made of TaN and / or TiN. BEVA 136 includes a material adapted to the electrical and magnetic properties of BEs 128, 130. In one embodiment, BEVA 136 is made of TiN. In some embodiments, the BEVA 136 also includes a barrier or liner layer (not shown for simplicity) of Ta and / or TaN that prevents penetration of the TiN material into the surrounding SiC layer 129 and the SRO / TEOS layer 127.

[0032] Fig. 2 shows an exemplary MRAM cell 112. Referring to Fig. 2, the MRAM cell 112 includes a BE 128. An anti-ferromagnetic layer 204 is disposed over the conductive bottom electrode 128, and a pinned magnetic layer 206 is disposed over the anti-ferromagnetic layer 204. The anti-ferromagnetic layer 204 includes a strong exchange coupling material having atoms with magnetic moments aligned in a regular pattern, with neighboring spins pointing in opposite directions. The strong exchange coupling enables the anti-ferromagnetic layer 204 to pin (i.e., fix) the magnetic polarization of the pinned magnetic layer 206 and thereby prevent the magnetic polarization of the pinned magnetic layer 206 from changing, e.g., during write operations of the MRAM cell 112. In this respect, the pinned magnetic layer 206 is also referred to as the fixed layer 206 of the MTJ structure 124.In some embodiments, a synthetic anti-ferromagnetic (SAF) layer (not shown for simplicity) may be disposed between the anti-ferromagnetic layer 204 and the pinned magnetic layer 206.

[0033] In the MTJ structure 124, the pinned magnetic layer 206 is vertically spaced from a free magnetic layer 210 by a dielectric barrier layer 208. The free magnetic layer 210, or free layer 210, has a magnetic polarization capable of alternating between a parallel configuration and an anti-parallel configuration with respect to the magnetic polarization of the pinned magnetic layer 206. The top electrode 132 is disposed over the free magnetic layer 210. Optionally, a dielectric cap or spacer layer 146, e.g., of silicon nitride (SiN), is disposed around the MTJ structure 124. The spacer layer 146 may also be made of carbide (SiC), silicon dioxide (SiO2), silicon oxynitride (SiON), silicon oxycarbide (SiOC), and / or a low-k dielectric material.

[0034] The pinned magnetic layer 206, the dielectric barrier layer 208, and the free magnetic layer 210 form the magnetic tunnel junction (MTJ) 124. In the MTJ 124, electrons can tunnel through the dielectric barrier layer 208 when a differential voltage is applied between the conductive bottom electrode 128 and the conductive top electrode 132. As the electrons tunnel through the dielectric barrier layer 208, the magnetic polarization of the free magnetic layer 210 can change, thereby changing a resistance value of the MTJ 124. For example, when a polarity of the free magnetic layer 210 is aligned with a polarity of the pinned magnetic layer 206, the MTJ 124 has a first resistance value corresponding to a first data state, e.g., a logic "0."When the polarity of the free magnetic layer 210 is not aligned with the polarity of the pinned magnetic layer 206, the MTJ 124 has a second resistance value corresponding to a second data state, e.g., a logic "1."

[0035] In some embodiments, the conductive bottom electrode BE 128 may include titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), and / or tantalum (Ta). In some embodiments, the BE 128 may have a thickness in a range between about 10 nm and about 100 nm. In some embodiments, the anti-ferromagnetic layer 204 may include iridium manganese (IrMn), iron manganese (FeMn), ruthenium manganese (RuMn), nickel manganese (NiMn), and / or palladium platinum manganese (PdPtMn). In some embodiments, the pinned magnetic layer 206 may include cobalt (Co), iron (Fe), boron (B), and / or ruthenium (Ru). In some embodiments, the pinned magnetic layer 206 may have a thickness in a range between about 5 nm and about 10 nm.

[0036] In some embodiments, the dielectric barrier layer 208 may include magnesium oxide (MgO) and / or aluminum oxide (Al2O3) and have a thickness in a range between about 0.5 nm and about 2 nm. In some embodiments, the free magnetic layer 210 may include cobalt (Co), iron (Fe), and / or boron (B) and have a thickness in a range between about 1 nm and about 3 nm.

[0037] In some embodiments, the conductive top electrode 132 may comprise titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), tungsten (W), and / or tantalum (Ta).

[0038] In some embodiments, cross-sections of the conductive top electrode 132, the free magnetic layer 210, the dielectric barrier layer 208, the pinned magnetic layer 206, the anti-ferromagnetic layer 204, and the conductive top electrode 132 are substantially acutely trapezoidal, either individually or together as a group. Widths of the conductive bottom electrode 132, the free magnetic layer 210, the dielectric barrier layer 208, the pinned magnetic layer 206, and the anti-ferromagnetic layer 204 progressively increase downward along the z-axis. In some embodiments, the acute-angled trapezoidal cross-sectional shape is formed by an ion beam etching (IBE) process used to form sidewalls 143 of the MTJ structure 124 and the sidewall 133 of the top electrode 132.In other words, the free magnetic layer 210, the dielectric barrier layer 208, the pinned magnetic layer 206, the anti-ferromagnetic layer 204, and the top electrode 132 have substantially aligned and sloped sidewalls.

[0039] Fig. 3A to 3D show a wafer 300 at various stages of fabrication in the manufacture of the IC 100, the MRAM cell 112, or other semiconductor structures. Referring to Fig. 3A, a wafer 300 is received. The wafer 300 includes a semiconductor substrate 302. The semiconductor substrate 302 may be a silicon substrate in a crystalline structure and / or other elemental semiconductors such as germanium. Alternatively or additionally, the semiconductor substrate 302 may include a compound semiconductor such as silicon carbide, gallium arsenide, indium arsenide, and / or indium phosphide. Furthermore, the semiconductor substrate 302 may also include a silicon-on-insulator (SOI) structure. The semiconductor substrate 302 may include an epitaxial layer and / or be strained to improve performance. As is common in this technical field, the semiconductor substrate 302 may also include various doping configurations depending on design requirements, such as a p-doped substrate and / or an n-doped substrate and various doped regions such as p-wells and / or n-wells.One or more selection transistors 304 are disposed in or above the semiconductor substrate 302. In some embodiments, the one or more selection transistors 304 are disposed between isolation regions 305 (e.g., STI regions).

[0040] In some embodiments, the one or more selection transistors 304 may comprise MOSFET (metal-oxide-semiconductor field-effect transistor) devices. The transistors 304 may be of various types, such as a planar transistor, a finFET transistor, a gate-all-around transistor, a vertical transistor, or other transistor types, without limiting the scope of the disclosure. In such embodiments, the one or more selection transistors 304 each comprise a source region 306 and a drain region 308 separated by a channel region 307. The source region 306 has a first doping type (e.g., an n-type dopant), the channel region 307 has a second doping type different from the first doping type, and the drain region 308 has the first doping type.In some embodiments, the first doping type comprises an n-type doping, while in other embodiments, the first doping type comprises a p-type doping. A gate structure 310, comprising a gate electrode 311 separated from the channel region 307 by a gate oxide layer 309, is configured to control the flow of charge carriers between the source region 306 and the drain region 308. In various embodiments, the gate structure 310 may include a doped polysilicon material or a metal material (e.g., TiN, Al, etc.). In some embodiments, sidewall spacers 312 (e.g., SiN spacers) may be arranged on opposite sides of the gate electrode 311.

[0041] Back-end-of-the-line (BEOL) metal structures 318, 320 or metallization elements are disposed over the semiconductor substrate 302, some of which contact the terminals of the transistors 304 via contact vias 314 (314a, 314b, 314c shown). The metallization elements 318, 320 are stacked in a vertical direction, with some of the metallization elements 318, 320 eventually leading to metallization elements 116 in the first region 110 and metallization elements 118 in the second region 120. The metallization elements are formed in ILD layers 322, including the ILD layer 122 in which the metallization elements 116 and 118 are formed. In some embodiments, the inter-level dielectric layers (ILD layers) 322, 122 are separated from each other by an etch stop layer 329, e.g., made of SiC or SiN.

[0042] In Fig. 3B, a composite etch stop layer 125 comprising a layer 127 of SRO or TEOS and a layer 129 of SiC is formed over the ILD layer 122. A composite etch stop layer formed from a tetraethoxysilane oxide (TEOS) layer overlying a conventional silicon-based SiC etch stop layer can further reduce the overall thickness and dielectric constant of the composite etch stop layer 125.

[0043] In Fig. 3C, a BEVA structure 136 is formed in the composite etch stop layer 125 in the first region 110, which BEVA via structure 136 contacts the metallization element 116 in the ILD layer 122. The BEVA via structure 136 includes a different material than the metallization element 116. In some embodiments, the BEVA via structure 136 is made of TiN and the metallization element 116 is made of copper. The layer 127 is made of a material suitable for deposition of the BEVA via structure 136, which is, for example, made of TiN. In some embodiments, the layer 127 is made of SRO, TEOS, and / or other suitable dielectric materials. In some embodiments, a barrier or liner layer 328 is formed between the BEVA via structure 136 and the surrounding composite etch stop layer 125. The barrier layer 328 is made of Ta and / or TaN. The barrier layer 328 prevents the TiN elements from penetrating the surrounding composite etch stop layer 125.In some embodiments, the BEVA via structure 136 is formed only in the SiC layer 127 and not in the SiC layer 129. That is, another interconnect structure is formed in the layer 129 between the BEVA via structure 136 and the metallization element.

[0044] In Fig. 3D, an MRAM cell 112 is formed in the first region 110 above the BEVA via structure and the composite etch stop layer 125. The MRAM cell includes an MTJ structure 124, a top electrode 132, and a bottom electrode 128. In some embodiments, a spacer layer 146 surrounds at least the MTJ structure 124 of the MRAM cell 112.

[0045] Fig. 4A to 4M show the further fabrication of the MRAM cell 112 and the metallization element over the MRAM cell 112.

[0046] In Fig. 4A, an exemplary wafer 400 is received. The exemplary wafer 400 may be the same wafer as the wafer 300 after the processes of Fig. 3A to 3D. The exemplary wafer 400 as shown includes a first region 110 for MRAM cells and a second region 120 for other circuit elements, e.g., logic elements.

[0047] In Fig. 4B, a laminate of two layers 402, 404 is formed globally over the wafer 400. The two layers 402, 404 have a high etch selectivity with respect to each other. In some embodiments, layer 402 is made of the same material as the etch stop layer 129 or of a material having similar etch properties as the etch stop layer 129. In the case that the etch stop layer 129 is made of SiC, layer 402 is made of SiC, SiOC, or other dielectric materials formed by PEALD. Layer 404 is made of aluminum oxide (AlO x) or aluminum nitride (AlN), or a material having similar etching properties. Layer 404 is deposited to a thickness in the range of about 5 nm to about 50 nm. Layer 402 is deposited to a thickness in the range of about 0.2 nm to about 5 nm.

[0048] In Fig. 4C, the layers 402 and 404 are selectively removed from the second region 120 by etching, wherein the first region 110 is covered, for example, by a mask layer (not shown for simplicity). A portion of the layer 127 of SRO or TEOS may also be removed by etching, such that the thickness of the layer 127 in the second region 120 is less than the thickness of the layer 127 in the first region 110. Due to the etch selectivity between the layer 404 of aluminum oxide (AlO x) or aluminum nitride (AiN) and the etch stop layer 129 made of SiC, the etch stop layer 129 remains after the layers 402 and 404 have been removed from the second region 120.

[0049] In Fig. 4D, an ILD layer 123 is formed globally or uniformly over the wafer 400. In particular, the ILD layer 123 is formed over both the first region 110 and the second region 120. In some embodiments, the ILD layer 123 is made of an extremely low-k material (ELK) such as SiCOH, porous SiCOH, NanoGlass, or other dielectric materials having a dielectric constant k ≤ 3. A CMP polishing process is performed to planarize the surface 410 of the ILD layer 123.

[0050] Fig. 5A-5D show an exemplary method for planarizing the surface 410 of the ILD 123. In Fig. 5A, the ILD layer 123 is formed globally over the first region 110 and the second region 120. Due to the MTJ structure 124, the ILD layer 123 has a protrusion or step height 510 above the MTJ structure 124. In Fig. 5B, a cap layer 520 made of a low-K dielectric material is applied to the ILD layer 123. The cap layer 520 covers the protrusion 510 and has a relatively flat surface 522. In Fig. 5C, an etch-back process is performed to remove the cap layer 520 and the protrusion 510. In some embodiments, residual portions 524 of the protrusion 510 remain after the etch-back process. In Fig. 5D, a CMP polishing process is performed to remove the residual parts 524 and planarize the surface 410 of the ILD layer 123.

[0051] In Fig. 4E, an anti-reflective layer 412 and a hard mask layer 414 are sequentially formed over the ILD layer 123. In some embodiments, the anti-reflective layer 412 is a nitrogen-free anti-reflective coating (NFARC) layer, and the hard mask layer 414 is a TiN / TaN layer. The two layers 412 and 414 function as sacrificial layers. The hard mask layer 414 is patterned to have recesses 420 in the first region 110 and recesses 422 in the second region 120. The recesses 420, 422 define the locations for forming metallization elements to be formed in the ILD layer 123 in the first regions 110 and the second regions 120. In some embodiments, the recesses 420, 422 in the first region 110 and in the second region 120, respectively, may have the same dimension, e.g., the same area.In some embodiments, a sacrificial dielectric hard mask layer 416 is formed between the ILD layer 123 and the NFARC layer 412. The layer 416 functions to prevent the kink defect at the surface of the low-k dielectric layer 123. The sacrificial dielectric hard mask layer 416 is formed, for example, from silicon-containing dielectric materials such as silicon nitride, using processes such as plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), and atmospheric pressure chemical vapor deposition (APCVD).

[0052] In Fig. 4F, a partial via etch process is performed to form partial via openings or trenches 424, 426 through the recesses 420, 422. In particular, the partial via etch opens the NFARC layer 412 to partially remove the material of the ILD layer 123 at the location where the via opening or trench is to be formed, leading to the MRAM cell 112 in the first region 110 or to the metallization elements 118 in the second region 120. The recesses 420, 422 are formed together in an integrated etch process. This means that neither the first region 110 nor the second region 120 is covered when the partial via etch process is performed in the other of the first region 110 or the second region 120. In some embodiments, the partial via openings or trenches 424, 426 have substantially the same dimensions, e.g., in depth and shape.

[0053] In Fig. 4G, a main etch process is performed through the recesses 420, 422 to form a via opening 430 leading to the MRAM cell 112 and a via opening 432 leading to the metallization element 118. The etch process also removes the SRO or TEOS layer 127 of the composite etch stop layer 125 in the second region 120. The layer 404 of SiC, SiOC, or other dielectric layers formed by plasma-enhanced ALD (PEALD) and the layer 129 of SiC thus function as an etch stop layer for the main etch process. In some embodiments, a dry plasma etch process is used in the main etch process.

[0054] Due to the partial via openings 424, 426, the via openings 430, 432 each have a stepped shape and include a wider portion 434, 436, respectively, and a narrower portion 438, 440. The wide portions 434, 436 are disposed near the surface 410 of the ILD 123. The narrower portions 438, 440 are disposed below the wider portions 434, 436 and near the MRAM cell 112 and the metallization elements 118, respectively. In some embodiments, the wider portions 434, 436 have the same dimensions, e.g., in area, shape, and depth / length. The narrower portion 438 in the first region 110 has a flatter / shorter dimension 439 than the dimension 441 of the narrower portion 440 in the second region 120. Thus, the SiC layer 404 over the MRAM cell 112 is exposed to more etchants than the SiC layer 129 in the second region 120.More SiC material is removed from the SiC layer 404 exposed in the via opening 430 than from the SiC layer 129 exposed in the via opening 432. Since the AlO. x -Layer 402, however, has a high etch selectivity towards SiC, the AlO x -layer 402 and covers the MRAM cell 112 including the top electrode 132, the MTJ structure 124 and the bottom electrode 128. On the other hand, since the SiC layer 404 covers the AlO x -layer 402 and the etchants of the main etching process before the AlO x -layer 402, the AlO x -layer 402 does not maintain a relatively large thickness. Instead, the AlO x -Layer 402 has a relatively small thickness of about 0.2 nm to about 5 nm.

[0055] In some embodiments, the wider sections 434, 436 and the narrower sections 438, 440 each have a tapered shape and represent the trenches into which the metal lines are filled.

[0056] In Fig. 4H, a liner removal method (LRM) etching process is applied to remove a selected portion of the SiC etch stop layer 129 downward from the via opening 432 and to remove a selected portion of the SiC layer 404 downward from the via opening 430. Other etching techniques may also be used to remove the SiC layers 121, 127, 404. In some embodiments, the etch is highly anisotropic, with very little lateral etching being performed. This may be achieved by using a lower pressure, e.g., less than 5.332895 Pa (40 mTorr), and a higher bias power, e.g., greater than 100 W. Since the AlO x-Layer 402 has a high etch selectivity towards the SiC, the AlO x Layer 402 is removed, covering the MRAM cell 112, and is exposed in the via opening 430. In the second region 120, the metallization element 118 is exposed in the via opening 432 by removing the SiC layer 129 below the via opening 432.

[0057] In Fig. 4I, a wet cleaning process is applied jointly to the first region 110 and the second region 120. The wet cleaning, e.g., using deionized water, removes the AlO exposed in the via opening 430 x-layer 402 and removes the deposits and residues in the via opening 432. The wet cleaning does not damage or attack the metallization element 118, e.g., made of copper, which is exposed in the via opening 432, and does not damage or attack the upper electrode 132, e.g., made of tungsten. Due to the relatively small thickness of the AlOx layer 402, about 0.2 nm to about 5 nm, it is comparatively easier or faster to remove the part of the AlO x -Layer 402 by wet cleaning. Thus, the removal of the AlO x -Layer 402 does not require any additional time in the fabrication process, since the wet cleaning is also used to clean the deposits and residues in the via opening 432. After the part of the AlO exposed in the via opening 430 x -layer 402 has been removed, the remaining layers 402, 404 become the protective layers 142, 144 of Fig. 1.

[0058] In Fig. 4J, a conductive material 439, e.g., copper, is deposited together into the via openings 430, 432, extending downward to the top electrode 132 and the metallization element 118, respectively. Because the sidewalls of the MTJ structure 124 and the top electrode 132 are covered by the remaining layers 402, 404, the sidewall of the MTJ structure 124 is not damaged or attacked even if the via opening 430 is misaligned and the conductive material 439 is deposited over the sidewalls of the top electrode 132 and the MTJ structure 124. Thus, the via opening 430 can have higher tolerance and flexibility in surface dimensions. Because the via openings 430, 432 are formed together, such tolerance and flexibility also benefits the process design of the via opening 432.

[0059] In Fig.4K chemical mechanical polishing is applied to remove layers above the top surface 410 of the ILD layer 123, including the excess conductive material 440, the hard mask layer 414, the NFARC layer 412, and the ESLK layer 416. Conductive material in the via opening 430 becomes an interconnect structure 442 to the top electrode 132 of the MRAM cell 112. Conductive material in the via opening 432 becomes an interconnect structure 444 to the metallization element 118 in the second region 120.

[0060] As shown here, with the layers 402, 404 enclosing the MRAM cell 112, the processes for forming the interconnect structure 442 to the MRAM cell 112 in the first region 110 and for forming the interconnect structure 444 to the metallization element 118 in the second region 120 are integrated into the same process. Neither the first region 110 nor the second region 120 is covered during the process for forming the interconnect structure in the other region. Such an integrated process saves cost and time in the BEOL processes. Furthermore, the layers 402, 404 protect the MRAM cell 112 from being damaged during the process for forming the interconnect structure 442.

[0061] The present disclosure can also be understood from the description of the following embodiments:

[0062] In some embodiments, an integrated circuit comprises a vertical magnetic tunnel junction stack having a first magnetic layer, a second magnetic layer, and a barrier layer between the first magnetic layer and the second magnetic layer; a first electrode below the vertical magnetic tunnel junction stack; a second electrode above the vertical magnetic tunnel junction stack; a first dielectric layer laterally enclosing the vertical magnetic tunnel junction stack; and a second dielectric layer laterally enclosing the first dielectric layer.

[0063] In some embodiments, a method comprises selectively forming a first dielectric layer over a first region of a wafer, the first region having a vertical magnetic tunnel junction structure over an etch stop layer, the etch stop layer extending through a second region of the wafer laterally adjacent to the first region; selectively forming a second dielectric layer over the first region of the wafer enclosing the first dielectric layer; forming a third dielectric layer over the first region and the second region of the wafer enclosing the second dielectric layer;in a first etching process, forming a first opening in the third dielectric layer, the opening exposing a first portion of the second dielectric layer above the vertical magnetic tunnel junction structure, together with a second opening exposing a second portion of the etch stop layer in the second region; in a second etching process, removing the first portion of the second dielectric layer exposed by the first opening and exposing a third portion of the first dielectric layer through the first opening together with removing the second portion of the etch stop layer exposed by the second opening; removing the third portion of the first dielectric layer by wet cleaning;and forming a first interconnect structure in the first opening contacting the vertical magnetic tunnel junction structure, together with a second interconnect structure in the second opening extending through the etch stop layer;

[0064] In some embodiments, an integrated circuit comprises a substrate; a first interlayer dielectric layer over the substrate; a first metallization element and a second metallization element in the first interlayer dielectric layer; an etch stop layer over the first interlayer dielectric layer; a second interlayer dielectric layer over the etch stop layer; a vertical magnetic tunnel junction stack in the second interlayer dielectric layer, the vertical magnetic tunnel junction stack comprising a first magnetic layer, a second magnetic layer, and a barrier layer in the vertical direction between the first magnetic layer and the second magnetic layer; a first protection layer surrounding a sidewall of the vertical magnetic tunnel junction stack; a second protection layer surrounding the first protection layer;a first electrode below the vertical magnetic tunnel junction stack, extending through the etch stop layer and contacting the first metallization element; a second electrode above the vertical magnetic tunnel junction stack; a first interconnect structure extending from a surface of the second interlayer dielectric layer to the second electrode; and a second interconnect structure extending from the surface of the second interlayer dielectric layer to the second metallization element.

[0065] The invention is defined by the independent claims. The dependent claims relate to embodiments of the invention.

Claims

[1] Integrated circuit comprising: a vertical magnetic tunnel junction stack (124) having a first magnetic layer (206), a second magnetic layer (210), and a barrier layer (208) between the first magnetic layer (206) and the second magnetic layer (210); a first electrode (128) below the vertical magnetic tunnel junction stack (124); a second electrode (132) above the vertical magnetic tunnel junction stack (124); a first dielectric layer (144) laterally enclosing the vertical magnetic tunnel junction stack (124); and a second dielectric layer (142) laterally enclosing the first dielectric layer (144); wherein the first dielectric layer (144) and the second dielectric layer (142) have an etch selectivity with respect to each other; wherein the first dielectric layer (144) contains aluminum oxide and / or aluminum nitride, wherein the vertical magnetic tunnel junction stack (124) is arranged in an interlayer dielectric layer (123) and above an etch stop layer (125), wherein the etch stop layer (125) is arranged below the interlayer dielectric layer (123), wherein the second dielectric layer (142) contains a dielectric material adapted to be etched out using the same etchant as the etch stop layer (125), and wherein in a region (120) of the integrated circuit which lies laterally next to the vertical magnetic tunnel junction stack (124), the etch stop layer (125) adjoins the interlayer dielectric layer (123) from below. [2] The integrated circuit of claim 1, further comprising a spacer layer (146) laterally between the first dielectric layer (144) and the vertical magnetic tunnel junction stack (124). [3] The integrated circuit of claim 2, wherein the spacer layer (146) is disposed on the first electrode (128). [4] Integrated circuit according to claim 2 or 3, wherein the spacer layer (146) at least partially laterally encloses the second electrode (132). [5] Integrated circuit according to one of the preceding claims, wherein the first dielectric layer (144) laterally encloses the first electrode (128) and at least partially the second electrode (132). [6] Integrated circuit according to one of the preceding claims, wherein the first dielectric layer (144) has a thickness between 0.2 nm and 5 nm. [7] Integrated circuit according to one of the preceding claims, wherein the second dielectric layer (142) has a thickness between 5 nm and 50 nm. [8] Integrated circuit according to one of the preceding claims, wherein the second dielectric layer (142) contains silicon carbide and / or oxide-rich silicon carbide. [9] The integrated circuit of any preceding claim, further comprising a first interconnect structure (152) contacting the second electrode (132) through a first opening in the first dielectric layer (144) and the second dielectric layer (142) and contacting the second dielectric layer (142) in a vertical direction. [10] The integrated circuit of claim 9, further comprising a second interconnect structure (156) extending through the interlayer dielectric layer (123) and the etch stop layer (125) and laterally of the vertical magnetic tunnel junction stack (124). [11] The integrated circuit of claim 9 or 10, wherein the first interconnect structure (152) contacts the first dielectric layer (144) in the vertical direction. [12] Method comprising: Forming a first dielectric layer (402) over a first region (110) of a wafer, the first region (110) having a vertical magnetic tunnel junction structure (124) over an etch stop layer (125), the etch stop layer (125) extending over a second region (120) of the wafer arranged laterally adjacent to the first region (110); Forming a second dielectric layer (404) over the first region (110) of the wafer such that the second dielectric layer (404) is disposed over the first dielectric layer (402) and encloses the first dielectric layer (402) and the vertical magnetic tunnel junction structure (124); Forming a third dielectric layer (123) over the first region (110) and the second region (120) of the wafer such that the third dielectric layer is disposed over the second dielectric layer (404) and encloses the second dielectric layer (404) and the vertical magnetic tunnel junction structure (124); in a first etching process, forming a first opening (430) in the third dielectric layer (123), the first opening (430) exposing a portion of the second dielectric layer (404) above the vertical magnetic tunnel junction structure (124), together with a second opening (432) exposing a portion of the etch stop layer (125) in the second region (120); in a second etching process, removing the portion of the second dielectric layer (404) exposed by the first opening (430) and exposing a portion of the first dielectric layer (402) through the first opening (430) together with removing the portion of the etch stop layer (125) exposed by the second opening (432); Removing the portion of the first dielectric layer (402) by wet cleaning; and Forming a first interconnect structure (442) in the first opening (430) that contacts the vertical magnetic tunnel junction structure (124), together with a second interconnect structure (442) in the second opening (432) that extends through the etch stop layer (125). [13] The method of claim 12, wherein the second dielectric layer (404) includes a dielectric material configured to be etched out with the same etchant as the etch stop layer (125). [14] The method of claim 12 or 13, wherein the first dielectric layer (402) contains aluminum oxide and / or aluminum nitride. [15] A method according to any one of claims 12 to 14, wherein the first etching step comprises: a partial via etching process forming a first partial opening (424) in the third dielectric layer (123) in the first region (110) before reaching the vertical magnetic tunnel junction structure (124) and a second partial opening (426) in the second region (120); and a main via etching process that forms the first opening (430) through the first partial opening and forms the second opening (432) from the second partial opening. [16] The method of claim 15, wherein the first opening (430) has a first portion (434) and a second portion (438) vertically connected to the first portion, the first portion (434) being wider than the second portion (438); and wherein the second opening (432) has a third portion (436) and a fourth portion (440) vertically connected to the third portion, the third portion (436) being wider than the fourth portion (440). [17] The method of claim 16, wherein the first portion (434) and the third portion (436) have a substantially equal dimension in an area, a shape and / or a length. [18] Integrated circuit comprising: a substrate (102); a first interlayer dielectric layer (122) over the substrate (102); a first metallization element (116) and a second metallization element (118) in the first interlayer dielectric layer (122); an etch stop layer (125) over the first interlayer dielectric layer (122); a second interlayer dielectric layer (123) over the etch stop layer (125); a vertical magnetic tunnel junction stack (124) in the second interlayer dielectric layer (123), the vertical magnetic tunnel junction stack (124) comprising a first magnetic layer (206), a second magnetic layer (210), and a barrier layer (208) in the vertical direction between the first magnetic layer (206) and the second magnetic layer (210); a first protective layer (144) surrounding a sidewall of the vertical magnetic tunnel junction stack (124); a second protective layer (142) surrounding the first protective layer (144); a first electrode (128) below the vertical magnetic tunnel junction stack (124) extending through the etch stop layer (125) and contacting the first metallization element (116); a second electrode (132) above the vertical magnetic tunnel junction stack (124); a first interconnect structure (442) extending from a surface of the second interlayer dielectric layer (123) to the second electrode (132); and a second interconnect structure (442) extending from the surface of the second interlayer dielectric layer (123) to the second metallization element (118); wherein the first protective layer (144) and the second protective layer (142) have an etch selectivity towards each other; wherein the first protective layer (144) contains aluminum oxide and / or aluminum nitride; wherein the second protective layer (142) contains a dielectric material adapted to be etched out using the same etchant as the etch stop layer (125), and wherein in a region of the integrated circuit which laterally adjoins the second connecting structure (442), the etch stop layer (125) adjoins the second interlayer dielectric layer (123) from below. [19] The integrated circuit of claim 18, wherein the etch stop layer (125) is made of SiC and / or SiOC and the second protective layer (142) is made of SiC, SiOC and / or a dielectric material adapted to be etched out in the same etching process as the SiC and / or SiOC. [20] The integrated circuit of claim 18 or 19, wherein the first protective layer (144) has a thickness between 0.2 nm and 5 nm, and the second protective layer (142) has a thickness between 5 nm and 50 nm.

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