Adaptive slope compensation

Abstract

Adaptive slope compensation circuit in a current-mode controlled DC-DC switching converter, comprising: a compensation ramp (840, 810) having two or more zones (Period1, Period2), each zone having a specific slope value (805, 815, 825, 820, 830), configured to respond to a duty cycle, and configured to maintain a maximum ramp current contribution for all values ​​of an output voltage at one end of a switching period, or for one-times > 50% of a total switching cycle time Tpd, to maintain a constant offset value at an application point for all values ​​of the output voltage, with a clock in antiphase to the main clock being provided to control the switching of the compensation ramp (840, 810).

Description

BackgroundRelated Patent ApplicationThis application relates to U.S. Patent Application US 2019 / 0 097 518 A1 filed Sep. 28, 2017 (serial number DS17-038), which is assigned to a common assignee and is incorporated herein in its entirety by reference.Field of InterestThe present disclosure relates generally to all types of switching DC-DC converters, and more particularly to a buck converter with adaptive slope compensation.BackgroundPresent day high power electronic systems require increasingly higher power from power supply subsystems, requiring higher operating efficiencies and load currents. This applies in particular to portable devices with battery power. Step-down DC-DC converters, most commonly Pulse Width Modulation (PWM) step-down converters, are frequently used to meet these requirements.US 2019 / 0097 518 A1 relates to a slope compensation circuit with an adaptive slope compensation method in a DC-DC switching converter operated in current regulation mode at duty cycles of more than 50%.US 2013 / 0 043 856 A1 relates to a circuit and a method for generating a ramp compensation voltage, as could be used in a switching regulator.US 2011 / 0 115 458 A1 describes a digital slope compensation device and a method for a switched mode power supply using a sensor for detecting and generating an analog inductor current.Current mode controlled buck regulators regulate the current supplied to a power inductor to regulate the output voltage. A current mode controller operates using two loops: an internal current loop that regulates the inductor current, and an external voltage loop.FIG. 1 shows 100 a circuit diagram for current mode control in a prior art buck converter. Since the internal current loop I_FB forms a high bandwidth loop, the inductor L 1 can be modeled as a current source such that the transfer function of the power stage is a single pole first order function defined by an output capacitor C 1 and the resistive load (LOAD). The compensation required to stabilize the current mode controller at 110 is much less complex than that required for the voltage mode controller for V_FB, and the overall performance is much better. A voltage feedback loop compares the sensed output voltage V_FB at the inverting input with a reference voltage V_ref at the noninverting input in comparator 130. A comparator 120 compares the inductor current at the inverting input to the output of the comparator 130.However, current mode control devices may be unstable under certain circumstances, for example, when the required duty cycle (V_OUT / V_IN) is higher than 50%, when the peak current of the inductor is regulated (peak mode control when the on-time of the high-side switch S 1 is greater than 50% of the total switching cycle time Tpd), or when the required duty cycle (V_OUT / V_IN) is lower than 50% when the valley current of the inductor is regulated (valley mode control when the on-time of the low-side switch S 2 is greater than 50% of the total switching cycle time Tpd). Current mode controllers tend to subharmonic oscillation, non-ideal loop responses, and higher sensitivity to noise. Slope compensation, in which a slope is added to the measured inductor current, may be used to overcome these difficulties.FIG. 2 shows 200 a circuit diagram for current mode control in a buck converter in which a slope compensation ramp is added to the measured inductor current. Similar to FIG. 1, there is a voltage feedback loop that compares the sensed output voltage V_FB with a reference voltage V_ref in the comparator 230. Without a slope compensation ramp, the current mode controller shows a subharmonic oscillation for (V_OUT / V_IN) above 50% when the peak current of the inductor L 1 is regulated or for (V_OUT / V_IN) less than 50% when the valley current of the inductor L 1 is regulated at 210. To overcome this problem, slope compensation may be added to the measured inductor current I_FB. An adder 240 is inserted between the comparator 220 and the inductor current to allow a fixed slope represented by the sawtooth signal 250 to be added to the measured inductor current / voltage to generate a slope compensated signal that is applied to the input of the comparator.However, the power density and output current requirements of present day hand-held devices shift the limits of the topologies and control methods of the prior art. Next generation buck converter designs used in portable high power devices require a wide range of operating duty cycle while minimizing the value of the output inductor to allow for higher system performance. This has increased the challenge of implementing the slope compensation ramp, particularly during operation in the valley mode. For example, it is assumed that under the following operating conditions, the peak of the slope compensation ramp would be nearly 10 Å.Theoretically required minimum compensation ramp slope for valley mode = [V_IN - V_OUT] / [2*L1], where:For the peak mode, the theoretically required minimum compensation ramp slope would be [V_OUT / [2*L1]]. The valley mode rather requires a larger compensation ramp due to the introduction of V_IN into the equation. This applies only to typical application cases in which [V_IN-V_OUT]>>V_OUT.If a large range of V_OUT and V_IN are considered, then the ramp will normally be set to the most extreme conditions, for example maximum V_OUT for the peak mode and maximum V_IN and minimum V_OUT for the valley mode, so that all conditions can recover from subharmonic conditions. This means that in some cases too much compensation ramp is added and in others just enough.Figure 3 shows 300 where a steep slope compensation ramp is used in a prior art buck converter. There are a number of problems that may occur with a large compensation ramp 305, including a ramp signal head room 310, particularly in high peak mode or low valley mode duty cycle conditions. Additionally, with a steeper compensation ramp, an error may occur in the final ramp value 320 caused by the delay between the intended end of the ramp and the actual time of completion of the ramp signal, which affects control performance. The steeper the ramp, the more severe this problem.For a steep slope compensation ramp, the amount of offset caused by the ramp termination delay may further increase the offset, and the larger offset causes a variation in the current limit threshold for different operating duty cycles. With too large a compensation ramp, the buck control scheme approaches voltage mode as opposed to current mode, resulting in a lower phase range that may not be compensated in the system originally designed for current mode operation.As an alternative to the steep slope compensation ramp of FIG. 3, other prior art control methods implement slope compensation only during switching cycles when the high-side switch for the peak mode or the low-side switch for the valley mode have an on-time greater than 50% of the total switching cycle time Tpd, the on-time being that of the PMOS switch in the peak mode and that of the NMOS switch in the valley mode.FIG. 4 shows 400 where a slope compensation ramp is used for the high side or low side switch with an on time greater than 50% Tpd. This prior art solution introduces another set of disadvantages. When the switching converter is operating at or near the 50% duty cycle point, it is close to when the slope compensation 405 is enabled or disabled on a cycle-by-cycle basis. This creates an operating jitter that affects output ripple, output regulation, and / or loop stability. In addition, while the greatest advantage of slope compensation is achieved by switching cycles that exceed more than 50% on-time for the high side switch in the peak mode or exceed more than 50% on-time for the low side switch in the valley mode, there is also a need for slope compensation for switching cycles of less than 50% on-time.SummaryAccordingly, it is an object of one or more embodiments of the present disclosure to provide an adaptive slope compensation method in a switching DC-DC converter.It is another object of one or more embodiments of the disclosure to reduce the required ramp headspace and operating jitter at or around the 50% duty cycle operating point of the switching converter.Further, it is an object of one or more embodiments of the disclosure to describe an implementation of a switching DC-DC converter that is stable in operating conditions with minimized complexity.Other objects will be apparent hereinafter.The above and other objects of the present disclosure can be achieved in the following manner. An adaptive slope compensation circuit in a switching DC-DC converter is disclosed that has a compensation ramp that is proportional to a downward slope of a current in an inductor summed with other contributions from the system to determine the final on-time. The compensation ramp further comprises two or more zones, each zone having a particular slope value. The compensation ramp is configured to respond to a particular operating duty cycle and maintain a maximum ramp current contribution at the end of the switching period (embodiment 1) or for on times >50% Tpd a constant offset value for all V_OUT at the application point (embodiment 2).The above and other objects of the present disclosure may be further achieved by a method for adaptive slope compensation in a DC-DC switching converter. The steps include providing a compensation ramp comprising two or more zones, each zone having a particular slope value. The steps also include modifying the slope compensation ramp and the zones making up the compensation ramp in response to a duty cycle. The steps also include maintaining a maximum ramp current contribution for all values of an output voltage V_OUT at the end of the switching period (embodiment 1) or for on times >50% of the total switching cycle time Tpd, a constant offset value for all V_OUT at the point of application (embodiment 2).In various embodiments, the function may be achieved with other types of DC-DC switching converters using current mode control, for example a boost or a buck-boost switching converter.Brief Description of the DrawingsThe present disclosure will be more clearly understood from the following description taken in conjunction with the accompanying drawings, in which like reference numerals designate like or corresponding elements, portions and parts, and in which: FIG. 1 is a circuit diagram for current mode control in a prior art buck converter. FIG. 2 shows a circuit diagram for current mode control in a buck-boost converter, where a slope compensation ramp is added to the measured inductor current. Figure 3 shows where a steep slope compensation ramp is used in a prior art buck converter. FIG. 4 shows where a slope compensation ramp is used for the high side or low side switch with an on-time greater than 50% of the total switching cycle time Tpd. FIG. 5A shows a slope compensation waveform with a wide dynamic range. FIG. 5B shows a slope compensation waveform with a small dynamic range and an additional clock. FIG. 5C shows a slope compensation waveform with a small dynamic range and an additional clock of the disclosure. FIG. 6A shows a first slope compensation configuration circuit of a related U.S. patent application. FIG. 6B shows a second slope compensation configuration circuit of a related U.S. patent application. FIG. 7A shows the slope compensation ramp during operation with an on-time between 50% and 100% of the total shift cycle time Tpd of the disclosure. FIG. 7B shows the slope compensation ramp during operation with an on-time equal to or less than 50% of the total shift cycle time Tpd of the disclosure. FIG. 7C shows the slope compensation ramp when the power converter is operating at 100% of the total switching cycle time Tpd of the disclosure. FIG. 7D shows other possible implementations of compensation ramps with an identical endpoint of the disclosure. FIGS. 7E and 7F are circuit diagrams illustrating in detail how the compensation ramps of the embodiments of the disclosure in FIGS. 7A-7C may be generated. FIG. 8 shows the transition of the slope compensation ramp at or near the 50% duty cycle operating condition of the disclosure. FIG. 9 is a flow diagram of a method for adaptive slope compensation in a DC-DC switching converter.Detailed DescriptionThe present disclosure enables slope compensation in a DC-DC switching converter while mitigating the disadvantages of prior art solutions. This includes reducing the required compensation ramp head space and operating jitter at or around the duty cycle operating point of 50%. Moreover, the preferred embodiment describes an implementation that is stable in operating conditions with minimized implementation complexity.The slope compensation ramp of the present disclosure provides compensation for subharmonic oscillation when the on-time of the high side switch is greater than 50% for the peak mode or the on-time of the low side switch is greater than 50% for the valley mode. The preferred embodiment makes the offset constant due to the ramp over several duty cycles (so that it can be easily removed), in addition to using two separate compensation ramps that are summed to produce a final compensation. It is also possible for one circuit to provide both compensation ramps.In switching DC-DC converters that use current mode control, a representation of the output current is used to determine when the converter is switching. This is proportional to the demanded output current and the current loop helps to regulate the output voltage faster than only in the voltage mode. The representation of the output current may be used as a form of current limiting and adjusts peak mode and valley mode currents for switching converters with non-uniform control types. It becomes necessary to add a compensation ramp to a current mode converter to prevent subharmonic oscillation.In most cases, a standard compensation ramp is added that is proportional to the maximum downward slope of current in a peak mode inductor or proportional to the maximum upward slope of current in a valley mode inductor, as shown in FIGS. 5A-5C, with only one ramp rate per half period. This is added during the on-time of a high side switching device for the peak mode or during the on-time of a low side switching device for the valley mode where the slopes are typically steeper.FIG. 5A shows a slope compensation waveform 500 with a wide dynamic range. Slope voltage (V) compensation 510 is presented over time (μs) for a wide dynamic range of a switching DC-DC converter. It should be noted that 500 may also be represented as current over time, depending on the type of controller (e.g., when added to the output current of an operational transconductance amplifier (OTA)). A large dynamic range indicates a long on-time case, for example, a high output voltage in the peak mode or a high input voltage and a low output voltage in the valley mode of a switching DC-DC converter.Compensation ramps add an offset at the point where current comparison is performed. This may mean that key elements in the design require a higher dynamic range than otherwise required and peak / valley current control imprecision is introduced into the system (unless removed with a separate circuit) as this offset conventionally varies with duty cycle. Subharmonic oscillation occurs when the decision to turn off the switching device is made high in the peak mode or low in the valley mode in the second half of the switching period. Therefore, the compensation ramp is only required for the second half of the switching period. This results in the use of half period ramps that add less offset to the current signal.FIG. 5B shows a slope compensation waveform 530 with a small dynamic range and an additional clock. This is the case when the starting point of the slope voltage compensation 540 is not at the beginning of the period but just before the half period point, because the compensation is not required for on-times less than 50% of the total switching cycle time Tpd. Here, a smaller dynamic range is used because during the first half period the slope voltage signal is flat. Note that an additional clock 550 is required to trigger the slope compensation. The variation of the offset for on-times >50% is the same as in Fig. 5A.It is also known that compensation ramps reduce jitter by more precisely defining the point at which the measured current exceeds the current control signal. For a ramp that only begins in the middle of the switching period for on-times of less than 50% of the total switching cycle time Tpd, this means that no compensation is added. It is therefore advantageous to add a smaller amount of compensation for the first half of the switching period to reduce jitter. This results in the use of a compensation ramp with two different slopes with a change in slope around the middle of the switching period as used in the current disclosure.FIG. 5C shows a slope compensation waveform 560 with a small dynamic range and an additional clock of the disclosure. As compared to FIG. 5A, the slope voltage compensation 575 is flatter at the beginning of the period, and two different slopes are required as compared to FIG. 5B. After some delay, the slope voltage becomes steeper to achieve the target slope for on-times of more than 50% of the total switching cycle time Tpd. Note that an additional clock 580 is required to trigger the slope compensations.Related U.S. patent application US 2019 / 0 097 518 A1, filed September 28, 2017, addresses the problem of large offset that a compensation ramp introduces, namely reducing the dynamic range of the switching converter in the current mode. It also removes the need for a second clock to trigger the ramp in the middle of a switching period.FIG. 6A shows 600 a first slope compensation configuration circuit of related U.S. patent application US 2019 / 0 097 518 A1 filed Sep. 28, 2017. The circuit includes a first capacitor C 1 and a current source Islope into the first capacitor at the drain of the first transistor 620, wherein the first transistor may be a MOS device. The switch 610, which is connected via the first capacitor at the output, generates a slope on a voltage compensation signal. This configuration further includes a second capacitor C 2 and a voltage reference Vref. The gate of the first transistor is connected to the voltage reference and the source of the first transistor is connected to the second capacitor.FIG. 6B shows 640 a second slope compensation configuration circuit of related U.S. patent application US 2019 / 0 097 518 A1 filed Sep. 28, 2017. Here, the voltage reference Vref is now reached with a compensated voltage reference Vref'+ Vgs. The circuit includes the first capacitor C 1 and the first current source Islope into the first capacitor at the drain of the first transistor 660, wherein the first transistor may be a MOS device. The switch 650, which is connected via the first capacitor at the output, generates a slope on the voltage compensation signal. This configuration further comprises a second capacitor C2 and a compensated voltage reference Vref'. The gate of the first transistor is connected to the virtual reference Vref= Vref'+ Vgs, and the source of the first transistor is connected to the second capacitor. This configuration further includes a second current source 670 at the drain of the second transistor 680, where the second transistor may be a MOS device. The source of the second transistor is connected to the voltage reference Vref', and its gate is connected to its drain, also the gate of the first transistor at the virtually compensated reference Vref.The circuits of FIGS. 6A and 6B are not used in the present disclosure, but show how V_OUT and V_IN control when switching of the compensation ramp occurs. The main difference is that the present disclosure uses a clock in phase opposition to the main clock to control the switching of the compensation ramp, where the ramp current varies with V_OUT and V_IN, but control does not. The present disclosure describes an adaptive slope compensation method in which the compensation ramp consists of two or more zones, each zone having a particular slope value. Moreover, the slope compensation ramp and the zones making up the compensation ramp are responsive to the particular operating duty cycle of the switching DC-DC converter.The general operation of the disclosed adaptive slope compensation ramp is illustrated in FIGS. 7A, 7B, and 7C. The figures show the slope compensation ramp at three different operating conditions over the duty cycle duration Tpd. FIG. 7A illustrates when the on-time is between 50% and 100% Tpd. FIG. 7B illustrates when the on-time is equal to or less than 50% Tpd. FIG. 7C illustrates when the on-time is at 100% Tpd. The final value of the current contributed from the slope at Tpd in all three cases is the same for all values of the output voltage V_OUT, namely [V_IN / [2*L1]]*Tpd. Also shown in FIGS. 7A, 7B, and 7C are the slope compensation ramps from the prior art examples of FIGS. 3 and 4.FIG. 7A shows 700 the slope compensation ramp during operation with an on-time between 50% and 100% of the total shift cycle time Tpd embodying the principles of the disclosure. During the second half of the switching cycle, period 2, the compensation ramp slope is provided to allow recovery from subharmonic conditions in the minimum time duration, one clock cycle. This corresponds to the upward slope of the current for the valley mode and the downward slope of the current for the peak mode. The slope calculated during operation in the valley mode is, for example:The slope compensation ramp of FIG. 7A is similar to the slope compensation ramp described in the prior art in FIG. 4 because both provide rapid recovery from subharmonic conditions while avoiding headspace problems found in the prior art in FIG. 3. However, there is a difference from the prior art in Figure 4 where the compensation ramp begins to avoid headspace problems at or near the middle of the switching cycle. In the present disclosure, there is a first period, period 1, starting at the beginning of the switching cycle and ending at or near the middle of the switching cycle, and a second period, period 2, starting at or near the middle of the switching cycle and ending at the end of the switching cycle. Both periods have a compensation ramp with a calculated slope, slope 705 for ramp 1 of period 1 and slope 710 for ramp 2 of period 2.FIG. 7B shows the slope compensation ramp during operation with an on-time equal to or less than 50% of the total shift cycle time Tpd. An important feature is that the slopes of the compensation ramps are the same during period 1, 735, ramp 1 and period 2, 740, ramp 2. The end point at the end of the switching cycle for the end current of the compensation ramps in FIGS. 7A, 715 and 7B, 715 is also the same for all V_OUT, namely [V_IN / [2*L1]]*Tpd. Note that the slope of the compensation ramp in FIGS. 7B, 740 is less than the slope of the compensation ramp during period 2 of FIGS. 7A, 710. This avoids differences in the compensation ramp when jitter is 50% duty cycle. For the valley mode, the slope of the entire compensation ramp is equivalent to V_OUT / L1 in period 1 and is equivalent to [V_IN-V_OUT] / L1 in period 2. For the peak mode, the slope of the entire compensation ramp is equivalent to [V_IN-V_OUT] / L1 in period 1 and is equivalent to [V_OUT] / L1 in period 2. Two separate ramp circuits may establish the final ramp and then the contributions are summed. If so, when ramp 1 is active for all on-time, the slope value of ramp 1 during period 2 must be subtracted from the total slope during period 2 when the two separate ramps are generated (so that when ramp 1 and ramp 2 are summed, the correct total slopes for period 2 are generated).It should be noted that for on-times of more than 50% Tpd, the resulting offset from the compensation ramp is constant. For on-times below 50% Tpd, the resulting offset from the compensation ramp is not constant. However, the dynamic range of the compensation ramp is significantly reduced overall, in particular if the slope is 0 or very flat.In operation with on-times of less than 50% Tpd, subharmonic effects are not as pronounced. Therefore, the slope of the compensation ramp need not ensure a worst case subharmonic recovery. Slope compensation also provides advantages beyond subharmonic recovery and is advantageous when operating with on-times of less than and greater than 50% Tpd. While the theoretical calculations indicate that no slope compensation is required for operation at less than 50% Tpd due to parasitic effects such as noise caused by equivalent series inductance (ESL) or equivalent series resistance (ESR) on the output capacitor, slope compensation is advantageous.In contrast to the case in FIG. 7A in which the difference in slopes between the ramp 1 of the period 1 and the ramp 2 of the period 2 was maximum, in FIG. 7B, the difference in slopes is minimum when the on-time is less than 50% Tpd. FIG. 7B shows that the slopes of the ramp 1 are equivalent to the period 1 and the ramp 2 is equivalent to the period 2. In a non-limiting example, the slope compensation ramp calculation for an on-time of 50% of the low side switch in the valley mode control may be calculated by:FIG. 7C shows 760 the slope compensation ramp when the power converter is operating at 100% of the total switching cycle time Tpd. The Period 1 ramp 1 765 and the Period 2 ramp 2 770 indicate the slopes of the compensation ramps when the required ramp is steepest. In a non-limiting example, the calculation of the slope compensation ramp in period 2 for an on-time of 75% of the low side switch in the valley mode control may be calculated by:For Embodiment 1, the final value at the end of the switching period 715 is the same value [V_IN / [2*L1]]*Tpd in FIGS. 7A, 7B, and 7C for maximum offset. The value at the application point is the offset value at the end of the on-time, which is also the same value in Embodiment 2. For Embodiment 1, the value at the end of the on-time varies with the duty cycle, and the value at the end of the switching period is constant. For Embodiment 2, the value at the end of the on-time is constant for all V_OUT (for more than 50% on-time), and the value at the end of the switching period is variable as a result. It should be noted that the offset and value at the end of the shift cycle still vary with V_IN when V_IN is a variable.The disadvantages of the prior art approach shown in FIG. 4, during operation at or near 50% duty cycle, include erratic operation or jitter as well as lack of advantageous slope compensation for less than 50% Tpd. It should be noted that when the duty cycle is discussed with respect to V_OUT and V_IN, this refers to the ideal / desired values of V_OUT and V_IN, rather than the actual values.The compensation ramp of the present disclosure shown in FIGS. 7A-7C demonstrates how these two problems are overcome. The slope of the ramp 1 of period 1 is greater than zero and the slope of the ramp 2 of period 2 is less than [V_OUT(max) / L1] for the peak mode or [V_IN(max) - V_OUT(min)] / L1 for the valley mode. Moreover, the end point of the ramp in period 1 is the same as the start point of the ramp in period 2.Finally, the fact that the endpoint of the compensation ramp in FIGS. 7A 715, 7B 715 and 7C 715 is the same for all V_OUT ([V_IN / [2*L1]]*Tpd) is not an essential aspect of the disclosure, but allows for a simpler implementation. The disclosure guarantees that a maximum current value is not exceeded when generating the compensation ramp. The endpoint value is designed to be less than the value achieved from the simple single constant ramp of the prior art of Fig. 3.It should be noted with reference to on-times that [V_OUT / V_IN]*Tpd for peak mode control (PMOS switch) and [[V_IN-V_OUT] / V_IN]*Tpd for valley mode control (NMOS switch) are relevant and must be compensated for when the on-time of the switch is greater than 50%Tpd.FIG. 7D shows 775 other possible implementations of compensation ramps of the disclosure with identical endpoint, cycle time Tpd. N periods instead of 3 periods are possible and when N approaches infinity, the corners of the compensation ramps are smoothed. In a non-limiting example of N periods, the compensation ramps look like lines 780, 785, 790, 795, etc. for different duty cycles.FIGS. 7E and 7F are circuit diagrams showing in detail how the compensation ramps may be generated for each embodiment of the disclosure in FIGS. 7A-7C. The compensation ramp 1 and compensation ramp 2 may use either the circuit in FIG. 7E or the circuit in FIG. 7F. The compensation ramp 1 controls the switch (either swA or swB) by opening it with clk1 and closing it at the end of the switching period Tpd. The compensation ramp 2 controls the switch (either swA or swB) by opening it with clk2 and closing it at the end of the on-time. To obtain the final compensation ramp, ramp 1 and ramp 2 are summed.FIGS. 7E and 7F show the output ramp current at the block level. To obtain the final ramp for control, it is normally passed through some type of sensing device or resistor to produce the correct magnitude in the voltage range. It should be noted that there are various ways to use the circuits, some examples of which follow for a buck converter. In the following examples, it is assumed that the term R1*R2*C in FIGS. 7E and 7F is equivalent to L1.• For the ramp with the fixed final value of [V_IN / [2*L1]]*Tpd (embodiment 1):◯ Valley Mode:▪ ramp 1 = FIG. 7E with VA = V_OUT▪ ramp 2 = FIG. 7F with VB = 2 * V_OUT▪ Total Slope during Period 2=[V_IN-V_OUT] / L1◯ Peak Mode:▪ ramp 1 = FIG. 7F with VB = V_OUT▪ ramp 2 = FIG. 7E with VA = [2 * V_OUT - V_IN]▪ Total Slope during Period 2 = V_OUT / L1• For the fixed offset ramp at the application point (embodiment 2):◯ Valley Mode:▪ ramp 1 = FIG. 7E with VA = 2 * V_OUT▪ ramp 2 = FIG. 7F with VB = 2 * V_OUT▪ Total Slope during Period 2 = V_IN / L1◯ Peak Mode:▪ ramp 1 = FIG. 7F with VB = V_OUT and using components to make the equivalent of [V_IN - V_OUT] 2 * [V_IN - V_OUT]▪ ramp 2 = FIG. 7E with VA = [2 * V_OUT - V_IN]▪ Total Slope during Period 2 = V_IN / L1FIG. 8 shows the transition of the slope compensation ramp at or near the 50% duty cycle operating condition. The compensation ramps for on-times greater than 50% Tpd and less than 50% Tpd are illustrated in period 2 by dashed lines 810 and 840, respectively, in period 1. FIG. 8 describes an adaptive compensation ramp during the transition from greater than 50% Tpd to less than 50% Tpd in 810, 820, 830 to 840 for period 2. FIG. 8 also describes the transition from less than 50% on-time to greater than 50% in 840, 825, 815 to 805 for period 1.During operation at more than 50% Tpd, the slope during period 1 tends to zero as the on-time increases. The slope during period 2 is [V_OUT / L1] for the peak mode and [V_IN-V_OUT] / L1] for the valley mode, as shown in FIG. 7A. As the on-time decreases and approaches 50% Tpd, the slope is increased during period 1 and the slope is decreased during period 2, according to the equations above. When the on-time further decreases, the slope during the period 1 is further increased, and the slope during the period 2 is further decreased. This continues until the on-time reaches less than 50% Tpd, as shown in FIG. 7B.During operation at less than 50% Tpd, the slopes during period 1 and period 2 are the same, as shown in FIG. 7B. As the on-time increases and approaches 50% Tpd, the slope is decreased during period 1 and the slope is increased during period 2, according to the equations above. When the on-time further increases, the slope during the period 1 is further decreased, and the slope during the period 2 is further increased. This continues until the on-time reaches more than 50% Tpd, as shown in FIG. 7A, where the slope during period 1 tends towards zero with increasing on-time and the slope during period 2 is for the peak mode [V_OUT / L1] and for the valley mode [V_IN-V_OUT] / L1.The compensation ramp of the present disclosure is obtained by changing the equations that generate the slopes of the ramp. These conditions occur when the total value of the ramp at the compensation point used for on-times of the low or high side switch of more than 50% Tpd is always the same value for each on-time >50% Tpd, while still being large enough for effective slope compensation.It should be noted that introducing the compensation ramp without correcting its contribution can introduce current imprecision into the system and the final current output by the switching converter. The imprecision at the application point of the compensation ramp varies.For example, in a valley mode implementation of Embodiment 1, the current imprecision at 100% Tpd is [V_IN / [2*L1]]* Tpd, the current imprecision at 50% duty cycle is [V_IN / [4*L1]]* Tpd, and the current imprecision at 75% Tpd is [5*V_IN / [16*L1]]* Tpd.In the valley mode, if the first slope is changed to [2*V_OUT] / L1 and the second slope to [V_IN / L1], then at the point where the compensation ramp is used, the value needed to correct this imprecision for on-times>50% Tpd is always [V_IN / [2*L1]]* Tpd (i.e., constant for all V_OUT). For the peak mode, the first slope becomes [2*[V_IN-V_OUT] / L1], and the second slope becomes [V_IN / L1] to obtain the same value required for the correction as in the case of the valley mode.In the valley mode, at 50% Tpd, when V_OUT = V_IN / 2, the first and in this case the total slope contribution is [V_IN / L1]*0.5*Tpd = [V_IN / [2*L1]]*Tpd. At 75% Tpd, when V_OUT=V_IN / 4, the total slope of the compensation ramp is [2*V_IN / [4*L1]]*0.5*Tpd+[V_IN / L1]*0.25*Tpd=[V_IN / [2*L1]]*Tpd.This results in a constant offset for all on-times >50% Tpd for all V_OUTs where a compensation ramp is required at stable conditions from which to simply subtract and correct the measurement. Even with small amounts of error in the system, the offset can be corrected quickly since the compensation ramp is close to the required value.The present disclosure may also be used with current mode in other DC-DC switching converters, where the compensation ramp may add an offset, and the disclosure attempts to reduce this offset.In summary, the present disclosure addresses the problem of the large offset introduced by a compensation ramp. It also reduces jitter for on-times less than 50% Tpd by using two different slopes for the ramp. Moreover, it reduces any discontinuities at the 50% duty cycle point where the slope changes between two compensation ramps. The disclosure particularly claims a compensation ramp in which the ramp rate for the first half of the switching period decreases with increasing on-time for on-times greater than 50% Tpd until and at 100% Tpd the ramp rate for the first half is approximately zero.Additionally, the disclosure particularly claims a ramp in which the ramp rate for the second half of the shift period decreases with decreasing on-time for on-times greater than 50% Tpd until at a duty cycle of 50% the ramp rate is equal to the ramp rate used for the first half of the shift period.Moreover, the disclosure particularly claims that at duty cycles of about 50% there is no discontinuity in the ramp slope and that the appropriate ramp is added for on-times greater than 50% Tpd, with the minimum offset being added by the ramp during the first half of the shift period.The first embodiment of the disclosure arranges the ramp rates so that the maximum offset that the ramp might add, the peak offset at the end of a switching period, is constant for all V_OUT. This is useful because it provides a clear limit for the offset that can be added. The second embodiment orders the ramp rates so that the actual offset added is constant for all V_OUT at all on-times >50% Tpd. This is useful because it can facilitate any correction for this offset.The present disclosure has a wide scope and covers several two-stage compensation ramp scenarios. This is useful in a current mode switching converter in which the current demand signal is used as a proxy for the output current. When the system generates the current demand signal, the current control loop ensures that the output current corresponds to the demand signal by adding a compensation ramp. The offset of the compensation ramp introduces errors that may be bulky for valley mode phases. The circuit of the disclosure is configured to adaptively eliminate this error, and when the duty cycle changes, the offset also changes. The adaptive circuit manages the changing offset by keeping the offset almost constant, thereby greatly improving the performance.FIG. 9 is a flow diagram 900 of a method for adaptive slope compensation in a current mode controlled DC-DC switching converter. The steps include 910 providing a compensation ramp comprising two or more zones, each zone having a particular slope value. The steps also include 920 modifying the slope compensation ramp and the zones making up the compensation ramp in response to a duty cycle. The steps also include 930 maintaining a maximum ramp current contribution for all values of an output voltage V_OUTat the end of the switching period (embodiment 1) or for on times >50% of the switching cycle time Tpdof a constant offset value for all V_OUTat the application point (embodiment 2).The main advantage of one or more embodiments of the present disclosure includes a compensation ramp that can be implemented with a constant offset value for all V_OUT, while most compensation ramps are achieved with a dynamic value or are not achieved at all.

Claims

An adaptive slope compensation circuit in a current mode controlled DC-DC switching converter, comprising: a compensation ramp (840, 810) comprising two or more zones (Period1, Period2), each zone having a particular slope value (805, 815, 825, 820, 830) configured to respond to a duty cycle and configured to maintain a maximum ramp current contribution for all values of an output voltage at an end of a switching period, or for on times > 50% of a total switching cycle time Tpd, to maintain a constant offset value at an application point for all values of the output voltage, wherein a clock is provided in anti-phase with the main clock to control switching of the compensation ramp (840, 810).The circuit of claim 1, wherein each of the slope values is configured to vary based on the duty cycle.The circuit of claim 1 or 2, wherein the slope value for a first zone is configured to decrease with increasing on-time for on-times greater than 50% of a total shift cycle time Tpd until at an on-time of 100% Tpd the slope value is approximately zero.The circuit of any of claims 1 to 3, wherein the slope value for a second zone is configured to decrease with decreasing on-time for on-times greater than 50% of a total switching cycle time Tpd until, at a duty cycle of 50%, the slope value is equal to a slope value used for a first zone.The circuit of any of claims 1 to 4, wherein the slope value for a first zone and the slope value for a second zone are approximately equal for a duty cycle of about 50%.The circuit of any of claims 1 to 5, wherein the two or more zones comprise two zones to generate a final compensation ramp.The circuit of any of claims 1 to 5, wherein the two or more zones comprise N zones to generate a final compensation ramp.The circuit of any of claims 1 to 7, wherein the DC-DC switching converter is a buck switching converter.The circuit of any of claims 1 to 7, wherein the switching DC-DC converter is a boost or other type of switching DC-DC converter.A method for adaptive slope compensation in a current mode controlled DC-DC switching converter, comprising: providing a compensation ramp (840, 810) comprising two or more zones (Period1, Period2), each zone having a particular slope value (805, 815, 825, 820, 830); modifying the compensation ramp (840, 810) and the zones (Period1, Period2) making up the compensation ramp (840, 810) in response to a duty cycle; providing a clock in phase opposition to the master clock to control switching of the compensation ramp (840, 810), maintaining a maximum ramp current contribution for all values of an output voltage at an end of a switching period, or for on-times >50% of a total switching cycle time Tpd, maintaining a constant offset value for all values of the output voltage at an application point.The method of claim 10, wherein each of the slope values varies based on the duty cycle.The method of claim 10 or 11, decreasing a slope value for a first zone with increasing on-time for on-times greater than 50% of a total shift cycle time Tpd until at 100% Tpd the slope value is approximately zero.The method according to any of claims 10 to 12, reducing a slope value for a second zone with decreasing on-time for on-times of more than 50% of a total switching cycle time Tpd until at a duty cycle of 50% the slope value is equal to a slope value used for a first zone.The method of any of claims 10 to 13, wherein a final compensation ramp comprises two zones.The method of any of claims 10 to 13, wherein a final compensation ramp comprises N zones.

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