DATA STORAGE AND METHOD OF PROVIDING THE SAME

Abstract

Data storage device comprising: a memory cell arrangement (12) with a plurality of planar memory cells; a multilayer arrangement (13) of access lines (14, 15) which provides a connection between the plurality of memory cells and which at least partially overlaps with the memory cell arrangement (12); wherein the multilayer arrangement (13) of access lines (14, 15) is configured such that when a first layer (161) of access lines (14) is removed while a second layer (162) of access lines (15) arranged between the first layer (161) and the memory cell arrangement (12) remains, at least one connection is interrupted;

Description

The present disclosure relates to a data storage device comprising a memory cell array and a protective multilayer array of connecting elements, as well as to a method for providing such a data storage device. The present disclosure further relates to securing a layout of an array of memory cells with variable (programmable) resistors (such as Resistive Random Access Memory—RRAM, CBRAM, PCRAM, MRAM). Non-volatile memory can consist of one or more arrays of memory cells, as well as additional supporting circuitry to operate the non-volatile memory elements located in the arrays. An attacker might be interested in physically reading the contents of the memory cells, for example, using needles or probes. EP 0 920 057 A2 describes an integrated data chip with a conductive shield. It describes the use of a chip with a secured area, a security element, and a device for changing the security element. Ideally, data storage devices and methods for providing them would be used that make such reading difficult for the attacker. According to one embodiment, a data storage device comprises a memory cell arrangement with a plurality of planar memory cells and a multilayer arrangement of connecting elements that provides a connection between the plurality of memory cells and that at least partially overlaps the memory cell arrangement. The multilayer arrangement of connecting elements is designed such that if a first layer of connecting elements is removed while a second layer of connecting elements, arranged between the first layer and the memory cell arrangement, remains, at least one connection is interrupted. According to one embodiment, a method for providing a data storage device comprises providing a memory cell arrangement with a plurality of planar memory cells and arranging an arrangement of connecting elements that provides a connection between the plurality of memory cells and that at least partially overlaps the memory cell arrangement. The method is implemented such that, due to the multilayered arrangement of connecting elements, the connection is interrupted when a first layer of connecting elements is removed, while a second layer of connecting elements remains between the first layer and the memory cell arrangement. Further advantageous embodiments are the subject of dependent patent claims. Advantageous embodiments are explained below with reference to the accompanying drawings. These show: Fig. 1 a schematic perspective view of a data storage device according to one embodiment; Fig. 2a a schematic view of a layout of a data storage device according to one embodiment, in which a plurality of memory cells are arranged in an exemplary matrix; Fig. 2b a schematic view of the data storage device from Fig. 2a, in which the memory cells are connected on one side according to one embodiment; Fig. 2c a schematic view of the data storage device from Fig. 2a with a connection on both sides according to one embodiment; Fig. 3a a schematic perspective view of a data storage device with a metallic bit line; Fig. 3b a schematic perspective view of a data storage device in which the arrangement from Fig.3a is extended by an additional line connected in parallel to the bit line; Fig. 4a a schematic perspective view of a data storage device in which a multi-layer arrangement of connecting elements is provided; Fig. 4b a schematic perspective view of a data storage device that can be obtained, for example, by removing the connecting elements of one layer as well as the connections to the layer below; Fig. 5 a schematic perspective view of a data storage device according to an embodiment in which the access lines in one layer have breaks as explained in connection with Fig. 1; Fig. 6 a schematic perspective view of a data storage device according to an embodiment in which an access line arranged in a first layer is connected in parallel with an access line arranged in another layer; Fig.7 a schematic perspective view of a data storage device according to an embodiment, which may be constructed similarly to the data storage device from Fig. 5, but supplemented by an additional line, which is explained in connection with Fig. 6; Fig. 8 a schematic perspective view of a data storage device according to an embodiment, which has a stacked arrangement of memory cells; and Fig. 9 a schematic flowchart of a method according to an embodiment. Before exemplary embodiments of the present invention are explained in detail below with reference to the drawings, it should be noted that identical, functionally equivalent or equivalent elements, objects and / or structures in the different figures are provided with the same reference numerals, so that the description of these elements shown in different exemplary embodiments is interchangeable or can be applied to one another. The following exemplary implementations are described in conjunction with a multitude of details. However, these implementations can also be implemented without these detailed features. Furthermore, for the sake of clarity, block diagrams are used to describe these implementations instead of detailed representations. Additionally, details and / or features of individual implementations can be readily combined unless explicitly stated otherwise. The following exemplary embodiments relate to the design of connecting elements configured to maintain a connection between memory cells of a memory cell arrangement in an undamaged or untampered state, thereby enabling the reading, programming, and / or operation of the memory cells. The connection can be, for example, electrical or optical. An electrical connection can be achieved using electrically conductive materials, particularly metals and / or doped semiconductor materials, while optical connections can utilize materials that are transparent in a relevant wavelength range, such as semiconductor materials or glass materials. The following embodiments are described with particular reference to RRAM memory cells (Resistive Random Access Memory - RRAM; a non-volatile electronic RAM memory type that stores information by changing its electrical resistance), although the embodiments are not limited to this but can be implemented with any memory cell with variable (programmable) resistances (such as RRAM, CBRAM, PCRAM, MRAM). These memory cells with variable (programmable) resistances can also be referred to by the English term "resistive-change memory cells". Fig. 1 shows a schematic perspective view of a data storage device 10 according to an exemplary embodiment. The data storage device 10 comprises a memory cell arrangement 12 with a plurality of at least two memory cells 121 to 124. The number of memory cells can also be significantly greater than 2, for example 5, 10, 100, or several thousand. The memory cells 121 to 124 are shown by way of example in a single-row arrangement along a y-direction, but can easily also be arranged in multiple rows, for example perpendicular to the y-direction along the x-direction. Both the single-row and the multi-row arrangement can be understood as a planar arrangement of the memory cells 121 to 124. The memory cell arrangement can also readily be arranged in multiple planes along the z-direction. The memory cells 121 to 124 can, for example, be configured as RRAM elements that change their resistance based on a programming current passed through them. For this purpose, a connecting element arrangement 13 can be arranged on one side of the memory cell arrangement 12, and another connecting element arrangement (not shown) can be arranged on the opposite side. In a simple case, this connecting element arrangement could, for example, comprise a common ground plane, an arrangement of circuit elements such as selection transistors or the like, and / or provide another means of current flow through the memory cells 121 to 124.As an alternative to memory cells with variable (programmable) resistors 121 to 124, the memory cell arrangement can also include any other current-programmable memory cells in which an electric current is passed through the memory cells 121 to 124 to change the programming status, such as RRAM, CBRAM, PCRAM, MRAM. The connecting element arrangement 13 can provide a multilayer arrangement of connecting elements 14, 15, which are arranged in two or more layers 161 and 162. The multilayer arrangement of connecting elements 14 and 15 overlaps at least partially with the memory cell arrangement 12, meaning that a projection of the memory cell arrangement into the x / y plane overlaps with a projection of the memory cell arrangement 12 into the x / y plane. Layer 161 and / or layer 162 can thus provide a shield layer for the memory cell arrangement 12. Position or plane 16 can be understood as an arrangement at a distance, height, or otherwise perpendicular to an x / y plane in the z-direction, such that, for example, the connecting element 15a, connected to memory cells 121 and 122, and the connecting element 15b, connected to memory cells 123 and 124, are arranged in position 162, which is located between memory cells 121 to 124 and position 161, in which the connecting element 14 is located. The connecting elements 15a and 15b can be two parts of a common connecting element 15, each implemented as electrically or optically isolated from the other. The electrical isolation can be achieved by an interruption or division into parts 15a and 15b, which is bridged by the connecting element 14 by connecting the connecting element 14 in parallel to parts 15a and 15b.The connecting elements 14 and 15 can each be access lines of the data storage 10 or implement other electrically / optically conductive data lines of the data storage 10. The connecting element 15, or the position 162 of connecting elements, thus provides an incomplete connection between the memory cells 121 to 124, which alone may not enable operation of the memory cells in the data storage device 10, since an interruption 18 is provided between the connecting element parts 15a and 15b, which can prevent electrical or optical signal transmission between the connecting element parts 15a and 15b. To bridge the interruption 18, the connecting element 14 can be provided, which is electrically or optically connected in at least one area to the connecting element part 15a and to the connecting element part 15b, so that the resulting parallel connection forms a combinational access line 15 for operating the memory elements 121 to 124.For example, the access line can individually and thus also combinationally comprise a bit line, a source line, a word line, or another line that is configured to transport a stream intended for accessing one or more memory cells 121 to 124. The layer 162 can also be described such that it provides an operational data storage only in combination with at least one further layer or layer of connecting elements. As shown in Fig. 1, the connecting elements in layers 161 and 162, through the connections 221 to 224, made of electrically or optically conductive material to provide a via, enable a connection between the memory cells 121 to 124 and thus access to the memory cells 121 to 124 during operation of the data storage device 10. In the event of an attack where layer 161 is removed, even if the connecting elements remain in layer 162, the connection between memory cells 121 to 124 may be interrupted. This would prevent or at least significantly impede the operation of the data storage 10, thus rendering the attack unattractive to the attacker. Connecting elements 14 and 15 can each form an access line for at least one memory cell 121 to 124, which are interconnected. Each layer 161 and 162 can have one or more connecting elements or access lines, depending, for example, on the chosen arrangement of the memory cells. Each connecting element can be connected to at least one memory cell. By connecting connecting elements 14 and 15 in parallel, the line break 18 can be bridged.A removal of position 161, for example in the course of the aforementioned attack, can therefore lead to a removal of the bridging and to the line interruption 18 becoming effective. The access line 15 can thus be interrupted along its axial path (running in the y-direction in Fig. 1) and, together with the access line 14, provide a combinational, uninterrupted access line based on the implemented parallel circuit. The access line can be used, for example, for a read access and / or a write access to at least one memory cell 121 to 124. Although the access line 15 is shown to have a single line break 18, alternative embodiments provide for two, three, five, or more line breaks along its axial path. These embodiments provide for connecting elements to be arranged in more than two layers 16 and connected to adjacent layers, for example, at least three layers, at least four layers, or at least five layers. It is possible, but not necessary, for a layer to be provided in which the connecting elements are implemented continuously. Therefore, line breaks can be provided in at least one, several, or optionally all layers 16. In other words, Fig. 1 shows an access line with stacked connecting elements and a break. Fig. 2a shows a schematic view of a layout of a data storage device 20 according to an embodiment in which a plurality of memory cells 1211 to 12ij are arranged in an exemplary matrix that can have i rows and j columns, where i ≥ 1 and j ≥ 1 with i + j ≥ 2. For example, the data storage device has a plurality of word lines 24, bit lines 26, and source lines 28 to enable read and / or write access to the memory cells 1211 to 12ij. One, several, or all of the word lines 24, bit lines 26, and / or source lines 28 can be implemented as a combinational access line, as described in connection with Fig. 1. In other words, the memory cells 12 of a memory array can be arranged in a matrix, meaning that each memory element can be selected using orthogonal (metal) lines, referred to, for example, as word lines and bit lines. Depending on the type of memory, additional lines may be provided, such as source lines. The data memory 20, for example, is an RRAM memory array. Fig. 2b shows a schematic view of the data memory 20, in which the memory cells 12 are connected on one side, which means that bit line drivers 321 and 322 as well as source line drivers 341 and 342 are arranged on the same side of the data memory 20. Fig. 2c shows a double-sided connection in which the bit line drivers 321 and 322 are arranged on opposite sides and the source line drivers 341 and 342 on opposite sides. Figures 2b and 2c show exemplary current flow patterns through the different lines. This illustrates that, particularly when using current-programmable lines, the specific resistance of the access lines can be significant. Depending on the memory type, a relatively high current (e.g., approximately 300 µA) can be used to program the memory cells, which must be driven through the cells. Such memory cells can be understood as current-programmable memory cells, in which, unlike voltage-based or voltage-programmable memory cells, the current flow influences or determines the change in the parameter representing the stored information. This current can lead to a voltage drop across the corresponding control lines, for example, bit lines and source lines. To avoid an excessive voltage drop, additional, parallel-connected connecting elements can be used, which, according to Ohm's law, can lead to a reduction in the effective resistance when compared to a single line, as exemplified in Fig. 3a using a data storage device 30' where memory cells 121 to 124 are connected by a metallic bit line 26. Fig. 3b shows a schematic perspective view of a data storage device 30' in which the arrangement from Fig. 3a is connected by an additional bit line 261 connected in parallel to the bit line, which is connected in parallel to the bit line 262 by means of the connecting elements 221 to 224 in order to reduce the effective resistance of the bit line 26 from Fig. 3a. In other words, for example, in RRAM cells, the programming current can be routed from the bit line driver through the bit line, through the memory cell, along the source line to a source line driver (or vice versa). Although the word line does not necessarily have to carry high currents, exemplary embodiments can readily be used for the word line as well. These exemplary embodiments provide for a corresponding multilayer configuration of the access lines by means of a break located in a position facing memory cells 121 to 124. Fig. 4a shows a schematic perspective view of a data storage device 40, in which a multi-layered arrangement of connecting elements 141 to 145 and 151 to 155 is provided, but in which the interruption in the connecting elements 15 explained for Fig. 1 is not implemented. Fig. 4b shows a schematic perspective view of a data storage device 40', which can be obtained, for example, by removing the connecting elements 141 to 145 and the connecting elements 22 of the data storage device 40, for example, during an attack. It becomes clear that although the aforementioned reduction in effective resistance may be lost, potentially electrically inefficient operation of the data storage device 40' is still possible. Fig. 5 shows a schematic perspective view of a data storage device 50 according to an embodiment in which the access lines in position 162 have the breaks 181 to 185 described in connection with Fig. 1. Adjacent connecting elements 151 to 155 of position 162 are arranged, by way of example, along an axial direction parallel to the y-direction. Several of these lines can be arranged perpendicular to this direction and offset from one another parallel to the x-direction. Along the x-direction, that is, perpendicular to the axial direction, the breaks 181 to 185 can be arranged at a position or in corresponding areas that are at least substantially the same within a tolerance range of ± 15%, ± 10%, or ± 5% or less. This can enable the formation of symmetrical island regions of memory cells when position 161 is removed.An island area can be understood as a region of memory cells that, despite the occurrence of the interruption 181 to 185, are still connected to each other by conductive structures, for example memory cells 1253 and 1254 or memory cells 1251 and 1252. Alternatively, adjacent access lines of the second layer may exhibit the interruption in different areas, which makes the attack more difficult, as the interruption must be found for each of the access lines 151 to 155. In other words, the lower metal conductors of the conductor stack can be interrupted at regular or irregular intervals, with the interruption resulting in only a slight increase in conductor resistance. This ensures that the upper layer of conductors can no longer be removed over a large area without preventing the operation of the data storage device. This means that as soon as the shielding layer is removed in the area of ​​the interruption 18, the data storage device is disabled in that area. In other words, Fig. 5 shows a planar layout with interruptions. Fig. 6 shows a schematic perspective view of a data storage device 60 according to an embodiment in which an access line 14 arranged in position 161 is connected to an access line 15 arranged in position 162, as explained, for example, in connection with Fig. 1. Furthermore, an additional line 36 of the data storage device 60 can be arranged in position 161 next to the access line 14. The additional line 36 may be provided or required for the operation of the data storage device 60, so that if position 161 is removed during an attack, the line 36 is also removed, thus making the operation of the data storage device 60 more difficult or impossible in addition to the occurrence of the interruption 18. For example, the additional line 36 may be a decoder line, a power supply line, or a line provided for integrity checking.It is possible without restriction to implement other functions for the additional line 36, either alternatively or additionally. Some embodiments provide that no overlap is implemented along the z-direction between the memory cell arrangement 12 and the additional line 36, meaning that the additional line 36 is arranged without overlap with memory cells of the memory cell arrangement 12 along the z-direction. This advantageously prevents memory cells from being accessible via a potentially uninterrupted access line if the additional line 36 is removed. In other words, Fig. 6 shows an access line layout with stacked metal wires and parallel routing of a decoder signal or a signal that is important for the operation of the data storage. Fig. 7 shows a schematic perspective view of a data storage device 70 according to an embodiment, which can be constructed similarly to the data storage device 50, but supplemented by the additional line 36, which is explained in connection with Fig. 6. The additional line 36 can be arranged between access lines 142 and 143 of layer 161. As explained in connection with the data storage device 60, the additional line 36 can be arranged without overlap with memory cells of the memory cell arrangement 12 along the z-direction. While the interruptions 181 to 184 enable segmentation of the memory cells of the memory cell arrangement 12 along the y-direction, the additional line 36 enables segmentation of the memory cells into island areas 381 to 384 along the x-direction. Thus, if layer 161 is removed, the size of the island areas 38 can be determined to specify the maximum distance along the x and / or y directions that allows layer 161 to be removed while still enabling, albeit in a degraded or limited, operation of the data storage 70. For example, the island area 383 can be configured by interruptions 183 and 184 on the one hand, and by the position of the additional line 36 on the other, such that layer 161 can be removed no further than the area of ​​memory cells 1231, 1232, 1241, and 1242, allowing the data storage 70 to continue operating in this area.Outside the respective island area, it is not possible to remove location 161 while avoiding an interruption of the connection in the access line. Exemplary embodiments provide that the multilayer arrangement of connecting elements 14, 15 is designed such that the connection is interrupted when the outermost layer of connecting elements, starting from the memory cell arrangement, is removed. In such an embodiment, the connecting element arrangement 13 can have more than two layers 16. The outermost layer can be understood as the layer that has the greatest comparative distance to the memory cells 12. By implementing the interruptions and by a suitable arrangement of the connecting elements 22, a combinatorial access link can be maintained, which, however, is interrupted by the removal of the outermost layer.Although the embodiments described herein show a regular arrangement of interruptions, access lines, parts thereof and also of the connecting elements 22, these arrangements can also be implemented irregularly, individually or in combination. In such an embodiment, the connecting element arrangement 13 can have more than two layers 16. The outermost layer can be understood as the layer that has the greatest comparative distance to the memory cells 12. By implementing the interruptions and by a suitable arrangement of the connecting elements 22, the maintenance of a combinational access line can be ensured, which, however, is interrupted by the removal of the outermost layer. Although the embodiments described herein show a regular arrangement of interruptions, access lines, and parts thereof, as well as the connecting elements 22, these arrangements can also be implemented irregularly, individually or in combination. The data storage devices described above can have a single-layer arrangement of memory cells, meaning that the memory cells of the memory cell arrangement 12 are arranged in a common x / y plane. A one-plane arrangement can be understood for any elements referenced herein as meaning that the elements are partially arranged in that plane, implying that the three-dimensional body penetrates the two-dimensional plane. In contrast, other embodiments provide that a subset of the memory cells is arranged in a first memory cell layer and another subset of memory cells in a different second memory cell layer. The different memory cell layers can be offset from each other along the z-direction. For example, the different memory cell layers can be arranged in a stacked configuration. In other words, Fig. 7 shows an embodiment in which the upper metal conductors of the connector stack are interrupted at regular or irregular intervals, or provided with gaps in which other conductors are arranged. These conductors are designed to carry signals essential for the operation of the data storage device, such as decoder lines. Here, too, it is possible to disable the data storage device by removing the upper signal conductors, which can act as a shielding layer. While the additional conductors may require additional space in the layout, they can also be used to replace dummy conductors, which are sometimes necessary to surround word line stitches. In other words, a combination of interrupting the access line and using additional lines in position 161 can provide a high degree of protection against the attacks described. Interrupting the access lines can provide a separation of the memory array into islands orthogonal to the interrupted lines, while the additional lines 36 can provide a separation of the memory array along this direction, that is, perpendicular to the direction of the interruptions. Boundaries of these island structures 38 can indicate areas where the attacker cannot remove the top layer without disabling the data storage (without further measures). It should be noted that the representations in the figures are merely exemplary and any number of memory cells, access lines, and / or additional lines in any geometry can be chosen.The structures shown can be repeated multiple times in any direction, especially x and / or y, but also along z. A division into many small island structures can lead to an efficient shielding position. Fig. 8 shows a schematic perspective view of a data storage device 80 according to an embodiment, which has a stacked arrangement of memory cells. Memory cells 121 to 124 can be arranged in a first layer 421 of memory cells, while further memory cells, in the same or a different number, can be arranged in a second layer 422, for example, memory cells 125 to 128. For example, layer 422 can also be connected by an access line 152 with a break 182, wherein the break 182 can be bridged by an access line 142, as described in connection with the data storage device 10.The data storage device 80 can, for example, be configured such that a mirror image of the data storage device 10 is performed on an x / y plane, with the two mirrored arrangements being connected, for example, via a common circuit plane 44, such as for the return of currents flowing through the storage elements. For example, selection transistors for selecting memory cells can be arranged in the circuit plane 44. A similar circuit plane can be provided in the data storage devices 10, 20, 50, 60, or 70, even in the case of a single-layer arrangement of memory cells. For example, the circuit plane 44 can be located on the side of the memory cells facing away from the connecting element arrangement 13. In the arrangement shown in Fig. 8, the connecting element arrangement 13 can also be designed such that the removal of an outer layer of connecting elements or access lines leads to interruptions. The memory cell layers 421 and 422 can each overlap with a part of the connecting element arrangement, which can provide protection for both or all layers of the memory cell arrangement. According to one embodiment, the memory cell layers 421 and 422 can be arranged in a cross-point arrangement (cross-point = intersection point). Fig. 9 shows a schematic flowchart of a method 900 according to an exemplary embodiment. Step 910 comprises providing a memory cell arrangement with a plurality of planar memory cells. Step 920 comprises arranging an arrangement of connecting elements that provides a connection between the plurality of memory cells and that at least partially overlaps the memory cell arrangement. The method is implemented such that, due to the multilayer arrangement of connecting elements, the connection between the memory cells is interrupted when a first layer of connecting elements is removed, while a second layer of connecting elements remains between the first layer and the memory cell arrangement. The effect of interruptions in the access lines can be used for both read and write access lines. For each of these uses, and especially for the combined use of the possible implementations, a high level of security for memory cells can be achieved against attacks aimed at reading the memory contents by performing a physical preparation step followed by imaging or contacting the memory cells. Such attacks can hardly be completely prevented.Exemplary implementations aim to make these attacks so difficult that the physical preparation becomes so complex that it is very hard for an attacker to maintain the functionality of the data storage after preparation, while keeping the costs of implementing the described security advantages low. This is achieved in particular by implementing special layout rules for the conductive intermediate contacts between the memory cells of the memory cell array / arrangement. Exemplary implementations are explained in connection with RRAM memories, but are equally applicable to other types of memory, especially non-volatile memories. These include, in particular, MRAM (magnetoresistive memory), CBRAM (conductor bridge memory), PCRAM (phase-transition memory), or other current-programmable memory cells. Exemplary embodiments rely on the use of a stack of conductive connecting elements at high currents to reduce the voltage drop described above, particularly to ensure the correct operation of the data storage device. The conductive connecting elements are stacked in different layers to reduce the effective resistance of the access lines. These lines can be connected at regular or irregular intervals using connecting elements 22, such as vias. The upper conductors can serve as a shielding layer, making it difficult to locate and read the memory cells. While in a simple stack of uninterrupted conductors, removing this layer can still allow the memory to operate, in other embodiments, the resulting interruption in the conductors prevents operation, at least outside of isolated areas, thus also preventing reprogramming of the memory cells across the entire area. Although some aspects have been described in connection with a device, it is understood that these aspects also constitute a description of the corresponding process, so that a block or component of a device is also to be understood as a corresponding process step or as a feature of a process step. Similarly, aspects described in connection with or as a process step also constitute a description of a corresponding block, detail, or feature of a corresponding device.

Claims

Data storage device comprising: a memory cell arrangement (12) with a plurality of planar memory cells; a multilayer arrangement (13) of access lines (14, 15) which provides a connection between the plurality of memory cells and which at least partially overlaps with the memory cell arrangement (12); wherein the multilayer arrangement (13) of access lines (14, 15) is configured such that when a first layer (161) of access lines (14) is removed while a second layer (162) of access lines (15) arranged between the first layer (161) and the memory cell arrangement (12) remains, at least one connection is interrupted; Data storage device according to claim 1, wherein the first layer (161) of access lines (14) comprises a first access line for at least one memory cell, which is connected in parallel with a second access line (15) of the second layer (162) of access lines having a line break (18) in order to provide a bridging of the line break (18). Data storage device according to claim 2, wherein a removal of the first layer (161) of access lines leads to a removal of the bridging and to the occurrence of the line interruption (18). Data storage device according to claim 2 or 3, wherein the second access line (15) is interrupted along its course, wherein the first access line (14) connected to the second access line (15) is connected to the second access line (15) in a parallel circuit, wherein the first access line (14) and the second access line (15) combine to provide an uninterrupted access line. Data storage device according to one of claims 2 to 4, wherein adjacent access lines of the second layer (162) are arranged along an axial extension direction (y) and have line breaks (18) at corresponding areas along a direction (x) perpendicular to the axial course. Data storage device according to one of claims 2 to 4, wherein adjacent access lines of the second layer (162) are arranged along an axial extension direction (y) and have line breaks (18) at different regions along a direction (x) perpendicular to the axial course. Data storage device according to one of claims 2 to 6, wherein the at least one first access line in the second layer (162) has at least one line break (18). Data storage device according to one of the preceding claims, wherein the multilayer arrangement of access lines (14, 15) comprises a combinational access line having an access line (15) arranged in the second layer (162) which is provided with an interruption (18), wherein the interruption (18) is bridged by access line (14) of the combinational access line arranged in the first layer (161) and connected to the second layer (162). Data storage device according to claim 8, wherein the combinational access line is a line that is configured to transport a current intended for accessing a memory cell. Data storage device according to claim 8 or 9, wherein the combinational access line is a bit line (26) or a source line (28) or word line (24). Data storage device according to one of the preceding claims, wherein an access line (14) arranged in the first layer (161) of the access lines is connected to an access line (15) arranged in the second layer (162) and an additional line (36) of the data storage device is arranged between access lines of the first layer (161). Data storage device according to claim 11, wherein the memory cell arrangement in the position of the memory cell arrangement (12) and the additional line (36) do not overlap. Data storage device according to claim 11 or 12, wherein a course of the additional line (36) on the one hand and an interruption (18) of the access line (15) in the second layer (162) on the other hand define an island area (38) of the second layer at least partially, wherein the island area (38) defines an area at least partially outside of which a removal of the first layer (161) without interrupting the connection is not possible. Data storage device according to one of the preceding claims, in which the multilayer arrangement of access lines (14, 15) is configured such that the connection is interrupted when an outermost layer (161) of the access lines is removed starting from the storage cell arrangement (12). Data storage device according to one of the preceding claims, wherein the majority of memory cells are memory cells with variable (programmable) resistors. Data storage device according to one of the preceding claims, wherein a first subset of the memory cells is arranged in a first memory cell layer (421) and a second subset of the memory cells is arranged in a second memory cell layer (422) different from the first, wherein the first memory cell layer (421) and the second memory cell layer (422) are arranged in a stacking arrangement. Data storage device according to claim 16, wherein the first memory cell layer (421) overlaps with a first part of the control circuit and the second memory cell layer (422) overlaps with a second part of the control circuit, wherein the first memory cell layer (421) and the second memory cell layer (422) are arranged in a stack arrangement between the first part and the second part of the control circuit. Data storage device according to claim 16 or 17, wherein the first memory cell layer (421) and the second memory cell layer (422) are arranged in a cross-point arrangement. Data storage device according to one of the preceding claims, wherein the memory cells are configured as RRAM cells. Data storage device according to one of the preceding claims, wherein the first layer (611) provides a shielding layer for the memory cell arrangement (12). Method (900) for providing a data storage device comprising the following steps: providing (910) a memory cell arrangement with a plurality of planar memory cells; arranging (920) an arrangement of access lines which provides a connection between the plurality of memory cells and which at least partially overlaps with the memory cell arrangement; such that, due to the multilayer arrangement of access lines, if a first layer of access lines is removed while a second layer of access lines arranged between the first layer and the memory cell arrangement remains, the connection is interrupted.

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