Semiconductor device and method for manufacturing a semiconductor device

Abstract

Semiconductor device comprising: an insulation substrate (5) containing a circuit structure (8); Semiconductor chips (10, 11) mounted on the circuit structure (8); a wire (14, 24) connecting between the semiconductor chips (10, 11) and between at least one semiconductor chip (11) and the circuit structure (8); and a conductor (20, 21, 22) formed integrally with the wire (14, 24), wherein the conductor (21, 22) comprises a conductive material (15) formed on the wire (14) and a plate-shaped conductive material (16, 17) attached to the wire (14), wherein the conductive material (15) is arranged between the plate-shaped conductive material (16, 17) and the wire (14), and a plurality of pairs of semiconductor chips (10, 11) are connected in parallel and a conductor (21) connects the plurality of pairs of semiconductor chips (10, 11).

Description

BACKGROUND OF THE INVENTIONField of the invention

[0001] The present invention relates to a semiconductor device used for any situations such as power generation, power transmission, and efficient use and recovery of energy. Description of the background technology

[0002] In most power semiconductor devices, a wire made of Al, Cu, or the like is used for connecting a semiconductor chip and a circuit pattern, and for connecting a plurality of semiconductor chips. However, as the semiconductor device is downsized, the number of wires is reduced, resulting in an increase in the current density per wire and excessive heat generation from the wires.

[0003] For example, JP 2009-027041 A discloses a method for suppressing the current density of a wiring. A wiring method described in JP 2009-027041 A is a method used when a plurality of stacked semiconductor chips are wired together. In this method, a gold wire is formed on a side surface of each of the plurality of semiconductor chips, and the plurality of semiconductor chips are connected together with a conductive paste.

[0004] However, when the method described in JP 2009-027041 A is applied to a power semiconductor device in which a current of several tens of amperes to several hundred amperes flows, the connection of a semiconductor chip and a circuit pattern and the connection of a plurality of semiconductor chips are made only with a conductive paste, resulting in an increase in the impedance of the connection of the semiconductor chip and the circuit pattern and an increase in the impedance of the connection of the plurality of semiconductor chips. Moreover, there is a possibility of separation due to poor molding of the formed conductive paste or poor contact of the formed conductive paste with a conductor, that is, poor wetting, or the like, and as a result, the characteristics of a product deteriorate, which in turn easily leads to a defect in product quality.

[0005] WO 2019 / 044 748 A1 discloses gates of a plurality of semiconductor switching elements electrically connected to a common gate control pattern by wires; and discloses sources of the plurality of semiconductor switching elements electrically connected to a common source control pattern by wires.

[0006] US 2010 / 0 308 457 A1 discloses a semiconductor device comprising a first electrode terminal, a second electrode terminal, and at least two wires connecting the first and second electrode terminals. At least two wires are electrically connected to each other using a conductive adhesive in an extending direction of the wires. The first electrode terminal is a terminal of an external lead electrode. The second electrode terminal is a terminal of a source electrode of a MOSFET.

[0007] JP 2000-243778 A discloses providing a semiconductor device structure in which Au wires are connected to an electrode pad on a semiconductor element formed on a substrate. The wires are connected at their other end to an equal-potential wiring part formed on the substrate. A conductive Au film is formed between the wires. A polyimide insulating film is formed on the semiconductor element while adjacent to the electrode pad, and an SiO2 insulating film is formed on the substrate.

[0008] DE 11 2017 007 430 T5 describes a semiconductor module comprising a substrate, a semiconductor element, and a wire. The semiconductor element is connected to the substrate and has a surface electrode. Both ends of the wire are connected to the substrate such that the wire runs over the surface electrode of the semiconductor element. The wire is electrically connected to the surface electrode.

[0009] DE 10 2012 208 251 A1 describes an electrical contact between two contact surfaces. The electrical contact is strip-shaped and designed as a sandwich structure.

[0010] DE 10 2005 028 951 A1 describes an electrical connection arrangement between a semiconductor circuit arrangement and an external contact device, as well as a method for producing the connection arrangement. In this method, a metallic layer is deposited on a contact terminal and / or the contacts and the wire. SUMMARY

[0011] It is therefore an object of the present invention to provide a technique that enables miniaturization of a semiconductor device without impairing reliability.

[0012] This problem is solved by the features of the independent claims. The subclaims contain advantageous embodiments of the invention.

[0013] A semiconductor device according to one aspect of the invention comprises an insulating substrate, a plurality of semiconductor chips, a wire, and a conductor. The insulating substrate contains a circuit structure. Semiconductor chips are mounted on the circuit structure. The wire connects between the semiconductor chips and between the semiconductor chip and the circuit structure. The conductor is formed integrally with the wire.

[0014] Since in addition to the wire, the conductor connects between the semiconductor chips and between the semiconductor chip and the circuit structure, it is possible to reduce a current density per wire, and consequently, it is possible to reduce the number of wires.

[0015] Since the conductor is connected in addition to the wire, it is possible to reduce not only the impedance of the wiring for connection between the semiconductor chips and between the semiconductor chip and the circuit structure, but also the probability of disconnection. As described above, it is possible to downsize the semiconductor device without compromising reliability.

[0016] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view of a semiconductor device according to a first example; Fig. 2 is a cross-sectional view of semiconductor chips included in the semiconductor device and surroundings of the semiconductor chips; Fig. 3 is a plan view of the semiconductor chips and the surroundings of the semiconductor chips; Fig. 4 is a cross-sectional view of semiconductor chips included in a semiconductor device according to a second example and surroundings of the semiconductor chips; Fig. 5 is a plan view of the semiconductor chips and the surroundings of the semiconductor chips; Fig. 6A and Fig. 6B are cross-sectional views of a semiconductor device according to a third example for describing a method of manufacturing the semiconductor device; Fig. 7 is a plan view of semiconductor chips included in the semiconductor device according to the third example and surroundings of the semiconductor chips; Fig. 8 is a plan view of semiconductor chips included in a semiconductor device according to a fourth example and surroundings of the semiconductor chips; Fig. 9 is a plan view of semiconductor chips included in a semiconductor device according to a fifth example and surroundings of the semiconductor chips; Fig. 10 is a plan view of semiconductor chips included in a semiconductor device according to a sixth example and surroundings of the semiconductor chips; Fig. 11 is a plan view of the semiconductor chips and the surroundings of the semiconductor chips without a conductor provided; Fig. 12 is a plan view of semiconductor chips included in a semiconductor device according to a seventh example and surroundings of the semiconductor chips; Fig. 13 is a plan view of semiconductor chips included in a semiconductor device according to an eighth example and surroundings of the semiconductor chips; Fig. 14A and Fig. 14B are plan views of a semiconductor device according to a ninth example for describing a method of manufacturing the semiconductor device; and Fig. 15 is a plan view of semiconductor chips included in a semiconductor device according to a tenth example and surroundings of the semiconductor chips. DESCRIPTION OF THE EXAMPLES<Erstes Beispiel>

[0017] A first example is described below with reference to the drawings. Fig. 1 is a cross-sectional view of a semiconductor device according to the first example. Fig. 2 is a cross-sectional view of semiconductor chips included in the semiconductor device and surroundings of the semiconductor chips, specifically an enlarged view of a region enclosed by a dashed line in Fig. 1 surrounding part of the area. Fig. 3 is a plan view of the semiconductor chips and the surroundings of the semiconductor chips.

[0018] As in Fig. 1, the semiconductor device is a power module and includes a package 1, a base plate 4, an insulating substrate 5, semiconductor chips 10, 11, a wire 14, a conductive material 15 serving as a conductor 20, a signal terminal 2, an electrode 3, a gel 12, and a cover 13.

[0019] The housing 1 includes a peripheral wall portion 1a with a rectangular frame shape in plan view, which surrounds the base plate 4, the insulating substrate 5, the semiconductor chips 10, 11, the wire 14, and the conductive material 15. The base plate 4 is made of metal such as Cu and has a rectangular shape in plan view. The base plate 4 is fixed to a bottom surface of the housing 1 in such a way as to allow a top surface of the insulating substrate 5 to be partially exposed.

[0020] The insulation substrate 5 is fixed to an upper surface of the base plate 4 with a solder 9 and includes a ceramic plate 7, a circuit pattern 8, and a metal pattern 6. The circuit pattern 8 is formed on an upper surface of the ceramic plate 7, and the metal pattern 6 is formed on a lower surface of the ceramic plate 7.

[0021] The semiconductor chips 10, 11 are each formed of a wide-bandgap semiconductor such as SiC and are mounted on an upper surface of the circuit structure 8 with the solder 9 disposed between the semiconductor chips 10, 11 and the upper surface of the circuit structure 8. The semiconductor chip 10 is, for example, an insulated-gate bipolar transistor (IGBT), and the semiconductor chip 11 is, for example, a diode.

[0022] The signal terminal 2 and the electrode 3 are attached to the peripheral wall portion 1a of the package 1. The wire 14 connects between the semiconductor chip 10 and the signal wire 2, between the semiconductor chips 10, 11, between the semiconductor chip 11 and the circuit pattern 8, and between the semiconductor chip 11 and the electrode 3.

[0023] The gel 12 fills an interior of the housing 1 to cause a part of the upper surface of the base plate 4, the insulating substrate 5, the semiconductor chips 10, 11, the wire 14, and the conductive material 15 to be encapsulated in the gel 12. The cover 13 is attached to an inner peripheral portion of an upper end portion of the peripheral wall portion 1a of the housing 1.

[0024] Next, a description will be given of the conductive material 15. As in Fig. 2 and Fig. As shown in Fig. 3, the conductive material 15 is integrally formed with a plurality of wires 14 along the upper sides in a longitudinal direction of the plurality of wires 14 connecting between the semiconductor chips 10, 11 and between the semiconductor chip 11 and the circuit pattern 8. Herein, the conductive material 15 has a lower linear expansion coefficient than the wires 14, making it possible to suppress expansion and contraction of the wires 14 while the semiconductor chips 10, 11 are in operation.

[0025] Next, a description will be given of a method for forming the conductive material 15. First, after bonding the plurality of wires 14 with a dispenser or the like, a conductive paste is applied to the upper surfaces of the wires 14 in the longitudinal direction. Then, the conductive paste is cured into the conductive material 15 by, for example, heat treatment. This causes the conductive material 15 to electrically connect the plurality of wires 14.

[0026] Note that when aluminum wires are used for the wires 14, wettability with the conductive paste cannot be maintained. Therefore, it is preferable to use an aluminum wire comprising an Al base and a Ni or Cu coating, with the coating wrapped around the base.

[0027] Selecting a combination having good wettability (for example, a combination of a chip surface made of Cu or Au and a conductive paste made of solder) for a metal on the surfaces of the semiconductor chips 10, 11 and the conductive paste enables the conductive paste to be applied to surroundings of a connection portion where the semiconductor chips 10, 11 are connected to the wires 14.

[0028] As described above, the semiconductor device according to the first example includes the insulating substrate 5 including the circuit pattern 8, the plurality of semiconductor chips 10, 11 mounted on the circuit pattern 8, and the wires 14 connecting between the semiconductor chips 10, 11 and between the semiconductor chips 11 and the circuit pattern 8, and the conductor 20 integrally formed with the wires 14.

[0029] Since the conductive material 15 serving as the conductor 20 connects between the semiconductor chips 10, 11 in addition to the wires 14 and connects between the semiconductor chip 11 and the circuit pattern 8, it is possible to reduce a current density per wire, and thus it is possible to reduce the number of wires 14.

[0030] Because the conductive material 15 is connected in addition to the wires 14, it is possible to reduce the impedance of the connection between the semiconductor chips 10, 11 and the impedance of the connection between the semiconductor chip 11 and the circuit pattern 8, which in turn makes it possible to reduce the probability of disconnection. As described above, it is possible to downsize the semiconductor device without compromising reliability.

[0031] Since the current density can be kept low even with a small number of wires 14, it is further possible to increase a degree of freedom in the design of the semiconductor device.

[0032] Since the conductor 20 is formed by applying the conductive paste to the wires 14 and curing it, it is possible to easily form the conductor 20 on the wires 14.

[0033] If the conductive material 15 is also formed near the connection portion where the semiconductor chips 10, 11 are connected to the wire 14, heat generated by the semiconductor chips 10, 11 is immediately dissipated by the conductive material 15, and thus, it is possible to achieve an effect of suppressing a temperature increase immediately after heat generation. Furthermore, it is possible to improve a power cycle (P / C) characteristic in view of the reliability of the semiconductor device.

[0034] While the semiconductor chips 10, 11 are in operation (when a temperature change occurs), a voltage is applied to respective interfaces of the semiconductor chips 10, 11; however, if the conductive material 15 has a lower linear expansion coefficient than the wires 14, it is possible to suppress expansion and contraction of the wires 14 while the semiconductor chips 10, 11 are in operation, which makes it possible to suppress mechanical stress applied to the interfaces between the semiconductor chips 10, 11 and the wires 14, and in turn makes it possible to further improve the P / C characteristic. <Zweites Beispiel>

[0035] Next, a semiconductor device according to a second example will be described. Fig. 4 is a cross-sectional view of the semiconductor chips 10, 11 included in the semiconductor device according to the second example and surroundings of the semiconductor chips 10, 11. Fig. 5 is a plan view of the semiconductor chips 10, 11 and the surroundings of the semiconductor chips 10, 11. Note that in the second example, the same components as described in the first example are denoted by the same reference numerals, and thus no description of the components will be given.

[0036] As in Fig. 4 and Fig. 5, in the second example, the semiconductor device includes flat wires 24 instead of the wires 14. The flat wires 24 are each made of a composite material consisting of dissimilar metals such as Al and Cu being bonded together.

[0037] The conductive material 15 serving as the conductor 20 is integrally formed with the flat wires 24 along the upper sides in a longitudinal direction of the flat wires 24 connecting between the semiconductor chips 10, 11 and between the semiconductor chip 11 and the circuit pattern 8. A method for forming the conductive material 15 on the flat wires 24 is the same as the method of the first example, and thus, no description of the method will be given.

[0038] As described above, since the flat wires 24 are used in the semiconductor device according to the second example, the same effect as in the first example can be achieved. <Drittes Beispiel>

[0039] Next, a semiconductor device according to a third example will be described. Fig. 6 is a cross-sectional view of a semiconductor device according to the third example for describing a method of manufacturing the semiconductor device. Specifically, Fig. 6A is a cross-sectional view showing a process of applying a conductive paste 15a to the wires 14 connected to the semiconductor chips 10, 11 and the circuit pattern 8. Fig. 6B is a cross-sectional view showing a process of forming the conductor 21 on the wires 14 connected to the semiconductor chips 10, 11 and the circuit pattern 8. Fig. 7 is a plan view of the semiconductor chips 10, 11 included in the semiconductor device according to the third example and the surroundings of the semiconductor chips 10, 11. Note that in the third example, the same components as described in the first and second examples are denoted by the same reference numerals, and thus no description of the components will be given.

[0040] As in Fig. 6A, Fig. 6B and Fig. 7, in the third example, the conductor 21 comprises the conductive material 15 formed on the wires 14 and a plate-shaped conductive material 16 attached to the wires 14, the conductive material 15 being arranged between the plate-shaped material 16 and the wires 14.

[0041] The conductor 21 is integrally formed with the wires 14 that connect between the semiconductor chips 10, 11 and between the semiconductor chip 11 and the circuit structure 8. Specifically, the conductive material 15 is formed on portions of the wires 14 that connect the semiconductor chips 10, 11 and the semiconductor chip 11 and the circuit structure 8, the portions of the wires 14 being located on the semiconductor chips 10, 11 and the circuit structure 8. The plate-shaped conductive material 16 is placed on a plurality of conductive materials 15 and attached to the plurality of wires 14, the plurality of conductive materials 15 being arranged between the plate-shaped material 16 and the plurality of wires 14.

[0042] Next, a method for forming the conductor 21 will be described. First, as shown in Fig. 6A, after bonding the plurality of wires 14 connecting between the semiconductor chips 10, 11 and between the semiconductor chip 11 and the circuit structure 8, the conductive paste 15a is applied with a dispenser 50 to the parts of the wires 14 located on the semiconductor chips 10, 11 and the circuit structure 8. Next, as shown in Fig. 6B, the plate-shaped conductive material 16 is placed on the wires 14, with the conductive paste 15a interposed between the plate-shaped conductive material 16 and the wires 14. Then, the conductive paste 15a is cured by, for example, heat treatment to cause the plate-shaped conductive material 16 to be fixed to the plurality of wires 14, with the conductive material 15 interposed between the plate-shaped conductive material 16 and the plurality of wires 14, and the conductive paste 15a to transform into the conductor 21. This causes the conductor 21 to be electrically connected to the plurality of wires 14. Note that the semiconductor device according to the third example may further include the conductor 20 described in the first and second examples.

[0043] As described above, in the semiconductor device according to the third example, the conductor 21 includes the conductive material 15 formed on the wires 14 and the plate-shaped conductive material 16 attached to the wires 14, with the conductive material 15 sandwiched between the plate-shaped conductive material 16 and the wires 14. This makes it possible to achieve the same effect as in the first example. Note that using a thick plate-shaped conductive material serving as the plate-shaped conductive material 16 will increase the effect of reducing the current density while the semiconductor chips 10, 11 are in operation.

[0044] Since the conductor 21 is formed by applying the conductive paste 15a to the wires 14, placing the plate-shaped conductive material 16 on the wires 14 with the conductive paste 15a interposed between the plate-shaped conductive material 16 and the wire 14, and curing the conductive paste 15a, it is possible to easily form the conductor 21 on the wires 14. <Viertes Beispiel>

[0045] Next, a semiconductor device according to a fourth example will be described. Fig. 8 is a plan view of the semiconductor chips 10, 11 included in the semiconductor device according to the fourth example and the surroundings of the semiconductor chips 10, 11. Note that in the fourth example, the same components as described in the first to third examples are denoted by the same reference numerals, and thus no description of the components will be given.

[0046] As in Fig. 8, in the fourth example, a conductor 21 is connected to the plurality of parallel-connected semiconductor chips 10, 11. Specifically, three pairs of semiconductor chips 10, 11 are connected in parallel, and a conductor 21 is connected to the three pairs of semiconductor chips 10, 11 and the circuit pattern 8. Note that a method for forming the conductor 21 on the wires 14 is the same as the method in the third example, and thus, no description of the method will be given.

[0047] As described above, in the semiconductor device according to the fourth example, since a plurality of pairs of the semiconductor chips 10, 11 are connected in parallel and the plurality of pairs of the semiconductor chips 10, 11 are connected to each other by a conductor 21, the same effect as in the third example can be achieved. <Fünftes Beispiel>

[0048] Next, a semiconductor device according to a fifth example will be described. Fig. 9 is a plan view of the semiconductor chips 10, 11 included in the semiconductor device according to the fifth example and the surroundings of the semiconductor chips 10, 11. Note that in the fifth example, the same components as described in the first to fourth examples are denoted by the same reference numerals, and thus no description of the components will be given.

[0049] As in Fig. 9, in the fifth example, a conductor is connected to each of the plurality of pairs of the plurality of semiconductor chips 10, 11 connected in parallel. Specifically, three pairs of semiconductor chips 10, 11 are connected in parallel, and three conductors 21 are each connected to a corresponding one of the three pairs of semiconductor chips 10, 11 and the circuit pattern 8. Note that a method for forming the conductors 21 on the wires 14 is the same as the method in the third example, and thus, no description of the method will be given.

[0050] As described above, in the semiconductor device according to the fifth example, since the conductors 21 are each connected to a corresponding one of the plurality of pairs of the semiconductor chips 10, 11 connected in parallel, the same effect as in the third example can be achieved. <Sechstes Beispiel>

[0051] Next, a semiconductor device according to a sixth example will be described. Fig. 10 is a plan view of the semiconductor chips 10, 11 included in the semiconductor device according to the sixth example and the surroundings of the semiconductor chips 10, 11. Fig. 11 is a plan view of the semiconductor chips 10, 11 and the surroundings of the semiconductor chips 10, 11, where no conductor 22 is provided. Note that in the sixth example, the same components as those described in the first to fifth examples are denoted by the same reference numerals, and thus no description of the components will be given.

[0052] As in Fig. 10, in the sixth example, wires 14 located between adjacent semiconductor chips 10 and between adjacent semiconductor chips 11 among the plurality of pairs of semiconductor chips 10, 11 connected in parallel are electrically connected to each other by the conductor 22. Specifically, the conductor 22 is integrally formed with the wire 14 located on one semiconductor chip 10, 11 on the other semiconductor chip 10, 11 side and the wire 14 located on the other semiconductor chip 10, 11 on the one semiconductor chip 10, 11 side in adjacent semiconductor chips 10 and adjacent semiconductor chips 11. The conductor 22 includes the conductive material 15 (see Fig. 6) and a plate-shaped conductive material 17.

[0053] To avoid overshoot without a designated conductor 22, as in Fig. 11, an overshoot suppression wire 14a connects three pairs of parallel-connected semiconductor chips 10. However, it is necessary to ensure a space where the overshoot suppression wire 14a is connected, which makes it difficult to downsize the semiconductor device.

[0054] In contrast, in the semiconductor device according to the sixth example, the conductor 22 is integrally formed with the wire 14 located in one semiconductor chip 10, 11 on the side of the other semiconductor chip 10, 11 and the wire 14 located in the other semiconductor chip 10, 11 on the side of the one semiconductor chip 10, 11 in adjacent semiconductor chips 10, 11.

[0055] This eliminates the need for the space where the overshoot suppression wire 14a is connected. This, in turn, makes it possible to downsize the semiconductor device even when anti-overshoot measures are taken. <Siebtes Beispiel>

[0056] Next, a semiconductor device according to a seventh example will be described. Fig. 12 is a plan view of the semiconductor chips 10, 11 included in the semiconductor device according to the seventh example and the surroundings of the semiconductor chips 10, 11. Note that in the seventh example, the same components as described in the first to sixth examples are denoted by the same reference numerals, and thus no description of the components will be given.

[0057] As in Fig. As shown in Figure 12, the seventh example corresponds to a combination of the fifth example and the sixth example. That is, in the seventh example, the conductors 21 are each connected to a corresponding one of the plurality of pairs of semiconductor chips 10, 11 connected in parallel, and the wires 14 located between adjacent semiconductor chips 10 and between adjacent semiconductor chips 11 among the plurality of pairs of semiconductor chips 10, 11 connected in parallel are electrically connected to each other by the conductors 22.

[0058] As described above, since the semiconductor device according to the seventh example has the above configuration, it is possible to achieve both the effect of the fifth example and the effect of the sixth example. <Achtes Beispiel>

[0059] Next, a semiconductor device according to an eighth example will be described.

[0060] Fig. 13 is a plan view of the semiconductor chips 10, 11 included in the semiconductor device according to the eighth example and the surroundings of the semiconductor chips 10, 11. Note that in the eighth example, the same components as described in the first to seventh examples are denoted by the same reference numerals, and thus no description of the components will be given.

[0061] As in Fig. 13, in the eighth example, the plurality of wires 14 are continuously arranged and arranged at an angle to each other, and the conductor 21 is integrally formed with the plurality of wires 14 along the longitudinal direction of the plurality of continuously arranged wires 14.

[0062] When connecting the wires 14 to the semiconductor chips 10, 11 and the circuit structure 8, it may be necessary to form an angle θ. When the wires 14 are connected at an angle to each other to avoid contact between the wires 14 and a wire bonding tool, the number of wires 14 tends to decrease compared to a configuration in which no angle is formed, which may increase the current density of the wires 14.

[0063] In contrast, in the semiconductor device according to the eighth example, the wire 14 includes a plurality of wires 14, and the plurality of wires 14 are continuously arranged at an angle to each other, and the conductor 21 is integrally formed with the plurality of wires 14 along the longitudinal direction of the plurality of continuously arranged wires 14. Since the same effect as in the first example can be achieved, the current density can be kept low even with a small number of wires 14. <Neuntes Beispiel>

[0064] Next, a semiconductor device according to a ninth example will be described. Fig. 14A and Fig. 14B are cross-sectional views of a semiconductor device according to the ninth example to describe a method of manufacturing the semiconductor device. Specifically, Fig. 14A is a plan view showing a state before the plate-shaped conductive material 16 connects the semiconductor chip 11 and the circuit pattern 8. Fig. 14B is a plan view showing a state after the plate-shaped conductive material 16 connects the semiconductor chip 11 and the circuit pattern 8. Note that in the ninth example, the same components as those described in the first to eighth examples are denoted by the same reference numerals, and thus, no description of the components will be given.

[0065] As in Fig. 14B, in the ninth example, the semiconductor chip 11 and the circuit pattern 8 are connected by the plate-shaped conductive material 16 instead of the wire 14.

[0066] The semiconductor device comprises the insulating substrate 5 containing the circuit structure 8, the plurality of semiconductor chips 10, 11 mounted on the circuit structure 8, and the plate-shaped conductive material 16 connecting between the semiconductor chip 11 and the circuit structure 8.

[0067] Next, a method for bonding the plate-shaped conductive material 16 will be described. As shown in Fig. 14A, first, after bonding the plurality of wires 14, the conductor 21 is formed between the semiconductor chips 10, 11 in the same manner as in the third example. As shown in Fig. Next, as shown in Fig. 14B, after applying the conductive paste to the connection portion where the semiconductor chip 11 and the circuit pattern 8 are connected to each other, the plate-shaped conductive material 16 is placed on the connection portion with the conductive paste interposed between the plate-shaped conductive material 16 and the connection portion. Next, the conductive paste is cured by, for example, a heat treatment, thereby connecting the plate-shaped conductive material 16 to the semiconductor chip 11 and the circuit pattern 8.

[0068] Note that, instead of the conductor 21 integrally formed with the wires 14, the semiconductor chips 10, 11 may be connected by the conductor 20 integrally formed with the wires 14. Furthermore, the semiconductor chips 10, 11 may be connected by the plate-shaped conductive material 16 instead of the conductor 21 integrally formed with the wires 14. Furthermore, the semiconductor chip 11 and the circuit pattern 8 may be connected by the conductor 20 or the conductor 21 integrally formed with the wires 14, and the semiconductor chips 10, 11 may be connected by the plate-shaped conductive material 16.

[0069] As described above, the semiconductor device according to the ninth example includes the insulating substrate 5 including the circuit pattern 8, the plurality of semiconductor chips 10, 11 mounted on the circuit pattern 8, and the plate-shaped conductive material 16 connecting the plurality of semiconductor chips 10, 11 and connecting the semiconductor chip 11 and the circuit pattern 8.

[0070] This makes it possible to achieve the same effect as in the first example. In particular, since wiring can be arranged in a layout that makes wiring difficult using the wires 14, it is possible to further increase the degree of freedom in designing the semiconductor device and downsize the semiconductor device.

[0071] The plate-shaped conductive material 16 is connected by applying the conductive paste to the connecting portion where the semiconductor chips 10, 11 are connected to each other, and the connecting portion where the semiconductor chip 11 and the circuit structure 8 are connected to each other, placing the plate-shaped conductive material 16 on the connecting portions with the conductive paste interposed between the plate-shaped conductive material 16 and the connecting portions, and curing the conductive paste. Therefore, the plate-shaped conductive material 16 can be easily connected to the connecting portion where the semiconductor chips 10, 11 are connected to each other, and the connecting portion where the semiconductor chip 11 and the circuit structure 8 are connected to each other.

[0072] Furthermore, wires 14 connecting between semiconductor chips 10, 11 and between semiconductor chip 11 and circuit pattern 8, and conductor 20 or conductor 21 integrally formed with wires 14 are provided. Therefore, providing both the plate-shaped conductive material 16 and the conductor 20 or conductor 21 further increases the degree of freedom in designing the semiconductor device. <Zehntes Beispiel >

[0073] Next, a semiconductor device according to a tenth example will be described. Fig. 15 is a plan view of the semiconductor chips 10, 11 included in the semiconductor device according to the tenth example and the surroundings of the semiconductor chips 10, 11. Note that in the tenth example, the same components as described in the first to ninth examples are denoted by the same reference numerals, and thus no description of the components will be given.

[0074] As in Fig. 15, in the tenth example, a plate-shaped conductive material 16 is connected to the parallel-connected semiconductor chips 10, 11. Specifically, three pairs of semiconductor chips 10, 11 are connected in parallel, and a plate-shaped conductive material 16 is connected to the three pairs of semiconductor chips 10, 11 and the circuit pattern 8. Note that a method for connecting the plate-shaped material 16 is the same as the method in the ninth example, and thus, no description of the method will be given.

[0075] Furthermore, as in the ninth example, for example, a connection may be formed between two pairs of semiconductor chips 10, 11 arranged adjacent to the circuit pattern 8 and between the semiconductor chips 10, 11 and the circuit pattern 8 by a plate-shaped conductive material 16, and a connection may be formed between the remaining pair of semiconductor chips 10, 11 by the conductor 20 or the conductor 21 integrally formed with the wires 14. That is, a plate-shaped conductive material 16 and the conductor 20 or the conductor 21 may be coexisting.

[0076] As described above, in the semiconductor device according to the tenth example, the plurality of pairs of semiconductor chips 10, 11 are connected in parallel, and a connection is formed between the plurality of pairs of semiconductor chips 10, 11 and between the semiconductor chips 10, 11 and the circuit pattern 8 by a plate-shaped conductive material 16.

[0077] Wires 14 connecting between semiconductor chips 10, 11 and between semiconductor chips 10, 11 and circuit pattern 8, and conductor 20 or conductor 21 integrally formed with wires 14 are further provided. According to the above, the same effect as in the ninth example can be achieved.

[0078] Note that the present invention can be implemented by any combination of the examples within the scope of the present invention.

Claims

[1] A semiconductor device comprising: an insulation substrate (5) containing a circuit structure (8); Semiconductor chips (10, 11) mounted on the circuit structure (8); a wire (14, 24) connecting between the semiconductor chips (10, 11) and between at least one semiconductor chip (11) and the circuit structure (8); and a conductor (20, 21, 22) formed integrally with the wire (14, 24), wherein the conductor (21, 22) comprises a conductive material (15) formed on the wire (14) and a plate-shaped conductive material (16, 17) attached to the wire (14), wherein the conductive material (15) is arranged between the plate-shaped conductive material (16, 17) and the wire (14), and a plurality of pairs of semiconductor chips (10, 11) are connected in parallel and a conductor (21) connects the plurality of pairs of semiconductor chips (10, 11). [2] The semiconductor device according to claim 1, wherein the conductor (20, 21, 22) is further formed near a connection portion where the semiconductor chip (11) is connected to the wire (14). [3] A semiconductor device according to claim 1, wherein the conductor (20, 21, 22) has a lower linear expansion coefficient than the wire (14). [4] A semiconductor device according to claim 1, wherein the wire (14) has a base made of Al and a coating made of Ni or Cu, the coating being applied around the base. [5] The semiconductor device according to claim 1, wherein the wire (24) is a flat wire (24). [6] A semiconductor device comprising: an insulation substrate (5) containing a circuit structure (8); Semiconductor chips (10, 11) mounted on the circuit structure (8); Wires (14, 24) connecting between the semiconductor chips (10, 11) and between at least one semiconductor chip (11) and the circuit structure (8); and a conductor (20, 21, 22) formed integrally with the wires (14, 24), wherein the conductor (22) is formed integrally with the wire (14) located on one semiconductor chip (10, 11) on the side of the other semiconductor chip (10, 11) and the wire (14) located on the other semiconductor chip (10, 11) on the side of the one semiconductor chip (10, 11) in adjacent semiconductor chips (10, 11), and the conductor (22) comprises a conductive material (15) formed on the wire (14) and a plate-shaped conductive material (17) attached to the wire (14), wherein the conductive material (15) is arranged between the plate-shaped conductive material (17) and the wire (14). [7] A semiconductor device according to claim 1, wherein the wire (14) has a plurality of wires (14), the plurality of wires (14) are arranged continuously and at an angle to one another, and the conductor (21) is integrally formed with the plurality of wires (14) along a longitudinal direction of the plurality of continuously arranged wires (14). [8] A semiconductor device according to any one of claims 1 to 7, wherein the semiconductor chips (10, 11) are each formed of a wide band gap semiconductor. [9] A method of manufacturing the semiconductor device according to claim 1, wherein the conductor (21, 22) is formed by applying a conductive paste to the wire (14), placing the plate-shaped conductive material (16, 17) on the wire (14) with the conductive paste interposed between the plate-shaped material (16, 17) and the wire (14), and curing the conductive paste.

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