MANAGEMENT OF DIGITALLY CONTROLLED CHARGE PUMP OPERATION IN A STORAGE SUBSYSTEM

Abstract

Storage device, comprising: a storage array; and a control logic that is functionally coupled to the memory array to perform operations, comprising: Determining, by a processing device, a first digitally controlled pump voltage level of a charge pump coupled to a word line related to the storage array; Determine that a first measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level satisfy a first condition; Generating, in response to determining that the first condition is satisfied, an update signal, causing the first digitally controlled pump voltage level applied to the charge pump to be changed to a second digitally controlled pump voltage level; Determine that a second measured digitally controlled voltage level satisfies a second condition; and In response to the fulfillment of the second condition, increase the number of stages of the charge pump from a first number of stages to a second number of stages.

Description

TECHNICAL AREA

[0001] Exemplary embodiments of the invention relate generally to storage subsystems, and in particular to the management of the digitally controlled charge pump operation in a storage subsystem. BACKGROUND

[0002] A storage subsystem can contain one or more storage devices that store data. These storage devices can be, for example, non-volatile or volatile. Generally, a host system can use a storage subsystem to store data in and retrieve data from the storage devices.

[0003] German patent application DE 10 2014 119 001 A1 describes a circuit with a charge pump and a feedback circuit. The charge pump comprises a first input, a second input designed to receive an offset signal, and an output terminal designed to provide a charge pump signal based on the first and second inputs. The feedback circuit comprises a first input coupled to the output of the charge pump, a second input designed to be coupled to a reference signal, an enable input designed to enable and disable the feedback circuit, and a feedback output coupled to the first input of the charge pump.

[0004] US Patent 2004 / 0017247 A1 discloses a charge pump booster circuit in which the control clock is adjusted in small steps to suppress boost amplitude and various disturbances. The circuit includes a charge pump booster section for increasing the absolute level of an external supply voltage, a boost voltage feedback section for controlling the booster section, and a clock buffer section. In the boost voltage feedback section, an output level of the booster section is detected by a voltage detection section. This level is compared to a reference level, and depending on the comparison result, a count is performed in an up / down counter section. Based on the count value, the control amount is shifted in small steps by the D / A converter section, thereby controlling the supply voltage of the clock buffer section via the level shifter section.

[0005] US 2016 / 0291629 A1 relates to a charge pump comprising a capacitor, a first transistor electrically connected between a first terminal of the first capacitor and ground, and a second transistor electrically connected between a second terminal of the first capacitor and an output node. During a first operating mode of the charge pump, a voltage amplified by the capacitor is output across the output node, and during a second operating mode of the charge pump, the first and second transistors are held in an ON state.

[0006] DE 11 2012 006 353 T5 describes a storage subsystem comprising a storage device for storing data, wherein the storage device receives an input voltage at a first voltage level, and wherein writing data to the storage device uses a second voltage level that is higher than the first voltage level; a charge pump to raise the input voltage from the first voltage level to the second voltage level; and an adaptive voltage supply to provide the first voltage level based on an energy profile of the storage device, wherein the energy profile specifies a maximum input voltage level for the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood with reference to the detailed description below and the accompanying drawings of various embodiments of the invention. Fig. Figure 1 shows an exemplary computer system that includes a memory subsystem according to some embodiments of the present invention. Fig. Figure 2 is a block diagram of a storage device communicating with a storage subsystem controller of a storage subsystem according to one or more embodiments of the present invention. Fig. Figure 3 is a flowchart of an exemplary method for managing a digitally controlled charge pump voltage related to the charging of a word line of a storage device of a storage subsystem, according to one or more embodiments of the present invention. Fig. Figure 4 shows an exemplary drawing with a representation of digitally controlled charge pump voltage levels related to the charging of digitally controlled word lines and the corresponding controller operation, according to one or more embodiments of the present invention. Fig. Figure 5 is a flowchart of an exemplary method for managing digitally controlled charge pump voltage levels and phase mode transitions of a charge pump according to one or more embodiments of the present invention. Fig. Figure 6 is a schematic diagram of an exemplary storage device with a charge pump management component according to one or more embodiments of the present invention. Fig. Figure 7 is a block diagram of an exemplary computer system in which implementations of the present invention can operate. DETAILED DESCRIPTION

[0008] Aspects of the present invention relate to the management of the digitally controlled charge pump operation in a storage subsystem. A storage subsystem can be a storage device, a storage module, or a hybrid of a storage device and a storage module. Examples of storage devices and storage modules are described below in connection with Fig. As described in section 1. In general, a host system can use a storage subsystem, which contains one or more components, such as storage devices that store data. The host system can provide data to be stored in the storage subsystem and can request data to be retrieved from the storage subsystem.

[0009] A storage subsystem may include high-density non-volatile storage devices designed to retain data even when the storage device is not powered. An example of a non-volatile storage device is a negative AND storage device (NAND flash memory). Further examples of non-volatile storage devices are discussed below in conjunction with... Fig. 1. A non-volatile memory device is a component consisting of one or more memory chips. Each chip can contain one or more layers. In some types of non-volatile memory devices (e.g., NAND devices), each layer comprises a set of physical blocks. Each block comprises a set of pages. Each page comprises a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell can store one or more bits of binary information and has different logical states that correlate with the number of bits stored. The logical states can be represented by binary values, such as “0” and “1,” or combinations of such values.

[0010] A storage device can consist of bits arranged in a two-dimensional or three-dimensional grid. The memory cells are formed on a silicon wafer in an array of columns (hereinafter also referred to as "bit lines") and rows (hereinafter also referred to as "word lines"). A word line can refer to one or more rows of memory cells of a storage device, which are used with one or more bit lines to generate the address of each of the memory cells. The intersection between a bit line and a word line forms the address of the memory cell. A block, hereinafter, refers to a unit of the storage device used to store data and can comprise a group of memory cells, a group of word lines, a single word line, or individual memory cells.

[0011] To perform operations (e.g., read operations and program operations) that involve the word lines of a storage device within the memory subsystem, the word lines are charged to pass-through voltage levels by a charge pump (e.g., a DC-DC converter that multiplies the incoming Vcc supply by a factor greater than 1, such as 10 for NAND flash memory). The charge pump typically operates in a free-running mode while charging the memory array. In free-running mode, the resulting voltage ramp V applied to the word lines by the charge pump has a decreasing exponential slope, approximated by the following equation: V = V start + V max * (1- exp(-t / C*R pmp )), where t is time, V start The starting voltage of the word lines is V maxwhere C is the maximum nominal open-load voltage of the charging pump, C is the NAND array charge, and R pmp This is equivalent to the resistance of the charge pump. The voltage ramp stops when the word lines reach the target value determined by the NAND operation, at which point the charge pump continues to reach its own regulated target voltage. The charge pump control voltage can be determined by setting a desired difference (also called the "headroom level," which is required to keep a charge pump-driven linear controller in an optimal saturation state) between the charge pump control voltage (e.g., 12 V) and the word line target voltage (e.g., 8 V - 10 V).

[0012] Every DC-DC converter with a charge pump has a current efficiency, which is represented by the ratio of the output current generated by the charge pump to the current consumed by the charge pump. The current efficiency varies with the converter's output voltage; in particular, it decreases monotonically with increasing output voltage level. For example, if the NAND array load needs to be charged from 2V to 8V to perform algorithm operations, using a charge pump at a fixed target voltage level of 12V would consume more current than using the same charge pump at a fixed target voltage level of 10V, because the converter's current efficiency is higher in the latter case.

[0013] Considering the efficiency of the charge pump, the charge pump can be designed to operate in different stage configurations. For example, the charge pump can operate in a two-stage mode (e.g., a first charge pump stage with a capacitor connected across a power supply, and a second charge pump stage with a capacitor in series with the power supply and the load) to raise the charge pump output voltage in a first range (e.g., 4V to 8V), and in a four-stage mode (e.g., comprising third and fourth stages, each with capacitors connected in series with the power supply and the load) to raise the charge pump output voltage in a second range (e.g., 8V to the charge pump control voltage).During operation, although each stage of the charge pump is designed to generate an intermediate increased output voltage, the current efficiency of the charge pump decreases as a function of the number of stages. Accordingly, the current efficiency of the charge pump is lower when operating in a four-stage mode compared to a two-stage mode.

[0014] Furthermore, using an unlimited or free-running charge pump to ramp up the word line voltage to the target voltage level, as occurs in certain cases, results in a fast charging time of the storage device's array load to the target voltage level, while simultaneously achieving the lowest average power consumption. When the pump operates in an unlimited mode, its output voltage closely follows the storage device's array load voltage, combined with a power efficiency that decreases monotonically with the converter's output voltage.

[0015] However, the use of an unlimited or free-running charge pump to ramp up the voltage of the word lines to the target voltage level results in undesirably high peak current levels and high peak current consumption levels, all of which have undesirable effects, including, but not limited to, increased error levels related to read and program operations, and reduced reliability of the storage device due to the rapid ramp-up by charge pumps, which can cause local word lines to lag behind the global word lines of a storage device.

[0016] Aspects of the present invention serve to overcome the above and other disadvantages by providing a charge pump configured to apply a digitally controlled voltage level (e.g., a pulsed or stepped voltage load) to charge one or more word lines of a storage device to a target voltage level. In one embodiment, the output voltage of the charge pump is digitally controlled to apply a digitally controlled output voltage (e.g., rising in a digitally controlled step-like manner) to drive the voltage of the NAND array in a uniformly increasing manner. To charge the word lines to the target voltage level using the digitally controlled step-like approach, the charge pump is regulated by a voltage regulator to operate within a voltage range from an initial control voltage level to a target control voltage level.The target control voltage level of the charge pump is determined based on a headroom requirement (e.g., a difference between the target voltage level of a word line and the control voltage level of the charge pump) which is related to a linear voltage regulator supplied by the charge pump itself.

[0017] According to various embodiments, the charge pump voltage level is digitally controlled to follow the digitally controlled word line voltage level. The charge pump voltage level is digitally controlled to gradually increase, update, or be raised from an initial charge pump voltage level through a series of updates corresponding to an offset level until a limit level of the charge pump control voltage is reached.

[0018] In one embodiment, the digitally controlled charge pump voltage level is increased by an offset level in response to a determination that a measured word line voltage level satisfies a condition. In one embodiment, the condition is met when the difference between the charge pump voltage level and the measured word line voltage level is less than a threshold level that meets the headroom requirement (also referred to as the "headroom threshold level"). In another embodiment, the charge pump voltage level is increased by the offset level when the headroom, or the difference between the current charge pump voltage level and the measured word line level, is less than the headroom threshold level.

[0019] As the digitally controlled word line voltage level increases, a comparison of the charge pump voltage and the word line voltage is performed at one or more word line voltage threshold levels to determine if the condition is met (e.g., whether the difference between the charge pump voltage level and a measured word line voltage level is less than the threshold level). In response to the condition being met, the charge pump voltage level is increased by the offset level to an updated or raised digitally controlled charge pump voltage level. The digital charge pump control may involve several steps, and this process continues until the charge pump voltage level has been incrementally raised to the charge pump control voltage level.

[0020] In one embodiment, one or more step control threshold levels can be defined. When the word line voltage level reaches a step control threshold level, the charge pump operation can be switched from a current step mode (e.g., a two-step mode) to an updated step mode (e.g., a four-step mode).

[0021] Advantageously, digitally controlling the charge pump voltage level as a function of the word line voltage level allows for minimizing the current consumed by the charge pump. By minimizing the charge pump's power consumption, the pump's efficiency is increased compared to an unmanaged charge pump (e.g., a charge pump without digital control that operates at or near the charge pump control voltage during the word line voltage rise).

[0022] Furthermore, according to some embodiments, digital control of the charge pump voltage level and charge pump stage control leads to a reduction in the energy per bit of the memory subsystem compared to an unmanaged charge pump (e.g., a charge pump without digital control operating at or near the charge pump control voltage during the word line voltage rise).

[0023] Fig. Figure 1 shows an exemplary computer system 100, which includes a storage subsystem 110 according to one or more embodiments of the present invention. The storage subsystem 110 can contain media such as one or more volatile storage devices (e.g., storage device 140), one or more non-volatile storage devices (e.g., storage device 130), or a combination thereof.

[0024] A Memory Subsystem 110 can be a storage device, a memory module, or a combination of both. Examples of a storage device include a solid-state drive (SSD), a flash drive, a USB flash drive (Universal Serial Bus Flash Drive), an eMMC drive (Embedded Multi-Media Controller Drive), a UFS drive (Universal Flash Storage Drive), an SD card (Secure Digital Card), and a hard disk drive (HDD). Examples of memory modules include a dual inline memory module (DIMM), a small-outline DIMM (SO-DIMM), and various types of non-volatile dual inline memory modules (NVDIMM).

[0025] The computer system 100 can be a computing device such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other means of transport), an Internet of Things (IoT)-enabled device, an embedded computer (e.g., one such as is contained in a vehicle, an industrial plant, or a networked commercial device), or a computing device that includes a memory and a processing device.

[0026] The computer system 100 can comprise a host system 120 connected to one or more storage subsystems 110. In some embodiments, the host system 120 is connected to different types of storage subsystems 110. Fig. Figure 1 shows an example of a host system 120 connected to a storage subsystem 110. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communicative connection or a direct communicative connection (e.g., without intermediary components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

[0027] The host system 120 can contain a processor chipset and a software stack that runs on the processor chipset. The processor chipset can contain one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a memory protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory subsystem 110 to, for example, write data to and read data from the memory subsystem 110.

[0028] The host system 120 can be connected to the storage subsystem 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a SATA (Serial Advanced Technology Attachment) interface, a PCIe (Peripheral Component Interconnect Express) interface, a USB (Universal Serial Bus) interface, Fibre Channel, SAS (Serial Attached SCSI), a DDR (Double Data Rate) memory bus, SCSI (Small Computer System Interface), a DIMM (Dual In-Line Memory Module) interface (e.g., a DIMM socket interface that supports DDR (Double Data Rate)), etc. The physical host interface can be used for data transfer between the host system 120 and the storage subsystem 110. The host system 120 can also use an NVMe (NVM Express) interface to access components (e.g.,Storage devices 130) can be accessed when the storage subsystem 110 is connected to the host system 120 via the PCIe interface. The physical host interface can provide an interface for the transmission of control, address, data, and other signals between the storage subsystem 110 and the host system 120. Fig. Figure 1 shows a storage subsystem 110 as an example. In general, the host system 120 can access multiple storage subsystems via the same communication link, multiple separate communication links, and / or a combination of communication links.

[0029] The storage devices 130 and 140 can comprise any combination of different types of non-volatile and / or volatile storage devices. The volatile storage devices (e.g., storage device 140) can include, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0030] Some examples of non-volatile storage devices (e.g., storage device 130) include negative AND-type flash memory (NAND-type) and write-in-place memory, such as a three-dimensional interface storage device (3D cross-point storage device), which is an interface array of non-volatile memory cells. A non-volatile memory interface array can perform bit storage based on a change in bulk resistance in conjunction with a stackable cross-grid data access array. Furthermore, unlike many flash-based memories, a non-volatile interface memory can perform a write-in-place operation, in which a non-volatile memory cell can be programmed without first erasing it. NAND-type flash memories include, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0031] Each of the storage devices 130 can contain one or more arrays of memory cells. One type of memory cell, for example, single-level cells (SLCs), can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple-level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the storage devices 130 can comprise one or more arrays of memory cells, such as SLCs, MLCs, TLCs, QLCs, or any combination thereof. In some embodiments, a particular storage device can comprise an SLC range and an MLC range, a TLC range, or a QLC range of memory cells. The memory cells of the storage devices 130 can be grouped as pages, which can refer to a logical unit of the storage device used to store data. For some types of memory (e.g.,NAND) allows pages to be grouped to form blocks.

[0032] Although non-volatile memory components, such as 3D interface arrays of non-volatile memory cells and NAND flash memory (e.g., 2D NAND, 3D NAND), are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-selecting memory, other chalcogenide-based memory, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto-random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), negative or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0033] A memory subsystem controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading, writing, or erasing data from the memory devices 130, and other such operations. The memory subsystem controller 115 can include hardware such as one or more integrated circuits and / or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, a special logic circuit (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or another suitable processor.

[0034] The memory subsystem controller 115 can contain a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the example shown, the local memory 119 of the memory subsystem controller 115 comprises embedded memory configured to store instructions for performing various processes, operations, logical sequences, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0035] In some embodiments, the local memory 119 can contain memory registers that store memory pointers, retrieved data, etc. The local memory 119 can also contain a read-only memory (ROM) for storing microcode. Although the exemplary memory subsystem 110 in Fig. 1 is shown to contain the memory subsystem controller 115, in another embodiment of the present invention a memory subsystem 110 may not contain a memory subsystem controller 115 and instead be based on an external controller (e.g. an external host or a processor or controller separate from the memory subsystem).

[0036] In general, the storage subsystem controller 115 can receive commands or operations from the host system 120 and translate these commands or operations into instructions or appropriate commands to achieve the desired access to the storage devices 130. The storage subsystem controller 115 can also be responsible for other operations, such as wear-leveling operations, garbage collection operations, error detection and correction (ECC) code operations, encryption operations, caching operations, and address translations between a logical block address (e.g., logical block address (LBA), namespace) and a physical block address (e.g., physical block address) associated with the storage devices 130. The storage subsystem controller 115 can also include a host interface circuit to communicate with the host system 120 via the physical host interface.The host interface circuit can convert commands received from the host system 120 into command instructions to access the storage devices 130, and convert responses to the storage devices 130 in relationships into information for the host system 120.

[0037] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and addressing circuitry (e.g., a row decoder and a column decoder) that can receive an address from the memory subsystem controller 115 and decode the address to access the memory devices 130.

[0038] In some embodiments, the storage devices 130 include local media controllers 135 that work in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the storage devices 130. An external controller (e.g., memory subsystem controller 115) can manage the storage device 130 externally (e.g., perform media management operations on the storage device 130). In some embodiments, a storage device 130 is a managed storage device that includes a raw storage device 130 with control logic (e.g., local media controller 135) on the chip and a controller (e.g., memory subsystem controller 115) for media management within the same storage device chip. An example of a managed storage device is a managed NAND device (MNAND device).

[0039] In one embodiment, the storage device 130 includes a charge pump management component 113, which can be used to manage digitally controlled charge pump voltage levels for loading one or more word lines of a storage device 130. In some embodiments, the local media controller 135 includes at least part of the charge pump management component 113.

[0040] In some embodiments, the memory subsystem controller 115 includes at least part of the charge pump management component 113. For example, the controller 115 may include a processor 117 (processing device) configured to execute instructions stored in local memory 119 for performing the operations described herein. In some embodiments, the charge pump management component 113 is part of the host system 110, an application, or an operating system.

[0041] The charge pump management component 113 can cause a digitally controlled voltage to be applied to a charge pump to increase a digitally controlled voltage level of at least one selected word line to a target word line voltage. The charge pump management component 113 manages the digitally controlled charge pump voltage level to track the digitally controlled word line voltage level. In one embodiment, the charge pump management component 113 generates the digitally controlled charge pump voltage level to incrementally increase, update, or raise from an initial charge pump voltage level through a series of updates corresponding to an offset level until a charge pump threshold voltage level (e.g., 12 volts) is reached.

[0042] In one embodiment, the charge pump management component 113 determines a measured word line voltage level to determine whether a first condition is met. In one embodiment, the condition is met if the difference between the charge pump voltage level and the measured word line voltage level is less than a headroom limit level (e.g., a selected minimum desired difference to be maintained between the charge pump voltage level and the word line voltage level). In another embodiment, the charge pump management component 113 checks or measures the word line voltage level at one or more time points to determine whether a headroom condition is being met or whether the first condition is satisfied.

[0043] In response to the determination that the first condition is satisfied (i.e., the difference between an actual digitally controlled charge pump voltage level and the measured word line voltage level is less than the headroom limit level), the charge pump management component 113 adjusts or increases the charge pump voltage level by an offset level (e.g., 2 volts) to a stepped, matched, or boosted charge pump voltage level.

[0044] In one embodiment, when the digitally controlled word line voltage level rises to one or more selected word line voltage thresholds (e.g., word line threshold voltages of 5 volts, 7 volts, 9 volts, 11 volts), the charge pump management component 113 compares a current charge pump voltage level and the word line voltage level to determine whether the first condition is met. The charge pump management component 113 can continue the process of increasing the charge pump voltage level in response to the first condition being met until a threshold voltage level for charge pump control is reached.

[0045] In one embodiment, the charge pump management component 113 can manage the operation of the charge pump in several stage modes (e.g., a two-stage mode, a four-stage mode, etc.). The charge pump management component 113 can set or change the operation of the charge pump from a current stage mode (e.g., a two-stage mode) to an updated stage mode (e.g., a four-stage mode) in response to a determination that a second condition is met. In one embodiment, the second condition is met when the word line voltage level reaches a stage control threshold level. In one embodiment, upon determining that the word line voltage level reaches or exceeds a stage control threshold level, the charge pump management component 113 switches the charge pump from a current stage mode (e.g.,a two-stage mode) into an updated stage mode (e.g., a four-stage mode). In one embodiment, the charge pump management component 113 can monitor and maintain any number of different stage control threshold levels, so that the charge pump stage mode is updated in response to each of the stage control threshold levels being reached or exceeded. Further details regarding the operations of the charge pump management component 113 are described below.

[0046] Fig. Figure 2 is a simplified block diagram of a first device in the form of a storage device 130, which according to an embodiment is connected to a second device in the form of a storage subsystem controller 115 of a storage subsystem (e.g. the storage subsystem 110 from Fig. 1) communicates. Some examples of electronic systems are personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, games, devices, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller outside the memory device 130) Fig. 1) can be a storage controller or other external host device.

[0047] The storage device 130 comprises an array of memory cells 204, logically arranged in rows and columns. Memory cells of a logical row are normally connected to the same access line (e.g., a word line), while memory cells of a logical column are normally selectively connected to the same data line (e.g., a bit line). A single access line can be connected to more than one logical row of memory cells, and a single data line can be connected to more than one logical column. Memory cells (in Fig. 2 (not shown) of at least one area of ​​the array of memory cells 204 can be programmed to one of at least two target data states.

[0048] Row decoding circuits 208 and column decoding circuits 210 are provided to decode address signals. Address signals are received and decoded to access the array of memory cells 204. The memory device 130 further includes an input / output control circuit 212 (I / O control circuit) to manage the input of instructions, addresses, and data to the memory device 130, as well as the output of data and status information from the memory device 130. An address register 214 is connected to the I / O control circuit 212 and the row decoding circuit 208 and the column decoding circuit 210 to lock the address signals before decoding. An instruction register 224 is connected to the I / O control circuit 212 and the control logic 216 to lock incoming instructions.

[0049] A controller (e.g., the local media controller 135 within the storage device 130) controls access to the array of memory cells 204 in response to instructions and generates status information for the external storage subsystem controller 115. That is, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on the array of memory cells 204. The local media controller 135 communicates with the row decoding circuit 208 and the column decoding circuit 210 to control these circuits in response to addresses.

[0050] The local media controller 135 is also connected to a cache register 218. The cache register 218 stores incoming or outgoing data according to the instructions of the local media controller 135 to temporarily store data while the array of memory cells 204 is busy writing or reading other data. During a programming operation (e.g., a write operation), data can be passed from the cache register 218 to the data register 22 to be transferred to the array of memory cells 204; then, new data can be temporarily stored in the cache register 218 by the I / O control circuit 212. During a read operation, data can be passed from the cache register 218 to the I / O control circuit 212 to be output to the memory subsystem controller 115; then, new data can be passed from the data register 220 to the cache register 218.The cache register 218 and / or the data register 220 can form a side buffer of the storage device 130 (e.g., a part thereof). A side buffer can also contain acquisition devices (in . Fig. (2 not shown) to capture a data state of a memory cell of the array of memory cells 204, e.g., by capturing a state of a data line connected to that memory cell. A status register 222 can communicate with the I / O control circuit 212 and the local memory controller 135 to store the status information for output to the memory subsystem controller 115.

[0051] The storage device 130 receives control signals at the storage subsystem controller 115 from the local media controller 135 via a control link 232. These control signals can include, for example, a chip enable CE#, a command latch enable CLE, an address latch enable ALE, a write enable WE#, a read enable RE#, and a write protect WP#. Additional or alternative control signals (not shown) can be received via the control link 232, depending on the type of storage device 130. The storage device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from the storage subsystem controller 115 via a multiplexed input / output (I / O) bus 234 and outputs data to the storage subsystem controller 115 via the I / O bus 234.

[0052] Commands can be received, for example, via the input / output pins (I / O pins) [7:0] of I / O bus 234 at I / O control circuit 212 and then written to instruction register 224. Addresses can be received via the input / output pins (I / O pins) [7:0] of I / O bus 234 at I / O control circuit 212 and then written to address register 214. Data can be received via the input / output pins (I / O pins) [7:0] for an 8-bit device or the input / output pins (I / O pins) [15:0] for a 16-bit device at I / O control circuit 212 and subsequently written to cache register 218. The data can then be written to data register 220 for programming the array of memory cells 204.

[0053] In one embodiment, the cache register 218 can be omitted, and the data can be written directly to the data register 220. The data can also be output via input / output (I / O) pins [7:0] for an 8-bit device or the input / output (I / O) pins [15:0] for a 16-bit device. Although reference is made to I / O pins, they can include any conductive node that allows an electrical connection to the storage device 130 through an external device (e.g., the memory subsystem controller 115), such as conductive pads or conductive bumps as are commonly used.

[0054] It is obvious to a person skilled in the art that additional circuits and signals may be provided and that the storage device 130 consists of Fig. 2 was simplified. It should be recognized that the functionality of the various block components, which refer to Fig. 2. These components do not necessarily have to be divided among different components or component parts of an integrated circuit. For example, a single component or a section of a component of an integrated circuit device can be adapted to provide the functionality of more than one block component. Fig. 2. Alternatively, one or more components or component parts of an integrated circuit could be combined to provide the functionality of a single block component. Fig. 2 to fulfill.

[0055] Furthermore, although specific I / O pins are described according to common conventions for receiving and outputting the various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in the various implementation examples.

[0056] Fig. Figure 3 is a flowchart of an exemplary method 300 for managing a digitally controlled charge pump voltage level according to some embodiments of the present invention to increase or boost a digitally controlled word line voltage level associated with a word line associated with a memory cell of a memory subsystem. The method 300 can be performed by processing logic that may comprise hardware (e.g., processing device, circuits, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions executed on or running on a processing device), or a combination thereof. In some embodiments, the method 300 is performed by the charge pump management component 113. Fig. 1 carried out.

[0057] Operation 310 sets a pump voltage level. For example, the processing logic (e.g., the charge pump management component 113) sets a first digitally controlled pump voltage level for a charge pump connected to a word line of a storage device in a storage subsystem. In one embodiment, the set first digitally controlled pump voltage level causes the charge pump to generate an output voltage that is applied to the word line to raise or increase a word line voltage level (also called a "word line voltage level") to a target word line voltage level. In one embodiment, a DAC (digital-to-analog converter) is used to digitally control the charge pump voltage level.In one embodiment, the processing device generates a series of update commands or signals to increase the pump voltage level in a series of stepped voltages (e.g., a series of voltage levels increased by an offset level) until the charge pump voltage reaches a charge pump limit voltage level (e.g., 12 volts).

[0058] In one embodiment, the word line voltage level set by the charge pump is a step or staircase voltage that is digitally controlled using a DAC to ramp the word line to a target word line voltage via a series of stepped voltage increments (e.g., a voltage level that is related to an operation on the word line, such as a read operation or a program operation).

[0059] Operation 320 involves an evaluation. For example, the processing logic determines whether a measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level satisfy a condition. In one embodiment, the condition is satisfied if the difference between the measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level is less than or equal to a threshold level (e.g., a headroom threshold level).

[0060] Operation 330 involves increasing a voltage. For example, in response to determining that the condition in Operation 320 is met, the processing logic causes the first digitally controlled pump voltage level applied to the charge pump to switch to a second digitally controlled pump voltage level. In one embodiment, the processing logic updates or increases the first digitally controlled pump voltage level by the offset voltage level (e.g., 2 volts) to switch to and establish the second digitally controlled pump voltage. In another embodiment, as shown in Operation 340, the first digitally controlled pump voltage level is maintained if the condition is not met.

[0061] Fig. Figure 4 shows an exemplary drawing 400, which represents the voltage 410, related to a word line (i.e., word line voltage 430) and a charge pump voltage (i.e., charge pump voltage 440), over time 420 as managed by the charge pump management component of the controller. As shown in Fig. As shown in Figure 4, the operation of the charge pump 440 can be initiated at time T0 to adjust the charge pump voltage 440 to a first digitally controlled pump voltage level 341. During operation, the charge pump voltage 440 is digitally controlled (e.g., with a DAC) to generate a series of stepped voltage levels, which are increased by an offset voltage level 450 (e.g., 2 volts) until the target control voltage 455 of the charge pump is reached. In one embodiment, the charge pump voltage 440 causes a digitally controlled word line voltage 430 to increase until a target word line voltage 435 is reached.

[0062] As in Fig. As shown in Figure 4, the processing logic at time T1 checks the difference between the first digitally controlled pump voltage level 441 and the digitally controlled voltage level of the word line 442 to determine whether the headroom requirement has been met (e.g., whether the difference between the two voltage values ​​is greater than the headroom limit level). In the Fig. In the example shown in 4, the processing logic determines whether the difference between the first digitally controlled pump voltage level 441 and the digitally controlled voltage level of the word line 442 is smaller than the headroom limit level (e.g. 1 volt), and therefore the first condition is met 470.

[0063] In the Fig. In the example shown, the controller 435, in response to the fulfillment of the first condition 470 at T1, sends a signal 436 to cause an increase in the charge pump voltage 340 from the first digitally controlled pump voltage level 441 to the second digitally controlled pump voltage level 443.

[0064] In one embodiment, the operations of Method 400 can be performed iteratively by the processing device to ramp up the word line voltage to the target word line voltage using a series of pump voltage update signals, in order to increase the charge pump voltage level in response to the condition being met (i.e., when the difference between the pump voltage and the word line voltage is less than or equal to the headroom requirement). As shown in Fig. As shown in Figure 4, the controller 435 can, for example, output update signals for the pump voltage 436 at times T1, T2, T3 and T4 in response to a determination that a difference between a level of the word line voltage 430 and the level of the charge pump voltage 340 is smaller than the headroom threshold.

[0065] Fig. Figure 5 is a flowchart of an exemplary method 500 for managing a digitally controlled charge pump voltage level and a charge pump stage mode of a charge pump according to some embodiments of the present invention to increase or ramp up a digitally controlled word line voltage level associated with a word line associated with a memory cell of a memory subsystem. The method 400 can be performed by processing logic that may include hardware (e.g., processing device, circuits, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by the charge pump management component 113. Fig. 1 controlled. In one embodiment, operations 510-540 of method 500 can be performed following the execution of the above in conjunction with the Fig. 3 and Fig. The 4 operations described in procedure 300 will be performed.

[0066] Operation 510 increases a digitally controlled voltage level. For example, the processing logic increases this level in response to the fulfillment of a first condition (e.g., the condition in Operation 330). Fig. 3 or the first condition 470 from Fig. 4) a first digitally controlled pump voltage level applied to a charge pump, to a second digitally controlled pump voltage level. In one embodiment, the processing logic updates or increases the first digitally controlled pump voltage level by the offset voltage level (e.g., 2 volts) to produce the second digitally controlled pump voltage. As described above and in Fig. As shown in Figure 4, the controller 435, in response to the fulfillment of the first condition 470 at T1, sends a signal 436 to cause an increase in the charge pump voltage 440 from the first digitally controlled pump voltage level 441 to the second digitally controlled pump voltage level 443.

[0067] Operation 520 involves a determination. For example, the processing logic determines whether a measured, digitally controlled voltage level of the word line satisfies a second condition. In one embodiment, the second condition is met if the voltage level of the word line exceeds a limit voltage level (also referred to as the "pump stage mode limit"). As in Fig. As shown in Figure 4, the processing logic of controller 435 determines at T2 whether the word line voltage level is greater than or equal to a pump stage transition threshold voltage level (e.g., the second condition) 460. In one embodiment, the threshold voltage level for the pump stage transition is a voltage level (e.g., 8 volts) at which the processing logic transitions the charge pump from a first stage mode (e.g., a two-stage mode) to a second stage mode (e.g., a four-stage mode) to improve the efficiency of the charge pump. In one embodiment, although in Fig. 4 where a pump stage transition limit voltage level is represented, any number of pump stage transition limit voltage levels can be used so that the stage mode can be switched to an updated number of stages in response to reaching the corresponding pump stage transition limit voltage level.

[0068] In Operation 530, the number of pump stages is increased. For example, in response to determining that the second condition is met, the processing logic increases the number of charge pump stages from a first number of stages to a second number of stages. For example, the processing logic in Operation 530 can increase the charge pump from a two-stage operation to a four-stage operation. In an embodiment, as shown in Operation 540, if the second condition is not met, the charge pump continues to operate with a first number of stages (e.g., the number of charge pump stages is not changed if the second condition is not met).

[0069] In the Fig. In example 4, the controller 435 generates a pump stage transition signal 437 at T2 to update the pump stage mode of the charge pump. Fig. 4. In response to the pump stage transition signal 437 at T2, the charge pump is switched to an updated stage mode to improve the efficiency of the charge pump.

[0070] Fig. Figure 6 shows a schematic representation comprising a storage device 610 with a charge pump management component 113 according to the embodiments of the present invention. As shown in Fig. As shown in Figure 6, in one embodiment, the charge pump management component 113 is part of a local media controller 135 of the storage device 610, which contains an array of word lines of a memory chip 680 having a selected word line 685 that is to be raised to a target word line voltage level. In one embodiment, the charge pump management component 113 transmits commands or signals to a control register 620 to control a first DAC 630, which is related to a charge pump 660, and a second DAC 650, which is coupled to a voltage regulator 670 configured to apply a voltage level to the selected word line 685, as indicated by the dashed lines in Figure 6. Fig. 6 shown.

[0071] In one embodiment, the charge pump management component 113 generates signals to determine an output voltage of the charge pump 660 (e.g., a charge pump voltage level), which is applied to the selected word line 685 via the voltage regulator 670.

[0072] In one embodiment, a finite state machine 690 can be provided between the control register 620 and the DACs (e.g., the first DAC 630 and the second DAC 650). The finite state machine 690 can be configured to start in response to a pulse received from the control register to perform operations for controlling the charge-pump DAC 630 and the word-line DAC 650. In one embodiment, the finite state machine 690 can be configured to apply a pulse to increase the charge pump 660 from a current pump voltage level to the next pump voltage level (e.g., a level increased by the offset voltage limit).

[0073] In one embodiment, a storage subsystem controller 115 (e.g., a host controller) can send commands to the charge pump management component 113 to initiate the execution of the digitally controlled charge pump management in order to perform the functions and operations described herein (e.g., the execution of methods 300 and 500 from Fig. 3 or 5). In one embodiment, the charge pump management component 113 digitally controls the charge pump voltage level to enable the charge pump 635 to efficiently ramp up to a charge pump limit voltage while a load is applied to ramp up the selected word line 685 to a target word line voltage at a controlled slew rate.

[0074] Fig. Figure 7 shows an exemplary machine of a computer system 700 in which a set of instructions can be executed to cause the machine to perform one or more of the methods discussed herein. In some embodiments, the computer system 700 may correspond to a host system (e.g., the host system 120 from Fig. 1), which is a memory subsystem (e.g., memory subsystem 110 from Fig. 1) contains, is coupled to, or uses, or can be used to perform the operations of a controller (e.g., to run an operating system, to perform operations that the charge pump management component 113 from Fig. 1 and Fig. 5). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and / or the Internet. The machine can function as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0075] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a web application, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify the actions to be performed by that machine. Even if a single machine is depicted, the term "machine" is intended to encompass any type of machine that, individually or collectively, executes a set (or multiple sets) of instructions to perform one or more of the methods discussed herein.

[0076] The exemplary computer system 700 comprises a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

[0077] The processing device 702 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. Specifically, the processing device may be a CISC (Complex Instruction Set Computing) microprocessor, a RISC (Reduced Instruction Set Computing) microprocessor, a VLIW (Very Long Instruction Word) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processing device 702 may also be one or more specialized processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like.The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 may also include a network interface device 708 for communication over the network 720.

[0078] The data storage system 718 may include a machine-readable storage medium 724 (also known as a computer-readable medium) on which one or more sets of instructions 726 or software embodying one or more of the methods or functions described herein are stored. The instructions 726 may also reside wholly or at least partially in the main memory 704 and / or the processing device 702 while being executed by the computer system 700, the main memory 704 and the processing device 702 also being machine-readable storage media. The machine-readable storage medium 724, the data storage system 718, and / or the main memory 704 may be connected to the storage subsystem 110. Fig. 1 corresponds.

[0079] In one embodiment, the instructions 726 contain instructions for implementing a functionality that is a selective displacement component (e.g., the charge pump management component 113 from Fig.1) corresponds. Although the machine-readable storage medium 724 is shown as a single medium in one embodiment, the term “machine-readable storage medium” shall be understood to include a single medium or multiple media that store one or more sets of instructions. The term “machine-readable storage medium” shall also include any medium capable of storing or encoding a set of instructions for execution by the machine, causing the machine to perform one or more of the methods of the present invention. Accordingly, the term “machine-readable storage medium” includes, but is not limited to, solid-state storage media, optical media, and magnetic media.

[0080] Some parts of the preceding detailed descriptions have been presented in the form of algorithms and symbolic representations of operations concerning data bits in a computer memory. These algorithmic descriptions and representations are used by those skilled in the art of data processing to communicate the content of their work most effectively to other skilled workers. An algorithm is understood here, and generally, as a consistent sequence of operations that leads to a desired result. The operations are those that require physical manipulations of physical quantities. Usually, though not necessarily, these quantities are in the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated.It has sometimes proven useful, mainly for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, concepts, numbers or the like.

[0081] It should be borne in mind, however, that all these and similar terms must be related to the corresponding physical quantities and are merely practical designations for these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates data represented as physical (electronic) quantities in the registers and memories of the computer system and transforms them into other data represented in a similar manner as physical quantities in the memories or registers of the computer system or other such information storage systems.

[0082] The present invention also relates to a device for performing the operations described herein. This device may be specifically designed for the intended purposes, or it may comprise a general-purpose computer that is selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of floppy disk, including floppy disks, optical disks, CD-ROMs and magnetic-optical disks, read-only memory (ROMs), random-access memory (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0083] The algorithms and representations presented here are not inherently tied to a specific computer or other device. Various general-purpose systems can be used with programs according to the teachings contained herein, or it may prove advantageous to construct a more specialized device for carrying out the method. The structure for a multitude of such systems is presented in the following description. Furthermore, the present invention is not described with reference to any particular programming language. It is obvious that a multitude of programming languages ​​can be used to implement the teachings of the disclosure as described herein.

[0084] The present invention can be provided as a computer program product or in the form of software, which may include a machine-readable medium containing instructions stored thereon that can be used to program a computer system (or other electronic devices) to carry out a method according to the present invention. A machine-readable medium comprises any mechanism for storing information in a form that can be read by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium comprises a machine-readable (e.g., computer-readable) storage medium, such as read-only memory (“ROM”), random-access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

[0085] In the preceding description, embodiments of the invention have been described with reference to specific embodiments. It is obvious that various modifications can be made to these embodiments without deviating from the basic concept and scope of the embodiments of the invention as set forth in the following claims. Accordingly, the description and the drawings are to be understood in an illustrative rather than a limiting sense.

Claims

[1] Storage device comprising: a storage array; and a control logic that is functionally coupled to the memory array to perform operations, comprising: Determining, by a processing device, a first digitally controlled pump voltage level of a charge pump coupled to a word line related to the storage array; Determine that a first measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level satisfy a first condition; Generating, in response to determining that the first condition is satisfied, an update signal, causing the first digitally controlled pump voltage level applied to the charge pump to be changed to a second digitally controlled pump voltage level; Determine that a second measured digitally controlled voltage level satisfies a second condition; and In response to the fulfillment of the second condition, increase the number of stages of the charge pump from a first number of stages to a second number of stages. [2] Storage device according to claim 1, wherein the first condition is satisfied if a difference between the first measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level is less than or equal to a limit level. [3] Storage device according to claim 1, wherein the operations further comprise generating a first update signal to increase the first digitally controlled pump voltage level to the second digitally controlled pump voltage level. [4] Storage device according to claim 1, wherein the operations further comprise generating a plurality of update signals to increase a charge pump voltage level until a target charge pump control voltage level is reached. [5] Storage device according to claim 1, wherein the operations further comprise causing the charge pump to set a target word line voltage level of the word line. [6] Storage device according to claim 1, wherein the first digitally controlled pump voltage level is lower than the second digitally controlled pump voltage level. [7] Storage device according to claim 1, wherein the second condition is met if the second measured digitally controlled voltage level exceeds a pump stage transition limit voltage level. [8] Storage device comprising: a storage array; and a control logic that is functionally coupled to the memory array to perform operations, comprising: Setting an initial digitally controlled pump voltage level of a charge pump coupled to a word line related to the storage array; Determine that a first measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level satisfy a first condition; Cause, in response to the fulfillment of the first condition, the first digitally controlled pump voltage level to be changed to a second digitally controlled pump voltage level; Determine that a second measured digitally controlled voltage level, related to the word line, satisfies a second condition; and Causing, in response to determining that the second condition is met, an increase in the number of charge pump stages from a first number of stages to a second number of stages. [9] Storage device according to claim 8, wherein the first condition is satisfied if a difference between a previously measured digitally controlled voltage level related to the word line and the first digitally controlled pump voltage level is less than or equal to a first limit voltage level. [10] Storage device according to claim 9, wherein the second condition is met if the second measured digitally controlled voltage level related to the word line exceeds a second limit voltage level. [11] Storage device according to claim 8, wherein the operations further include generating an update signal to increase the number of stages of the charge pump from the first number of stages to the second number of stages. [12] Storage device according to claim 8, wherein the operations further comprise generating a plurality of update signals to increase a charge pump voltage level to a target charge pump control voltage level. [13] Storage device according to claim 8, wherein the first number of stages is smaller than the second number of stages. [14] Non-transitory computer-readable medium containing instructions which, when executed by a processing device, cause the processing device to perform operations, comprising: Setting a first digitally controlled pump voltage level of a charge pump coupled to a word line of a storage device; Determine that a first measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level satisfy a first condition; and Causing, in response to determining that the first condition is met, the first digitally controlled pump voltage level applied to the charge pump to be changed to a second digitally controlled pump voltage level; Determine that a second measured digitally controlled voltage level satisfies a second condition; and In response to the fulfillment of the second condition, increase the number of stages of the charge pump from a first number of stages to a second number of stages. [15] Non-transitory computer-readable medium according to claim 14, wherein the first condition is satisfied if a difference between the first measured digitally controlled voltage level of the word line and the first digitally controlled pump voltage level is less than or equal to a limit level. [16] Non-transitory computer-readable medium according to claim 14, wherein the operations further comprise generating a first update signal to increase the first digitally controlled pump voltage level to the second digitally controlled pump voltage level. [17] Non-transitory computer-readable medium according to claim 14, wherein the operations further comprise generating a plurality of update signals to increase a charge pump voltage level to a charge pump limit voltage level. [18] Non-transitory computer-readable medium according to claim 14, wherein the operations further comprise: Causing the charge pump to set a target word line voltage level for the word line. [19] Non-transient computer-readable medium according to claim 14, wherein the first digitally controlled pump voltage level is lower than the second digitally controlled pump voltage level. [20] Non-transitory computer-readable medium according to claim 19, wherein the second condition is met if the second measured digitally controlled voltage level exceeds a pump stage transition threshold voltage level.

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