Thin-film transistor, method for manufacturing the thin-film transistor and display device comprising the thin-film transistor

Abstract

A thin-film transistor (100, 200, 300, 301, 400, 401, 500), comprising: a first gate electrode (121) that forms a lower electrode; an active layer (140) spaced apart from the first gate electrode (121), which has a channel region (140a); and a second gate electrode (122) which is spaced apart from the active layer (140) and is arranged on the side opposite the first gate electrode (121) with respect to an active layer (140), wherein at least part of the first gate electrode (121) does not overlap the second gate electrode (122) and at least part of the second gate electrode (122) does not overlap the first gate electrode (121), the channel area (140a) overlaps at least one of the first gate electrode (121) and the second gate electrode (122), part of the channel area (140a) overlaps only one of the first gate electrode (121) and the second gate electrode (122), and another part of the channel area (140a) overlaps only the other of the first gate electrode (121) and the second gate electrode (122), the active layer (140) exhibits: a first active layer (141) facing the first gate electrode (121) and comprising an oxide semiconductor material; and a second active layer (142) arranged on top of the first active layer (141) and comprising an oxide semiconductor material, and wherein the first active layer (141) has a higher hydrogen concentration and a lower oxygen concentration than the second active layer (142).

Description

BACKGROUND Area of ​​the invention

[0001] The present disclosure relates to a thin-film transistor, a method for manufacturing the thin-film transistor, and a display device comprising the thin-film transistor. Description of the related technology

[0002] Since a thin-film transistor can be manufactured on a glass substrate or a plastic substrate, the thin-film transistor has found widespread application as a switching element or a driver element of a display device such as a liquid crystal display device or an organic light-emitting device.

[0003] The thin-film transistor can be categorized as an amorphous silicon thin-film transistor, in which amorphous silicon is used as an active layer, a polycrystalline silicon thin-film transistor, in which polycrystalline silicon is used as an active layer, and an oxide semiconductor thin-film transistor, in which oxide semiconductors are used as an active layer, based on a material that forms the active layer.

[0004] Since amorphous silicon can be deposited within a short time to form an active layer, an amorphous silicon thin-film transistor (a-Si TFT) has the advantages of a short manufacturing process time and low production costs. On the other hand, the amorphous silicon thin-film transistor has the disadvantage that its use is limited to active-matrix organic light-emitting diodes (AMOLEDs) because its current driving capability is poor due to low mobility and there is a change in the threshold voltage.

[0005] A polycrystalline silicon thin-film transistor (poly-Si TFT) is manufactured by depositing amorphous silicon and crystallizing the deposited amorphous silicon. Polycrystalline silicon thin-film transistors offer advantages such as high electron mobility, excellent stability, the ability to achieve a thin profile and high resolution, and high energy efficiency. Examples of polycrystalline silicon thin-film transistors include low-temperature polysilicon (LTPS) thin-film transistors and polysilicon thin-film transistors. However, since the manufacturing process for polycrystalline silicon thin-film transistors requires a crystallization step of the amorphous silicon, production costs are increased due to the additional process steps and the need for high-temperature crystallization.Therefore, it is difficult to use the polycrystalline silicon thin-film transistor in a large-format display device. Furthermore, it is difficult to ensure uniformity of the polycrystalline silicon thin-film transistor due to its polycrystalline properties.

[0006] An oxide semiconductor thin-film transistor (TFT), which exhibits high mobility and a large resistance change depending on oxygen content, has the advantage that desired properties can be easily achieved. Furthermore, since it is possible to grow the oxide forming the active layer at a relatively low temperature during the manufacturing process, the production costs of the oxide semiconductor thin-film transistor are reduced. Regarding the properties of oxides, their transparency makes them preferable for creating transparent displays. However, the oxide semiconductor thin-film transistor suffers from reduced stability and electron mobility compared to the polycrystalline silicon thin-film transistor.

[0007] When an oxide semiconductor thin-film transistor (TFT) is operated in an ON state for an extended period, its threshold voltage tends to change continuously. This change in the TFT's driver characteristics can shorten the device's lifespan, degrade image quality, and necessitate costly compensation techniques and additional circuitry. Therefore, improving the driver stability of the oxide semiconductor thin-film transistor is essential.

[0008] US 2016 / 0240683A1 discloses a semiconductor device for reducing parasitic capacitance in a semiconductor device comprising a transistor containing an oxide semiconductor. The transistor includes a first gate electrode, a first gate insulating film over the first gate electrode, an oxide semiconductor film over the first gate insulating film, and source and drain electrodes electrically connected to the oxide semiconductor film. The oxide semiconductor film comprises a first oxide semiconductor film on the side of the first gate electrode and a second oxide semiconductor film over the first oxide semiconductor film. The atomic fraction of In is greater than the atomic fraction of M (M being Ti, Ga, Sn, Y, Zr, La, Ce, Nd, or Hf) in the first oxide semiconductor layer, and the atomic fraction of In in the second oxide semiconductor layer is less than that in the first oxide semiconductor layer.

[0009] US Patent 2009 / 0283763A1 discloses a transistor with a self-aligning top-gate structure. The transistor comprises an oxide semiconductor layer with a source region, a drain region, and a channel region between the source and drain regions. The transistor further comprises a gate insulating layer and a gate electrode, which are stacked sequentially on the channel region. Semiconductor devices comprising at least one transistor and methods for their fabrication are also disclosed.

[0010] US 2012 / 0319 118 A1 discloses a display device comprising a first gate electrode; a first gate insulating film over the first gate electrode; an oxide semiconductor film over the first gate insulating film; a source electrode and a drain electrode over the oxide semiconductor film; a second gate insulating film over the source electrode, the drain electrode, and the oxide semiconductor film; a second gate electrode over the second gate insulating film; a planar organic resin film over the second gate insulating film; and a pixel electrode over the planar organic resin film, wherein the concentration of hydrogen atoms contained in the oxide semiconductor film and measured by secondary ion mass spectrometry is less than 1 × 10⁻⁶ 16 cm -3 amounts. OVERVIEW

[0011] A thin-film transistor according to claim 1, a display device according to claim 16, and a method for manufacturing a thin-film transistor according to claims 17 and 24 are provided. Further embodiments are described in the dependent claims.

[0012] The present disclosure was prepared with regard to the above problems, and it is an objective of the present disclosure to provide a thin-film transistor that has features of a top-gate structure and a bottom-gate structure for minimizing a rate of change of a threshold voltage.

[0013] Another objective of the present disclosure is to provide a thin-film transistor that exhibits improved drive stability due to the presence of a portion influenced by a top gate and a portion influenced by a bottom gate in a channel region.

[0014] Another objective of the present disclosure is to provide a thin-film transistor which has improved driving stability, since a part for moving a threshold voltage in a positive (+) direction and a part for moving the threshold voltage in a negative (-) direction are connected together in series in a channel area.

[0015] Furthermore, another objective of the present disclosure is to provide a thin-film transistor having a channel region that has an oxygen excess region and a hydrogen excess region.

[0016] Furthermore, another objective of the present disclosure is to provide a thin-film transistor that can minimize a change in a threshold voltage by moving a threshold voltage in a positive (+) direction by means of an electron trap in an oxygen excess region and moving the threshold voltage in a negative (-) direction by means of a hole trap in a hydrogen excess region.

[0017] Furthermore, another objective of the present disclosure is to provide a method for manufacturing the thin-film transistor.

[0018] Furthermore, another objective of the present disclosure is to provide a display device incorporating the thin-film transistor.

[0019] In addition to the objectives of this Revelation mentioned above, further objectives and features of this Revelation are clearly understood by experts based on the following description of this Revelation.

[0020] According to one aspect of the present disclosure, the above and further objectives can be achieved by providing a thin-film transistor and a method for fabricating a thin-film transistor according to the independent claims. Further embodiments are described in the dependent claims. According to one aspect of the present disclosure, the above and further objectives can be achieved by providing a thin-film transistor comprising a first gate electrode, an active layer spaced apart from the first gate electrode and having a channel region, and a second gate electrode spaced apart from the active layer and located on a side opposite the first gate electrode with respect to an active layer. At least a portion of the first gate electrode does not overlap the second gate electrode, and at least a portion of the second gate electrode does not overlap the first gate electrode.The channel region overlaps at least one of the first and second gate electrodes, part of the channel region overlaps only one of the first and second gate electrodes, and another part of the channel region overlaps only the other of the first and second gate electrodes. The active layer comprises a first active layer, which is an oxide semiconductor material, and a second active layer, which is arranged on top of the first active layer and is also an oxide semiconductor material. One of the first and second active layers has a higher hydrogen concentration and a lower oxygen concentration than the other.

[0021] The channel region can have a first channel region that overlaps the first gate electrode but not the second gate electrode, and a second channel region that overlaps the second gate electrode but not the first gate electrode.

[0022] The first canal area can be located at one end of the canal area, and the second canal area can be located at the other end of the canal area.

[0023] The active layer can have a first connection area and a second connection area, which are separate from each other and each is connected to the channel area.

[0024] The first connection area can be in contact with the first canal area, and the second connection area can be in contact with the second canal area.

[0025] The first connection area may not overlap the second gate electrode, and the second connection area may not overlap the first gate electrode.

[0026] At least part of the first connection area can overlap the first gate electrode.

[0027] Part of the first gate electrode and part of the second gate electrode can overlap.

[0028] Part of the channel area can overlap both the first gate electrode and the second gate electrode.

[0029] The thin-film transistor may also have a hydrogen supply layer located between the first gate electrode and the active layer.

[0030] The thin-film transistor may also have an oxygen provision layer located between the active layer and the second gate electrode.

[0031] The first active layer and the second active layer can have the same metal composition.

[0032] The first active layer can have a higher hydrogen concentration than the second active layer, and the second active layer can have an oxygen concentration that is higher than that of the first active layer.

[0033] The thin-film transistor can also have a hydrogen delivery layer on the active layer.

[0034] The first active layer can have a higher oxygen concentration than the second active layer, and the second active layer can have a higher hydrogen concentration than the first active layer.

[0035] The first active layer may have a first region that overlaps with the first gate electrode, and the first region may have a hydrogen concentration that is higher than that of the other region of the first active layer.

[0036] The second active layer may have a second region that overlaps with the second gate electrode, and the second region may have an oxygen concentration that is higher than that of the other region of the second active layer.

[0037] According to another aspect of the present disclosure, the above and further objectives can be achieved by providing a display device which includes the above thin-film transistor.

[0038] According to a further aspect of the present disclosure, the above and further objectives can be achieved by providing a method for manufacturing a thin-film transistor, which comprises forming a first gate electrode on a substrate, forming a first gate insulating layer on the first gate electrode, forming an active layer on the first gate insulating layer, and forming a second gate electrode on the active layer, wherein at least a part of the first gate electrode does not overlap the second gate electrode and at least a part of the second gate electrode does not overlap the first gate electrode, the active layer has a channel region, and the channel region overlaps at least one of the first gate electrode and the second gate electrode, and the active layer has a first active layer and a second active layer on the first active layer.and one of the first active layers and the second active layer has a higher hydrogen concentration and a lower oxygen concentration than the other.

[0039] Part of the first gate electrode and part of the second gate electrode can overlap.

[0040] The process for manufacturing a thin-film transistor may further include the formation of a hydrogen provision layer prior to the formation of the first gate insulating layer.

[0041] The process for manufacturing a thin-film transistor may also include oxygen treatment of a surface of the active layer.

[0042] Oxygen treatment can involve treating the surface of the active layer with N2O gas.

[0043] The formation of the second gate electrode can exhibit the formation of a second gate electrode pattern.

[0044] The method for manufacturing a thin-film transistor can further include making the active layer conductive by using the second gate electrode pattern as a mask. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] The above and further objectives, features and other advantages of the present disclosure will be more clearly understood by reference to the following detailed description in combination with the accompanying drawings, in which: Fig. 1 is a cross-sectional view representing a thin-film transistor according to an embodiment of the present disclosure; Fig. 2 is an enlarged partial cross-sectional view showing a channel area of ​​a Fig. 1 represents the thin-film transistor shown; Fig. 3 is a cross-sectional view representing a thin-film transistor according to a further embodiment of the present disclosure; Fig. 4A and Fig. 4B Cross-sectional views are shown, representing thin-film transistors according to yet another embodiment of the present disclosure; Fig. 5A and Fig. 5B Cross-sectional views, each representing a thin-film transistor according to a further embodiment of the present disclosure; Fig. 6 is a cross-sectional view, each representing a thin-film transistor according to a further embodiment of the present disclosure; Fig. 7 and Fig. Eight cross-sectional views are shown, representing thin-film transistors according to comparative examples; Fig. 9 is a diagram that represents a change in a threshold voltage; Fig. 10A, Fig. 10B and Fig. 10C diagrams are those that represent a change in a threshold voltage as a function of time; Fig. 11A to 11M process views are which describe a method for manufacturing a thin-film transistor according to an embodiment of the present disclosure; Fig. 12 is a schematic view representing a display device according to an embodiment of the present disclosure; Fig. 13 is a circuit view that selects any pixel from Fig. 12 represents; Fig. 14 is a circuit view representing any pixel of a display device according to a further embodiment of the present disclosure; Fig. 15 is a circuit view representing any pixel of a display device according to yet another embodiment of the present disclosure; and Fig. 16 is a circuit view that represents any pixel of a display device according to a further embodiment of the present disclosure. DETAILED DESCRIPTION OF THE REVELATION

[0046] The advantages and features of the present disclosure, and methods for implementing them, are clarified by means of the following embodiments, which are described with reference to the accompanying figures. The present disclosure may, however, be expressed in various forms and should not be understood as being limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure is comprehensive and complete and conveys the full scope of the present disclosure to those skilled in the art. Furthermore, the present disclosure is limited only by the scope of the claims.

[0047] A shape, size, ratio, angle, and number shown in the accompanying figures to describe exemplary embodiments of the present disclosure are merely examples, and therefore the present disclosure is not limited to the details shown. The same reference numerals denote the same elements throughout the specification. In the following description, a detailed explanation of the relevant known function may be omitted if it is deemed to unnecessarily obscure the important point of the present disclosure.

[0048] In cases where 'exhibit', 'have', and 'comprise', as described in this specification, are used, an additional part may be added unless 'only-' is used. Singular forms may have plural forms unless otherwise stated.

[0049] When interpreting an element, the element is interpreted in such a way that it includes an error area, even if there is no explicit description.

[0050] When describing a positional relationship, for example, when the positional relationship is described using terms such as "on", "above", "below", and "next to", one or more parts may be positioned between the other parts unless "straight" or "directly" is used.

[0051] Spatially relative terms such as "below," "under," "lower," "above," and "above" may be used herein to easily describe the relationship of one or more elements to another element or elements, as depicted in the figures. It is to be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures. For example, if the device shown in the figures is reversed, the device that is "below" or "under" another device may be "above" another device. Therefore, an exemplary term "below" or "under" may include orientations "below" or "under" and "above" orientations. Similarly, an exemplary term "above" or "on" may include orientations "above" and "below" or "under" orientations.

[0052] When describing a temporal relationship, for example when the time rank is described as "after", "subsequent", "afterwards" and "before", a case which is not continuous may be included unless "straight ahead" or "directly" is used.

[0053] It is to be understood that, although the terms "first," "second," etc., are used to describe different elements, these terms are not intended to limit their use. They are used only to distinguish one element from another. For example, a first element may be called its second element, and similarly, a second element may be called a first element, without altering the scope of the present disclosure.

[0054] The term "at least one" should be understood to include any and all combinations of one or more of the listed elements. For example, "at least one of a first element, a second element, and a third element" means the combination of all proposed elements, of two or more of the first element, the second element, and the third element, as well as the first element, the second element, or the third element alone.

[0055] Features of different embodiments of the present disclosure can be partially or wholly combined or linked together and can be applied and operated in different ways, as persons skilled in the art can reasonably understand. The embodiments of the present disclosure can be carried out independently of one another or can be carried out together in a relationship of mutual dependence.

[0056] In the figures, identical or similar elements are designated with the same reference numeral, even if they are depicted in different figures. Whenever possible, the same reference numerals are used consistently throughout the figures so that they refer to the same or similar parts.

[0057] In the embodiments of the present disclosure, a source electrode and a drain electrode are distinguished from one another for the sake of simplicity. However, the source electrode and the drain electrode can be used interchangeably. The source electrode can be the drain electrode, and the drain electrode can be the source electrode. Furthermore, the source electrode in any embodiment of the present disclosure can be the drain electrode in another embodiment of the present disclosure, and the drain electrode in any embodiment of the present disclosure can be the source electrode in another embodiment of the present disclosure.

[0058] In some embodiments of the present disclosure, for the sake of simplicity, a source region is distinguished from a source electrode, and a drain region is distinguished from a drain electrode. However, the embodiments of the present disclosure are not limited to this structure. For example, the source region can be the source electrode, and the drain region can be the drain electrode. Furthermore, the source region can be the drain electrode, and the drain region can be the source electrode.

[0059] Fig. Figure 1 is a cross-sectional view showing a thin-film transistor 100 according to an embodiment of the present disclosure.

[0060] The thin-film transistor 100 according to an embodiment of the present disclosure has a first gate electrode 121, an active layer 140 and a second gate electrode 122.

[0061] The active layer 140 is arranged to be spaced apart from the first gate electrode 121. At least part of the active layer 140 overlaps the first gate electrode 121.

[0062] The second gate electrode 122 is spaced apart from the active layer 140 and arranged to be opposite the first gate electrode 121 with respect to the active layer 140. The first gate electrode 121 is arranged on one side of the active layer 140, and the second gate electrode 122 is arranged on the other side of the active layer 140.

[0063] The active layer 140 has a channel region 140a. The channel region 140a overlaps at least one of the first gate electrode 121 and the second gate electrode 122. Furthermore, the first gate electrode 121 can be wider than the second gate electrode 122, and the first gate electrode 121 can overlap more of the channel region 140a than the second gate electrode 122.

[0064] Fig. Figure 2 is an enlarged partial cross-sectional view showing channel area 140a of the thin-film transistor 100, which is located in Fig. 1 is shown.

[0065] The thin-film transistor 100 according to an embodiment of the present disclosure is described in more detail with reference to Fig. 1 and Fig. 2 described.

[0066] Referring to Fig. 1 and Fig. 2 is the first gate electrode 121 arranged on a substrate 110.

[0067] Glass or plastic can be used as substrate 110. A transparent plastic, e.g., polyimide, which has flexible properties, can be used as the plastic. If polyimide is used as substrate 110, a heat-resistant polyimide that tolerates high temperatures can be used, given that a high-temperature deposition process is carried out on substrate 110.

[0068] The first gate electrode 121 can comprise at least one of the following: aluminum-based metals such as aluminum (Al) or aluminum alloy, silver-based metals such as silver (Ag) or silver alloy, copper-based metals such as copper (Cu) or copper alloy, molybdenum-based metals such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), or titanium (Ti). The first gate electrode 121 can have a multilayer structure comprising at least two conductive layers that differ in their respective physical properties.

[0069] A first gate insulating layer 131 is arranged on the first gate electrode 121. The first gate insulating layer 131 can have insulating properties and can comprise at least one silicon oxide, a silicon nitride, or a metal-based oxide. According to one embodiment of the present disclosure, the first gate insulating layer 131 can comprise a silicon nitride. The silicon nitride contains hydrogen at a relatively higher concentration than the silicon oxide and the metal-based oxide.

[0070] The first gate insulating layer 131 can have a single-layer structure, or it can have a multi-layer structure.

[0071] The active layer 140 is arranged on the first gate insulating layer 131.

[0072] According to one embodiment of the present disclosure, the active layer 140 comprises an oxide semiconductor material. The active layer 140 can be formed from an oxide semiconductor layer.

[0073] The active layer 140 can, for example, comprise at least one of the following oxide semiconductor materials: IZO(InZnO)-based, IGO(InGaO)-based, ITO(InSnO)-based, IGZO(InGaZnO)-based, IGZTO(InGaZnSnO)-based, ITZO(InSnZnO)-based, IGTO(InGaSnO)-based, GO(GaO)-based, GZTO(GaZnSnO)-based, and GZO(GaZnO)-based. However, an embodiment of the present disclosure is not limited to this example, and the active layer 140 can be formed from other oxide semiconductor materials known in the art.

[0074] The active layer 140 has a channel region 140a, a first connection region 140b, and a second connection region 140c, each formed on both sides of the channel region 140a. The first connection region 140b and the second connection region 140c are spaced apart from each other and are each connected to the channel region 140a.

[0075] A second gate insulating layer 132 is arranged on the active layer 140. The second gate insulating layer 132 can have insulating properties and can comprise at least one silicon oxide, a silicon nitride, or a metal-based oxide. The second gate insulating layer 132 can have a single-layer structure or a multi-layer structure.

[0076] According to one embodiment of the present disclosure, the second gate insulating layer 132 can comprise a silicon oxide. The silicon oxide can contain oxygen at a relatively higher concentration than the silicon nitride.

[0077] The second gate insulating layer 132 may be structured or unstructured. The structured second gate insulating layer 132 may cover at least the channel region 140a of the active layer 140, but an embodiment of the present disclosure is not limited thereto. The second gate insulating layer 132 may cover the entire upper surface of the active layer 140.

[0078] The second gate electrode 122 is arranged on the second gate insulating layer 132.

[0079] The second gate electrode 122 can be made of the same material as the first gate electrode 121, or it can be made of a different material. The second gate electrode 122 is located on the opposite side of the first gate electrode 121 with respect to the active layer 140. For example, the active layer 140 is located between the first gate electrode 121 and the second gate electrode 122.

[0080] According to one embodiment of the present disclosure, at least a portion of the first gate electrode 121 does not overlap the second gate electrode 122, and at least a portion of the second gate electrode 122 does not overlap the first gate electrode 121. A portion of the first gate electrode 121 and a portion of the second gate electrode 122 may overlap each other. For example, the first gate electrode 121, the channel region 140a, and the second gate electrode 122 may be vertically stacked in a stepped arrangement, wherein the first gate electrode 121 may mainly overlap about half of the channel region 140a, and the second gate electrode 122 may mainly overlap the other half of the channel region 140a.

[0081] Referring to Fig. 1 An interlayer dielectric layer 150 is arranged on the second gate electrode 122. The interlayer dielectric layer 150 can be formed from an insulating material.

[0082] A source electrode 161 and a drain electrode 162 are arranged on the interlayer dielectric layer 150. The source electrode 161 and the drain electrode 162 are spaced apart from each other and connected to the active layer 140.

[0083] Referring to Fig. The source electrode 161 is connected to the first connection region 140b by a contact hole formed in the interlayer dielectric layer 150, and the drain electrode 162 is connected to the second connection region 140c by another contact hole formed in the interlayer dielectric layer 150. The first connection region 140b, which is connected to the source electrode 161, can be referred to as a source connection region, and the second connection region 140c, which is connected to the drain electrode 162, can be referred to as a drain connection region.

[0084] According to one embodiment of the present disclosure, the first interconnection region 140b and the second interconnection region 140c can be formed by selectively making the active layer 140 conductive. In this context, making the active layer 140 conductive can be understood as increasing the electrical conductivity of the active layer 140 to become similar to that of a conductor (e.g., a metal). Additionally, making it conductive can be understood as providing conductivity to a semiconductor material to increase its conductivity. For example, the active layer 140 can be selectively made conductive by doping using a dopant, thereby forming the first interconnection region 140b and the second interconnection region 140c.

[0085] For doping, at least one of boron (B) ions, phosphorus (P) ions or fluorine (F) ions can be used.

[0086] According to one embodiment of the present disclosure, the first connection area 140b can be a drain connection area, and the second connection area 140c can be a source connection area. Additionally, one of the first connection area 140b and the second connection area 140c can be a source electrode, and the other of the first connection area 140b and the second connection area 140c can be a drain electrode.

[0087] The first connection area 140b and the second connection area 140c can serve as conduits.

[0088] The following section describes in more detail the channel area 140a of the active layer 140 with reference to Fig. 2.

[0089] According to one embodiment of the present disclosure, the channel region 140a overlaps at least one of the first gate electrode 121 and the second gate electrode 122. If all regions of the channel region 140a overlap at least one of the first gate electrode 121 and the second gate electrode 122, continuity of the channel region 140a can be ensured, for example from one end of the channel region 140a, for example a left side of the channel region 140a, as illustrated in Fig. 2, to the other end of channel area 140a, for example a right side of channel area 140a, shown in Fig. 2 (e.g. all areas of channel region 140a can be overlapped by at least one of the first gate electrode 121 or the second gate electrode 122, which allows complete coverage of the channel).

[0090] Referring to Fig. 1 and Fig. 2 at least part of the first gate electrode 121 does not overlap the second gate electrode 122, and at least part of the second gate electrode 122 does not overlap the first gate electrode 121.

[0091] Due to the arrangement of the first gate electrode 121 and the second gate electrode 122, part of the channel region 140a overlaps only one of the first gate electrode 121 and the second gate electrode 122, and another part of the channel region 140a overlaps only the other of the first gate electrode 121 and the second gate electrode 122. Furthermore, the channel region 140a can have a central region that overlaps with both the first and the second gate electrode 121, 122.

[0092] More detailed reference to Fig. 2. According to an embodiment of the present disclosure, the channel region 140a of the active layer 140 has a first channel region a1 which overlaps with the first gate electrode 121 but does not overlap with the second gate electrode 122, and a second channel region a2 which overlaps with the second gate electrode 122 but does not overlap with the first gate electrode 121.

[0093] Accordingly, the first channel region a1 of channel region 140a is operated by means of the first gate electrode 121, and the second channel region a2 of channel region 140a is operated by means of the second gate electrode 122. The first channel region a1 of channel region 140a is a region that is influenced by the first gate electrode 121, and the second channel region a2 of channel region 140a is influenced by the second gate electrode 122.

[0094] Referring to Fig. 2 The first channel region a1 is arranged at one end of the channel region 140a, and the second channel region a2 is arranged at the other end of the channel region 140a. According to one embodiment of the present disclosure, as in Fig. 2 shown, the first connection area 140b is in contact with the first channel area a1, and the second connection area 140c can be in contact with the second channel area a2.

[0095] Referring to Fig. 1 and Fig. 2. The first connection area 140b does not overlap the second gate electrode 122, and the second connection area 140c does not overlap the first gate electrode 121. According to one embodiment of the present disclosure, at least a portion of the first connection area 140b can overlap the first gate electrode 121. To enable the first gate electrode 121 to adequately cover the first channel region a1, the first gate electrode 121 can have an area larger than the first channel region a1. Consequently, a portion of the first connection area 140b can overlap the first gate electrode 121. Although a portion of the first connection area 140b overlaps the first gate electrode 121, the first connection area 140b is made conductive and therefore does not serve as a channel.Therefore, although there is an area where the first connection area 140b overlaps the first gate electrode 121, the driving of the thin-film transistor 100 is not affected by the overlap area.

[0096] On the other hand, according to one embodiment of the present disclosure, the first connection area 140b may not overlap the second gate electrode 122. The second gate electrode 122 is part of a pattern that serves as a mask during the selective conductivity process of the active layer 140. Therefore, the second gate electrode 122 may not overlap the first connection area 140b and the second connection area 140c.

[0097] According to one embodiment of the present disclosure, a part of the first gate electrode 121 and a part of the second gate electrode 122 can overlap each other. Therefore, a part of the channel region 140a can overlap both the first gate electrode 121 and the second gate electrode 122.

[0098] According to one embodiment of the present disclosure, the channel region 140a can have a third channel region a3 that overlaps with both the first gate electrode 121 and the second gate electrode 122. The third channel region a3 is a region that is influenced by both the first gate electrode 121 and the second gate electrode 122.

[0099] To ensure the continuity of the channel region 140a, it is necessary that the channel region 140a overlaps at least one of the first gate electrode 121 or the second gate electrode 122, and the first gate electrode 121 and the second gate electrode 122 can be designed to partially overlap each other with regard to a process defect in the manufacturing process of the first gate electrode 121 and the second gate electrode 122. According to one embodiment of the present disclosure, the length of the third channel region a3 can be designed to be as small as possible.

[0100] If the third canal area a3 exists in canal area 140a, continuity of canal area 140a from one end of canal area 140a to the other end of canal area 140a can be ensured.

[0101] According to one embodiment of the present disclosure, the active layer 140 has a first active layer 141 and a second active layer 142 on the first active layer 141. Referring to Fig. 1 and Fig. In Figure 2, the first active layer 141 is arranged on the first gate insulating layer 131, and the second active layer 142 is arranged on the first active layer 141. The first active layer 141 and the second active layer 142 are oxide semiconductor material layers. The oxide semiconductor material forming the first active layer 141 and the second active layer 142 can comprise metal and oxygen. According to one embodiment of the present disclosure, the first active layer 141 and the second active layer 142 can have the same metal composition. According to another embodiment of the present disclosure, the first active layer 141 and the second active layer 142 can have the same metal composition and can differ from each other by a difference in the content of at least one of oxygen and hydrogen.

[0102] According to one embodiment of the present disclosure, one of the first active layer 141 and the second active layer 142 has a higher hydrogen concentration and a lower oxygen concentration than the other of the first active layer 141 and the second active layer 142.

[0103] For example, the first active layer 141 may have a hydrogen concentration that is higher than that of the second active layer 142, and may have an oxygen concentration that is lower than that of the second active layer 142. The second active layer 142 may have a hydrogen concentration that is lower than that of the first active layer 141, and may have an oxygen concentration that is higher than that of the first active layer 141.

[0104] According to one embodiment of the present disclosure, the first active layer 141 has an excess of hydrogen (H) compared to the second active layer 142. The first active layer 141 can be a hydrogen excess layer, which has a higher hydrogen concentration than an ordinary oxide semiconductor material layer used as a channel of the thin-film transistor.

[0105] If the first active layer 141 has an excess of hydrogen, a hole-catching effect occurs due to an ionization effect of hydrogen (H), which can cause the threshold voltage of the thin-film transistor 100 to shift in a more negative (-) direction. Therefore, the threshold voltage Vth can be shifted in the negative (-) direction.

[0106] According to one embodiment of the present disclosure, the second active layer 142 has an excess of oxygen (O) compared to the first active layer 141. The second active layer 142 can be an oxygen-excess layer having an oxygen concentration higher than that of a conventional oxide semiconductor material used as a channel of the thin-film transistor.

[0107] If the second active layer 142 has an excess of oxygen, an electron trapping effect occurs, causing the threshold voltage of the thin-film transistor 100 to shift in a positive (+) direction. Therefore, the threshold voltage Vth can be shifted in the positive (+) direction.

[0108] According to one embodiment of the present disclosure, the thin-film transistor 100 can simultaneously exhibit a negative (-) shift effect of the threshold voltage Vth due to the layer containing excess hydrogen and a positive (+) shift effect of the threshold voltage Vth due to the layer containing excess oxygen, thereby suppressing a change in the threshold voltage Vth of the thin-film transistor 100 itself over time.

[0109] According to one embodiment of the present disclosure, the case in which the oxide semiconductor material layer has an “excess oxygen” means that the oxygen ratio is higher than that when the metal and oxygen forming the oxide semiconductor form a stable chemical compound in a stoichiometric manner.

[0110] An example case in which In, Ga and Zn are contained in an IGZO(InGaZnO)-based oxide semiconductor in a ratio of 1:1:1 is described.

[0111] Indium (In) can combine with oxygen in a state of In₂O₃. Gallium (Ga) can combine with oxygen in a state of Ga₂O₃. Additionally, zinc (Zn) can combine with oxygen in a state of ZnO. Therefore, if the stoichiometric ratio of In, Ga, and Zn is 1:1:1, the corresponding stoichiometric ratio of oxygen is 1.5:1.5:1. Consequently, if In, Ga, and Zn are used in a 1:1:1 ratio, the stoichiometric ratio of oxygen will be 4. In this case, the stoichiometric ratio of In, Ga, Zn, and O is 1:1:1:4 (In:Ga:Zn:O = 1:1:1:4), and the stoichiometric ratio of oxygen can be 4. Therefore, the case that the oxide semiconductor material layer has "excess oxygen" means that the stoichiometric ratio of oxygen exceeds 4 when the stoichiometric ratio of In, Ga and Zn is 1:1:1.This can be expressed using the following equation 1. InGaZnO 4+x (where x>0) [Equation 1]

[0112] In general, excess hydrogen can be described as an oxygen-deficient state. For example, in an oxide semiconductor layer where the stoichiometric ratio of In, Ga, and Zn is 1:1:1, if the stoichiometric oxygen content is less than 4, it can be described as being in an oxygen-deficient state. The oxygen-deficient state can be described, for example, by Equation 2. InGaZnO 4-y (where y>0) [Equation 2]

[0113] In general, a gap resulting from a lack of oxygen in the oxide semiconductor layer can be filled by hydrogen (H). The case where the oxide semiconductor material layer has "excess hydrogen" means that the oxide semiconductor contains more hydrogen than a stable oxygen-deficient state. According to one embodiment of the present disclosure, if the hydrogen content is at least twice the oxygen deficiency, the oxide semiconductor layer can be described as having a hydrogen excess state. More specifically, in Equation 2, if the stoichiometric hydrogen content of the oxide semiconductor layer is 2y or more, it can be described as having a hydrogen excess state.

[0114] Referring to Fig. 2. The first channel region a1 of channel region 140a is driven by the first gate electrode 121, and the first active layer 141 in the first channel region a1 is arranged to be closer to the first gate electrode 121 than the second active layer 142. Therefore, the driving of the first channel region a1 of channel region 140a is mainly influenced by the first active layer 141. Consequently, if the first active layer 141 has a higher hydrogen concentration and a lower oxygen concentration than the second active layer 142, the first channel region a1 can serve to enable the threshold voltage of the thin-film transistor 100 to be driven in the negative (-) direction.

[0115] The second channel region a2 of channel region 140a is driven by the second gate electrode 122, and the second active layer 142 in the second channel region a2 is arranged to be closer to the second gate electrode 122 than the first active layer 141. Therefore, the driving of the second channel region a2 of channel region 140a is mainly influenced by the second active layer 142. Consequently, if the second active layer 142 has a higher oxygen concentration and a lower hydrogen concentration than the first active layer 141, the second channel region a2 can serve to enable the threshold voltage of the thin-film transistor 100 to be driven in the positive (+) direction.

[0116] As described above, the channel region 140a of the thin-film transistor 100, according to one embodiment of the present disclosure, has a first channel region a1, which serves to shift the threshold voltage in the negative (-) direction, and a second channel region a2, which serves to shift the threshold voltage Vth in the positive (+) direction. Therefore, in the thin-film transistor 100, according to one embodiment of the present disclosure, the shifting effect of the threshold voltage Vth in the negative (-) direction and the shifting effect of the threshold voltage Vth in the positive (+) direction are balanced, thereby suppressing any change in the threshold voltage Vth. Therefore, the thin-film transistor 100, according to one embodiment of the present disclosure, can be operated stably without a significant change in the threshold voltage Vth.In particular, even if the thin-film transistor is operated in an ON state for an extended period, it can be operated stably without any change in the threshold voltage. For example, due to this unique design, the invention can effectively set the threshold voltage Vth to a specific value and maintain it there, even after the device has been used for a long time.

[0117] However, an embodiment of the present disclosure is not limited to the above example, and the first active layer 141 may have a lower hydrogen concentration and a higher oxygen concentration than the second active layer 142, and the second active layer 142 may have a higher hydrogen concentration and a lower oxygen concentration than the first active layer 141 (referring to Fig. 4B and Fig. 5B).

[0118] Referring to Fig. 2. The first channel region a1 of channel region 140a is driven by means of the first gate electrode 121, and the first active layer 141, which is contained in the first channel region a1, is arranged to be closer to the first gate electrode 121 than the second active layer 142. Therefore, the driving of the first channel region a1 of channel region 140a is mainly influenced by the first active layer 141. Consequently, if the first active layer 141 has a lower hydrogen concentration and a higher oxygen concentration than the second active layer 142, the first channel region a1 can serve to allow the threshold voltage of the thin-film transistor 301 or 401 to move in the positive (+) direction.

[0119] The second channel region a2 of channel region 140a is operated by means of the second gate electrode 122, and the second active layer 142, contained in the second channel region a2, is arranged to be closer to the second gate electrode 122 than the first active layer 141. Therefore, the second channel region a2 of channel region 140a is mainly influenced by the second active layer 142. Consequently, if the second active layer 142 has a higher hydrogen concentration and a lower oxygen concentration than the first active layer 141, the second channel region a2 can serve to allow the threshold voltage of the thin-film transistor 301 or 401 to move in the negative (-) direction.

[0120] As described above, the channel region 140a of the thin-film transistor 301 or 401, according to an embodiment of the present disclosure, has both a first channel region a1, which serves to shift the threshold voltage Vth in the positive (+) direction, and a second channel region a2, which serves to shift the threshold voltage Vth in the negative (-) direction (referring to Fig. 4B and Fig. 5B). Therefore, in the thin-film transistor 301 or 401 according to an embodiment of the present disclosure, the shift effect of the threshold voltage Vth in the positive (+) direction and the shift effect of the threshold voltage Vth in the negative (-) direction can be balanced, thereby suppressing a change in the threshold voltage Vth. Therefore, the thin-film transistor 301 or 401 according to an embodiment of the present disclosure can be operated stably without a large change in the threshold voltage Vth.

[0121] As described above, according to one embodiment of the present disclosure, the first active layer 141 can have a higher hydrogen concentration and a lower oxygen concentration than the second active layer 142, and vice versa. Due to the difference between the hydrogen and oxygen concentrations of the first active layer 141 and the second active layer 142, and the arrangement characteristics of the first gate electrode 121 and the second gate electrode 122, the thin-film transistor 100, according to one embodiment of the present disclosure, can exhibit excellent stability without a change in the threshold voltage Vth.

[0122] The hydrogen concentration and the oxygen concentration of the first active layer 141 and the second active layer 142 can be adjusted in various ways.

[0123] For example, the material used in the manufacturing process of the first active layer 141 and the second active layer 142 can be appropriately selected so that the hydrogen concentration and the oxygen concentration of the first active layer 141 and the second active layer 142 can be adjusted.

[0124] According to one embodiment of the present disclosure, the first active layer 141 and the second active layer 142 can be formed by means of a metal-organic chemical vapor deposition (MOCVD) process. At this point, the hydrogen and oxygen concentrations of the first active layer 141 and the second active layer 142 can be adjusted by adjusting the content of hydrogen gas (H2) or ozone (O3) used in the MOCVD process.

[0125] The hydrogen concentration and the oxygen concentration of the first active layer 141 and the second active layer 142 can be adjusted by depositing a hydrogen supply layer near the first active layer 141 or the second active layer 142, or by treating the first active layer 141 or the second active layer 142 with oxygen, for example with N2O gas.

[0126] Fig. Figure 3 is a cross-sectional view showing a thin-film transistor 200 according to a further embodiment of the present disclosure. The description of the elements already described is omitted here to avoid repetition.

[0127] Referring to Fig. 3. The second gate insulating layer 132 can cover the entire upper surface of the active layer 140. In Fig. 3 We refer to the surface of the active layer 140 facing the second gate electrode 122 as an upper surface. According to a further embodiment of the present disclosure, the second gate insulating layer 132 may be unstructured.

[0128] Referring to Fig. 3 A contact hole can be formed in the second gate insulating layer 132.

[0129] According to a further embodiment of the present disclosure, the source electrode 161 can be connected to the first connection area 140b of the active layer 140 by means of a contact hole formed in the interlayer dielectric layer 150 and the second gate insulating layer 132. The drain electrode 162 can be connected to the second connection area 140c of the active layer 140 by means of another contact hole formed in the interlayer dielectric layer 150 and the second gate insulating layer 132.

[0130] Fig. Figure 4A is a cross-sectional view showing a thin-film transistor 300 according to yet another embodiment of the present disclosure. The thin-film transistor 300 according to a further embodiment of the present disclosure has a hydrogen delivery layer 135 formed between the first gate electrode 121 and the active layer 140.

[0131] Referring to Fig. 4A A buffer layer 118 can be arranged on a substrate 110. The buffer layer 118 can comprise at least one silicon oxide or silicon nitride. The buffer layer 118 can protect the active layer 140 and can have a planarization property for planarizing an upper part of the substrate 110.

[0132] The first gate electrode 121 is arranged on the buffer layer 118, and a first passivation layer 133 is arranged on the first gate electrode 121. The first passivation layer 133 can serve to insulate and protect the first gate electrode 121. The first passivation layer 133 can be made of the same material as the first gate insulating layer 131.

[0133] The hydrogen supply layer 135 is arranged on the first passivation layer 133. The hydrogen supply layer 135 supplies hydrogen to the active layer 140. Consequently, the first active layer 141, which contains hydrogen at a higher concentration than the second active layer 142, can be formed. The first active layer 141 contains hydrogen at a concentration higher than a typical hydrogen concentration in the oxide semiconductor layer. According to a further embodiment of the present disclosure, the first active layer 141 is a hydrogen excess layer containing excess hydrogen.

[0134] The hydrogen supply layer 135 can, for example, be formed by a silicon nitride (SiNx). The silicon nitride layer (SiNx), which is used as the hydrogen supply layer 135, can contain hydrogen at a high concentration.

[0135] The first gate insulating layer 131 is arranged on the hydrogen delivery layer 135. The first gate insulating layer 131 can have insulating properties and can comprise at least one silicon oxide, a silicon nitride, or a metal-based oxide. The first gate insulating layer 131 can be formed from the same material as that of the first passivation layer 133. The first gate insulating layer 131 and the first passivation layer 133 can be collectively referred to as a first gate insulating layer or as a lower gate insulating layer.

[0136] The active layer 140 is arranged on the first gate insulating layer 131, and the second gate insulating layer 132 is arranged on the active layer 140.

[0137] The second gate electrode 122 is arranged on the second gate insulating layer 132, and the interlayer dielectric layer 150 is arranged on the second gate electrode 122. The source electrode 161 and the drain electrode 162 are arranged on the interlayer dielectric layer 150.

[0138] However, another embodiment of the present disclosure is not related to the one in Fig. The configuration shown in Figure 4A is limited. According to yet another embodiment of the present disclosure, the hydrogen supply layer 135 can be arranged above the active layer 140. For example, the hydrogen supply layer 135 can be arranged in the second gate insulating layer 132, or it can be arranged in the intermediate dielectric layer 150.

[0139] Fig. Figure 4B is a cross-sectional view showing a thin-film transistor 301 according to yet another embodiment of the present disclosure. Referring to Fig. 4B The hydrogen supply layer 135 can be arranged on the second gate insulating layer 132. If the hydrogen supply layer 135 is arranged above the active layer 140 as in Fig. As described in 4B, the second active layer 142 can have an excess of hydrogen.

[0140] Fig. Figure 5A is a cross-sectional view showing a thin-film transistor according to a further embodiment of the present disclosure. The thin-film transistor 400 from Fig. 5A also features an oxygen provision layer 136, comparable to the thin-film transistor 300 from Fig. 4A.

[0141] In detail, according to yet another embodiment of the present disclosure, the thin-film transistor 400 has an oxygen supply layer 136, which is arranged between the active layer 140 and the second gate electrode 122. The oxygen supply layer 136 supplies oxygen to the active layer 140. Consequently, a second active layer 142, which contains oxygen at a concentration higher than that of the first active layer 141, can be formed. The second active layer 142 can have oxygen at a concentration higher than that of the typical oxide semiconductor layer. According to yet another embodiment of the present disclosure, the second active layer 142 is an oxygen excess layer, which has an excess of oxygen.

[0142] Fig. Figure 5B is a cross-sectional view showing a thin-film transistor according to a further embodiment of the present disclosure. The thin-film transistor 401 from Fig. 5B has a hydrogen delivery layer 135 and an oxygen delivery layer 136.

[0143] Referring to Fig. 5B The oxygen supply layer 136 can be arranged on the first passivation layer 133. The oxygen supply layer 136 can supply oxygen to the lower region of the active layer 140. Consequently, the first active layer 141 can have a higher oxygen concentration than the second active layer 142.

[0144] The first gate insulating layer 131 is arranged on the oxygen delivery layer 136, and the active layer 140 is arranged on the first gate insulating layer 131. The second gate insulating layer 132 is arranged on the active layer 140, and the second gate electrode 122 is arranged on the second gate insulating layer 132.

[0145] Referring to Fig. 5B The hydrogen supply layer 135 can be located in the second gate insulating layer 132. The hydrogen supply layer 135 can supply hydrogen to the lower region of the active layer 140. Consequently, the second active layer 142 can have a higher hydrogen concentration than the first active layer 141. The second gate insulating layer 132 can be subdivided into a lower layer 132a and an upper layer 132b based on the hydrogen supply layer 135. For example, the hydrogen supply layer 135 can be located between the lower layer 132a and the upper layer 132b of the second gate insulating layer 132.

[0146] In the thin-film transistor 401 according to a further embodiment of the present disclosure, which is in Fig. As shown in Figure 5B, the first active layer 141 can have a higher oxygen concentration than the second active layer 142, and the second active layer 142 can have a higher hydrogen concentration than the first active layer 141.

[0147] Fig. Figure 6 is a cross-sectional view showing a thin-film transistor 500 according to a further embodiment of the present disclosure.

[0148] Referring to Fig. 6 The hydrogen supply layer 135 is arranged on the first gate electrode 121. The hydrogen supply layer 135 supplies hydrogen to a predetermined region of the active layer 140. Consequently, a first region 141a1, which is provided above the hydrogen supply layer 135 of the first active layer 141, can have a higher hydrogen concentration than other regions.

[0149] In more detail, the first active layer 141 has a first region 141a1 which overlaps with the first gate electrode 121, with the first region 141a1 having a higher hydrogen concentration than the other regions of the first active layer 141.

[0150] Referring to Fig. 6. The second active layer 142 can have a second region 142a2. The second region 142a2 of the second active layer 142 overlaps the second gate electrode 122. The second region 142a2 can have an oxygen concentration that is higher than that of the other regions of the second active layer 142.

[0151] For example, according to a further embodiment of the present disclosure, the second active layer 142 can be selectively oxygen-treated to form the second region 142a2 in the second active layer 142.

[0152] Referring to Fig. 6. According to a further embodiment of the present disclosure, the thin-film transistor 500 has an oxygen supply layer 136 arranged between the second gate insulating layer 132 and the second gate electrode 122. The oxygen supply layer 136 can supply oxygen to the second active layer 142 to form the second region 142a2 in the second active layer 142. For example, oxygen and hydrogen can be concentrated at opposite corners / sides of the channel region 140a of the thin-film transistor.

[0153] Fig. 7 and Fig. Figure 8 shows cross-sectional views of a thin-film transistor according to comparative examples. The thin-film transistor described in the following section will be further detailed below. Fig. Figure 7 is shown, designated as comparative example 1, and the thin-film transistor, which is in Fig. The example shown in Figure 8 is referred to as comparative example 2.

[0154] As in Fig. As shown in Figure 7, the thin-film transistor according to comparative example 1 does not have the first gate electrode 121, but only the second gate electrode 122. The thin-film transistor shown in Fig. Figure 7 is also referred to as a thin-film transistor of a top-gate structure.

[0155] Channel 140a of the thin-film transistor, which is in Fig. As shown in Figure 7, only one gate electrode overlaps. Therefore, the thin-film transistor shown in Fig. Figure 7 shows no configuration in which part of the channel area 140a overlaps only one of the first gate electrode 121 and the second gate electrode 122, and another part of the channel area 140a overlaps only the other of the first gate electrode 121 and the second gate electrode 122.

[0156] The thin-film transistor according to comparative example 2, which is in Fig. Figure 8 shows both the first gate electrode 121 and the second gate electrode 122. The thin-film transistor, which is shown in Fig. Figure 8 is also referred to as a thin-film transistor of a double-gate structure.

[0157] In the thin-film transistor, which is in Fig. As shown in Figure 8, the entire area of ​​channel 140a overlaps the first gate electrode 121 and the second gate electrode 122. Therefore, the thin-film transistor, which is shown in Fig. Figure 8 shows no configuration in which part of the channel area 140a overlaps only one of the first gate electrode 121 and the second gate electrode 122, and another part of the channel area 140a overlaps only the other of the first gate electrode 121 and the second gate electrode 122.

[0158] The thin-film transistor, which is in Fig. 7 or Fig. The configuration shown in Figure 8 exhibits a change in the threshold voltage Vth which is greater than that of each of the thin-film transistors 100, 200, 300, 301, 400, 401 and 500 according to the embodiments of the present disclosure.

[0159] Fig. Figure 9 is a diagram representing a change in a threshold voltage Vth.

[0160] In the diagram in the middle of the diagrams, which are in Fig. Figure 9 shows a threshold voltage Vth close to 0V. On the other hand, in a diagram on the left side of the diagrams, which is shown in Fig. As shown in Figure 9, the threshold voltage is shifted towards a negative (-) voltage direction. This is illustrated in the diagram on the left side of the diagrams in Figure 9. Fig. As shown in Figure 9, if the threshold voltage is shifted in the negative (-) direction, the threshold voltage Vth is shifted in the negative (-) direction.

[0161] In a diagram on the right side of the diagrams, which are in Fig. As shown in Figure 9, the threshold voltage is shifted in a positive (+) voltage direction. This is shown in the diagram on the right side of the diagrams in Figure 9. Fig. As shown in Figure 9, if the threshold voltage is shifted in the positive (+) voltage direction, the threshold voltage Vth is shifted in the positive (+) direction.

[0162] Fig. 10A, Fig. 10B and Fig. 10C are diagrams that depict the change of a threshold voltage as a function of time. In detail, they represent Fig. 10A, Fig. 10B and Fig. 10C the results of a positive bias temperature stress test (PBTS).

[0163] PBTS stands for stress under conditions where a positive (+) bias voltage and a constant temperature are applied. When PBTS is increased, the voltage in the oxide semiconductor layer 120 or the thin-film transistor 100 is increased, which can increase the rate of change ΔVth of the threshold voltage.

[0164] In Fig. 10A is in a state where PBTS is present in the thin-film transistor according to comparison example 1, which is in Fig. As shown in Figure 7, the rate of change ΔVth of the threshold voltage Vth is measured as a function of time. Referring to Fig. 10A points out that the rate of change of the threshold voltage Vth is continuously increased over time when the PBTS is used with the thin-film transistor (comparative example 1) that is in Fig. Figure 7 is shown, and is applied. In the case of the thin-film transistor (comparative example 1), which is shown in Fig. Figure 7 shows that when the PBTS is applied, the threshold voltage Vth is continuously increased without converging to a specific value, and the rate of change ΔVth of the threshold voltage is 0.254V or so after 40,000 seconds.

[0165] In Fig. 10B, in a state that PBTS at the thin-film transistor according to comparison example 2, which is in Fig. As shown in Figure 8, when applied, the rate of change ΔVth of the threshold voltage Vth is measured as a function of time. Referring to Fig. 10B points out that the rate of change of the threshold voltage Vth is continuously increased over time when the PBTS is used in the thin-film transistor (comparative example 2), which is in Fig. Figure 8 is used. In the case of the thin-film transistor (comparative example 2), which is shown in Fig. Figure 8 shows that when the PBTS is applied, the threshold voltage Vth is continuously increased without converging to a specific value, and the rate of change ΔVth of the threshold voltage is 2.54V or so after 40,000 seconds.

[0166] The thin-film transistor according to comparison example 2, which is in Fig. Figure 8 shows that it can exhibit excellent current-on characteristics due to its double-gate structure, but it has a problem in that the rate of change ΔVth of the threshold voltage Vth increases over time.

[0167] Fig. Figure 10C is a diagram showing a threshold voltage of the thin-film transistor 300 according to a further embodiment of the present disclosure, which is described in Fig. 4A is shown. Referring to Fig. It is noted in Section 10C that the threshold voltage Vth changes only slightly, even though PBTS is applied to the thin-film transistor 300 according to a further embodiment of the present disclosure. Accordingly, the specific type of stepped double-gate configuration of the implemented invention provides a significantly more stable threshold voltage over time compared to the exemplary configurations from Fig. 7 and Fig. 8.

[0168] Hereinafter, a method for manufacturing a thin-film transistor 300 according to a further embodiment of the present disclosure is described with reference to Fig. Described in sections 11A to 11M.

[0169] Fig. Figures 11A to 11M are process views that describe a method for manufacturing a thin-film transistor 300 according to a further embodiment of the present disclosure.

[0170] Referring to Fig. 11A a buffer layer 118 is formed on a substrate 110, and a first gate electrode 121 is formed on the buffer layer 118.

[0171] Referring to Fig. 11B a first passivation layer 133 is formed on the first gate electrode 121, a hydrogen supply layer 135 is formed on the first passivation layer 133, and a first gate insulating layer 131 is formed on the hydrogen supply layer 135.

[0172] The first passivation layer 133 can be formed from an insulating material. The hydrogen supply layer 135 is a layer for supplying hydrogen to the active layer 140. The hydrogen supply layer 135 can, for example, be formed from silicon nitride (SiNx). The silicon nitride layer, which can be applied as the hydrogen supply layer 135, can contain hydrogen at a high concentration. The first gate insulating layer 131 has insulating properties.

[0173] Referring to Fig. In step 11C, an active layer 140 is formed on the first gate insulating layer 131. The active layer 140 comprises an oxide semiconductor material. The active layer 140 can be an oxide semiconductor layer. For example, the active layer 140 can comprise at least one of the following oxide semiconductor materials: IZO(InZnO), IGO(InGaO), ITO(InSnO), IGZO(InGaZnO), IGZTO(InGaZnSnO), ITZO(InSnZnO), IGTO(InGaSnO), GO(GaO), GZTO(GaZnSnO), or GZO(GaZnO).

[0174] Referring to Fig. 11D is an oxygen-treated surface of the active layer 140. The oxygen treatment, which is in Fig. Figure 11D shows that the surface of the active layer 140 can be treated with N2O gas.

[0175] Hydrogen is supplied to the active layer 140 by means of the hydrogen supply layer 135, and oxygen (O) is supplied to the surface of the active layer 140 by means of the oxygen treatment, which allows the first active layer 141 and the second active layer 142 to be formed.

[0176] Accordingly, as in Fig. Figure 11E shows the active layer 140, which comprises the first active layer 141 and the second active layer 142. The first active layer 141 can have a higher hydrogen concentration and a lower oxygen concentration than the second active layer 142. Furthermore, the second active layer 142 can have a lower hydrogen concentration and a higher oxygen concentration than the first active layer 141.

[0177] However, another embodiment of the present disclosure is not limited to the above example, and the first active layer 141 may have a lower hydrogen concentration and a higher oxygen concentration than the second active layer 142, and the second active layer 142 may have a higher hydrogen concentration and a lower oxygen concentration than the first active layer 141.

[0178] For example, the first active layer 141 and the second active layer 142 can be formed using a metal-organic chemical vapor deposition (MOCVD) process. At this stage, the hydrogen and oxygen concentrations of the first active layer 141 and the second active layer 142 can be adjusted by modifying the amount of hydrogen gas (H2) or ozone (O3) used in the MOCVD process. The first active layer 141 can have a lower hydrogen concentration and a higher oxygen concentration than the second active layer 142 by increasing the amount of ozone (O3) used in the formation of the first active layer 141 and increasing the amount of hydrogen used in the formation of the second active layer 142.

[0179] Referring to Fig. In step 11F, a second gate insulating layer 132 is formed on the active layer 140, and a second gate electrode material layer 122a is formed on the second gate insulating layer 132. The second gate electrode material layer 122a can comprise at least one of an aluminum-based metal such as aluminum (Al) or aluminum alloy, a silver-based metal such as silver (Ag) or silver alloy, a copper-based metal such as copper (Cu) or copper alloy, a molybdenum-based metal such as molybdenum (Mo) or molybdenum alloy, chromium (Cr), tantalum (Ta), neodymium (Nd), or titanium (Ti). The second gate electrode material layer 122a can have a multilayer structure comprising at least two conductive layers that differ in their respective physical properties.

[0180] Referring to Fig. In step 11G, a first photoresist pattern 190a is formed on the second gate electrode material layer 122a. The first photoresist pattern 190a can be formed by exposing and developing a photoresist.

[0181] Referring to Fig. In step 11H, the second gate electrode material layer 122a is etched using the first photoresist pattern 190a as a mask. Consequently, a second gate electrode pattern 122b is formed.

[0182] Referring to Fig. 11I The second gate insulating layer 132 can be structured by etching using the second gate electrode pattern 122b as a mask. At this point, part of the first photoresist pattern 190a is removed to form a second photoresist pattern 190b.

[0183] However, another embodiment of the present disclosure is not limited to the above example, and the second gate insulating layer 132 may not be structured.

[0184] Referring to Fig. 11J makes the active layer 140 selectively conductive. For example, a dopant can be selectively doped onto the active layer 140.

[0185] Fig. Figure 11j illustrates an example of a process in which the active layer 140 is selectively made conductive by doping.

[0186] Referring to Fig. 11J The active layer 140 can be made selectively conductive by doping using the second gate electrode pattern 122b as a mask. An area of ​​the active layer 140 that is not protected by the second gate electrode pattern 122b is made selectively conductive.

[0187] The dopant can comprise at least one of boron (B), phosphorus (P), or fluorine (F). The dopant can be doped with an ionic state. According to one embodiment of the present disclosure, conductivity can be achieved by ion doping via ion implantation.

[0188] Referring to Fig. 11K can be formed as a result of selectively conducting the active layer 140 using the second gate electrode pattern 122b as a mask, forming the first connection area 140b and the second connection area 140c. Referring to Fig. At least part of the second connection area 140c can overlap the first gate electrode 121. To ensure that the first gate electrode 121 adequately covers the first channel region a1, the first gate electrode 121 can have a larger area than the first channel region a1. Consequently, part of the first connection area 140b can overlap the first gate electrode 121. Although part of the first connection area 140b overlaps the first gate electrode 121, the first connection area 140b has been made conductive and therefore does not serve as a channel. Therefore, although there is an area where the first connection area 140b overlaps the first gate electrode 121, the driving of the thin-film transistor 300 is not affected by the overlap area.

[0189] According to one embodiment of the present disclosure, the channel region 140a of the active layer 140 is made non-conductive. The second gate electrode pattern 122b serves as a mask to protect the channel region 140a during the conductivity process.

[0190] Referring to Fig. In process 11L, the second gate electrode pattern 122b is etched using the second photoresist pattern 190b as a mask, thereby forming the second gate electrode 122. After the formation of the second gate electrode 122, the second photoresist pattern 190b is removed.

[0191] According to a further embodiment of the present disclosure, at least a part of the first gate electrode 121 does not overlap the second gate electrode 122, and at least a part of the second gate electrode 122 is formed so as not to overlap the first gate electrode 121. The first gate electrode 121 may overlap a part of the second gate electrode 122.

[0192] The channel area 140a is formed to overlap at least one of the first gate electrode 121 or the second gate electrode 122.

[0193] Additionally, at least part of the first gate electrode 121 is formed to overlap the second gate electrode 122, and at least part of the second gate electrode 122 is formed to not overlap the first gate electrode 121.

[0194] According to a further embodiment of the present disclosure, the channel area 140a is designed such that one part overlaps only one of the first gate electrode 121 and the second gate electrode 122, and another part overlaps only the other of the first gate electrode 121 and the second gate electrode 122.

[0195] Referring to Fig. In 11M, an interlayer dielectric layer 150 is formed on the second gate electrode 122, and a source electrode 161 and a drain electrode 162 are arranged on the interlayer dielectric layer 150. The source electrode 161 and the drain electrode 162 are spaced apart from each other and connected to the active layer 140.

[0196] Referring to Fig. 11M Before the source electrode 161 and the drain electrode 162 are formed, a contact hole can be formed in the interlayer dielectric layer 150. The source electrode 161 is connected to the first connection area 140b through the contact hole formed in the interlayer dielectric layer 150, and the drain electrode 162 is connected to the second connection area 140c through another contact hole formed in the interlayer dielectric layer 150.

[0197] The thin-film transistors 100, 200, 300, 301, 400, 401 and 500 according to the embodiments of the present disclosure can be usefully applied to the display device. In particular, the thin-film transistors 100, 200, 300, 301, 400, 401 and 500 according to the embodiments of the present disclosure can be usefully applied to an outdoor display device that is operated in an ON state for a long time, or to a display device using a micro-LED.

[0198] Fig. 12 is a schematic view representing a display device 600 according to a further embodiment of the present disclosure.

[0199] The display device 600 according to a further embodiment of the present disclosure, as in Fig. Figure 12 shows a display panel 310, a gate driver 320, a data driver 330 and a controller 340.

[0200] The display panel 310 has gate lines GL, data lines DL, and pixel P, which are arranged in intersection areas between the gate lines GL and the data lines DL. Pixel P has a display element 710 and a pixel driver circuit PDC for driving the display element 710. An image is displayed on the display panel 310 by driving pixel P.

[0201] The controller 340 controls the gate driver 320 and the data driver 330.

[0202] The controller 340 outputs a gate control signal (GCS) to control the gate driver 320 and a data control signal (DCS) to control the data driver 330 by using a synchronization signal and a timer signal provided by an external system (not shown). Furthermore, the controller 340 samples input image data from the external system, aligns the sampled data, and provides the aligned RGB digital image data to the data driver 330.

[0203] The gate control signal GCS provides a gate start pulse GSP, a gate shift time signal GSC, a gate output enable signal GOE, a start signal Vst, and a gate time signal GCLK. Furthermore, control signals for controlling a shift register 350 can be included in the gate control signal GCS.

[0204] The data control signal DCS includes a source start pulse SSP, a source shift time signal SSC, a source output enable signal SOE, and a polarity check signal POL.

[0205] The data driver 330 provides a data voltage to the data lines DL of the display panel 310. Specifically, the data driver 330 converts the RGB image data input by the controller 340 into an analog data voltage and provides a data voltage from one horizontal line to the data lines DL for each first horizontal period, with a gate pulse being provided to the gate line GL.

[0206] The gate driver 320 can have a shift register 350.

[0207] The shift register 350 provides successive gate pulses to the gate lines GL for a frame by using the start signal and the gate time signal, which are transmitted by the controller 340. In this case, a frame represents a time interval when an image is output via the display panel 310. The gate pulse has a turn-on voltage that can switch on a switching element (thin-film transistor) located in the pixel P.

[0208] Furthermore, the shift register 350 provides a gate-off signal, capable of switching off a switching element, to the gate lines GL for the other period of a frame in which the gate pulse is not provided. Hereinafter, the gate pulse and the gate-off signal are collectively referred to as the scan signal SS or scan.

[0209] According to one embodiment of the present disclosure, the gate driver 320 can be packaged on the substrate 310. In this way, a structure in which the gate driver 320 is directly packaged on the substrate 310 can be referred to as a Gate In Panel (GIP) structure. The gate driver 320 can incorporate at least one of the thin-film transistors 100, 200, 300, 301, 400, 401 or 500 described in Fig. shown in 1 and 3 to 6.

[0210] Fig. 13 is a circuit view that selects any pixel P from Fig. 12 represents.

[0211] The circuit diagram from Fig. Figure 13 is an equivalent circuit representation for a pixel P of a display device 600, which has an organic light-emitting diode (OLED) as a display element 710. The pixel P has a display element 710 and a pixel driver circuit PDC for driving the display element 710.

[0212] The pixel driver circuit PDC from Fig. 13 features a first thin-film transistor TR1, which is a switching transistor, and a second thin-film transistor TR2, which is a driver transistor. Each of the thin-film transistors 100, 200, 300, 301, 400, 401 and 500, which are in Fig. 1 and 3 to 6 can be used as the first thin-film transistor TR1 or the second thin-film transistor TR2.

[0213] The first thin-film transistor TR1 is connected to the gate line GL and the data line DL and is switched on or off by means of the scan signal SS, which is provided by the gate line GL.

[0214] The data line DL provides a data voltage Vdata to the pixel driver circuit PDC, and the first thin-film transistor TR1 controls the application of the data voltage Vdata.

[0215] A driver power line PL provides a driver voltage Vdd to the display element 710, and the second thin-film transistor TR2 controls the driver voltage Vdd. The driver voltage Vdd is a pixel driver voltage for driving the organic light-emitting diode (OLED), i.e., the display element 710.

[0216] When the first thin-film transistor TR1 is switched on by the scan signal SS, which is applied by the gate driver 320 via the gate line GL, the data voltage Vdata, supplied via the data line DL, is applied to a gate electrode of the second thin-film transistor TR2, which is connected to the display element 710. The data voltage Vdata is charged into a first capacitor C1, which is formed between the gate electrode and a source electrode of the second thin-film transistor TR2. The first capacitor C1 is a storage capacitor Cst.

[0217] The amount of current supplied to the organic light-emitting diode (OLED), which is the display element 710, by the second thin-film transistor TR2 is controlled depending on the data voltage Vdata, thereby controlling a gray level of light emitted by the display element 710.

[0218] Fig. Figure 14 is a circuit view representing a pixel P of a display device 700 according to yet another embodiment of the present disclosure.

[0219] The Pixel P of the Display Device 700, which is in Fig. Figure 14 shows an organic light-emitting diode (OLED), which is a display element 710, and a pixel driver circuit (PDC) for driving the display element 710. The display element 710 is connected to the pixel driver circuit (PDC).

[0220] In the pixel P, signal lines DL, GL, PL, RL and SCL are arranged to provide a signal to the pixel driver circuit PDC.

[0221] The data voltage Vdata is provided to the data line DL, the scan signal SS is provided to the gate line GL, the driver voltage Vdd to drive the pixel is provided to the driver power line PL, a reference voltage Vref is provided to a reference line RL, and a measurement control signal SCS is provided to a measurement control line SCL.

[0222] Referring to Fig. 14, assuming that a gate line of an nth pixel P “GL n “ is, is a gate line of an (n-1)th pixel P that is adjacent to the n-th pixel P, “GL n-1 “, and the gate management “GL” n-1 “ of the (n-1)th pixel P serves as a measurement control line SCL of the n-th pixel P.

[0223] The pixel driver circuit PDC, for example, has a first thin-film transistor TR1 (switching transistor) connected to the gate line GL and the data line DL, a second thin-film transistor TR2 (driver transistor) for controlling the strength of a current output to the display element 710 according to the data voltage Vdata transmitted through the first thin-film transistor TR1, and a third thin-film transistor TR3 (reference transistor) for detecting characteristics of the second thin-film transistor TR2.

[0224] A first capacitor C1 is arranged between a gate electrode of the second thin-film transistor TR2 and the display element 710. The first capacitor C1 is referred to as its storage capacitor Cst.

[0225] The first thin-film transistor TR1 is switched on by means of the scan signal SS, which is provided to the gate line GL to transmit the data voltage Vdata, which is provided to the data line DL, to the gate electrode G2 of the second thin-film transistor TR2.

[0226] The third thin-film transistor TR3 is connected to a first node n1 between the second thin-film transistor TR2 and the display element 710 and the reference line RL, and is accordingly switched on or off by means of the measurement control signal SCS, and detects properties of the second thin-film transistor TR2, which is a driver transistor, during a measurement period.

[0227] A second node n2, connected to the gate electrode of the second thin-film transistor TR2, is connected to the first thin-film transistor TR1. The first capacitor C1 is formed between the second node n2 and the first node n1.

[0228] When the first thin-film transistor TR1 is switched on, the data voltage Vdata, supplied via the data line DL, is applied to the gate electrode of the second thin-film transistor TR2. The data voltage Vdata is then charged in the first capacitor C1, which is connected between the gate and source electrodes of the second thin-film transistor TR2.

[0229] When the second thin-film transistor TR2 is switched on, the current to the display element 710 is supplied by the second thin-film transistor TR2 according to the driver voltage Vdd to drive the pixel, causing light to be emitted from the display element 710.

[0230] At least one of the first thin-film transistor TR1, the second thin-film transistor TR2 or the third thin-film transistor TR3 from Fig. 14 can have the same structure as one of the thin-film transistors 100, 200, 300, 301, 400, 401 and 500, which are in Fig. 1 and 3 to 6 are shown.

[0231] Fig. Figure 15 is a circuit view representing an arbitrary pixel P of a display device 800 according to a further embodiment of the present disclosure.

[0232] The Pixel P of the Display Device 800, which is in Fig. Figure 15 shows an organic light-emitting diode (OLED), which is a display element 710, and a pixel driver circuit (PDC) for driving the display element 710. The display element 710 is connected to the pixel driver circuit (PDC).

[0233] The pixel driver circuit PDC features thin-film transistors TR1, TR2, TR3 and TR4.

[0234] In the pixel P, signal lines DL, EL, GL, PL, SCL and RL are arranged to provide a driver signal to the pixel driver circuit PDC.

[0235] Compared to the Pixel P from Fig. 14 indicates the pixel P Fig. 15. Furthermore, an emission control line EL is provided. An emission control signal EM is supplied to the emission control line EL.

[0236] Furthermore, the pixel driver circuit features PDC. Fig. 15 additionally a fourth thin-film transistor TR4, which is an emission control transistor for controlling a light emission timing control of the second thin-film transistor TR2 compared to the pixel driver circuit PDC from Fig. 14.

[0237] Referring to Fig. 15, assuming that a gate line of an nth pixel P “GL n “ is, is a gate line of an (n-1)th pixel P that is adjacent to the n-th pixel P, “GL n-1 “, and the gate management “GL” n-1 “ of the (n-1)th pixel P serves as a measurement control line SCL of the n-th pixel P.

[0238] A first capacitor C1 is arranged between a gate electrode of the second thin-film transistor TR2 and the display element 710. A second capacitor C2 is arranged between one of the terminals of the fourth thin-film transistor TR4, to which a driver voltage Vdd is supplied, and an electrode of the display element 710.

[0239] The first thin-film transistor TR1 is switched on by means of the scan signal SS, which is provided to the gate line GL to transmit the data voltage Vdata, which is provided to the data line DL, to the gate electrode of the second thin-film transistor TR2.

[0240] The third thin-film transistor TR3 is connected to the reference line RL and is accordingly switched on or off by means of the detection control signal SCS, and detects properties of the second thin-film transistor TR2, which is a driver transistor, during a measurement period.

[0241] The fourth thin-film transistor, TR4, either transmits the driver voltage Vdd to the second thin-film transistor, TR2, according to the emission control signal EM, or shields the driver voltage Vdd. When the fourth thin-film transistor is switched on, a current is supplied to the second thin-film transistor, TR2, causing light to be emitted by the display element 710.

[0242] At least one of the first thin-film transistor TR1, the second thin-film transistor TR2, the third thin-film transistor TR3 or the fourth thin-film transistor TR4 from Fig. 15 can have the same structure as one of the thin-film transistors 100, 200, 300, 301, 400, 401 and 500, which are in Fig. 1 and 3 to 6 are shown.

[0243] The pixel driver circuit (PDC) according to a further embodiment of the present disclosure can be formed as different structures in addition to the structures described above. The pixel driver circuit (PDC) can, for example, comprise five or more thin-film transistors.

[0244] Fig. Figure 16 is a circuit view representing a pixel P of a display device 900 according to a further embodiment of the present disclosure.

[0245] The display device 900 from Fig. 16 is a liquid crystal display device.

[0246] The Pixel P of the Display Device 900, which is in Fig. Figure 16 shows a pixel driver circuit (PDC) and a liquid crystal capacitor (Clc) connected to the PDC. The liquid crystal capacitor (Clc) corresponds to a display element.

[0247] The pixel driver circuit (PDC) comprises a thin-film transistor (TR) connected to the gate line (GL) and the data line (DL), and a storage capacitor (Cst) connected between the thin-film transistor (TR) and a common electrode (372). The liquid crystal capacitor (Clc) is connected in parallel with the storage capacitor (Cst) between a pixel electrode (371) connected to the thin-film transistor (TR) and the common electrode (372).

[0248] The liquid crystal capacitor Clc charges a differential voltage between a data signal supplied to a pixel electrode by the thin-film transistor TR and a common voltage Vcom supplied to the common electrode 372, and controls the amount of light transmittance by driving liquid crystals according to the charged voltage. The storage capacitor Cst stabilizes the voltage charged into the liquid crystal capacitor Clc.

[0249] The display device 900 according to a further embodiment of the present disclosure can incorporate at least one of the thin-film transistors 100, 200, 300, 301, 400, 401 or 500, which are described in Fig. 1, Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are shown.

[0250] According to the present disclosure, the following beneficial effects can be achieved.

[0251] Since the thin-film transistor according to one embodiment of the present disclosure has in each channel area a region influenced by a top gate and a region influenced by a bottom gate, the rate of change of the threshold voltage is small, thereby achieving driver stability.

[0252] The thin-film transistor according to one embodiment of the present disclosure has a channel region comprising an oxygen excess region and a hydrogen excess region. A movement of the threshold voltage in the positive (+) direction is induced in the oxygen excess region by means of an electron trap, and a movement of the threshold voltage in the negative (-) direction is induced in the hydrogen excess region by means of a hole trap. In the thin-film transistor according to one embodiment of the present disclosure, the oxygen excess region for moving the threshold voltage in the positive (+) direction and the hydrogen excess region for moving the threshold voltage in the negative (-) direction are connected in series, thereby reducing the rate of change of the threshold voltage of the thin-film transistor and improving driver stability.In particular, according to an embodiment of the present disclosure, the thin-film transistor can be operated stably without changing the threshold voltage, even in the case that the thin-film transistor is operated in an ON state for a long time.

[0253] The thin-film transistor according to one embodiment of the present disclosure can be arranged in various electronic devices, and when the thin-film transistor according to one embodiment of the present disclosure is used, the driver stability of the electronic device can be improved. The thin-film transistor according to one embodiment of the present disclosure can be usefully applied in the display device, and can be used in particular in an outdoor display device that is operated in an ON state for a long time, and in a display device that uses a micro-LED.

Claims

[1] A thin film transistor (100, 200, 300, 301, 400, 401, 500), comprising: a first gate electrode (121) forming a lower electrode; an active layer (140) spaced from the first gate electrode (121) having a channel region (140a); and a second gate electrode (122) which is spaced from the active layer (140) and is arranged on a side opposite the first gate electrode (121) with respect to an active layer (140), wherein at least a part of the first gate electrode (121) does not overlap the second gate electrode (122) and at least a part of the second gate electrode (122) does not overlap the first gate electrode (121), the channel region (140a) overlaps at least one of the first gate electrode (121) and the second gate electrode (122), a part of the channel region (140a) overlaps only one of the first gate electrode (121) and the second gate electrode (122) and another part of the channel region (140a) overlaps only the other of the first gate electrode (121) and the second gate electrode (122), the active layer (140) comprises: a first active layer (141) facing the first gate electrode (121) and comprising an oxide semiconductor material; and a second active layer (142) disposed on the first active layer (141) and comprising an oxide semiconductor material, and wherein the first active layer (141) has a higher hydrogen concentration and a lower oxygen concentration than the second active layer (142). [2] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to claim 1, wherein the channel region (140a) comprises: a first channel region (a1) overlapping the first gate electrode (121) and not overlapping the second gate electrode (122); and a second channel region (a2) overlapping the second gate electrode (122) and not overlapping the first gate electrode (121). [3] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to claim 2, wherein the first channel region (a1) is arranged at one end of the channel region (140a), and the second channel region (a2) is arranged at the other end of the channel region (140a). [4] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to claim 2 or 3, wherein the active layer (140) has a first connection region (140b) and a second connection region (140c) which are separated from each other and are each connected to the channel region (140a). [5] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to claim 4, wherein the first connection region (140b) is in contact with the first channel region (a1), and the second connection region (140c) is in contact with the second channel region (a2). [6] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to claim 5, wherein the first connection region (140b) does not overlap the second gate electrode (122), and the second connection region (140c) does not overlap the first gate electrode (121). [7] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to claim 5 or 6, wherein at least a part of the first connection region (140b) overlaps the first gate electrode (121). [8] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to any one of claims 1 to 7, wherein a part of the first gate electrode (121) and a part of the second gate electrode (122) overlap each other. [9] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to any one of claims 1 to 8, wherein a part of the channel region (140a) overlaps both the first gate electrode (121) and the second gate electrode (122). [10] The thin film transistor (300, 400) according to any one of claims 1 to 9, further comprising a hydrogen supply layer (135) disposed between the first gate electrode (121) and the active layer (140). [11] The thin film transistor (400, 500) according to any one of claims 1 to 10, further comprising an oxygen supply layer (136) disposed between the active layer (140) and the second gate electrode (122). [12] The thin film transistor (100, 200, 300, 301, 400, 401, 500) according to any one of claims 1 to 11, wherein the first active layer (141) and the second active layer (142) have the same metal composition. [13] The thin film transistor (301, 401) according to any one of claims 1 to 12, further comprising a hydrogen supply layer (135) on the active layer (140). [14] The thin film transistor (500) according to any one of claims 1 to 13, wherein the first active layer (141) has a first region (141a1) overlapped with the first gate electrode (121), and the first region (141a1) has a hydrogen concentration higher than that of the other region of the first active layer (141). [15] The thin film transistor (500) according to any one of claims 1 to 14, wherein the second active layer (142) has a second region (142a2) overlapped with the second gate electrode (122), and the second region (142a2) has an oxygen concentration higher than that of the other region of the second active layer (142). [16] A display device (600, 700, 800, 900) comprising the thin film transistor (100, 200, 300, 301, 400, 401, 500) according to any one of claims 1 to 15. [17] A method of manufacturing a thin film transistor (100, 200, 300, 301, 400, 401, 500), the method comprising: Forming a first gate electrode (121) on a substrate (110); Forming a first gate insulating layer (131) on the first gate electrode (121); Forming an active layer (140) on the first gate insulating layer (131); and Forming a second gate electrode (122) on the active layer (140), wherein at least a part of the first gate electrode (121) does not overlap the second gate electrode (122) and at least a part of the second gate electrode (122) does not overlap the first gate electrode (121), the active layer (140) has a channel region (140a), and the channel region (140a) overlaps at least one of the first gate electrode (121) and the second gate electrode (122), the active layer (140) comprises a first active layer (141) facing the first gate electrode (121) and a second active layer (142) on the first active layer (141), and the first active layer (141) has a higher hydrogen concentration and a lower oxygen concentration than the second active layer (142). [18] The method according to claim 17, wherein a part of the first gate electrode (121) and a part of the second gate electrode (122) overlap each other. [19] The method according to claim 17 or 18, further comprising forming a hydrogen supply layer (135) before forming the first gate insulating layer (131). [20] The method according to any one of claims 17 to 19, further comprising oxygen treating a surface of the active layer (140). [21] The method of claim 20, wherein the oxygen treatment comprises treating the surface of the active layer (140) with N2O gas. [22] The method according to any one of claims 17 to 21, wherein forming the second gate electrode (122) comprises forming a second gate electrode pattern (122b). [23] The method of claim 22, further comprising making the active layer (140) conductive using the second gate electrode pattern (122b) as a mask. [24] A method of manufacturing a thin film transistor (100, 200, 300, 301, 400, 401, 500), the method comprising: Forming a first gate electrode (121) on a substrate (110); Forming a first gate insulating layer (131) on the first gate electrode (121); Forming an active layer (140) on the first gate insulating layer (131); Forming a second gate electrode (122) on the active layer (140), wherein forming the second gate electrode (122) comprises forming a second gate electrode pattern (122b); and Making the active layer (140) conductive using the second gate electrode pattern (122b) as a mask; wherein at least a part of the first gate electrode (121) does not overlap the second gate electrode (122) and at least a part of the second gate electrode (122) does not overlap the first gate electrode (121), the active layer (140) has a channel region (140a), and the channel region (140a) overlaps at least one of the first gate electrode (121) and the second gate electrode (122), the active layer (140) comprises a first active layer (141) facing the first gate electrode (121) and a second active layer (142) on the first active layer (141), and the first active layer (141) has a higher hydrogen concentration and a lower oxygen concentration than the second active layer (142).

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