STORAGE ARRANGEMENT AND METHOD FOR MAKING THIS ARRANGEMENT

Abstract

Integrated circuit device (100A) comprising the following: a memory cell (101A) comprising: a channel (111A) extending between a source (117A) and a drain (113A), a gate electrode (105A), a ferroelectric layer (107A) arranged between the gate electrode (105A) and the channel (111A), which is chlorine-free and formed by atomic layer deposition using chlorine-free precursor substances, and a dielectric layer (109A) arranged between the ferroelectric layer (107A) and the channel (111A); wherein the storage cell (101A) has a leakage current and a TDDB rate, the TDDB rate being defined as an initial value of the leakage current divided by an operating time over which the leakage current doubles compared to the initial value; and where the TDDB rate is less than the amount by which the TDDB rate would increase if 1 PPM of chlorine were added to the ferroelectric layer (107A), wherein the dielectric layer (109A) has a thickness of 0.1 to 10 nm, preferably 0.3 to 3 nm; wherein the ferroelectric layer Hf x Zr 1-x O2 has, where 0 ≤ x ≤ 1.

Description

BACKGROUND

[0001] Many modern electronic devices contain electronic memory. Electronic memory can be volatile or non-volatile. Non-volatile memory retains its stored data even without a power supply, while volatile memory loses its stored data when the power fails. Dynamic random-access memory (DRAM), which requires frequent updates, is a type of volatile memory. Examples of non-volatile electronic memory include resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and others.

[0002] US 7 833 913 B2 describes a method for the production of crystallographically stabilized, doped hafnium-zirconium-based thin films by atomic layer deposition (ALD / PEALD).

[0003] US 2015 / 0340372A1 discloses methods for the fabrication and structure of ferroelectric memory cells, wherein the ferroelectric material used is either doped dielectrics such as hafnium oxide, zirconium oxide, titanium oxide and mixtures thereof, or alternative materials with polar and chiral crystal structure without inversion symmetry.

[0004] WO 2019 / 188 249 A1 describes semiconductor devices and manufacturing processes for ferroelectric storage devices in which doped hafnium oxide thin films with a stabilized orthorhombic phase are used as the ferroelectric material.

[0005] US 2020 / 0 035 493 A1 describes a method for the production of crystallographically stabilized ferroelectric films based on hafnium zirconium for semiconductor devices.

[0006] US 8 568 530 B2 describes a method for manufacturing an integrated circuit device in which a ferroelectric layer is produced using precursors suitable for chemical vapor deposition, in particular atomic layer deposition, of hafnium oxide and zirconium oxide.

[0007] US 6 921 702 B2 relates to a dielectric layer made of HfO2 / ZrO2 nanolaminates and a manufacturing process for it, in which HfO2 and then ZrO2 are deposited first by atomic layer deposition to produce a reliable gate dielectric with a particularly thin equivalent oxide layer thickness, which is thinner than achievable with conventional SiO2.

[0008] US 7 217 643 B2 discloses semiconductor structures and methods for manufacturing them, wherein these are a stacked dielectric structure with amorphous layers of hafnium zirconium oxide and an intermediate layer, wherein the entire structure has a particularly high dielectric constant, which is at least equal to that of HfZrO4.

[0009] CN 1 08 470 773 A discloses a ferroelectric thin-film transistor and its manufacturing process, which enables high storage density, good miniaturization and broad applicability, thus overcoming the technical disadvantages of conventional ferroelectric thin-film transistors.

[0010] SHI, X. [et al.]: Development of ALD HfZrOx with TDEAH / TDEAZ and H2O. In: J. Electrochem. Soc., Vol. 158, 2011, No. 1, H69-H74, describes the development of an ALD process for the production of HfZrO. x-Nanolaminates as gate dielectric for CMOS transistors (complementary metal-oxide-semiconductor transistors), using TDEA-based precursors and H2O.

[0011] LUO, Q. [et al.]: Composition-dependent ferroelectric properties in sputtered HfXZr1-XO2 thin films. In: IEEE Electron Device Letters, Vol. 40, 2019, No. 4, pp. 570-573, describes the fabrication of ferroelectric HfXZr1-XO2 thin films. 1-X O2 thin films using sputtering technology.

[0012] XIAO, W. [et al.]: Performance improvement of Hf0.5Zr0.5O2-based ferroelectric-field-effect transistors with ZrO2 seed layers. In: IEEE Electron Device Letters, Vol. 40, 2019, No. 5, pp. 714-717, discloses a ferroelectric field-effect transistor in which the ferroelectric Hf 0,5 Zr 0,5 An O2-based layer is formed using a ZrO2 seed layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for the sake of clarity of discussion. Fig. Figure 1A shows a side cross-sectional view of an integrated circuit device according to some aspects of the present teaching. Fig. Figure 1B shows a side cross-sectional view of an integrated circuit device according to some other aspects of the present teaching. Fig. Figure 2 shows a side cross-sectional view of an integrated circuit device according to some other aspects of the present teaching. Fig. Figures 3-6 are a series of cross-sectional representations illustrating a method for manufacturing a device such as the device made of Fig. Illustrate 1A. Fig. Figure 7 shows a flowchart illustrating a method for manufacturing an integrated circuit device with a ferroelectric layer according to the present teaching. DETAILED DESCRIPTION

[0014] The present disclosure provides many different embodiments or examples of the implementation of various features of this disclosure. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, only examples and are not intended to be limiting. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features do not have to be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself represent a relationship between the various designs and / or configurations discussed.

[0015] Furthermore, to simplify the description, spatially relative terms such as "under," "below," "below," "above," "above," and the like can be used to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative terms used here can be interpreted accordingly.

[0016] Many integrated circuit devices incorporate layers of ferroelectric material. For example, certain storage devices use a ferroelectric layer as a data storage layer. In some of these storage devices, the ferroelectric layer stores data by maintaining a polarization of electric dipoles. A first orientation of these electric dipoles can represent a logic "1," and a second orientation a logic "0." There are various storage structures in which ferroelectric material can be used. In some embodiments of a ferroelectric memory, the ferroelectric layer is located between two plates in a capacitor that stores data. A 1T-1C memory architecture, for example, can use ferroelectric capacitors.In other embodiments of a ferroelectric memory, the ferroelectric layer is located between a gate electrode and a channel in a transistor structure that stores data. A ferroelectric field-effect transistor (FeFET) is one example. Regardless of the structure in which the ferroelectric layer is located, it is desirable for the device to have a long lifetime and high reliability. One mechanism that can limit lifetime is time-dependent dielectric breakdown (TDDB) in the ferroelectric layer. Although the mechanisms of TDDB are not fully understood, it can be observed that leakage current through the ferroelectric layer increases over extended operating times. One mechanism that can limit reliability is bias temperature instability (BTI), such as...Positive bias temperature instability (PBTI) and negative bias temperature instability (NBTI). BTI can refer to charge trapping in a ferroelectric layer and manifests as a threshold voltage fluctuation of a device containing the ferroelectric layer over a period of continuous operation.

[0017] The inventors of the present disclosure have found that TDDB and BTI can be mitigated by removing chlorine residues from ferroelectric layers. They have found that even 1 ppm of chlorine can lead to TDDB / BTI and that TDDB / BTI can be substantially mitigated by producing ferroelectric materials with less than 1 ppm of chlorine. This phenomenon was observed particularly in ferroelectric materials containing the compound Hf x Zr 1-xO2 was observed. It is expected that this result can also be applied to other ferroelectric materials. In the formula, x has a value range from 0 to 1. Examples according to the formula include HfO2, HfZrO2, and ZrO2.

[0018] Ferroelectric layers are conventionally produced by atomic layer deposition (ALD) using metal chloride precursors. The performance of a ferroelectric layer is strongly influenced by its thickness. ALD allows for precise control of the layer thickness. Metal chloride precursors have volatilities and reaction rates that are well suited for the ALD process. However, in accordance with some embodiments of the present disclosure, the ferroelectric layer is produced from precursors containing chlorine-free metal compounds. The use of precursors that are chlorine-free metal compounds can eliminate chlorine residues.

[0019] In some embodiments, the precursors comprise metal compounds in which the metal is directly bonded to oxygen, nitrogen, carbon, or a combination thereof. In some embodiments, the precursors comprise a metal compound in which the metal is directly bonded to carbon. In some embodiments, the precursors comprise a metal compound in which the metal is directly bonded to oxygen. In some embodiments, the precursors comprise a metal compound in which the metal is directly bonded exclusively to oxygen and / or carbon. In some embodiments, the precursors comprise a metal compound in which the metal is directly bonded to nitrogen. In some embodiments, the precursors comprise a metal compound in which the metal is directly and exclusively bonded to nitrogen. Excellent results have been achieved with precursors of the form M(NR 1 R 2)4 achieved, where M is zirconium (Zr), hafnium (Hf) or the like and R 1 and R 2 These are organic functional groups. In some embodiments, the organic functional groups are alkanes, alkenes, alkynes, alcohols, amines, ethers, aldehydes, ketones, carboxylic acids, esters, amides, or the like. In some embodiments, the precursors include one or more of: Zirconium(IV) tert-butoxide (Zr[OC(CH3)3]4 or ZTB); Bis(methyl-η5-cyclopentadienyl)methoxymethylzirconium (Zr[CH3C5H4]2CH3OCH3, ZRCMMM, or ZrD-CO4); Tetrakis(dimethylamino)zirconium(IV) (Zr[N(CH3)2]4 or TDMAZ); Tetrakis(ethylmethylamido)zirconium(IV) (Zr[N(CH3)(C2H3)]4 or TEMAZ); Bis(methyl-η5-cyclopentadienyl)dimethylhafnium (Hf[CH3C5H4]2CH3OCH3, HFCMME, or HfD-CO2); Bis(methyl-η5-clyclopentadienyl)methoxymethylhafnium (HfCH3OCH3[C5H4]2 or HfD-CO4); tetrakis(dimethylamino)hafnium(IV) (Hf[N(CH3)2]4 or TDMAH); Tetrakis(ethylmethylamido)hafnium(IV) (Hf[N(CH3)(C2H5)]4 or TEMAH); or the like.

[0020] The ferroelectric layer can be incorporated into any type of integrated circuit device. In some embodiments, the ferroelectric layer is contained within a memory cell of a storage device. The storage device can be of any type. In some embodiments, the ferroelectric storage device contains the ferroelectric layer within a transistor structure. In some embodiments, the transistor has a bottom gate. In some embodiments, the transistor has an top gate. In some embodiments, the transistor is arranged in a three-dimensional (3D) storage array. In some embodiments, the transistor has a metal-ferroelectric-semiconductor (MFS) structure. In some embodiments, the transistor has a metal-ferroelectric-insulator-semiconductor (MFIS) structure. In some embodiments, the ferroelectric storage device contains the ferroelectric layer within a capacitor structure.In some embodiments, the memory is a ferroelectric random-access memory (FeRAM) in which the ferroelectric capacitor is coupled to a drain region of a field-effect transistor (FET). In some embodiments, the memory has a metal-ferroelectric-metal-insulator-semiconductor (MFMIS) structure in which the ferroelectric capacitor is coupled to the gate of a FET.

[0021] A ferroelectric storage cell according to the present teaching exhibits a lower time-dependent dielectric breakdown rate (TDDB rate) and a lower BTI rate compared to an equivalent ferroelectric storage cell with only 1 ppm more chlorine in the ferroelectric layer. TDDB rates cannot be well characterized over short operating periods, but they can be consistently determined when considered over a longer operating period, such as a period during which the leakage current doubles or a period during which the Weibull slope decreases. Accordingly, the TDDB rate can be defined for use in comparisons as the initial leakage current divided by an operating time during which the initial leakage current doubles. Alternatively, the TDDB rate can be determined over a period during which the Weibull slope decreases.

[0022] The ferroelectric layer of a ferroelectric storage cell according to the present disclosure is formed with chlorine-free precursors. The ferroelectric layer of a ferroelectric reference storage cell can be formed by adding some chloride precursors to the process gas mixture. The ferroelectric reference storage cell will have a higher TDDB rate than the ferroelectric storage cell according to the present teaching. In some embodiments, the TDDB rate is half that of or less than that of a reference storage cell that has 1 ppm more chlorine in the ferroelectric layer. In some embodiments, the BTI rate, defined as the rate at which the threshold voltage changes during continuous operation, is half that of or less than that of the reference storage cell.

[0023] According to the present invention, a device according to the present teaching has a ferroelectric layer comprising an HfZrO layer according to the formula Hf x Zr 1-x O2 is where x lies in the range from 0 to 1. In some embodiments, the ferroelectric layer is Hf. x Zr 1-x O2 where x is in the range of 0.1 to 0.9. In some embodiments, the ferroelectric layer is 107A Hf 0,5 Zf 0,5O2. In some embodiments, the ferroelectric layer HfZrO has a combined t-phase (tetragonal), o-phase (orthorhombic), and c-phase (cubic) of more than 50% and an m-phase (monoclinic) of less than 50%. In some embodiments, the HfZrO is doped with smaller-radius ions that increase 2Pr. Smaller-radius ions include ions of aluminum (Al), silicon (Si), and the like. In some embodiments, the HfZrO is doped with larger-radius ions that increase 2Pr. Larger-radius ions include ions of lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), and the like. 2Pr is a measure of the switching polarization of a ferroelectric material. According to the present invention, the ferroelectric layer is chlorine-free. In some embodiments, the ferroelectric layer has oxygen gaps.

[0024] Fig. Figure 1A shows an integrated circuit device 100A with a memory cell 101A according to some aspects of the present teaching. The memory cell 101A comprises a ferroelectric layer 107A in a transistor structure. The transistor structure comprises the ferroelectric layer 107A, a channel layer 111A, a gate electrode 105A, a source coupling 117A, and a drain coupling 113A. The ferroelectric layer 107A is arranged between the channel layer 111A and the gate electrode 105A. Optionally, the ferroelectric layer 107A and the channel layer 111A are separated by a dielectric layer 109A. The gate electrode 105A is arranged below the ferroelectric layer 107A. Accordingly, the gate electrode 105A is a bottom gate. The gate electrode 105A can be buried in a substrate 103A.The source coupling 117A and the drain coupling 113A can be vias in an interlevel dielectric 115A and can be connected to a metal compound structure formed over the substrate 103A.

[0025] The ferroelectric layer 107A contains no chlorine residues. In some embodiments, the ferroelectric layer 107A is HfZrO and is chlorine-free. In some embodiments, the ferroelectric layer 107A is aluminum nitride (AlN) doped with scandium (Sc) or the like. Alternatively, the ferroelectric layer 107A can be another ferroelectric material containing no chlorine at all. Examples of other ferroelectric materials that may be used include, but are not limited to, hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), hafnium zirconium oxide (HfZrO), hafnium cerium oxide (HfCeO), hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium gadolinium oxide (HfGdO), or the like.

[0026] In some embodiments, the ferroelectric layer 107A is between 0.1 nm and 100 nm thick. In other embodiments, the ferroelectric layer 107A is between 1 nm and 30 nm thick. If the ferroelectric layer 107A is too thin, it may not provide sufficient threshold voltage switching in the memory cell 101A. If the ferroelectric layer 107A is too thick, it may not have the desired concentration of oxygen vacancies.

[0027] The dielectric layer 109A, if present, can be an insulating layer or a barrier layer. According to the present invention, the dielectric layer 109A has a thickness in the range of 0.1 nm to 10 nm. In some embodiments, the dielectric layer 109A has a thickness in the range of 0.3 nm to 3 nm. If the dielectric layer 109A is too thin, it may not function. If the dielectric layer 109A is too thick, it may impair the operation of the memory cell 101A. The dielectric layer 109A can consist of silicon (Si), magnesium (Mg), aluminum (Al), yttrium (Y), lanthanum (La), strontium (Sr), gadolinium (Gd), scandium (Sc), calcium (Ca), a compound thereof, a combination thereof, or the like. In some embodiments, the dielectric layer 109A contains hafnium oxide (HfO2).In some embodiments, the dielectric layer 109A contains hafnium oxide (HfO2) and silicon (Si), wherein the atomic ratio of silicon is 10% or more.

[0028] Channel layer 111A can be or comprise a semiconductor. In some embodiments, channel layer 111A is or comprises an oxide semiconductor. Oxide semiconductors suitable for channel layer 111A include, but are not limited to, zinc oxide (ZnO), magnesium oxide (MgO), gadolinium (GdO), indium tungsten oxide (InWO), indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium zinc tin oxide (InGaZnSnO or IGZTO), indium tin oxide (InSnO or ITO), combinations thereof, or the like. In some embodiments, channel layer 111A is or comprises polysilicon, amorphous silicon, silicon geranium (SiGe), or the like. In some embodiments, the channel layer 111A has a thickness in the range of 0.1 nm to 100 nm. In some embodiments, the channel layer 111A has a thickness in the range of 2 nm to 30 nm.In some embodiments, the channel layer 111A has a thickness in the range of 5 nm to 20 nm.

[0029] The source coupling 117A, the drain coupling 113A, and the gate electrode 105A can be formed from any suitable conductive material. Suitable conductive materials can include doped polysilicon, graphene, metals, and the like. In some embodiments, the source coupling 117A, the drain coupling 113A, and the gate electrode 105A are formed from metals. Some examples of metals that can be used are tungsten (W), copper (Cu), ruthenium (Ru), molybdenum (Mo), cobalt (Co), aluminum (Al), nickel (Ni), silver (Ag), gold (Au), and the like, as well as alloys thereof. One or more of the source coupling 117A, the drain coupling 113A, and the gate electrode 105A can also include a diffusion barrier layer, an adhesive layer, or another such layer.Some examples of materials that can be used for a diffusion barrier layer or an adhesive layer are titanium nitride (TiN), tantalum nitride (TaN), molybdenum nitride (MoN), zirconium nitride (ZrN), hafnium nitride (HfN) and the like.

[0030] The interlevel dielectric 115A can be undoped silicate glass (USG) or similar. In some embodiments, the interlevel dielectric 115A is a low-k dielectric. In some embodiments, the interlevel dielectric 115A is an extremely low-k dielectric. A low-k dielectric is a material with a dielectric constant lower than that of silicon dioxide. Examples of low-k dielectrics include organosilicate glasses (OSG) such as carbon-doped silicon dioxide, fluorine-doped silicon dioxide (also known as fluorinated silica or FSG), and low-k organic polymer dielectrics. Examples of low-k organic polymer dielectrics include polyarylene ethers, polyimide (PI), benzocyclubbutene, and amorphous polytetrafluoroethylene (PTFE). An extremely low dielectric is a material with a dielectric constant of about 2.1 or less.An extremely low-k dielectric can be formed by depositing a dielectric with a low k-value in such a way that it has porosity or air gaps, wherein the effective dielectric constant of the composite including pores and air gaps is 2.1 or less.

[0031] Substrate 103A can be a chip cut from a wafer, e.g., a silicon wafer or similar. Substrate 103A can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or similar. Other substrates, such as a multilayer or gradient substrate, can also be used. In some embodiments, the semiconductor material of substrate 103A is or contains silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, gallium indium arsenide phosphide, combinations thereof, or similar. Substrate 103A can be or contain a dielectric material. For example, substrate 103A can be a dielectric substrate or contain a dielectric layer on a semiconductor substrate.The dielectric material can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, a carbide, such as silicon carbide, combinations thereof, such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, etc., or any other suitable dielectric.

[0032] In memory cell 101A, there is a threshold voltage at the gate electrode 105A at which the channel layer 111A between the source coupling 117A and the drain coupling 113A begins to conduct. This threshold voltage can be varied by write and erase operations, which change the polarization of the electric dipoles within the ferroelectric layer 107A. A first alignment of these electric dipoles yields a first threshold voltage, which can represent a logic "1", and a second alignment of these electric dipoles yields a second threshold voltage, which can represent a logic "0".

[0033] A write operation for memory cell 101A can involve setting the gate electrode 105A to a programming voltage Vth while the source coupling 117A and the drain coupling 113A are grounded. Vth can be the highest possible threshold voltage for memory cell 101A. For an erase operation, the gate electrode 105A can be set to -Vth while the source coupling 117A and the drain coupling 113A are grounded. A read operation can involve setting the gate electrode 105A to a voltage between the first and second threshold voltages, e.g., ½ Vth, setting the source coupling 117A to Vdd, setting the drain coupling 113A, and determining whether a resulting current is above or below a threshold value. The operation of memory cell 101A comprises a combination of the read, write, and erase operations.To determine the TDDB rate or the BTI rate, a specific operating protocol can be set. In some embodiments, the operating protocol includes the application of constant voltage stress (CVS). For the BTI rate, small gate voltage pulses can be applied to measure Vth while the voltage stress is continuously maintained.

[0034] Fig. Figure 1B shows an integrated circuit device 100B with a memory cell 101B according to some other aspects of the present teaching. The memory cell 101B has a transistor structure with a source region 118B, a drain region 104B, a channel layer 111B, a ferroelectric layer 107B, and a gate electrode 105B. The source region 118B, the drain region 104B, and the channel layer 111B are all provided by semiconductor sections of a substrate 103B. The source region 118B and the drain region 104B have one type of doping, and the channel layer 111B has the opposite type of doping. A source coupling 117B is connected to the source region 118B. A drain coupling 113B is connected to the drain region 104B. The source coupling 117B and the drain coupling 113B are vias in an interlevel dielectric 115B and can be connected to a metal compound structure formed over the substrate 103B.The gate electrode 105B is positioned above the ferroelectric layer 107B and the channel layer 111B, making the gate electrode 105B a top gate. The ferroelectric layer 107B is positioned between the channel layer 111B and the gate electrode 105B. Optionally, the ferroelectric layer 107B and the channel layer 111B are separated by a dielectric layer 109B. The layer thicknesses and connections in the memory cell 101B can be described as for corresponding structures in the memory cell 101A.

[0035] While the 101B memory cell was presented as a memory cell, the same arrangement of materials can be used in a conventional metal-oxide-semiconductor field-effect transistor (MOSFET). The 107B ferroelectric layer with the same compound can be used as a high k-value dielectric layer, although a different thickness might be more suitable for this application. As with the memory cell application, a low chlorine content facilitates achieving a low TDDB.

[0036] Fig. Figure 2 shows an integrated circuit device 200 with a 1T1C storage device, which includes a transistor 227 and a ferroelectric capacitor 235 according to some aspects of the present teaching. The ferroelectric capacitor 235 includes a ferroelectric layer 107C between an upper electrode 237 and a lower electrode 211. The ferroelectric capacitor 235 can be arranged in a metallic interconnect structure 223 formed over a semiconductor substrate 239. The metallic interconnect structure 223 includes conductors 231 and vias 233, which can be surrounded by an interlevel dielectric 115C. The ferroelectric capacitor 235 can be arranged between the 3rd and 4th metallic interconnect layers, the 4th and 5th metallic interconnect layers, or any other adjacent pair of metallic interconnect layers in the metallic interconnect structure 223.The transistor 227 can comprise a gate electrode 225 and a gate dielectric 229 formed over a doped region 228 of the semiconductor substrate 239. Source / drain regions 221 can be formed by other regions of the semiconductor substrate 239 having a contrasting doping type.

[0037] The ferroelectric layer 107C is a material with a compound as described for the ferroelectric layer 107A. Likewise, the interlevel dielectric 115C has the same compound options as the interlevel dielectric 115A. The ferroelectric capacitor 235 can be operated as a memory cell by applying suitable voltages to a word line (WL), a bit line (BL), and a source line (SL). If the ferroelectric layer 107C has a suitable thickness and operating characteristics, it stores data according to the polarization of the electric dipoles. In this case, the ferroelectric capacitor 235 is a ferroelectric memory cell. If the ferroelectric layer 107C has a suitable thickness and operating characteristics, it stores data according to a charge on the capacitor. In this case, the ferroelectric capacitor 235 is a DRAM (Dynamic Random Access Memory) cell.

[0038] Fig. 3, Fig. 4, Fig. 5 to Fig. Figure 6 are cross-sectional views that exemplify a method according to the present teaching for producing a memory cell with a ferroelectric layer according to the present teaching. While the Fig. 3, Fig. 4, Fig. 5 to Fig. 6, which describes various embodiments of a method, it will be understood that the methods described in the Fig. 3, Fig. 4, Fig. 5 to Fig. The structures shown in 6 are not limited to the procedure, but rather are independent of the procedure. While the Fig. 3, Fig. 4, Fig. 5 to Fig. While the actions described in section 6 are a series of actions, the order of the actions can be changed in other embodiments. While the Fig. 3, Fig. 4, Fig. 5 to Fig. 6. While a specific series of actions is illustrated and described, some actions that are illustrated and / or described may be omitted in other embodiments. Furthermore, other embodiments may contain actions that are not illustrated and / or described. While the method of Fig. 3, Fig. 4, Fig. 5 to Fig. 6, which is described in relation to the formation of the integrated circuit device 100A, the method can be used to form other integrated circuit devices.

[0039] As shown in the cross-sectional view 300 of Fig. As shown in Figure 3, the process can begin with the formation of the gate electrode 105A in the substrate 103A. The gate electrode 105A can be formed, for example, by forming a photoresist mask over the substrate 103A, etching to create a trench in the substrate 103A, removing the photoresist mask, filling the trench with a metal or other conductive material for the gate electrode 105A, and chemical-mechanical polishing (CMP) to remove the metal or other conductive material located outside the trench. Filling the trench with metal can involve atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, electroless deposition, or any other suitable method.

[0040] As shown in the cross-sectional view 400 of Fig. As shown in Figure 4, the process can be continued with the formation of the ferroelectric layer 107A. The ferroelectric layer 107A is formed by chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar processes using chlorine-free gaseous precursors. In some embodiments, the ferroelectric layer 107A is formed by ALD, as described in more detail below.

[0041] As shown in the cross-sectional view 500 of Fig. As shown in Figure 5, the process can be continued with the formation of the channel layer 111A and optionally the dielectric layer 109A. The dielectric layer 109A and the channel layer 111A can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), any combination thereof, or by other suitable methods.

[0042] As shown in the cross-sectional view 600 of Fig. As shown in Figure 6, the process can be continued with the formation of the interlevel dielectric 115A above the channel layer 111A. The interlevel dielectric 115A can be formed by CVD, a liquid process such as a spinon glass process, or similar methods. In some embodiments, the interlevel dielectric 115A is undoped silicate glass (USG) formed by CVD with silane (SiH4) or tetraethyl orthosilicate (TEOS).

[0043] As in Fig. As further shown in Figure 6, a photoresist mask 601 can be formed and used for etching trenches 603 into the interlevel dielectric 115A. Etching the trenches 603 can involve a dry etching process such as plasma etching or another suitable method. The trenches 603 can be filled with conductive material by atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), electroplating, electroless deposition, or any other suitable method, followed by planarization to create a structure as shown in Figure 6. Fig. 1A to form. Planarization can be CMP or another suitable method.

[0044] Fig. Figure 7 shows a flowchart for a process 700 that can be used to form an integrated circuit device according to the present disclosure. The process 700 comprises steps for forming the integrated circuit device 100A. Fig. 1A and also includes a method for forming the ferroelectric layer 107A, which can be used to form other ferroelectric layers according to other embodiments of the present disclosure. While the method 700 of the Fig. 7. Where the sequence of actions or events presented and described herein is understood to be not to be interpreted in a restrictive sense. For example, some actions may occur in a different order and / or concurrently with other actions or events than those presented and / or described herein. Furthermore, not all of the actions presented are necessary to implement one or more aspects or embodiments of the description contained herein, and one or more of the actions presented herein may be performed in one or more separate actions and / or phases.

[0045] Process 700 can begin with action 701, which forms a lower electrode. The cross-sectional view of Fig. shows a vivid example.

[0046] The process continues with step 703, in which the ferroelectric layer is formed. The cross-sectional view of Fig. Figure 4 provides a clear example, although it is understood that a ferroelectric layer can be formed in a different structure or at a different stage of processing according to the present teaching. Action 703 may include an atomic layer deposition (ALD) process, as further described in Actions 711 to 725.

[0047] After the formation of the ferroelectric layer, process 700 can be continued with step 705, the formation of a dielectric layer, and step 707, the formation of a channel layer. The cross-sectional view in Fig. This shows a clear example. Action 707, the formation of the dielectric layer, is optional.

[0048] The process can be continued with action 709, forming source and drain structures. Fig. shows together with Fig. an example.

[0049] Action 703, the formation of the ferroelectric layer, can be ALD. ALD involves the cyclic repetition of a series of steps, resulting in the uniform deposition of the ferroelectric layer at a controlled rate. As shown, the ALD process can begin with action 711, pulsing with steam or a similar substance.

[0050] Pulsation means that the reagent is introduced into a process gas stream for a limited period of time. The process gas may contain an inert carrier, such as nitrogen or argon, which flows continuously through a chamber containing the substrate. The chamber may be continuously evacuated by a vacuum system. In some embodiments, the ALD process is carried out at subatmospheric pressure. In some embodiments, the process is carried out at a pressure at or below 50 Torr. In some embodiments, the process is carried out at pressures in the range of approximately 1 Torr to approximately 10 Torr. In some embodiments, the process is carried out at pressures in the range of approximately 2 Torr to approximately 5 Torr.

[0051] Through absorption or adsorption, a layer of water vapor forms on the substrate surface. The water provides an oxygen source in the chemical reactions that form the ferroelectric layer. Instead of water, another suitable oxygen source can be used, such as O₂, O₃, or plasma-O₂ or plasma-O₃. The pulse continues until the surface layer has formed. In some embodiments, the water pulse lasts 60 seconds or less. In other embodiments, the water pulse ranges from one to ten seconds.

[0052] After the water has formed a layer on the surface, the process can continue with action 713, the purging of the chamber. The purging of the chamber can be performed with a non-reactive gas. Nitrogen can be a non-reactive gas. In some embodiments, the purging takes 30 seconds or less. In some embodiments, the purging takes between one and 10 seconds. In some embodiments, the purging takes 5 seconds or less.

[0053] The process can continue with action 715, which involves pulsed application of a chlorine-free zirconium precursor. The chlorine-free zirconium precursor is a zirconium compound that reacts with the oxygen source on the surface to form a layer containing zirconium. The precursor is selected to be volatile under the process conditions, to deposit only to an extent limited by the amount of oxygen source, such as water, present on the surface, and to have an acceptable reaction rate. In some embodiments, the zirconium precursor pulse lasts 60 seconds or less. In some embodiments, the zirconium precursor pulse lasts from 0.5 seconds to 10 seconds. In some embodiments, the zirconium precursor pulse lasts from about 1 second to about 5 seconds.

[0054] In some embodiments, the zirconium precursor is a zirconium compound in which the zirconium is directly bonded to carbon. Bis(methyl-η5-cyclopentadienyl)methoxymethylzirconium (Zr[CH3C5H4]2CH3OCH3 or ZRCMMM) is an example. In some embodiments, the zirconium precursor is a zirconium compound in which the zirconium is directly bonded to oxygen. Zirconium(IV) tert-butoxide (Zr[OC(CH3)3]4 or ZTB) is an example. In some embodiments, the zirconium precursor is a zirconium compound in which the zirconium is directly bonded to nitrogen. In some embodiments, the zirconium precursor has the form Zr(NR 1 R 2 )4, where and R 1 and R 2organic functional groups are used. Tetrakis(dimethylamino)zirconium(IV) (Zr[N(CH3)2]4 or TDMAZ) and Tetrakis(ethylmethylamido)zirconium(IV) (Zr[N(CH3)(C2H5)]4 or TEMAZ) are examples. In some embodiments, the zirconium precursor is one of the precursors listed in the following table or the like: Bis(methyl-η5-clyclopentadienyl)methoxymethylzirkonium Zr[CH3C5H4]2CH3OCH3 Zirkonium(IV)-tert.-butoxid Zr[OC(CH3)3]4 Tetrakis(dimethylamino)zirkonium(IV) (Zr[N(CH3)2]4 Tetrakis(ethylmethylamido)zirkonium(IV) Zr[N(CH3)(C2H5)]4 Bis(cyclopentadienyl)zirkonium(IV) C 10 H 12 Zr Bis(methyl-η5-cyclopentadienyl)methoxymethylzirkonium Zr(CH3C5H4)2CH3OCH3 Dimethylbis(pentamethylcyclopentadienyl)zirkonium(IV) C 22 H 36 Zr Tetrakis(dimethylamido)zirkonium(IV) [(CH3)2N]4Zr Tetrakis(ethylmethylamido)zirkonium(IV) Zr(NCH3C2H5)4 Zirkonium(IV)-dibutoxid(bis-2,4-pentandionat) C 18 H 32 O6Zr Zirkonium(IV)-2-Ethylhexanoat Zr(C8H 15 O2)4 Zirkoniumtetrakis(2,2,6,6-Tetramethyl-3,5-Heptandionat) Zr(OCC(CH3)3CHCOC(CH3)3)4

[0055] Action 715 is followed by action 717, a further purification. This purging can be like the purging of action 713. Action 719, another water pulse like action 711, and action 721, yet another purging, can then follow. Actions 719 and 721 can be similar to or identical to actions 711 and 713 and allow for the same description.

[0056] The process can continue with action 723, which involves pulsed action using a chlorine-free hafnium precursor. The chlorine-free hafnium precursor is a hafnium compound that reacts with the oxygen source on the surface to form a hafnium-containing layer. The precursor is selected to be volatile under process conditions, to deposit only to an extent limited by the amount of water or similar present on the surface, and to have an acceptable reaction rate. In some embodiments, the hafnium precursor pulse lasts 60 seconds or less. In some embodiments, the hafnium precursor pulse lasts between 0.5 and 10 seconds. In some embodiments, the hafnium precursor pulse lasts from about 1 second to about 5 seconds.

[0057] In some embodiments, the hafnium precursor is a hafnium compound in which the hafnium is directly bonded to carbon. Bis(methyl-η5-cyclopentadienyl)dimethylhafnium (Hf[CH3C5H4]2CH3OCH3 or HfD-CO2) and bis(methyl-η5-cyclopentadienyl)methoxymethylhafnium (HfCH3OCH3[C5H4]2 or HfD-CO4) are examples. In some embodiments, the hafnium precursor is a hafnium compound in which the hafnium is directly bonded to oxygen. In some embodiments, the hafnium precursor is a hafnium compound in which the hafnium is directly bonded to nitrogen. In some embodiments, the hafnium precursor has the form Hf(NR 1 R 2 )4, where R 1 and R 2organic functional groups are present. Tetrakis(dimethylamino)hafnium(IV) (Hf[N(CH3)2]4 or TDMAH) and Tetrakis(ethylmethylamido)hafnium(IV) (Hf[N(CH3)(C2H5)]4 or TEMAH) are examples. In some embodiments, the hafnium precursor is one or more of the precursors described in the following table, or the like: Bis(methyl-η5-clyclopentadienyl)dimethylhafnium Hf[CH3C5H4]2CH3OCH3 Bis(methyl-η5-clyclopentadienyl)methoxymethylhafnium HfCH3OCH3[C5H4]2 Tetrakis(dimethylamino)hafnium(IV) (Hf[N(CH3)2]4 Tetrakis(ethylmethylamido)hafnium(IV) Hf[N(CH3)(C2H5)]4 Dimethylbis(cyclopentadienyl)hafnium(IV) (C5H5)2Hf(CH3)2 Hafnium(IV)-tert.-butoxid Hf[OC(CH3)3]4 Hafnium-Isopropoxid Isopropanol C12H 28 HfO4 Tetrakis(diethylamido)hafnium (IV) [(CH2CH3)2N]4Hf Tetrakis(dimethylamido)hafnium(IV) [(CH3)2N]4Hf Tetrakis(ethylmethylamido)hafnium (IV) [(CH3)(C2H5)N]4Hf

[0058] Step 723 is followed by step 725, another rinse, and a repetition of the steps until the ferroelectric layer has built up to the desired thickness. In the described process, steps that introduce zirconium into the ferroelectric layer alternate with steps that introduce hafnium into the ferroelectric layer. Optionally, the proportions of these steps are varied, or only the steps that include zirconium or only the steps that include hafnium are used. In some embodiments, a layer is deposited every 60 seconds or at a higher frequency. The desired rate can be achieved by selecting suitable precursors.

[0059] In some embodiments, an additional precursor providing a metal ion is included, either with the zirconium precursor or the hafnium precursor. Examples of metal ions that may be provided by the additional precursor include ions of aluminum (Al), silicon (Si), lanthanum (La), scandium (Sc), calcium (Ca), barium (Ba), gadolinium (Gd), yttrium (Y), and the like. In some embodiments, the precursor is one of the precursors listed in the following table or the like: Aluminium-tris(2,2,6,6-tetramethyl-3,5-heptandionat) Al(OCC(CH3)3CHCOC(CH3)3)3 Triisobutylaluminium Al[(CH3) 2C HCH2]3 Trimethylaluminium Al(CH3)3 Tris(dimethylamido)aluminium(III) Al(N(CH3)2)3 (3-Aminopropyl)triethoxysilan H2N(CH2)3Si(OC2H5)3 N-sec-Butyl(trimethylsilyl)amin C7H 19 NSi 1,3-Diethyl-1,1,3,3-tetramethyldisilazan CsH 23 NSi2 Dodecamethylcyclohexasilan (Si(CH3)2)6 Hexamethyldisilan (Si(CH3)3)2 Hexamethyldisilazan (CH3)3SiNHSi(CH3)3 2,4,6,8,10-Pentamethylcyclopentasiloxan (CH3SiHO)5 Pentamethyldisilan (CH3)3SiSi(CH3)2H Silizium-Tetrabromid SiBr4 Tetraethylsilan Si(C2H5)4 2,4,6,8-Tetramethylcyclotetrasiloxan (HSiCH3O)4 1,1,2,2-Tetramethyldisilan (CH3)2SiHSiH(CH3)2 Tetramethylsilan Si(CH3)4 N,N',N''-Tri-tert-butylsilanetriamin HSi(HNC(CH3)3)3 Tris(tert.-butoxy)silanol ((CH3)3CO)3SiOH Tris(tert-pentoxy)silanol (CH3CH2C(CH3) 2O 3SiOH Tris[N,N-Bis(trimethylsilyl)amid]gadolinium(III) Gd(N(Si(CH3)3)2)3 Tris(tetramethylcyclopentadienyl)gadolinium(III) C 27 H 39 Gd Tris(isopropylcyclopentadienyl)gadolinium C 24 H 33 Gd Triethylgallium (CH3CH2)3Ga Trimethylgallium Ga(CH3)3 Tris(dimethylamido)gallium(III) C 12 H 36 Ga2N6 Lanthan(III)-Isopropoxid C9H 21 LaO3 Tris[N,N-bis(Trimethylsilyl)amid]Lanthan(III) La(N(Si(CH3)3)2)3 Tris(cyclopentadienyl)lanthan(III) La(C5H5)3 Lanthan (2,2,6,6-Tetramethyl-3,5-heptanedionato) La(OCC(CH3)3CHCOC(CH3)3)3 Tris(tetramethylcyclopentadienyl)lanthan(III) C 27 H 39 to Tris[N,N-bis(Trimethylsilyl)amid]yttrium [[(CH3)3Si]2N]3Y Tris(butylcyclopentadienyl)yttrium(III) Y(C5H4CH2(CH2)2CH3)3 Tris(cyclopentadienyl)yttrium(III) Y(C5H5)3 Yttrium 2-Methoxyethoxid C9H 21 O6Y Yttrium(III)-tris(isopropoxid) C9H 21 O3Y Yttrium(III)-Tris(2,2,6,6-tetramethyl-3,5-heptandionat) Y(OCC(CH3)3CHCOC(CH3)3)3

[0060] In some embodiments, the metal ion is aluminum (Al) or the like. In some embodiments, the metal ion is silicon (Si) or the like. In some embodiments, the metal ion is lanthanum (La) or the like. In some embodiments, the metal ion is gadolinium (Gd) or the like. In some embodiments, the metal ion is yttrium (Y) or the like. In some embodiments, the additional precursor comprises the metal ion directly bonded to oxygen, nitrogen, carbon, or a combination thereof. In some embodiments, the additional precursor comprises the metal ion directly bonded to carbon. In some embodiments, the additional precursor comprises the metal ion directly bonded to oxygen. In some embodiments, the additional precursor includes the metal ion directly bonded exclusively to oxygen and / or carbon.In some embodiments, the additional precursor comprises the metal ion that is directly bonded to nitrogen.

[0061] Also disclosed, but not part of the present invention, is an integrated circuit device containing a material layer that emits Hf x Zr 1-x O2 comprises, where 0 ≤ x ≤ 1, and the material layer contains less than 1 ppm of chlorine. The layer is ferroelectric and can be used as a data storage layer in a storage device.

[0062] Some aspects of the present teachings relate to an integrated circuit device with a memory cell comprising a channel extending between a source and a drain, a gate electrode, and a ferroelectric layer between the gate electrode and the channel, wherein the ferroelectric layer is chlorine-free and formed by atomic layer deposition using chlorine-free precursor substances, and wherein the ferroelectric layer Hf x Zr 1-x The storage cell contains O2, where 0 ≤ x ≤ 1. It has a leakage current and a time-dependent dielectric breakdown rate (TDDB rate). The TDDB rate is defined as an initial value of the leakage current divided by an operating time during which the leakage current doubles from the initial value. The TDDB rate is less than the amount by which the TDDB rate would increase if 1 ppm of chlorine were added to the ferroelectric layer.

[0063] Some aspects of the present teaching relate to a method for forming an integrated circuit device, which includes the formation of a chlorine-free ferroelectric layer by atomic layer deposition using chlorine-free precursors. The chlorine-free precursors may include a zirconium (Zr) precursor, a hafnium precursor, or both types of precursors.

Claims

[1] Integrated circuit device (100A) comprising the following: a memory cell (101A) comprising: a channel (111A) extending between a source (117A) and a drain (113A), a gate electrode (105A), a ferroelectric layer (107A) arranged between the gate electrode (105A) and the channel (111A), which is chlorine-free and formed by atomic layer deposition using chlorine-free precursor substances, and a dielectric layer (109A) arranged between the ferroelectric layer (107A) and the channel (111A); wherein the storage cell (101A) has a leakage current and a TDDB rate, the TDDB rate being defined as an initial value of the leakage current divided by an operating time over which the leakage current doubles compared to the initial value; and where the TDDB rate is less than the amount by which the TDDB rate would increase if 1 PPM of chlorine were added to the ferroelectric layer (107A), wherein the dielectric layer (109A) has a thickness of 0.1 to 10 nm, preferably 0.3 to 3 nm; wherein the ferroelectric layer Hf x Zr 1-x O2 has, where 0 ≤ x ≤ 1. [2] Integrated circuit device according to claim 1, wherein x = 0.

5. [3] Integrated circuit device according to one of claims 1 to 2, wherein the ferroelectric layer (107A) has a thickness of 1 nm to 30 nm [4] Integrated circuit device according to one of claims 1 to 3, wherein the ferroelectric layer (107A) is arranged in a transistor structure. [5] Method for manufacturing an integrated circuit device (100A) according to any one of the preceding claims, wherein the method comprises: Forming a gate electrode (105A) directly on a substrate (103A), Formation of a ferroelectric layer (107A) over the gate electrode (105A) by atomic layer deposition using chlorine-free precursor substances, Formation of a dielectric layer (109A) over the ferroelectric layer (107A), Forming a channel layer (111A) over the dielectric layer (109A), and Formation of source / drain structures (113A, 117A) above the channel layer (111A), wherein the chlorine-free precursors comprise a zirconium precursor and / or a hafnium precursor, and wherein the chlorine-free precursors further comprise a compound comprising aluminium, silicon, lanthanum, scandium, calcium, barium, gadolinium or yttrium. [6] The method of claim 5, wherein the chlorine-free precursors comprise a metal compound in which nitrogen is bonded to a metal. [7] Method according to one of claims 5 or 6, wherein the chlorine-free precursors comprise a metal compound in which carbon is bonded to a metal. [8] Method according to any one of claims 5 to 7, wherein the chlorine-free precursors are a metal compound of the form M-(NR) n comprise, where M is a metal, R is an organic functional group, and n is an integer. [9] Method according to claim 8, wherein the organic functional groups are alkanes, alkenes, alkynes, alcohols, amines, ethers, aldehydes, ketones, carboxylic acids, esters or amides.

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