Controller, storage device containing the controller and reading method of the storage device

Abstract

A controller comprising: control terminals for providing control signals to a non-volatile memory device (100; 1000); a buffer memory (220) configured to store a first table, a second table, and a third table; and an error correction code (ECC) circuit (230) configured to correct an error in first data read from the non-volatile memory device (100;1000), wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, the third offset information corresponding to a past read level and being determined by the first offset information and the second offset information, and wherein the error of the first data is not correctable by the error correction code circuit (230), an on-chip valley search operation is performed by the non-volatile memory device (100; 1000) according to a second read command, detection information of the on-chip valley search operation is received according to a specific command, and the second offset information corresponding to the detection information is generated, and wherein an off-chip valley search operation is performed when a read operation based on the on-chip valley search operation fails.

Description

Technical FieldThe present inventive concept relates to a controller, a storage device including the controller, and a reading method of the storage device.DESCRIPTION OF THE RELATED ARTAn error correction code (ECC) memory is one type of computer data memory that detects and corrects an n-bit data corruption occurring in the memory. In general, a storage device generates an ECC using an ECC circuit in a write operation and corrects an error of data of the ECC in a read operation. However, there may be a case where memory cells of a storage device have deteriorated so much that correction by an ECC circuit cannot be performed. In this case, a read retry operation may be performed using a sensing method different from that of a normal read operation.US 2016 / 0132256 A1 discloses an operating method for a nonvolatile memory system including receiving a read request for at least one page from a host. After receiving the read request, the read voltages are set using a read history table to execute a first read operation in which the data stored in the nonvolatile memory is read. An optimum set of read voltages is set when the data read according to the first read operation includes an uncorrectable error, and a second read operation is performed in which the stored data is read based on the set optimum set of read voltages. The read history table is updated based on a reliability parameter indicating a property of the nonvolatile memory, a property of the data in the first or second read operation, the optimal read voltage, or the read history table.US 2016 / 0004437 A1 discloses a reading method of a storage device, which includes: performing a first reading operation on a nonvolatile storage device based on a time stamp table storing a program time and a time read level lookup table indicating a read level shift due to an elapsed program time. Based on a result of the first read operation, it is decided whether to adjust the time read level lookup table. As a result of determining to adjust the time-read level lookup table, the time-read level lookup table is adjusted by a valley search operation and a second read operation is performed on the nonvolatile memory device based on the time stamp table and the adjusted time-read level lookup table.DE 10 2013 107 626 A1 discloses a memory device including a memory cell array including(s) a plurality of memory cells; a page buffer unit including a plurality of page buffers configured to store a plurality of data sequentially read from some of the plurality of memory cells under different read voltages, respectively, and to perform a logic operation on the plurality of data parts, respectively; and a counting unit configured to count the number of memory cells existing in each of a plurality of sections defined by the different read voltage levels, based on results of the logic operation.US 2020 / 0090766 A1, US 2014 / 0153330 A1 and US 2017 / 0133087 A1 likewise relate to reading methods on storage devices.Summary of the InventionEmbodiments are set forth in the claims. According to an embodiment of the inventive concept, there is provided a controller including: control terminals for providing control signals to a nonvolatile memory device; a buffer memory configured to store a first table, a second table, and a third table; and an error correction code (ECC) circuit configured to correct an error in first data read from the nonvolatile memory device according to a first read command, wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a past read level and is determined by the first offset information and the second offset information, and wherein the error of the first data is uncorrectable by the error correction code circuit, performing an on-chip-valley search operation from the nonvolatile memory device according to a second read command, receiving determination information of the on-chip-valley search operation according to a specific command, and generating the second offset information corresponding to the determination information.Brief Description of the DrawingsFor a clearer understanding of the above and other features of the inventive concept, the following detailed description is provided in conjunction with the accompanying drawings. FIG. 1 illustrates a storage device according to an embodiment of the inventive concept. FIG. 2 illustrates an example of a nonvolatile memory device illustrated in FIG. 1. FIG. 3 is a circuit diagram of a memory block among memory blocks shown in FIG. 1. FIG. 4 is a flowchart illustrating a read operation performed using an on-chip-valley search (OVS) in a general storage device. FIG. 5 is a diagram illustrating extraction of an optimal read level of a storage device according to an embodiment of the inventive concept. FIGS. 6A and 6B are diagrams illustrating different read voltages of a distribution valley and corresponding development times. FIG. 7 is a diagram illustrating read level offset compensation using an OVS table (OVST) according to an embodiment of the inventive concept. FIGS. 8A and 8B illustrate an OVST according to an embodiment of the inventive concept. FIGS. 9A, 9B, and 9C illustrate an example of an optimal valley search using an OVST according to an embodiment of the inventive concept when a predefined table (PDT) offset is deficient. FIGS. 10A, 10B, and 10C illustrate an example of an optimum valley search using an OVST according to an embodiment of the inventive concept when a PDT offset is excessive. FIG. 11A illustrates an example of a distribution to which an OVS mode of a read operation according to an embodiment of the inventive concept is applied. FIG. 11B illustrates an example of distributions to which an OVS mode of a read operation according to another embodiment of the inventive concept is applied. FIG. 11C illustrates an example of distributions to which an OVS mode of a read operation according to another embodiment of the inventive concept is applied. FIG. 12 is a flowchart illustrating a reading method of a storage device according to an embodiment of the inventive concept. FIG. 13 is a flowchart illustrating a reading method of a storage device according to another embodiment of the inventive concept. FIG. 14 is a circuit diagram illustrating a process of extracting a read level offset from the storage device according to an embodiment of the inventive concept. FIG. 15 is a circuit diagram illustrating a read operation using a read level offset extracted from a storage device according to an embodiment of the inventive concept. FIG. 16 is a circuit diagram illustrating a read operation of a storage device according to another embodiment of the inventive concept. FIG. 17 is a circuit diagram illustrating a read operation of another storage device according to another embodiment of the inventive concept. FIGS. 18A and 18B illustrate examples of OVS determination cases of a nonvolatile memory device according to embodiments of the inventive concept. FIG. 19 illustrates an example of OVS determination information and a method of outputting the OVS determination information according to an embodiment of the inventive concept. FIG. 20 illustrates an example of outputting OVS determination information as a specific command. FIG. 21 illustrates a storage device according to another embodiment of the inventive concept. FIG. 22 illustrates a storage device according to another embodiment of the inventive concept. FIG. 23 illustrates a storage device according to another embodiment of the inventive concept. FIG. 24 illustrates table management of a storage device according to an embodiment of the inventive concept. FIG. 25 illustrates a nonvolatile memory device implemented in a chip-to-chip (C 2C) structure according to an embodiment of the inventive concept.DETAILED DESCRIPTION OF THE EMBODIMENTSHereinafter, embodiments of the inventive concept will be described with reference to the accompanying drawings. In the drawings, like reference numerals may refer to like elements.A controller, a storage device including the controller, and a reading method of the storage device according to an embodiment of the inventive concept may reflect on-chip valley search (OVS) determination information as an optimal reading level to perform a read operation, thereby preventing performance degradation while ensuring reliability. FIG. 1 illustrates a storage device 10 according to an embodiment of the inventive concept. Referring to FIG. 1, the storage device 10 may include at least one nonvolatile memory device (NVM(s)) 100 and a controller (CNTL) 200.The at least one nonvolatile memory device 100 may store data. The nonvolatile memory device 100 may be a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a resistive random access memory (RRAM), a phase transition RAM (PRAM), a magneto-resistive RAM (MRAM), a ferroelectric RAM (FRAM), a spin transfer torque RAM (STT-RAM), or the like. The nonvolatile memory device 100 may be realized in a three-dimensional array structure. The present inventive concept can be applied not only to a flash memory device in which a charge storage layer includes a conductive floating gate, but also to a charge trap flash (CTF) in which a charge storage layer includes an insulating layer. Hereinafter, for convenience of description, the nonvolatile memory device 100 will be referred to as a vertical NAND flash memory device ("VNAND").The nonvolatile memory device 100 may include a plurality of memory blocks BLK 1 to BLKz (where z is an integer greater than or equal to 2) and control logic 150.Each of the plurality of memory blocks BLK 1 to BLKz may include a plurality of pages page 1 to page m (where m is an integer greater than or equal to 2). Each of the plurality of page 1 to page m may include a plurality of memory cells. Each of the plurality of memory cells may store at least one bit.The control logic 150 may receive a command CMD and an address ADD from the controller (CNTL) 200, and may perform an operation corresponding to the received command CMD (e.g., a program operation, a read operation, an erase operation, or the like) on memory cells corresponding to the received address ADD.The control logic 150 may include an OVS circuit 155. The OVS circuit 155 may perform an on-chip valley search (OVS) operation. The on-chip valley search operation may include a first detection operation for determining an OVS determination case based on a cell count, and a second detection operation for changing and detecting an actual development time according to the determined OVS determination case. Details of the on-chip valley search operation are disclosed in U.S. Patent Application Nos. 2020-0286545 and 2020-0098436 and U.S. Patent Nos. 10,090,046, 10,559,362, 10,607,708 and 10,629,259, the disclosures of which are incorporated herein by reference in their entirety.The OVS circuit 155 may store OVS determination information OVSDI corresponding to a result of the on-chip valley search operation. Such OVS determination information OVSDI may include information (for example, development time information) indicating an optimum distribution valley corresponding to a state.The controller (CNTL) 200 may be connected to at least one nonvolatile memory device 100 through a plurality of control pins that transmit control signals (for example, an enable (CLE) signal for latching commands, an enable (ALE) signal for latching addresses, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and the like). In addition, the controller (CNTL) 200 may control the nonvolatile memory device 100 using the control signals (e.g., CLE, ALE, CE(s), WE, RE, and the like). For example, the nonvolatile memory device 100 may latch a command CMD or an address ADD on an edge of a write enable signal WE according to an enable (CLE) signal for latching commands and an enable (ALE) signal for latching addresses to perform program / read / erase operations.The controller (CNTL) 200 may include a buffer memory 220 and an error correction code (ECC) circuit 230.The buffer memory 220 may be implemented as a volatile memory (for example, a static random access memory (SRAM) RAM, a dynamic RAM (DRAM) DRAM (synchronous DRAM) or the like) or a nonvolatile memory (for example, a flash memory, a phase transition RAM (PRAM), a magneto-resistive RAM (MRAM), a resistive RAM (ReRAM), a ferroelectric RAM (FRAM) or the like). The buffer memory 220 may include a plurality of tables, such as at least a predefined table (PDT), an OVS table (OVST), and a past read level table (HRT).A first table PDT may include first read level offset information. In an embodiment of the inventive concept, the first table PDT may include first read level offset information corresponding to an elapsed programming time. In an embodiment of the inventive concept, the first table PDT may include, in addition to the elapsed program time, first read level offset information corresponding to various pieces of degradation information (e.g., a temperature, a program / erase cycle, a read cycle, an open word line case, and the like).A second table OVST may include second read level offset information corresponding to OVS determination information OVSDI. In this case, the OVS determination information OVSDI may be development time information corresponding to an optimum distribution valley. For example, the second read level offset information may include read level offset information corresponding to development time information in which an OVS operation is performed. Accordingly, the second table OVST may be a table for converting the OVS determination information OVSDI into read level offset information.A third table HRT may include third read level offset information associated with a past read operation. In an embodiment of the inventive concept, the third read level offset information may be determined using the first read level offset information and the second read level offset information. The third read level offset information may include information on an optimal read level at which the past read operation is performed. Details of the past read operation are disclosed in U.S. Patent Nos. 10,120,589 and 10,373,693, the disclosures of which are incorporated herein by reference in their entirety.The ECC circuit 230 may generate an error correction code during a program operation and restore DATA using the error correction code during a read operation. For example, the ECC circuit 230 may generate an error correction code (ECC) for correcting a failed bit or an error bit of the DATA received from the nonvolatile memory device 100. The ECC circuit 230 may perform error correction coding of data provided to the nonvolatile memory device 100 to generate DATA to which a parity bit is added. The parity bit may be stored in the nonvolatile memory device 100. In addition, the ECC circuit 230 may perform error correction decoding on the DATA output from the nonvolatile memory device 100. The ECC circuit 230 may correct an error using parity. The ECC circuit 230 may correct an error using a low density parity check (LDPC) code, a Bose-Chaudhuri-Hocquenghem (BCH) code, a turbo code, a Reed-Solomon code, a convolutional code, a recursive systematic code (RSC), or a coded modulation such as a Trellis coded modulation (TCM), a Block Coded Modulation (BCM), or the like.When the error correction circuit 230 cannot perform error correction, a read retry operation may be performed. In an embodiment of the inventive concept, the read retry operation may include an OVS operation. In another embodiment of the inventive concept, the read retry operation may include an OVS operation reflecting the first table PDT.The storage device 10 according to an embodiment of the inventive concept may not perform an OVS operation before an uncorrectable error correction code (UECC) occurs, and may enable the OVS operation after the UECC occurs. The nonvolatile memory device 100 may output OVS determination information OVSDI to the controller 200, and the controller (CNTL) 200 may search read level offset information corresponding to the OVS determination information OVSDI, and may shift a standard read level (e.g., a read level of past read operations / normal read operations) with respect to the searched read level offset information during the next read operation.FIG. 2 illustrates an example of the nonvolatile memory device 100 illustrated in FIG. 1. Referring to FIG. 2, the nonvolatile memory device 100 may include a memory cell array 110, a row decoder 120, a page buffer circuit 130, an input / output (I / O) buffer circuit 140, a control logic 150, a voltage generator 160, and a cell counter 170.The memory cell array 110 may be connected to the row decoder 120 through word lines WLs or string select and ground select lines SSL and GSL. The memory cell array 110 may be connected to the page buffer circuit 130 through bit lines BLs. The memory cell array 110 may include a plurality of cell strings. A channel of each of the cell strings may be formed in a vertical or horizontal direction. Each of the cell strings may include a plurality of memory cells. The plurality of memory cells may be programmed, erased, or read by a voltage provided to the bit lines BLs or the word lines WLs. Generally, a program operation is performed in units of pages and an erase operation is performed in units of blocks.The row decoder 120 may select one of the memory blocks BLK 1 to BLKz of the memory cell array 110 in response to an address ADD. Row decoder 120 may select a word line among word lines of the selected memory block in response to address ADD. The row decoder 120 may transfer a word line voltage VWL corresponding to an operation mode to the word line of the selected memory block. During a program operation, the row decoder 120 may apply a program voltage and a verify voltage to a selected word line and may apply a pass voltage to a non-selected word line. During a read operation, row decoder 120 may apply a read voltage to a selected word line and a read pass voltage to an unselected word line.The page buffer circuit 130 may operate as a write driver or a sense amplifier. During a program operation, the page buffer circuit 130 may apply a bit line voltage corresponding to data to be programmed to bit lines of the memory cell array 110. During a read operation or a verify operation, the page buffer circuit 130 may detect data stored in a selected memory cell through a bit line BL. A plurality of page buffers PB 1 to PBn (where n is an integer greater than or equal to 2) included in the page buffer circuit 130 may be connected to at least one bit line, respectively.Each of the plurality of page buffers PB 1 to PBn may perform sensing and latching operations for performing an OVS operation. For example, each of the plurality of page buffers PB 1 to PBn may perform a plurality of sensing operations to identify a state stored in the selected memory cells under control of the control logic 150. After storing data acquired by a plurality of acquisition operations, each of the plurality of page buffers PB 1 to PBn may select a certain data part under the control of the control logic 150. For example, each of the plurality of page buffers PB 1 to PBn may perform a sensing operation twice or more to identify a state. In addition, each of the plurality of page buffers PB 1 to PBn may select or output optimum data among a plurality of detected data pieces under the control of the control logic 150.The I / O buffer circuit 140 may provide externally provided data to the page buffer circuit 130. I / O buffer circuit 140 may provide an externally provided command CMD to control logic 150. I / O buffer circuit 140 may provide an externally provided address ADD to control logic 150 or row decoder 120. In addition, the I / O buffer circuit 140 may output data, which is captured and latched by the page buffer circuit 130, to an external unit.The control logic 150 may control the row decoder 120 and the page buffer circuit 130 in response to an externally transmitted command CMD.The control logic 150 may include an OVS circuit 155 for performing an OVS operation.The OVS circuit 155 may control the page buffer circuit 130 and the voltage generator 160 for the OVS operation. The OVS circuit 155 may control the page buffer circuit 130 such that the page buffer circuit 130 performs a sensing operation twice or more to identify a specific state of selected memory cells. The OVS circuit 155 may control the plurality of page buffers PB 1 to PBn such that the plurality of page buffers PB 1 to PBn store sensing data corresponding to each of a plurality of sensing results in a plurality of buffer sets included in each of the plurality of page buffers PB 1 to PBn. In addition, the OVS circuit 155 may perform processing for selecting optimum data among a plurality of acquired data pieces. The OVS circuit 155 may refer to a count result nC provided by the cell counter 170 to select the optimal data. For example, the OVS circuit 155 may control the page buffer circuit 130 such that the page buffer circuit 130 selects or outputs a read result closest to a distribution valley among a plurality of detection results.In addition, the OVS circuit 155 may store development time information corresponding to the OVS operation. The OVS circuit 155 may output the stored development time information to the controller 200 as OVS determination information OVSDI. In an embodiment of the inventive concept, the OVS determination information OVSDI may be output using a Universal Internal Bus (UIB), or may be output in response to a feature fetch command, or may be output in response to a state read command. For convenience of description, the following description is given for a case where the OVS determination information OVSDI is output in response to the feature fetch instruction.The voltage generator 160 may generate various kinds of wordline voltages to be applied to each wordline under the control of the control logic 150 and well voltages to be supplied to a ground (for example, a well region) in which memory cells are formed. Wordline voltages applied to wordlines, respectively, may include a programming voltage, a pass voltage, a read voltage, and a read pass voltage, and the like.The cell counter 170 may count memory cells corresponding to a specific threshold voltage range from data acquired from the page buffer circuit 130. For example, the cell counter 170 may process data detected from each of the plurality of page buffers PB 1 to PBn to count the number of memory cells having a threshold voltage within a specific threshold voltage range.The nonvolatile memory device 100 according to an embodiment of the inventive concept may perform an OVS operation to ensure reliability of a read operation. In addition, the nonvolatile memory device 100 according to an embodiment of the inventive concept may output OVS determination information OVSDI to the controller 200 to perform a read operation at an optimal read level in the next read operation. Accordingly, occurrence of a UECC of the reading operation can be reduced. As a result, a read retry operation for data recovery can be reduced.FIG. 3 is a circuit diagram of a memory block BLK 1 among memory blocks illustrated in FIG. 1. The memory block BLK 1 illustrated in FIG. 3 has a three-dimensional structure. The memory block BLK 1 may include a plurality of cell strings CS 11, CS 12, CS 21, and CS 22. The plurality of cell strings CS 11, CS 12, CS 21, and CS 22 may be arranged in a row direction and a column direction to form rows and columns.In an embodiment of the inventive concept, the cell strings CS 11 and CS 12 may be connected to string selection lines SSL 1 aand SSL 1 bto form a first row. The cell strings CS 21 and CS 22 may be connected to string selection lines SSL 2 aand SSL 2 bto form a second row. For example, the cell strings CS 11 and CS 21 may be connected to a first bit line BL 1 to form a first column. The cell strings CS 12 and CS 22 may be connected to a second bit line BL 2 to form a second column.Each of the plurality of cell strings CS 11, CS 12, CS 21, and CS 22 may include a plurality of cell transistors. For example, each of the plurality of cell strings CS 11, CS 12, CS 21, and CS 22 may include string selection transistors SSTa and SSTb, a plurality of memory cells MC 1, MC 2, MC 3, MC 4, MC 5, MC 6, MC 7, and MC 8, ground selection transistors GSTa and GSTb, and dummy memory cells DMC 1 and DMC 2. For example, each of a plurality of cell transistors included in the plurality of cell strings CS 11, CS 12, CS 21, and CS 22 may be a charge trap flash (CTF) memory cell.The plurality of memory cells MC 1 to MC 8 may be connected in series and may be stacked in a height direction perpendicular to a plane defined by a row direction and a column direction. The plurality of memory cells MC 1 to MC 8 may be connected to a plurality of word lines WL 1, WL 2, WL 3, WL 4, WL 5, WL 6, WL 7, and WL 8. The string selection transistors SSTa and SSTb may be connected in series. The string selection transistors SSTa and SSTb connected in series may be provided between the plurality of memory cells MC 1 to MC 8 and the first or second bit lines BL 1 and BL 2. The ground selection transistors GSTa and GSTb may be connected in series. The ground selection transistors GSTa and GSTb connected in series may be provided between the plurality of memory cells MC 1 to MC 8 and a common source line CSL.In an embodiment of the inventive concept, a first dummy memory cell DMC 1 may be provided between the plurality of memory cells MC 1 to MC 8 and the ground selection transistors GSTa and GSTb. For example, the first dummy memory cell DMC 1 may be disposed between the first memory cell MC 1 and the ground selection transistor GSTb. For example, a second dummy memory cell DMC 2 may be provided between the plurality of memory cells MC 1 to MC 8 and the string selection transistors SSTa and SSTb.The ground selection transistors GSTa and GSTb of the cell strings CS 11, CS 12, CS 21, and CS 22 may be commonly connected to a ground selection line GSL. For example, ground selection transistors of the same row may be connected to the same ground selection line and ground selection transistors of different rows may be connected to different ground selection lines. For example, first ground selection transistors GSTa of the cell strings CS 11 and CS 12 of a first row may be connected to a first ground selection line. Similarly, among second string selection transistors SSTb having the same height, string selection transistors of the same row may be connected to the same string selection line, and string selection transistors of different rows may be connected to different string selection lines. For example, second string selection transistors SSTb of the cell strings CS 11 and CS 12 of a first row may be commonly connected to a string selection line SSL 1 band second string selection transistors SSTb of the cell strings CS 21 and CS 22 of a second row may be commonly connected to a string selection line SSL 2 b.In addition, string selection transistors of cell strings of the same row may be commonly connected to the same string selection line. For example, first and second string selection transistors SSTa and SSTb of the cell strings CS 11 and CS 12 of the first row may be commonly connected to the same string selection line. First and second string selection transistors SSTa and SSTb of the second row cell strings CS 21 and CS 22 may be commonly connected to the same string selection line.In an embodiment of the inventive concept, dummy memory cells having the same height may be connected to the same dummy word line, and dummy memory cells having different heights may be connected to different dummy word lines. For example, first dummy memory cells DMC 1 may be connected to a first dummy word line DWL 1, and second dummy memory cells DMC 2 may be connected to a second dummy word line DWL 2.In the first memory block BLK 1, an erase operation may be performed in units of memory blocks or sub-blocks. When an erase operation is performed in units of memory blocks, all memory cells MC of the first memory block BLK 1 may be simultaneously erased in response to a single erase request. When an erase operation is performed in units of sub-blocks, some of the memory cells MC of the first memory block BLK 1 may be simultaneously erased in response to a single erase request, and the other memory cells MC may be erase-inhibited. A low voltage (e.g., a ground voltage) may be supplied to a word line connected to the erased memory cells, and a word line connected to the erase-inhibited memory cells may be floating.The first memory block BLK 1 illustrated in FIG. 3 is an example memory block. In an embodiment of the present inventive concept, it is understood that the number of lines GSL, WL, DWL, SSL and the like connected to cell transistors GST, MC, DMC, SST is not limited according to the number of cell strings, the number of rows, the number of columns, the number of cell transistors GST, MC, DMC, SST and the like.Generally, an OVS operation is used only for an entry of a restore code for satisfying read time (e.g., tR) conditions of a nonvolatile memory device. However, in an existing protection code, the OVS operation encounters a problem such as using an optimum read level.FIG. 4 is a flowchart illustrating a read operation performed using an OVS in a general storage device. It is assumed that a read operation is performed on memory cells connected to a first word line WL1 using a standard read level (401). If such a read operation fails (402), the OVS operation performed on the memory cells connected to the first word line WL1 is activated (403). For example, a nonvolatile memory device enters a protection code. The OVS operation is performed by reflecting a predefined table PDT (404). When the read operation performed on the memory cells connected to the first word line WL1 is due to the OVS operation (405), a past read level table HRT is updated (406). In this case, offset information of the PDT used for the OVS operation is updated to the HRT.Then, when a read operation is performed on memory cells connected to the next word line, for example, a second word line WL2 (407), the OVS operation is basically disabled. For example, a read operation is performed on the memory cells connected to the second word line WL2 during an enable of the protection code (408). In this case, a past read operation is performed using the updated HRT (409). A general storage device does not reflect an optimal read level offset sought in an OVS operation into an HRT. Thus, there is a high probability that a read operation of the memory cells connected to the next word line fails ( 410).The storage device 10 according to an exemplary embodiment of the inventive concept may reflect determination information OVSDI (see FIG. 1 ) based on the OVS operation into a past read level table HRT to use an optimal read level in the next read operation.FIG. 5 is a diagram illustrating extraction of an optimum read level of a storage device 10 according to an embodiment of the inventive concept. Referring to FIG. 5, the storage device 10 may update the past read level table HRT (a third table) using a predefined table PDT (a first table) and an OVST (a second table) to extract an optimal read level. In other words, the storage device 10 may update the past read level table HRT using a first table and a second table to extract an optimal read level.The OVS determination information OVSDI (see FIG. 1 ) may include result information based on an OVS operation. A second read level offset OST_ovst corresponding to the OVS determination information OVSDI may be reflected into the OVST. In other words, the second read level offset OST_ovst may be output from the second table. The second read level offset OST_ovst may be added to a first read level offset OST_pdt depending on an elapse of a program time to determine a third read level offset OST_hrt. The first read level offset OST_pdt may be output from the first table. The third read level offset OST_hrt may not be determined by simply adding the first read level offset OST_pdt and the second read level offset OST_ovst. For example, the third read level offset OST_hrt may be added by applying a weight to both the first and second read level offsets OST_pdt and OST_ovst. The third read level offset OST_hrt may be stored in the third table.The storage device 10 according to an embodiment of the inventive concept may reflect the second read level offset OST_ovst into an HRT based on an OVS operation to perform a read operation at an optimal read level during deactivation of the OVS operation (e.g., without applying a protection code). Thus, data reliability of the read operation may be increased and the entry of the protection code may be reduced to increase performance of the read operation.Generally, memory cells distributed around a distribution valley are memory cells arranged on a boundary between an ON cell and an OFF cell. Thus, an identification of an ON cell or an OFF cell for such cells may vary depending on a development time. For example, if the development time is slightly decreased, memory cells distributed around the distribution valley may be identified as OFF cells. Further, when the development time is slightly increased, the memory cells distributed around the distribution valley may be identified as ON cells. For example, in a read operation, decreasing a development time for memory cells having a threshold voltage of a level similar to a level of a read voltage applied to a word line may have an effect that increases the read voltage for performing a sense operation. Further, in a read operation, an increase in development time for memory cells having a threshold voltage around a read voltage has an effect that decreases the read voltage for performing a sensing operation. Thus, sensing a sensing node of a page buffer a plurality of times at different development times may have an effect that varies a word line voltage for pre-charging and sensing a bit line. For example, a sense operation at different development times has the same effect as read voltages of different levels applied to a word line.FIGS. 6A and 6B are diagrams illustrating different read voltages of a distribution valley and corresponding development times. As illustrated in FIG. 6A, an OVS operation for searching distribution models of states S 1 and S 2 may be performed from a plurality of sensing operations. The plurality of acquisition operations may be performed in each of a plurality of page buffer groups simultaneously.Referring to FIG. 6B, an OVS operation may be performed in such a manner that first page buffers PGB 1 and second page buffers PGB 2 sequentially latch sensing nodes at the same time during different development periods to store a sensing result.A precharge operation may be performed from a time point T 0 to a time point T 1. A first bit line and a first detection node connected to each of the first page buffers PBG1 may be loaded to perform the precharge operation. When bit line setup signals are activated, the sense node and the first bit line may be precharged to a specific level. When a first bit line establishment signal is inactivated to a high level at a time T1, a precharge circuit of each of the first page buffers PBG1 may be turned off. In addition, when a second bit line establishment signal is deactivated to a high level at a time T2 subsequent to the time T1, a precharge circuit of each of the second page buffers PBG2 may be turned off. In this case, a level of a sensing node of each of the first page buffers PBG 1 and a level of a sensing node of each of the second page buffers PBG 2 may vary with the intensity of a current flowing to a corresponding bit line depending on whether a memory cell is turned on or off.As illustrated in FIG. 6B, each of the first page buffers PBG 1 may pre-charge a sensing node from a time T 0 to a time T 1, and may develop the first bit lines from the time T 1 to a time T 4. Each of the second page buffers PBG 2 may pre-charge a sensing node from time T 0 to time T 1, and may develop the second bit lines from time T 2 to time T 4, where time T 2 is later than time T 1.A first sensing operation may include a latch reset (nS) sensing operation performed at a time T 3 and a latch set (S) sensing operation performed at a time T 5. First cell count information may be calculated using ON cell count values of the latch reset (nS) detection operation and the latch set (S) detection operation in the first page buffers PGB 1. In addition, second cell count information may be calculated using ON cell count values of the latch reset (nS) detection operation and the latch set (S) detection operation in the second page buffers PGB 2. A determination case (one of C 1, C 2, C 3, C 4, and C 5) corresponding to an optimum reading level corresponding to a distribution valley may be determined based on the first cell count information and the second cell count information of the first sensing operation. A development time tSODev 1, tSODev 2, tSODev 3, tSODev 4, and tSODev 5 of the second detection operation corresponding to the determined determination case may be determined. A time point T 9 at a time point T 7 may correspond to a precharge operation, and development and sensing operations may be performed from the time point T 7.FIG. 7 is a diagram illustrating read level offset compensation using an OVST according to an embodiment of the inventive concept.An offset of a development time corresponding to an optimal distribution valley based on an OVS operation may be determined. In the case of an uppermost page, the offset of the development time is +80 ns. In this case, a determination case of the OVS operation corresponds to a third determination case C 3 (case 3 in FIG. 7 ). The OVS circuit 155 (see FIG. 1 ) of the nonvolatile memory device 100 (see FIG. 1 ) may perform a first conversion operation on a determination case corresponding to an optimal development time of the OVS operation. The OVS circuit 155 may store or buffer data bits for each detection case.Then, OVS determination information OVSDI (see FIG. 1 ) may be output from the nonvolatile memory device 100 to the controller 200 (see FIG. 1 ). The controller 200 may search a read level offset (+20 mV) corresponding to the OVS determination information, for example, the OVS determination case C 3 in the OVST. In this case, the controller 200 may perform a second conversion operation at a read level corresponding to the OVS determination case. Finally, the controller 200 may compensate a default / past read level using the OVST. It is understood that when the OVS determination case was C1 or case 1, the read level offset would be -20 mV, for example.FIGS. 8A and 8B illustrate an OVST according to an embodiment of the inventive concept.Referring to FIG. 8A, there are shown eight states S1, S2, S3, S4, S5, S6, S7 and S8 corresponding to a 3-bit memory cell, and seven read levels R1, R2, R3, R4, R5, R6 and R7 for discriminating the states S1 to S8. Referring to FIG. 8B, OVST includes offsets for detection cases C1 to C5 corresponding to the seven read levels R1 to R7.Although five OVS determination cases are illustrated in FIG. 8B, it is understood that the number of determination cases according to the present embodiment is not limited thereto.FIGS. 9A, 9B, and 9C illustrate an example of an optimal valley search using an OVST according to an embodiment of the inventive concept when a predefined table (PDT) offset is deficient.Referring to FIG. 9A, it is assumed that a memory cell degrades more than one PDT offset (e.g., -50 mV). Under the assumption as shown in FIG. 9B, a read operation using only an existing PDT offset (-50 mV) has a high read miss probability. In addition, as illustrated in FIG. 9C, an optimal read offset (-110 mV) obtained by adding an OVST offset (-60 mV) to the existing PDT offset (-50 mV) may be reflected to perform a read operation according to an embodiment of the present inventive concept at an optimal distribution valley. As a result, the read operation may have a high read best probability.FIGS. 10A, 10B, and 10C illustrate an example of an optimum valley search using an OVST according to an embodiment of the inventive concept when a PDT offset is excessive. Referring to FIG. 10A, a memory cell is assumed to degrade less than a PDT offset (e.g., -90 mV). Under the assumption illustrated in FIG. 10B, a read operation using only an existing PDT offset (-90 mV) has a high read miss probability. In addition, as illustrated in FIG. 10C, an optimal read offset (-30 mV) obtained by adding an OVST offset (+60 mV) to the existing PDT offset (-90 mV) may be reflected to perform a read operation according to an embodiment of the present inventive concept at an optimal distribution valley. As a result, the read operation has a high read best probability.The offset compensation methods illustrated in FIGS. 9C and 10C are not intended to limit the present inventive concept.The read operation of the nonvolatile memory device 100 according to an embodiment of the inventive concept may be performed in a normal mode or an OVS mode. The OVS mode may be applied to at least one state.FIG. 11A illustrates an example of a distribution to which an OVS mode of a read operation according to an embodiment of the inventive concept is applied.Referring to FIG. 11A, an OVS operation may be applied only to a highest state (e.g., S 8). It is understood that a state to which the OVS operation is applied is not limited to the highest state S 8.FIG. 11B illustrates an example of distributions to which an OVS mode of a read operation according to another embodiment of the inventive concept is applied.Referring to FIG. 11B, the OVS operation may be applied to some of the states (e.g., S 6, S 7, and S 8). The three states to which the OVS operation is applied are illustrated in FIG. 11B, but the present inventive concept is not limited thereto.FIG. 11C illustrates an example of distributions to which an OVS mode of a read operation according to another embodiment of the inventive concept is applied. Referring to FIG. 11C, the OVS operation may be applied to all states (e.g., S 1 to S 8).In FIGS. 11A, 11B and 11C, the application of the OVS mode to states of a 3-bit memory cell (a triple-level cell (TLC)) has been described. However, a memory cell according to an embodiment of the present inventive concept is not limited to TLC. A memory cell according to an embodiment of the present inventive concept may be a 4-bit memory cell (a four-level cell (QLC)). In this case, the OVS mode may be applied to at least one state among 16 states.FIG. 12 is a flowchart illustrating a reading method of a storage device according to an embodiment of the inventive concept. Referring to FIGS. 1 to 12, a read operation of the storage device 10 is performed as follows.The storage device 10 may receive a read request from a host (e.g., the read request may be provided externally from the host). The storage device 10 may identify a past of such a read request. A check as to whether there was a currently received read request may be made in a past buffer (S 110). If there is a currently received read request among previous read requests stored in the past buffer, a past read operation may be performed (S 111). In this case, the past read operation may be performed at an optimum read level included in a past read level table HRT. If there is no current read request among the previous read requests stored in the past buffer, a normal read operation may be performed (S 112). In this case, the normal read operation may be performed at a standard read level.As a result of the past read operation or the normal read operation, a determination as to whether a UECC occurs may be made (S 113). The UECC means that read data cannot be recovered by the ECC circuit 230 (see FIG. 1 ). If the UECC does not occur, the read operation may be terminated immediately. When the UECC occurs, an OVS mode is activated (S 114), and the nonvolatile memory device 100 (see FIG. 1 ) may perform a read retry operation according to the OVS mode. The read retry operation may include a read operation using a PDT and OVS. For example, a read level offset of the PDT and an OVS operation may be performed to perform the read retry operation (S 115).A determination as to whether the read retry operation exists may be made (S 116). As a result of the determination, offset information corresponding to an OVS determination case may be determined using an OVST when the read retry operation exists (S 117). A past read level table HRT into which offset information of the OVST and offset information of the PDT are reflected may be updated (S 118). The updating of the past read level table HRT may be performed periodically or non-periodically.If the read retry operation fails, the controller 200 may perform an off-chip valley search operation for restoring data (S 119). The off-chip valley search means that a distribution valley is searched by sequentially scanning a predetermined voltage period while the predetermined voltage period is increased or decreased by a predetermined voltage.A read operation may be performed according to a distribution valley based on the off-chip valley search operation, and a determination as to whether the read operation fails may be made (S 120). If the read operation fails, the read operation may be terminated. If the read operation fails, a UECC may occur for a read request from a host. The UECC may be output to the host.The read operation of the nonvolatile memory device 100 according to an embodiment of the inventive concept may include a first read operation performed according to a first read command and a second read operation performed according to a second read command. The nonvolatile memory device 100 may perform a read operation using a standard read level in response to the first read command, and may perform an OVS operation in response to the second read command.In an embodiment of the inventive concept, a time of the second read operation may be longer than a time of the first read operation. In another embodiment of the inventive concept, the time of the second read operation may be the same as the time of the first read operation.FIG. 13 is a flowchart illustrating a reading method of a storage device according to another embodiment of the inventive concept. Referring to FIGS. 1 to 11 and FIG. 13, a read operation of the storage device 10 may be performed as follows.The nonvolatile memory device 100 (see FIG. 1 ) may perform a first read operation using a standard read level in response to a first command transmitted from the controller 200 (see FIG. 1 ) (S 210). Information corresponding to the standard reading level may be transmitted from the controller 200 together with the first command. Standard read level information may include optimum read level offset information of a past read level table HRT.The controller 200 may determine whether a UECC occurs as a result of the first read operation (S 220). If the UECC does not occur, the read operation may be terminated.When the UECC occurs, the nonvolatile memory device 100 may perform a second read operation using OVS detection in response to the second command transmitted from the controller 200. Thus, the read operation can be ended.FIG. 14 is a circuit diagram illustrating a process of extracting a read level offset from the storage device 10 according to an embodiment of the inventive concept. Referring to FIGS. 1 to 14, the read operation of the storage device 10 may be performed as follows.A default read level corresponding to a host or an internal read request may be determined. In an embodiment of the inventive concept, in the case of a past read operation, the default read level may be determined using read level offset information of an HRT. The controller 200 may transmit a standard read level to the nonvolatile memory device 100 along with a first read command for a page 1. The nonvolatile memory device 100 may perform a main sensing operation using a standard read level based on the first read command. Data read in the main sensing operation is output to the controller 200.The controller 200 may determine whether read data received from the nonvolatile memory device 100 passes through the ECC circuit 230. When the read data passes through the ECC circuit 230, a read operation may be ended. When the read data does not pass through the ECC circuit 230, the controller 200 may enable an OVS mode of the nonvolatile memory device 100, and may transmit a second read command for the page 2 to the nonvolatile memory device 100. The second read command may include information for enabling the OVS mode.The nonvolatile memory device 100 may perform an OVS sensing operation and a main sensing operation on the page 1 in response to the second read command. The OVS detection operation may be applied to only a predetermined state. At the same time, the nonvolatile memory device 100 may perform the main sensing operation in a state where the OVS sensing operation is not performed. Data read by the OVS sensing operation and the main sensing operation may be output to the controller 200.Then, the controller 200 may transmit a specific command (for example, a feature fetch command) to the nonvolatile memory device 100 to obtain OVS determination information. The nonvolatile memory device 100 may output OVS determination information to the controller 200 in response to the specific command. Then, the controller 200 may extract a read level offset using the OVS determination information and apply the extracted read level offset to a past read level table (HRT).In addition, a determination may be made as to whether the read data passes through the ECC circuit 230 again. When the read data passes through the ECC circuit 230, the read operation may be ended. When the read data does not pass through the ECC circuit 230, the controller 200 may enable the OVS mode of the nonvolatile memory device 100, and may transmit a second read command for the page 1 to the nonvolatile memory device 100 again. In this case, a transmitted standard read level may include a lowest read level applied to the past read level table HRT.Then, the nonvolatile memory device 100 may perform an OVS sensing operation and a main sensing operation on the page 1 in response to the second read command. Data read by the OVS sensing operation and the main sensing operation may be output to the controller 200.Then, the controller 200 may transmit a specific command to the nonvolatile memory device 100 to obtain OVS determination information. The nonvolatile memory device 100 may output the OVS determination information to the controller 200 in response to the specific command. Then, the controller 200 may extract a read level offset using the OVS determination information, and may apply the extracted read level offset to the past read level table HRT.In an embodiment of the inventive concept, the normal read operation may be performed by a standard read level, and the standard read level may be changed by OVS determination information. In an embodiment of the inventive concept, the specific instruction may include a feature fetch instruction. In an embodiment of the inventive concept, performing an on-chip valley search operation may include performing a plurality of sensing operations at development times corresponding to different determination cases, respectively, and performing a sensing operation at a selected development time according to a result of the plurality of sensing operations. In an embodiment of the inventive concept, the reading method may further include storing determination case information corresponding to the selected development time, and outputting the determination case information through a plurality of data lines.FIG. 15 is a circuit diagram illustrating a read operation using a read level offset extracted from a storage device according to an embodiment of the inventive concept. Referring to FIG. 15, a read operation using a read level offset may be performed as follows.As shown in FIG. 15, a read level offset corresponding to the OVS sensing operation may be applied to the standard read level. Then, the controller 200 may transmit a first read command for the second page 2 to the nonvolatile memory device 100 together with the standard read level. The nonvolatile memory device 100 may perform a main sensing operation using an optimal standard read level in response to the first read command. Data read in the main sensing operation may be output to the controller 200. Since the read data is read by an optimum read level, there is a high possibility that the read data passes through the ECC circuit 230. When the read data passes through the ECC circuit 230, the read operation may be ended. When the read data does not pass through the ECC circuit 230, data recovery may be performed by another protection code.Similar to the above-described read operation, a read operation using an optimal read level based on a first read command may be performed on one page 1 to the other third to m-th pages (page 3 to page m) in the same block.A read retry operation according to an embodiment of the present inventive concept may include an OVS operation. However, the read retry operation according to an embodiment of the present inventive concept is not limited to the OVS operation.FIG. 16 is a circuit diagram illustrating a read operation of a storage device according to another embodiment of the inventive concept. Referring to FIGS. 1 and 16, a read operation of a storage device may be performed as follows.A host may transmit a read request together with an address ADD to the storage device 10 (see FIG. 1 ) (S 30). The controller 200 of the storage device 10 may receive the read request and may search a past buffer to determine whether to perform a past read operation or a normal read operation, and may transmit a normal read command / past read command corresponding to the determined operation to a nonvolatile memory device (NVM) 100 (see FIG. 1 ) (S 31). The nonvolatile memory device 100 may perform a read operation in response to the normal read command / past read command (S 31), and may transmit read data to the controller 200 (S 32).Then, the controller 200 may perform an error correction operation on data read from the ECC circuit 230 (S 33). If there is no error or if an error is correctable, read data or corrected data may be transmitted to the host (S 34- 1).If an error is uncorrectable, the controller 200 may transmit a read retry command to the nonvolatile memory device 100 (S 34- 2). The nonvolatile memory device 100 may perform a read operation in response to the read retry command, and may transmit the read data to the controller 200 (S 35). Then, the controller 200 may perform an error correction operation again on the data read by the ECC circuit 230 (S 36). If there is no error or if an error is correctable, read data or corrected data may be transmitted to the host (S 37). Then, the controller 200 may transmit a specific command to the nonvolatile memory device 100 to obtain read retry information having optimal read level information (S 38). The nonvolatile memory device 100 may output the read retry information in response to the specific command (S 39). Then, the controller 200 may update a past read level table HRT using the read retry information (S 40).Then, when a read request for the same address ADD is received from the host (S41), the storage device 10 transmits a past read command to the nonvolatile memory device 100 using the optimum read level reflected into the past read level table HRT (S42).In the read operation of the storage device 10 illustrated in FIG. 16, a past read operation is performed. However, the storage device 10 according to an embodiment of the present inventive concept is not limited thereto. For example, the storage device 10 may not perform the past read operation.FIG. 17 is a circuit diagram illustrating a read operation of another storage device according to another embodiment of the inventive concept. Referring to FIG. 17, unlike the read operation illustrated in FIG. 16, a past read operation may not be performed and normal read operations are performed (S 31 aand S 42 a), the normal read operation may be performed using an optimal read level included in a standard read level table. The default read level may include an optimal read level based on read retry information.The nonvolatile memory device 100 according to an embodiment of the inventive concept may define OVS determination cases for all states.FIGS. 18A and 18B illustrate examples of OVS determination cases of a nonvolatile memory device according to embodiments of the inventive concept. Referring to FIG. 18A, five determination cases are shown for respective OVS determination levels R 1 to R 5. Referring to FIG. 18B, seven determination cases are shown for respective OVS determination levels R 1 to R 7. In an embodiment of the inventive concept, at least one of the seven determination cases may be set to each of most significant / mean / least significant bit (MSB / CSB / LSB) sides.It should be understood that the number of determination cases corresponding to a determination level according to an embodiment of the inventive concept is not limited thereto.A decoding operation may be performed to output OVS determination information corresponding to the OVS determination case. However, the present inventive concept is not limited thereto. Output of OVS determination information according to an embodiment of the present inventive concept may be implemented such that the OVS determination case and a program state of a cell are mapped in one-to-one correspondence without performing a decoding operation on the OVS determination case.FIG. 19 illustrates an example of OVS determination information and a method of outputting the OVS determination information according to an embodiment of the inventive concept.As shown in FIG. 19, OVS determination cases may match states in a one-to-one match. For example, case 1 may match state [0] and case 6 may match state [5]. In an embodiment of the inventive concept, the determination case may not match the most significant state.FIG. 20 illustrates an example of outputting OVS determination information as a specific command.An example of a time point at which OVS determination information is output based on a specific command is illustrated in FIG. 20. A plurality of pieces of OVS determination information for a first mat address MAT2 are output. The output OVS determination information may include first determination level detection result information R 6, second determination level detection result information R 4, and third determination level detection result information R 2.The storage device 10 shown in FIGS. 1 to 20 changes a standard read level from normal read operations / past read operations using a first table PDT and a second table OVST. However, a storage device of the present inventive concept is not limited thereto. The storage device according to an embodiment of the present inventive concept may change a standard reading level of normal read operations / past read operations using only one OVST.FIG. 21 illustrates a storage device 20 according to another embodiment of the inventive concept.Referring to FIG. 21, the storage device 20 does not have a first table PDT compared to the storage device 10 illustrated in FIG. 1, and may include a controller 200 afor updating a past read level table HRT using an OVST. The storage device 20 of FIG. 21 further illustrates the CLE, ALE, CE(s), WE, RE, DQS(s), and the DQ pins.The storage device according to an exemplary embodiment of the inventive concept may include a coarse offset table for coarsely managing an offset and a fine offset table for finely managing an offset with respect to table management.FIG. 22 illustrates a storage device 30 according to another embodiment of the inventive concept. Referring to FIG. 22, the storage device 30 may include a nonvolatile memory device 100 and a controller 200 bfor controlling the nonvolatile memory device 100.The controller 200 bmay manage a past read level table using a coarse offset table and a fine offset table, and may transmit an optimal read level to the nonvolatile memory device 100 based on the past read level table. The nonvolatile memory device 100 may perform a read operation using the optimal read level. In an embodiment of the inventive concept, the fine offset table may include offset information corresponding to OVS determination information OVSDI based on an OVS operation.The storage device according to an exemplary embodiment of the inventive concept may be additionally reflected into a past read level table based on surrounding information.FIG. 23 illustrates a storage device 40 according to another embodiment of the inventive concept. Referring to FIG. 23, the storage device 40 may include a nonvolatile memory device 100 and a controller 200 cto control the nonvolatile memory device 100.The controller 200 cmay additionally reflect environmental information into a past read level table compared to the controller 200 illustrated in FIG. 1. The environmental information may be at least one of an elapsed program time associated with a memory cell to be read, a program temperature, a read temperature, a wordline address, a block address, a contact address, an erase cycle, a program cycle, a read cycle, and the like.FIG. 24 illustrates table management of a storage device 10 according to an embodiment of the inventive concept.Referring to FIG. 24, a nonvolatile memory device 100 may include a user area and a meta area. The user area may store user data and may be implemented as a plurality of memory blocks described in FIGS. 1 to 3, e.g., memory blocks BLK 1 to BLKz. The meta region may store management information for managing the nonvolatile memory device 100, and may be implemented as at least one memory block described in FIGS. 1 to 3, e.g., one of the memory blocks BLK 1 to BLKz. The meta-region may not be implemented as the same memory block as the user region.The meta-region may include a predefined table and an OVS table. The predefined table may store a value indicating the degree of variation of a read level depending on the elapse of a programming time. When the storage device 10 is initialized, the predefined table and the OVS table of the meta region may be loaded into a buffer memory 220 (for example, an SRAM, a DRAM, or the like) of the controller 200. In an embodiment of the inventive concept, a past read level table 223 of the buffer memory 220 may be periodically or non-periodically updated to the meta-region of the buffer memory 220.The controller 200 may be connected to the nonvolatile memory device 100 through a channel CH. The controller 200 may include a timer 202, at least one processor 210, and the buffer memory 220. Timer 202 may be implemented in hardware / software / firmware. The timer 202 may receive information associated with a time externally and generate / output a current time. For example, timer 202 may receive and count a system clock to generate the current time. In another embodiment of the inventive concept, the timer 202 may receive time information externally and may count an internal clock to generate a current time. In this case, the internal clock may be generated from an oscillator inside the storage device 10.The at least one processor 210 may control the overall operation of the storage device 10. The at least one processor 210 may perform various management operations such as cache / buffer management, firmware management, free storage collection management, wear level management, data deduplization management, data update / recovery management, bad block management, multi-stream management, host data and nonvolatile memory mapping management, quality of service (QoS) management, read level management, erase / program management, hot / cold data management, power loss protection management, dynamic thermal management, initialization management, redundant array of inexpensive disk (RAID) management, and the like.For example, the at least one processor 210 may drive a read level management module 212. The read level management module 212 may manage related tables to transmit an optimal read level to the nonvolatile memory device 100, as described with reference to FIGS. 1 to 23.In an embodiment of the inventive concept, the read level management module 212 may issue a special / specific command (for example, a feature fetch command) to the nonvolatile memory device 100 to receive OVS determination information OVSDI (see FIG. 1 ) and generate an OVS table 222 corresponding to the OVS determination information. In an embodiment of the inventive concept, the reading level management module 212 may update a past reading level table 223 using a predefined table 221 and the OVS table 222. In an embodiment of the inventive concept, the read level management module 212 may transmit an optimal read level to the nonvolatile memory device 100 during a normal read operation or a past read operation.The buffer memory 220 may temporarily store data required for driving. For example, the buffer memory 220 may store at least a predefined table 221, an OVS table 222, and a past read level table 223.The buffer memory 220 shown in FIG. 24 is disposed inside the controller 200. However, the present inventive concept is not limited thereto. The buffer memory 220 may be arranged as an external configuration of the controller 200. The controller 200 may further include a code memory storing at least one instruction. Since the at least one instruction stored in the code memory is executed by the at least one processor 210, various management operations can be performed. The controller 200 may further include a host interface device for connecting to a host and a nonvolatile interface device for connecting to the nonvolatile memory device 100.The nonvolatile memory device according to an exemplary embodiment of the inventive concept may be implemented in a chip-to-chip (C 2C) structure.FIG. 25 illustrates a nonvolatile memory device 1000 implemented in a C 2C structure according to an embodiment of the inventive concept.The C2C structure may mean that an upper chip including a cell region CELL is fabricated on a first wafer and a lower chip including a peripheral circuit region PERI is fabricated on a second wafer separately from the first wafer, and the upper chip and the lower chip are then bonded together. Here, the bonding process may be a method of electrically connecting a bonding metal formed on an uppermost metal layer on an upper chip and a bonding metal formed on an uppermost metal layer of a lower chip to each other. In an embodiment of the inventive concept, when a bonding metal is copper (Cu), Cu-to-Cu bonding may be performed. However, the inventive concept is not limited thereto. For example, the bonding metal may be formed of aluminum (Al) or tungsten (W).Each of the peripheral circuit region PERI and the cell region CELL of the nonvolatile memory device 1000 may include an external pad bonding region PA, a word line bonding region WLBA, and a bit line bonding region BLBA.The peripheral circuit region PERI may include a first substrate 1210, an interlayer insulating film 1215, a plurality of switching elements 1220 a, 1220 b, and 1220 cdisposed on the first substrate 1210, first metal films 1230 a, 1230 b, and 1230 cconnected to the plurality of switching elements 1220 a, 1220 b, and 1220 c, respectively, and second metal films 1240 a, 1240 b, and 1240 cdisposed on the first metal films 1230 a, 1230 b, and 1230 c. In an embodiment of the inventive concept, the first metal layers 1230 a, 1230 band 1230 cmay be formed of tungsten (W) having a relatively high electric resistance. In an embodiment of the inventive concept, the second metal layers 1240 a, 1240 band 1240 cmay be formed of copper (Cu) having a relatively low resistance.In FIG. 25, the first metal layers 1230 a, 1230 band 1230 cand the second metal layers 1240 a, 1240 band 1240 care illustrated, but the present inventive concept is not limited thereto. One or more additional metal layers may be further provided on metal layers 1240 a, 1240 band 1240 c. At least some of the one or more additional metal layers provided on the second metal layers 1240 a, 1240 band 1240 cmay be formed of aluminum (Al) or the like having a lower electrical resistance than copper (Cu) used to form the second metal layers 1240 a, 1240 band 1240 c.In an embodiment of the inventive concept, the interlayer insulating layer 1215 may be disposed on the first substrate 1210 to cover the plurality of switching elements 1220 a, 1220 b, and 1220 c, the first metal layers 1230 a, 1230 b, and 1230 c, and the second metal layers 1240 a, 1240 b, and 1240 c. In an embodiment of the inventive concept, the interlayer insulating layer 1215 may include an insulating material such as a silicon oxide, a silicon nitride, or the like.Lower bonding metals 1271 band 1272 bmay be provided on the second metal layer 1240 bin the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 1271 band 1272 bof the peripheral circuit region PERI may be electrically bonded to upper bonding metals 1371 band 1372 busing a bonding method. In an embodiment of the inventive concept, the lower bonding metals 1271 band 1272 band the upper bonding metals 1371 band 1372 bmay be formed of aluminum (Al), copper (Cu), tungsten (W), or the like. Further, the upper bonding metals 1371 band 1372 bin the cell region CELL may be referred to as first metal pads, and the lower bonding metals 1271 band 1272 bin the peripheral circuit region PERI may be referred to as second metal pads.The cell area CELL may include at least one memory block. In an embodiment of the inventive concept, the cell region CELL may include a second substrate 1310 and a common source line 1320. A plurality of word lines 1331, 1332, 1333, 1334, 1335, 1336, 1337, and 1338 (collectively 1330) may be stacked on the second substrate 1310 in a direction perpendicular to an upper surface of the second substrate 1310 (e.g., a Z-axis direction). In an embodiment of the inventive concept, string selection lines and a ground selection line may be respectively disposed above and below the word lines 1330. In an embodiment of the inventive concept, a plurality of word lines 1330 may be disposed between the string selection lines and the ground selection line.In the bit line bonding region BLBA, a channel pattern CH may extend in a direction (e.g., a Z-axis direction) perpendicular to the upper surface of the second substrate 13 10 to penetrate the word lines 1330, the string selection lines, and the ground selection line. The channel structure CH may include a data storage layer, a channel layer, a buried insulating layer, and the like. The channel layer may be electrically connected to a first metal layer 1350 cand a second metal layer 1360 c. For example, the first metal layer 1350 cmay be a bit line contact and the second metal layer 1360 cmay be a bit line. In an embodiment of the inventive concept, the bit line 1360 cmay extend in a first direction (e.g., a Y-axis direction) parallel to the top surface of the second substrate 1310.As illustrated in FIG. 25, a region where the channel pattern CH and the bit line 1360 care arranged may be the bit line bonding region BLBA. In an embodiment of the inventive concept, the bit line 1360 cin the bit line bonding region BLBA may be electrically connected to switching elements 1220 cthat provide a page buffer 1393 in the peripheral circuit region PERI. The bit line 1360 cmay be connected to upper bonding metals 1371 cand 1372 cin the peripheral circuit area PERI. The upper bonding metals 1371 cand 1372 cmay be connected to lower bonding metals 1271 cand 1272 cconnected to the switching elements 1220 cof the page buffer 1393.In the word line bonding region WLBA, the word lines 1330 may extend in a second direction (e.g., an X-axis direction) parallel to the top surface of the second substrate 1310 and perpendicular to the first direction. In an embodiment of the inventive concept, the wordline bonding region WLBA may be connected to a plurality of cell contact plugs 1341, 1342, 1343, 1344, 1345, 1346, and 1347 (collectively 1340). For example, the word lines 1330 and the cell contact plugs 1340 on pads in which at least some of the word lines 1330 are provided to extend in different lengths may be connected to each other in the second direction. In an embodiment of the inventive concept, a first metal layer 1350 band a second metal layer 1360 bmay be sequentially connected to upper portions of the cell contact plugs 1340 connected to the word lines 1330. In an embodiment of the inventive concept, the cell contact plugs 1340 in the word line bonding region WLBA may be connected to the peripheral circuit region PERI through the upper bonding metals 1371 band 1372 bin the cell region CELL and the lower bonding metals 1271 band 1272 bin the peripheral circuit region PERI.In an embodiment of the inventive concept, the cell contact plugs 1340 may be electrically connected to switching elements 1220 bforming a row decoder 1394 in the peripheral circuit region PERI. In an embodiment of the inventive concept, an operation voltage of the switching elements 1220 bforming the row decoder 1394 may be different from an operation voltage of the switching elements 1220 cforming the page buffer 1393. For example, the operating voltage of the switching elements 1220c forming the page buffer 1393 may be higher than the operating voltage of the switching elements 1220b forming the row decoder 1394.A common source line contact plug 1380 may be disposed in the external pad bonding region PA. In an embodiment of the inventive concept, the common source line contact plug 1380 may be formed of a conductive material such as a metal, a metal compound, polysilicon, or the like. The common source line contact plug 1380 may be electrically connected to the common source line 1320. A first metal layer 1350 aand a second metal layer 1360 amay be sequentially stacked on the common source line contact plug 1380. For example, a region where the common source line contact plug 1380, the first metal layer 1350 a, and the second metal layer 1360 aare disposed may be an external pad bonding region PA.Input / output pads 1205 and 1305 may be disposed in the external pad bonding region PA. Referring to FIG. 25, a lower insulating layer 1201 may be provided below the first substrate 1210 to cover a lower surface of the first substrate 1210. A first input / output pad 1205 may be provided on the lower insulating layer 1201. In an embodiment of the inventive concept, the first input / output pad 1205 may be connected to at least one of the plurality of switching elements 1220 a, 1220 b, and 1220 cdisposed in the peripheral circuit region PERI through the first input / output contact plug 1203. In an embodiment of the inventive concept, the first input / output pad 1205 may be separated from the first substrate 1210 by the lower insulating layer 1201. In addition, a side insulating layer may be disposed between the first input / output contact plug 1203 and the first substrate 1210 to electrically separate the first input / output contact plug 1203 and the first substrate 1210 from each other. In the present embodiment, the second input / output pad 1305 is electrically connected to a switching element 1220 a.Referring to FIG. 25, an upper insulating layer 1301 may be provided on the second substrate 1310 to cover the upper surface of the second substrate 1310. A second input / output pad 1305 may be disposed on the upper insulating layer 1301. In an embodiment of the inventive concept, the second input / output pad 1305 may be connected to at least one of the plurality of switching elements 1220 a, 1220 b, and 1220 cdisposed in the peripheral circuit region PERI through the second input / output contact plug 1303.In an embodiment of the inventive concept, the second substrate 1310, the common source line 1320, and the like may not be disposed in a region where the second input / output contact plug 1303 is disposed. The second input / output pad 1305 may not overlap the word lines 1380 in the third direction (e.g., the Z-axis direction). Referring to FIG. 25, the second input / output contact plug 1303 may be separated from the second substrate 1310 in a direction parallel to the upper surface of the second substrate 1310. In addition, the second input / output contact plug 1303 may be connected to the second input / output pad 1305 through the interlayer insulating film 1315 in the cell region CELL.In an embodiment of the inventive concept, the first input / output pad 1205 and the second input / output pad 1305 may be selectively provided. For example, the nonvolatile memory device 1000 may include only the first input / output pad 1205 provided on the first substrate 1201 or only the second input / output pad 1305 provided on the second substrate 1301. In another embodiment of the inventive concept, the nonvolatile memory device 1000 may include both the first input / output pad 1205 and the second input / output pad 1305.A metal pattern provided on an uppermost metal layer may be present as a dummy pattern, or may be present neither in the external pad bonding region PA nor the bit line bonding region BLBA included in both the cell region CELL and the peripheral circuit region PERI.In the external pad bonding region PA, the nonvolatile memory device 1000 according to an embodiment of the inventive concept may include a lower metal pattern 1273 aprovided on the uppermost metal layer in the peripheral circuit region PERI to correspond to an upper metal pattern 1372 aprovided on the uppermost metal layer in the cell region CELL and having the same cross-sectional shape as the upper metal pattern 1372 in the cell region CELL to be connected to each other. The lower metal pattern 1273 aprovided on the uppermost metal layer in the peripheral circuit region PERI may not be connected to an additional contact in the peripheral circuit region PERI. Similarly, the nonvolatile memory device 1000 may include, in the external pad bonding area PA, an upper metal pattern 1372 aprovided on the uppermost metal layer in the peripheral circuit area PERI to correspond to a lower metal pattern 1273 aprovided on the uppermost metal layer in the peripheral circuit area PERI and having the same shape as the lower metal pattern 1273 ain the peripheral circuit area PERI.Lower bonding metals 1271 band 1272 bmay be provided on the second metal layer 1240 bin the word line bonding region WLBA. In an embodiment of the inventive concept, in the word line bonding region WLBA, the lower bonding metals 1271 band 1272 bin the peripheral circuit region PERI may be electrically connected to the upper bonding metals 1371 band 1372 bin the cell region CELL by Cu-to-Cu bonding.Further, the nonvolatile memory device 1000 may include, in the bit line bonding area BLBA, an upper metal pattern 1392 provided on the uppermost metal layer in the cell area CELL to correspond to a lower metal pattern 1252 provided on the uppermost metal layer in the peripheral circuit area PERI and having the same cross-sectional shape as the lower metal pattern 1252 in the peripheral circuit area PERI. A contact may not be formed on the metal pattern 1392 provided on the uppermost metal layer in the cell region CELL.In an embodiment of the inventive concept, according to a metal pattern formed in an uppermost metal layer in the cell region CELL or the peripheral circuit region PERI, a reinforcing metal pattern having the same cross-sectional shape as the metal pattern may be formed in an uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI. No contact may be formed on the reinforcing metal pattern.The nonvolatile memory device according to an embodiment of the inventive concept may perform a main sensing operation using a standard read level and an OVS sensing operation using an on-chip-valley search. A controller controlling the nonvolatile memory device may include a predefined table PDT and an OVST to correct a read miss. The predefined table PDT is a read level offset table predetermined in consideration of preservation, and may be referred to when a read miss occurs, and may be used to change a read level. The OVST is a table in which a development time depending on each valley position is converted into a read level offset using an OVS detection operation, and may include a product of the number of valleys (N) searched by the OVS detection operation and the number of program states (M). For example, when the number of TLC valley search determination cases is 5, N is 5 and M is 7. the OVST is a table pre-formed in an evaluation step of a nonvolatile memory device (for example, a NAND flash memory). In a first step, a table is formed which compares a determination case with a development time offset. In a second step, a table is formed that compares a development time offset with a read level offset. In a third and last step, a table comparing a determination case with a read level offset is formed as the OVST.The OVST is stored in a memory of the controller and may be used to determine a read level of the next word line according to a determination case information output as a status output / a fetch feature / a UIB output during a solution operation. The predefined table PDT and the OVST included in the controller may be used after adding two level offsets. Alternatively, only the level offset of the OVST may be used.A main sense operation may be performed using a standard read level before a read miss occurs. On the other hand, an OVS detection operation may be performed when a read miss occurs, and accordingly a read retry operation and a restore operation are performed. The OVS detection operation may include a first detection step of searching an OVS detection case based on a cell count, and a second detection step of changing an actual development time based on the searched detection case and detecting the changed actual development time.In a read method of a nonvolatile memory device according to an embodiment of the inventive concept, a sensing operation using an on-chip valley search may be activated only during a read retry operation after a read miss has occurred. When a read operation passes an optimal development time searched by an OVS acquisition operation during a read retry operation, OVS determination information corresponding to the development time at which the read operation passes may be output as a status output / a fetch feature / a UIB output after the read operation is finished. In an embodiment of the inventive concept, the development time may be converted into a read level offset corresponding to OVS determination information by a pre-formed OVST, and read level offset information may be stored by adding PDT information and OVST output information to a past read level table. In an embodiment of the inventive concept, a read operation in the next word line read operation may be performed at a past read level updated to first PDT information and OVST information. In this case, an OVS detection operation is not activated. Then, when a read miss occurs at the past read level in the next word line read operation, a read operation may be performed using second PDT information. In this case, the OVS sensing operation may be reactivated.In the storage device and the reading method of the storage device according to an embodiment of the inventive concept, an optimal valley position in a current read operation may be searched in a first read step and data may be acquired in a second read step, and then information on the searched OVS valley position may be output as a status output or a retrieval feature. In the next read operation, the storage device may determine the next read level using the OVS position information, an output to the previous read operation, and a pre-formed table.In the storage device and the reading method of the storage device according to an embodiment of the inventive concept, position information can be obtained by a development time after searching a valley in a data recovery flow. After searching the valley, the position information may be output as a status output or a retrieval feature, and a table comparing a development time to a read level conversion may be pre-formed to correct a read level.In the storage device and the reading method of the storage device according to an embodiment of the inventive concept, since a UECC is issued and then used only as a protection code, a reading time may be increased only when a first protection code is input, and a user reading time may not be increased.In the storage device and the reading method of the storage device according to an embodiment of the inventive concept, an on-chip valley search may be used for only a recovery flow after a UECC is issued. In addition, a table for converting a development time to a read level may be used as a correction device, and a read operation for data recovery may be performed only once.As described above, according to embodiments of the inventive concept, OVS determination information may reflect to an optimal reading level to perform a read operation to prevent performance degradation while ensuring reliability.

Claims

A controller, comprising: control ports for providing control signals to a nonvolatile memory device (100; 1000); a buffer memory (220) configured to store a first table, a second table, and a third table; and an error correction code (ECC) circuit (230) configured to store an error in first data stored according to a first read command from the nonvolatile memory device (100; 1000), wherein the first table stores first offset information, the second table stores second offset information, and the third table stores third offset information, wherein the third offset information corresponds to a past read level and is determined by the first offset information and the second offset information, and wherein the error of the first data is uncorrectable by the error correction code circuit (230), an on-chip valley search operation from the nonvolatile memory device (100; 1000) according to a second read command, determination information of the on-chip valley search operation according to a specific command is received, and the second offset information corresponding to the determination information is generated, and wherein an off-chip valley search operation is performed when a read operation based on the on-chip valley search operation fails.The controller of claim 1, wherein the first offset information includes read level offset information based on an elapsed programming time.The controller according to claim 1 or 2, wherein the determination information includes information corresponding to a development time of the on-chip valley search operation, and the second offset information includes read level offset information corresponding to the development time.The controller according to any one of claims 1 to 3, wherein the past read level includes a standard read level of a normal read operation or a past read operation.The controller according to any one of claims 1 to 4, wherein when an external read request is received, a determination is made as to whether a normal read operation or a past read operation is to be performed.The controller of any of claims 1 to 5, wherein the specific instruction includes a feature fetch instruction.The controller according to any one of claims 1 to 6, wherein the control signals may include an enable (CLE) signal for latching commands, an enable (ALE) signal for latching addresses, a chip enable (CE) signal, a write enable (WE) signal, a read enable (RE) signal, and DQS signals, the nonvolatile memory device (100; 1000) performs a read operation by latching a command or an address at an edge of the WE signal according to the CLE signal and the ALE signal.

Images