Semiconductor package

Abstract

Semiconductor package, comprehensive: a first stack (100) containing a first semiconductor substrate (110); a multitude of through-silicon vias, TSVs (150) passing through the first semiconductor substrate (110); a second stack (200) on top of the first stack (100), wherein the second stack (200) contains a second surface (100U) facing a first surface of the first stack (100); a first contact point (180, 180a, 180b) on the first surface of the first stack (100), wherein the first contact point (180, 180a, 180b) is in contact with one or more of the plurality of TSVs (150); a second contact point (270) on the second surface (200L) of the second stack (200); a hump (28, 48, 190, 290, 390) connecting the first contact point (180, 180a, 180b) and the second contact point (270); a first redundancy contact point (185, 185a-e) on the first surface of the first stack (100), wherein the first redundancy contact point (185, 185a-e) is spaced apart from the first contact point (180, 180a, 180b) and is not in direct contact with the plurality of TSVs (150); a second redundancy contact point (275) on the second surface (200L) of the second stack, wherein the second redundancy contact point (275) is spaced apart from the second contact point (270); and a redundancy hump (49, 95, 195, 295) connecting the first redundancy contact point (185, 185a-e) and the second redundancy contact point (275), where: the first contact point (180, 180a, 180b) and the first redundancy contact point (185, 185a-e) are electrically connected to each other, and the second contact point (270) and the second redundancy contact point (275) are electrically connected to each other.

Description

BACKGROUND 1. Area

[0001] The embodiments relate to a semiconductor package. 2. Description of the state of the art

[0002] US Patent 2010 / 0 224 977 A1 discloses a semiconductor device and a method for its fabrication. The semiconductor device can comprise a substrate with a cell region and a scribbled track region defining the cell region, at least one contact point on the cell region, at least one through-electrode penetrating the substrate and electrically connected to the at least one contact point, and at least one dummy through-electrode penetrating the substrate and spaced apart from the at least one through-electrode. The semiconductor device can further comprise at least one conductive pattern on the substrate that electrically connects the at least one through-electrode to the at least one dummy through-electrode.

[0003] With the rapid development of the electronics industry and user demand, electronic devices have become smaller, lighter, and more multifunctional. Accordingly, smaller, lighter, and multifunctional semiconductor packages can be used in these electronic devices. SUMMARY

[0004] The embodiments can be realized by providing a semiconductor package comprising a first stack containing a first semiconductor substrate; a plurality of through-silicon vias (TSVs) passing through the first semiconductor substrate; a second stack on top of the first stack, the second stack comprising a second surface facing a first surface of the first stack; a first contact point on the first surface of the first stack, the first contact point being in contact with one or more of the plurality of TSVs; a second contact point on the second surface of the second stack; a ridge connecting the first contact point and the second contact point; and a first redundant contact point on the first surface of the first stack, the first redundant contact point being spaced apart from the first contact point and not in contact with the plurality of TSVs.a second redundant contact point on the second surface of the second stack, wherein the second redundant contact point is spaced apart from the second contact point; and a redundant hump connecting the first redundant contact point and the second redundant contact point, wherein: the first contact point and the first redundant contact point are electrically connected to each other, and the second contact point and the second redundant contact point are electrically connected to each other.

[0005] The embodiments can be realized by providing a semiconductor package comprising a first stack containing a central region and a peripheral region around the central region, wherein the first stack contains a first semiconductor substrate; a plurality of through-hole silicon vias (TSVs) passing through the first semiconductor substrate; one or more first contacts on a top surface of the peripheral region of the first stack, wherein the one or more first contacts are in contact with one or more of the plurality of TSVs; one or more first redundant contacts on the top surface of the peripheral region of the first stack, wherein the one or more first redundant contacts are spaced apart from the one or more first contacts and are not in contact with the plurality of TSVs;and one or more first connecting lines extending along the top of the edge region of the first stack to electrically connect the one or more first contact points and the one or more first redundant connection surfaces.

[0006] The embodiments can be realized by providing a semiconductor package comprising a first semiconductor chip containing a first semiconductor substrate and a first semiconductor device layer on a bottom side of the first semiconductor substrate; a second semiconductor chip containing a second semiconductor substrate and a second semiconductor device layer on a bottom side of the second semiconductor substrate on the first semiconductor chip; a plurality of first through-silicon vias (TSVs) traversing the first semiconductor substrate; a first contact point on a top side of the first semiconductor substrate, the first contact point being in contact with one or more of the plurality of first TSVs; a second contact point on a bottom side of the second semiconductor device layer; and a bump connecting the first contact point and the second contact point.a first redundant contact point on the top surface of the first semiconductor substrate, wherein the first redundant contact point is spaced apart from the first contact point and is not in contact with the plurality of first TSVs; a connecting line extending along the top surface of the first semiconductor substrate and connecting the first contact point and the first redundant contact point; a second redundant contact point on the underside of the second semiconductor device layer, wherein the second redundant contact point is spaced apart from the second contact point; and a redundant hump connecting the first redundant contact point and the second redundant contact point, wherein the second semiconductor device layer electrically connects the second contact point and the second redundant contact point. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The features will become clear to the person skilled in the art through the detailed description of exemplary embodiments with reference to the accompanying drawings, in which: Fig. Figure 1 is a layout diagram of a semiconductor package according to some embodiments. Fig. 2 is a cross-sectional view along the AA line from Fig. 1. Fig. Figure 3 is an enlarged view to describe area R1 of Fig. 2. Fig. 4A and Fig. Figure 4B shows enlarged views of semiconductor packages according to some embodiments. Fig. Figure 5 is a cross-sectional view of a semiconductor package according to some embodiments. Fig. Figures 6 to 11 are layout diagrams of semiconductor packages according to some embodiments. Fig. Figures 12 to 15 are cross-sectional views of semiconductor packages according to some embodiments. DETAILED DESCRIPTION

[0008] Although first, second, and similar terms are used here to describe different elements or components, these elements or components are not limited by these terms. These terms are used only to distinguish one element or component from another and are not intended to require a sequential inclusion of the elements. Accordingly, it should be understood that a first element or component described below may be a second element or component in the technical sense of this disclosure.

[0009] The following describes a semiconductor package according to several embodiments with reference to Fig. 1 to 3 described.

[0010] Fig. Figure 1 is a layout diagram of a semiconductor package according to some embodiments. Fig. 2 is a cross-sectional view along the AA line from Fig. 1. Fig. Figure 3 is an enlarged view to describe area R1 of Fig. 2.

[0011] With reference to Fig. 1 to 3, according to some embodiments, the semiconductor package can include a first stack 100, a second stack 200, a plurality of first through-silicon vias (TSVs) 150, a first contact point 180, a second contact point 270, a first bump 290, a first redundancy contact point 185, a second redundancy contact point 275 and a first redundancy bump 195.

[0012] The first stack of 100 can contain a central area CA and a marginal area EA. In one implementation, the marginal area EA can be, as in Fig. Figure 1 shows the first stack 100 lying around the central region CA and forming a boundary of the first stack 100. In one implementation, the first stack 100 can contain a boundary surface 100S that extends (e.g., longitudinally) in a second direction Y. The boundary region EA can be defined as a region spaced from the boundary surface 100S by a predetermined distance (e.g., inwards), for example, in a first direction X (intersecting the second direction Y). In one implementation, a distance D1 by which the boundary region EA is spaced from the boundary surface 100S (e.g., a width of the boundary region EA in the first direction X) can be less than or equal to approximately 200 µm.

[0013] The first stack 100 can contain a first surface 100L and a second surface 100U, which are opposite each other. In an implementation such as in Fig. As shown in Figure 2, the first surface 100L can be a bottom of the first stack 100, and the second surface 100U can be a top of the first stack 100.

[0014] The second stack of 200 can be stacked on top of the first stack of 100. The second stack of 200 can have a third surface 200L and a fourth surface 200U, which are opposite each other. The third surface 200L of the second stack of 200 can be opposite the second surface 100U of the first stack of 100. In one implementation, the third surface 200L can be the bottom of the second stack of 200, and the fourth surface 200U can be the top of the second stack of 200.

[0015] Each of the first stack of 100 and the second stack of 200 can be a substrate that forms or consists of the semiconductor package. In one implementation, each of the first stack of 100 and the second stack of 200 can be, for example, a printed circuit board (PCB), a ceramic substrate, or an intermediate connector. In another implementation, each of the first stack of 100 and the second stack of 200 can be a semiconductor chip containing a semiconductor device. In one implementation, as described below, the first stack of 100 and the second stack of 200 can be semiconductor chips.

[0016] In one implementation, the first stack 100 can contain a first semiconductor substrate 110 and a first semiconductor device layer 120, and the second stack 200 can contain a second semiconductor substrate 210 and a second semiconductor device layer 220.

[0017] Each of the first semiconductor substrate 110 and the second semiconductor substrate 210 can be, for example, a bulk silicon substrate or a silicon-on-insulator (SOI) substrate. In one implementation, both the first semiconductor substrate 110 and the second semiconductor substrate 210 can be a silicon substrate or contain other materials such as silicon germanium, silicon germanium-on-insulator (SGOI), indium antimonide, lead tellurium compounds, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. As used here, the term "or" is not exclusive; for example, "A or B" would include A, B, or A and B.

[0018] The first semiconductor device layer 120 can be located on the first semiconductor substrate 110, and the second semiconductor device layer 220 can be located on the second semiconductor substrate 210. In one implementation, the first semiconductor device layer 120 can cover a bottom surface of the first semiconductor substrate 110, and the second semiconductor device layer 220 can cover a bottom surface of the second semiconductor substrate 210. In one implementation, a bottom surface of the first semiconductor device layer 120 can form the first surface 100L of the first stack 100, and a bottom surface of the second semiconductor device layer 220 can form the third surface 200L of the second stack 200.

[0019] Each of the first semiconductor device layer 120 and the second semiconductor device layer 220 can contain a variety of different types of individual devices and an insulating layer between the lines. The variety of individual devices can include various microelectronic devices, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), such as a complementary metal-oxide-semiconductor transistor (CMOS), a large-scale integration (LSI) system, flash memory, dynamic random-access memory (DRAM), static random-access memory (SRAM), electrically erasable programmable read-only memory (EEPROM), phase-change random-access memory (PRAM), magnetoresistive random-access memory (MRAM), resistance random-access memory (RRAM), an image sensor such as a CMOS image sensor (CIS), a microelectromechanical system (MEMS), an active device, or a passive device.

[0020] In one implementation, a first protective layer 130 can be located on the first semiconductor substrate 110, and a second protective layer 230 can be located on the second semiconductor substrate 210. In one implementation, the first protective layer 130 can cover one top surface of the first semiconductor substrate 110, and the second protective layer 230 can cover one top surface of the second semiconductor substrate 210. In one implementation, one top surface of the first protective layer 130 can form the second face 100U of the first stack 100, and one top surface of the second protective layer 230 can form the fourth face 200U of the second stack 200.

[0021] Each of the first protective layer 130 and the second protective layer 230 can contain a non-conductive film (NCF). In one implementation, each of the first protective layer 130 and the second protective layer 230 can contain an insulating polymer. In another implementation, the first protective layer 130 and the second protective layer 230 can be formed, for example, by a spin coating process or a spraying process.

[0022] In an implementation, a base contact point 170 and a base bump 190 can be located on the first surface 100L of the first stack 100. A plurality of base contacts 170 can be located on the first surface 100L of the first stack 100. Each of the base contacts 170 can be electrically connected to the first semiconductor device layer 120. The base bump 190 can be connected to the base contact point 170. The base bump 190 can have various shapes, such as a column structure, a sphere structure, or a solder layer.

[0023] The multitude of first TSVs 150 can pass through the first semiconductor substrate 110. In one implementation, each of the first TSVs 150 can be exposed from or at the second surface 100U of the first stack 100 and pass through the first semiconductor substrate 110 and the first protective layer 130. Each of the first TSVs 150 can have a columnar shape extending in a third direction Z, e.g., a direction that intersects the first surface 100L and the second surface 100U.

[0024] A plurality of second TSVs 250 can pass through the second semiconductor substrate 210. In one implementation, each of the second TSVs 250 can be exposed from or at the fourth surface 200U of the second stack 200 and pass through the second semiconductor substrate 210 and the second protective layer 230. Each of the second TSVs 250 can have a columnar shape extending in the third direction Z, where the direction intersects the third surface 200L and the fourth surface 200U.

[0025] In one implementation, the first TSVs 150 can be connected to the first semiconductor device layer 120 via the first semiconductor substrate 110, and the second TSVs 250 can be connected to the second semiconductor device layer 220 via the second semiconductor substrate 210. In one implementation, the second semiconductor device layer 220 can be, as in Fig. Figure 3 shows a first intermediate conductor insulating film 222 and first conductors 224a, 224b, and 224c contained within the first intermediate conductor insulating film 222. The first conductors 224a, 224b, and 224c can be stacked sequentially from the underside of the second semiconductor substrate 210. The second TSV 250 can be electrically connected to the second semiconductor device layer 220 via the first conductors 224a, 224b, and 224c.

[0026] In one implementation, the second TSV 250 can be in contact (in direct contact) with a top line 224a of the first lines 224a, 224b, and 224c. The top line 224a of the second semiconductor device layer 220 can be a line that is closest to the second semiconductor substrate 210 (e.g., in the third direction Z) among the first lines 224a, 224b, and 224c.

[0027] In one implementation, each of the first TSV 150 and the second TSV 250 can contain a barrier film on a columnar surface and a buried conductive layer embedded within the barrier film. The barrier film can contain, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), ruthenium (Ru), cobalt (Co), manganese (Mn), tungsten nitride (WN), nickel (Ni), or nickel-boron (NiB). The buried conductive layer can contain, for example, copper (Cu), a copper alloy such as copper-tin (CuSn), copper-magnesium (CuMg), copper-nickel (CuNi), copper-zinc (CuZn), copper-palladium (CuPd), copper-gold (CuAu), copper-rhenium (CuRe), or copper-tungsten (CuW), tungsten (W), a tungsten alloy, Ni, Ru, or Co.

[0028] In one implementation, an insulating layer can be located between the first semiconductor substrate 110 and the first TSV 150, and between the second semiconductor substrate 210 and the second TSV 250. The insulating layer can be, for example, an oxide layer, a nitride layer, a carbide layer, a polymer, or a combination thereof.

[0029] A multitude of first contact points 180 can be located on the second surface 100U of the first stack 100. Each of the first contact points 180 can be in contact (in direct contact) with at least one of the multiple first TSVs 150. In one implementation, the first contact point 180 can be located on the first protective layer 130 and be in contact with the first TSV 150 exposed by the first protective layer 130.

[0030] In an implementation, the width W1 of the first contact point 180 (e.g. in the first direction X) can be in a range of 15 µm to 30 µm.

[0031] On the third surface 200L of the second stack 200, a plurality of second contact points 270 can be located. Each of the second contact points 270 can be electrically connected to the second semiconductor device layer 220. In one implementation, the second contact point 270 can be electrically connected to the individual devices of the second semiconductor device layer 220 or the second TSV 250.

[0032] Both the first contact point 180 and the second contact point 270 can contain, for example, aluminum (Al), Cu, Ni, W, platinum (Pt), gold (Au) or combinations thereof.

[0033] The first hump 290 can be located between the first contact point 180 and the second contact point 270. The first hump 290 can have various shapes, e.g., a column structure, a spherical structure, or a solder layer.

[0034] The first protrusion 290 can electrically connect the first contact point 180 and the second contact point 270. In one implementation, the first stack 100 and the second stack 200 can be electrically connected. In another implementation, the first semiconductor device layer 120 can be electrically connected to the second semiconductor device layer 220 or the second TSV 250 via the first TSV 150, the first contact point 180, the first protrusion 290, and the second contact point 270.

[0035] The first redundancy contact point 185 can be located on the second surface 100U of the first stack 100. The first redundancy contact point 185 can be spaced apart from the first contact point 180 (e.g., in the first direction X). In one implementation, the first redundancy contact point 185 can be out of contact with the plurality of first TSVs 150. In one implementation, the first protection layer 130 can completely cover a lower surface (e.g., facing the first stack 100) of the first redundancy contact point 185.

[0036] The first redundant contact point 185 can contain, for example, Al, Cu, Ni, W, Pt, Au, and combinations thereof. In an implementation, the first redundant contact point 185 can be located on the same level as the first contact point 180. The term "same level" used here means that it is formed by the same manufacturing process (e.g., at the same time with the same material(s)).

[0037] The first redundant contact point 185 can be electrically connected to at least one of the multiple first contact points 180. In one implementation, the first contact point 180 and the first redundant contact point 185 can be electrically connected by a first connecting line 160. The first connecting line 160 can extend along the second surface 100U of the first stack 100 (e.g., in the first direction X). In one implementation, the first connecting line 160 can extend along the top surface of the first protective layer 130 to electrically connect the first contact point 180 and the first redundant contact point 185. In one implementation, the first connecting line 160 can be a redistribution layer (RDL) on the second surface 100U of the first stack 100.

[0038] In one implementation, the first redundancy contact point 185 can be located on the edge region EA. The first redundancy contact point 185 on the edge region EA can be electrically connected to the first contact point 180 on the edge region EA. In one implementation, the first contact point 180 and the first redundancy contact point 185 can be, as in Fig. As shown in Figure 1, they should be arranged so that they lie side by side in the first direction X on the edge region EA (e.g., aligned along this direction). The first connecting line 160 can extend (e.g., longitudinally) in the first direction X on the edge region EA to connect the first contact point 180 and the first redundant contact point 185.

[0039] In one implementation, the width W2 of the first redundancy contact point 185 (e.g., in the first direction X) can be in a range of approximately 15 µm to approximately 30 µm. In another implementation, the width W2 of the first redundancy contact point 185 can be identical to the width W1 of the first contact point 180. The term "identical to," as used here, includes the meaning of a minor difference that may occur due to the edge or similar factors in the process, as well as the meaning of being completely identical.

[0040] In an implementation, the distance D2 between the first contact point 180 and the first redundant contact point 185 can range from approximately 3 µm to approximately 8 µm. Maintaining the distance D2 between the first contact point 180 and the first redundant contact point 185 at approximately 3 µm or greater ensures that the first redundant contact point 185 is not too close to the first TSV 150, thus preventing non-wetting failure of the ridge described below. Maintaining the distance D2 between the first contact point 180 and the first redundant contact point 185 at approximately 8 µm or less can help prevent failure of the electrical connection between the first contact point 180 and the first redundant contact point 185.

[0041] In one implementation, the first connecting line 160 can be lower or shorter than the first contact point 180 and the second contact point 270 (e.g., measured in the third direction Z). In another implementation, the height H1 of the first contact point 180 and the height H2 of the first redundant contact point 185 can be, as in Fig. 3 shown, greater than a height H3 of the first connecting line 160, on the basis of or measured from the second surface 100U of the first stack 100 in the third direction Z, be.

[0042] In one implementation, the height H2 of the first redundancy contact point 185 can be identical to the height H1 of the first contact point 180.

[0043] In an implementation, the first connecting line 160 can be in contact (in direct contact) with a side face of the first contact point 180 and a side face of the first redundancy contact point 185.

[0044] The second redundancy contact point 275 can be located on the third surface 200L of the second stack 200. The second redundancy contact point 275 can contain, for example, Al, Cu, Ni, W, Pt, Au, or combinations thereof. In one implementation, the second redundancy contact point 275 can be located on the same level as the second contact point 270.

[0045] The second redundancy contact point 275 can be electrically connected to at least one of the multiple second contact points 270. In one implementation, the second contact point 270 and the second redundancy contact point 275 can be electrically connected through the second semiconductor device layer 220. In one implementation, the second contact point 270 and the second redundancy contact point 275 can be connected as shown in Fig. 3 shown, are electrically connected by the first lines 224a, 224b and 224c of the second semiconductor device layer 220.

[0046] In one implementation, the second contact point 270 and the second redundant contact point 275 can be electrically connected by a bottom line 224c of the first lines 224a, 224b, and 224c. The bottom line 224c of the second semiconductor device layer 220 can be a line that is closest (e.g., along the third direction Z) to the first lines 224a, 224b, and 224c of the third surface 200L of the second stack 200. The second contact point 270 and the second redundant contact point 275 can each be connected to the bottom line 224c of the second semiconductor device layer 220 to be electrically connected to each other. In one implementation, a trench exposing the bottom line 224c can be located in the first inter-line insulating film 222. The second contact point 270 and the second redundant contact point 275 can fill the gap.

[0047] In one implementation, the height H5 of the second redundancy contact point 275 (e.g. measured in the third direction Z) can be identical to the height H2 of the second contact point 270.

[0048] The first redundancy bump 195 can be located between the first redundancy contact point 185 and the second redundancy contact point 275. The first redundancy bump 195 can have various forms, such as a column structure, a sphere structure, or a solder layer. In one implementation, the first redundancy bump 195 can be located on the same level as the first bump 290.

[0049] The first redundancy hump 195 can electrically connect the first redundancy contact point 185 and the second redundancy contact point 275. In one implementation, the first stack 100 and the second stack 200 can be electrically connected. In one implementation, the first semiconductor device layer 120 can be electrically connected to the second semiconductor device layer 220 or the second TSV 250 via the first TSV 150, the first contact point 180, the first connecting line 160, the first redundancy contact point 185, the first redundancy hump 195, the second redundancy contact point 275, and the first lines 224a, 224b, and 224c.

[0050] In one implementation, the first redundancy hump 195 (e.g., in the first direction X) can be spaced away from the first hump 290. In another implementation, the first hump 290 and the first redundancy hump 195 can be out of contact with each other.

[0051] In a semiconductor chip (e.g., the first stack of 100 or the second stack of 200) where a TSV (e.g., the first TSV 150) is formed, and in a multi-chip semiconductor package where several semiconductor chips are stacked, contact points (e.g., the first contact point 180 and the second contact point 270) and a ridge (e.g., the first ridge 290) connected to the TSV can connect the semiconductor chips. In a process for forming the ridge at the contact point, the TSV could act as a heat transfer path, potentially leading to ridge failure. For example, the ridge could be formed by a thermal compression bonding process to connect the contact points of the semiconductor chips. The contact point in contact with the TSV might be at a low temperature during the thermal compression bonding process, causing non-wetting failure of the ridge.Such a failure could be more pronounced in an edge area of ​​the semiconductor chip.

[0052] The semiconductor package, according to some embodiments, can help prevent failure by including the first redundant contact point 185 and the first redundant hump 195. In one implementation, the first redundant contact point 185 can be out of contact (in direct contact) with the first TSV 150, thus preventing a non-wetting failure of the first redundant hump 195 due to the first TSV 150. In another implementation, the first redundant contact point 185 can be electrically connected to the first contact point 180 in contact with the first TSV 150, and even if a non-wetting failure were to occur in the first hump 290 on the first contact point 180, the electrical connection between the first redundant contact point 185 and the first TSV 150 can be maintained. Accordingly, a semiconductor package with improved product reliability can be provided, e.g.,by preventing the failure of the first hump 290.

[0053] In some embodiments of the semiconductor package, the first redundant contact point 185 can be electrically connected to the first contact point 180 on the edge region EA. In one implementation, a semiconductor package with improved product reliability can be provided by preventing the failure of the first ridge 290 in the edge region EA.

[0054] In one implementation, a third stack 300 can be located on top of the second stack 200. The third stack 300 can have a fifth surface 300L and a sixth surface 300U, which are opposite each other. The fifth surface 300L of the third stack 300 can be opposite the fourth surface 200U of the second stack 200. In one implementation, the fifth surface 300L can be a bottom surface of the third stack 300, and the sixth surface 300U can be a top surface of the third stack 300.

[0055] In one implementation, the third stack 300 can contain a third semiconductor substrate 310 and a third semiconductor device layer 320. The third semiconductor substrate 310 can be similar to the first semiconductor substrate 110 or the second semiconductor substrate 210 described above, and the third semiconductor device layer 320 can be similar to the first semiconductor device layer 120 or the second semiconductor device layer 220 described above, so that repeated detailed descriptions of the same can be omitted in the following description.

[0056] In one implementation, the stacked first stack of 100, the second stack of 200, and the third stack of 300 can form a multi-chip semiconductor package such as a high-bandwidth memory (HBM).

[0057] In an implementation, there can be a third contact point 280, a fourth contact point 370, a second hump 390, a third redundant contact point 285, a fourth redundant contact point 375, a second redundant hump 295 and a second connecting line 260 between the second stack 200 and the third stack 300. The third contact point 280, the fourth contact point 370, the second hump 390, the third redundant contact point 285, the fourth redundant contact point 375, the second redundant hump 295 and the second connecting line 260 can be similar to the first contact point 180, the second contact point 270, the first hump 290, the first redundant contact point 185, the second redundant contact point 275, the first redundant hump 195 and the first connecting line 160, each of which is described above.In an implementation, the first contact point 180, the second contact point 270, the first hump 290, the first redundant contact point 185, the second redundant contact point 275, the first redundant hump 195 and the first connecting line 160 described above can be stacked and repeatedly formed over a plurality of stacked stacks.

[0058] In one implementation, a first filler layer 140 can be located between the first stack 100 and the second stack 200, and a second filler layer 240 can be located between the second stack 200 and the third stack 300. The first filler layer 140 can be filled into a space between the first stack 100 and the second stack 200, and the second filler layer 240 can be filled into a space between the second stack 200 and the third stack 300. The first filler layer 140 can cover the first contact point 180, the second contact point 270, the first hump 290, the first redundant contact point 185, the second redundant contact point 275, the first redundant hump 195, and the first connecting line 160.The second filler layer 240 can cover the third contact point 280, the fourth contact point 370, the second hump 390, the third redundancy contact point 285, the fourth redundancy contact point 375, the second redundancy hump 295 and the second connecting line 260.

[0059] The first filler layer 140 and the second filler layer 240 can, for example, contain epoxy resins. In one implementation, each of the first filler layer 140 and the second filler layer 240 can contain a filler. The filler can, for example, contain silicon dioxide. In one implementation, the fillers can each have a size from 0.1 µm to several µm and can have an average size of approximately 0.3 µm to 1 µm. In one implementation, the first filler layer 140 and the second filler layer 240 can contain the filler in an amount of approximately 55 wt% to 75 wt%, based on 100 wt% of the first filler layer 140 and the second filler layer 240, respectively.

[0060] The following section describes various semiconductor packages according to several embodiments, with reference to Fig. 4A to 15 described.

[0061] Fig. 4A and Fig. Figure 4B shows enlarged views of semiconductor packages according to some embodiments. For the sake of simplicity, parts that overlap with those described above with reference to Fig. Items 1 to 3 have been described, can be briefly described, or the descriptions can be omitted.

[0062] Referring to Fig. 4A, according to some embodiments, a semiconductor package may further comprise a first underhump metal layer 184, a second underhump metal layer 274, a third underhump metal layer 189 and a fourth underhump metal layer 279.

[0063] The first sub-hump metal layer 184 can be located between the first contact point 180 and the first hump 290. In one embodiment, the first sub-hump metal layer 184 can extend along a top surface of the first contact point 180. The first sub-hump metal layer 184 can help to improve the adhesion between the first contact point 180 and the first hump 290 and to improve the wettability of the first hump 290.

[0064] The second metal layer 274 beneath the hump can be located between the second contact point 270 and the first hump 290. In one implementation, the second metal layer 274 beneath the hump can extend along the underside of the second contact point 270. The second metal layer 274 beneath the hump can help improve the adhesion between the second contact point 270 and the first hump 290 and improve the wettability of the first hump 290.

[0065] The sub-hump metal layer 189 can be located between the first redundancy contact point 185 and the first redundancy hump 195. In one implementation, the sub-hump metal layer 189 can extend along a top surface of the first redundancy contact point 185. The third sub-hump metal layer 189 can help improve the adhesion between the first redundancy contact point 185 and the first redundancy hump 195 and improve the wettability of the first redundancy hump 195. In one implementation, the sub-hump metal layer 189 can be located at the same level as the first sub-hump metal layer 184.

[0066] The fourth sub-hump metal layer 279 can be located between the second redundancy contact point 275 and the first redundancy hump 195. In one implementation, the fourth sub-hump metal layer 279 can extend along a bottom surface of the second redundancy contact point 275. The fourth sub-hump metal layer 279 can contribute to improving the adhesion between the second redundancy contact point 275 and the first redundancy hump 195 and to improving the wettability of the first redundancy hump 195. In one implementation, the fourth sub-hump metal layer 279 can be located at the same level as the second sub-hump metal layer 274.

[0067] Each of the first to fourth under-hump metal layers 184, 274, 189 and 279 can be formed from a single layer or from multiple layers, including an adhesive layer and a solder wetting layer.

[0068] In one implementation, a first conducting pattern 272 can connect the second contact point 270 and the first conductors 224a, 224b, and 224c. In another implementation, a trench exposing the lowest conductor 224c can be located in the first intermediate conductor insulating film 222. The first conducting pattern 272 can conformally extend along the first intermediate conductor insulating film 222 and the trench. The second contact point 270 can extend along the first conducting pattern 272.

[0069] In one implementation, a second conducting pattern 277 can be formed, connecting the second redundancy contact point 275 and the first conductors 224a, 224b, and 224c. In one implementation, a trench exposing the lowest conductor 224c can be located in the first intermediate conductor insulating film 222. The second conducting pattern 277 can extend conformally along the first intermediate conductor insulating film 222 and the trench. The second redundancy contact point 275 can extend along the second conducting pattern 277. In one implementation, the second conducting pattern 277 can be at the same level as the first conducting pattern 272.

[0070] Referring to Fig. 4B, in some embodiments of the semiconductor package, the first contact point 180 and the first redundancy contact point 185 can be located on a top side of the first connecting line 160.

[0071] In one implementation, each of the first contact point 180 and the first redundant contact point 185 can be in contact (in direct contact) with the top surface of the first connecting line 160. In another implementation, the height H1 of the first contact point 180 and the height H2 of the first redundant contact point 185, based on or measured from the second surface 100U of the first stack 100 in the third direction Z, can be greater than the height H3 of the first connecting line 160. For example, a second surface of the first connecting line 160 facing the stack 200 can be closer to the second surface 100U of the first stack 100 in the third direction Z than the second surfaces of the first contact point 180 and the first redundant contact point 185 facing the stack 200 can be closer to the second surface 100U of the first stack 100 in the third direction Z.

[0072] Fig. Figure 5 is a cross-sectional view of a semiconductor package according to some embodiments. For the sake of simplicity, parts that overlap with those described above with reference to Fig. Sections 1 to 4B have been described, can be briefly described, or the descriptions can be omitted.

[0073] Referring to Fig. 5. According to some embodiments, the semiconductor package may also contain a third connecting line 165 and a fourth connecting line 265.

[0074] The third interconnect 165 can electrically connect the second contact point 270 and the second redundant contact point 275. The third interconnect 165 can extend along the third surface 200L of the second stack 200. In one implementation, the third interconnect 165 can extend along the underside of the second semiconductor device layer 220 to electrically connect the second contact point 270 and the second redundant contact point 275. In one implementation, the third interconnect 165 can be an RDL on the third surface 200L of the second stack 200.

[0075] In one implementation, the electrical connection between the second contact point 270 and the second redundant contact point 275 cannot be established through the second semiconductor device layer 220. In another implementation, the second contact point 270 and the second redundant contact point 275 cannot be connected to the first lines 224a, 224b, and 224c of Fig. 3 connected.

[0076] The fourth interconnect 265 can electrically connect the fourth contact point 370 and the fourth redundant contact point 375. The fourth interconnect 265 can extend along the fifth surface 300L of the third stack 300. In one implementation, the fourth interconnect 265 can extend along a bottom surface of the third semiconductor device layer 320 to electrically connect the fourth contact point 370 and the fourth redundant contact point 375. In one implementation, the fourth interconnect 265 can be an RDL on the fifth surface 300L of the third stack 300.

[0077] In one implementation, the electrical connection between the fourth contact point 370 and the fourth redundancy contact point 375 cannot be established through the third semiconductor device layer 320.

[0078] Fig. Figures 6 to 11 are layout diagrams of semiconductor packages according to some embodiments. For the sake of simplicity, parts relating to the above with reference to Fig. Parts 1 to 5 described may overlap, be briefly described, or descriptions of them may be omitted.

[0079] Referring to Fig. 6 In some embodiments of a semiconductor package, the first redundancy contact point 185 can be located closer to the edge surface 100S than the first contact point 180 is located closer to the edge surface 100S.

[0080] In one implementation, the first redundancy contact point 185 can be located between the boundary surface 100S and the first pad 180 (e.g., in the first direction X). In another implementation, the first contact point 180 and the first redundancy contact point 185 can be arranged such that they lie adjacent to each other on the boundary surface EA in the first direction X. The first connecting line 160 can extend along the boundary surface EA in the first direction X to connect the first contact point 180 and the first redundancy contact point 185.

[0081] Referring to Fig. 7 In some embodiments of a semiconductor package, the first contact point 180 and the first redundancy contact point 185 can be arranged parallel to the edge surface 100S (e.g. equidistant from the edge surface 100S in the first direction X).

[0082] In one implementation, the first contact point 180 and the first redundant contact point 185 can be arranged so that they lie next to each other in the second direction Y or are aligned along this direction. The first connecting line 160 can extend in the second direction Y to connect the first contact point 180 and the first redundant contact point 185.

[0083] Referring to Fig. In some embodiments of a semiconductor package, each of the first contact points 180 can be connected to a plurality of first redundant contact points 185a and 185b.

[0084] In one implementation, the semiconductor package can contain a fifth redundant contact point 185a and a sixth redundant contact point 185b, which can be connected to each of the first contact points 180. The fifth redundant contact point 185a and the sixth redundant contact point 185b can be spaced apart from each other.

[0085] In one implementation, the first contact point 180 and the fifth redundancy contact point 185a can be arranged so that they lie next to each other or are aligned along the first direction X, and the first contact point 180 and the sixth redundancy contact point 185b can be arranged so that they lie next to each other or are aligned along the second direction Y.

[0086] In one implementation, the semiconductor package can contain a fifth interconnect 160a connecting the first contact point 180 and the fifth redundant contact point 185a, and a sixth interconnect 160b connecting the first contact point 180 and the sixth redundant contact point 185b. In one implementation, the fifth interconnect 160a can extend in the first direction X to connect the first contact point 180 and the fifth redundant contact point 185a, and the sixth interconnect 160b can extend in the second direction Y to connect the first contact point 180 and the sixth redundant contact point 185b.

[0087] Referring to Fig. 9 In some embodiments of a semiconductor package, each of the first contact points 180 can be connected to three or more first redundant contact points 185a, 185b and 185c.

[0088] In one implementation, the semiconductor package can contain a seventh redundant contact point 185c, which is connected to the first contact point 180. The seventh redundant contact point 185c can be spaced apart from the fifth redundant contact point 185a and the sixth redundant contact point 185b.

[0089] In one implementation, the first contact point 180 and the seventh redundant contact point 185c can be arranged such that they are adjacent in a direction different from the first direction X and the second direction Y (e.g., a diagonal direction). In another implementation, the seventh redundant contact point 185c can be arranged with the fifth redundant contact point 185a in the first direction X and with the sixth redundant contact point 185b in the second direction Y.

[0090] In one implementation, the semiconductor package can include a seventh interconnect 160c that connects the first contact point 180 and the seventh redundant contact point 185c. In one implementation, the seventh interconnect 160c can extend in a direction different from the first direction X and the second direction Y (e.g., a diagonal direction) to connect the first contact point 180 and the seventh redundant contact point 185c.

[0091] Referring to Fig. 10 In a semiconductor package according to some embodiments, the number of first redundancy contact points 185a, 185b, 185c, 185d, 185e and 185f, which are connected to each of the first contact points 180a, 180b and 180c, can increase with increasing distance from a center 100C of the first stack 100 in a top view.

[0092] In one implementation, the semiconductor package can contain a fifth to seventh contact point 180a, 180b and 180c on the first stack 100.

[0093] The distance from the center 100C of the first stack 100 to the sixth contact point 180b can be greater than the distance from the center 100C of the first stack 100 to the fifth contact point 180a. In one implementation, the number of first redundant contact points connected to the sixth contact point 180b can be greater than the number of first redundant contact points connected to the fifth contact point 180a. In another implementation, the fifth contact point 180a can be connected to one first redundant contact point (e.g., the fifth redundant contact point 185a), and the sixth contact point 180b can be connected to two first redundant contact points (e.g., the sixth redundant contact point 185b and the seventh redundant contact point 185c).

[0094] In one implementation, the distance from the center 100C of the first stack 100 to the seventh contact point 180c can be greater than the distance from the center 100C of the first stack 100 to the sixth contact point 180b. In another implementation, the number of first redundant contact points connected to the seventh contact point 180c can be greater than the number of first redundant contact points connected to the sixth contact point 180b. In an implementation, the sixth contact point 180b can be connected to two first redundant contact points (e.g., the sixth redundant contact point 185b and the seventh redundant contact point 185c), and the seventh contact point 180c can be connected to three first redundant contact points (e.g., an eighth redundant contact point 185d, a ninth redundant contact point 185e, and a tenth redundant contact point 185f).

[0095] In one implementation, the semiconductor package may contain an eighth interconnect 160d connecting the seventh contact point 180c and the eighth redundancy contact point 185d, a ninth interconnect 160e connecting the seventh contact point 180c and the ninth redundancy contact point 185e, and a tenth interconnect 160f connecting the seventh contact point 180c and the tenth redundancy contact point 185f.

[0096] Referring to Fig. In some embodiments of a semiconductor package, the plurality of first contact points 180a and 180b can jointly use the first redundant contact point 185.

[0097] In one implementation, the fifth contact point 180a and the sixth contact point 180b can both be connected to the first redundant contact point 185. The fifth contact point 180a and the sixth contact point 180b can be spaced apart from each other.

[0098] In an implementation, the fifth contact point 180a, the first redundancy contact point 185 and the sixth contact point 180b can be arranged sequentially such that they lie next to each other in the second direction Y.

[0099] In one implementation, the fifth connection line 160a can connect the first contact point 180 and the fifth redundant contact point 185a, and the sixth connection line 160b can connect the first contact point 180 and the sixth redundant contact point 185b. In another implementation, the fifth connection line 160a can extend in the second direction Y to connect the first contact point 180 and the fifth redundant contact point 185a, and the sixth connection line 160b can extend in the second direction Y to connect the first contact point 180 and the sixth redundant contact point 185b.

[0100] Fig. Figures 12 to 15 are cross-sectional views of semiconductor packages according to some embodiments. For the sake of simplicity, parts that overlap with those described above with reference to Fig. Items 1 to 11 have been described, can be briefly described, or the descriptions can be omitted.

[0101] Referring to Fig. 12. According to some embodiments, a semiconductor package may further contain a substrate 10 and a semiconductor chip 20.

[0102] Substrate 10 can be a substrate for a package. In one implementation, substrate 10 can be a PCB, a ceramic substrate, or something similar. In another implementation, substrate 10 can be a substrate for a wafer-level package (WLP). Substrate 10 can have a bottom and a top surface facing each other.

[0103] The semiconductor chip 20 can be located on the substrate 10. The semiconductor chip 20 can be an integrated circuit (IC) in which more than a few hundred to several million semiconductor devices are integrated on a single chip. In one implementation, the semiconductor chip 20 can be an application processor (AP), such as a central processing unit (CPU), a graphics processing unit (GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, or the like. In another implementation, the semiconductor chip 20 can be a logic chip, such as an analog-to-digital converter (ADC), an application-specific integrated circuit (ASIC), or the like, and it can be a memory chip, such as volatile memory (e.g., DRAM), non-volatile memory (e.g., read-only memory (ROM) or flash memory), or the like.In one implementation, the semiconductor chip 20 can be formed by combining these chips together.

[0104] The semiconductor chip 20 can be stacked on the top side of the substrate 10. In one implementation, a substrate contact point 14 can be located on the top side of the substrate 10, and a first chip contact point 22 can be located on the bottom side of the semiconductor chip 20. The substrate contact point 14 and the first chip contact point 22 can be connected by a third protrusion 28. In one implementation, the substrate 10 and the semiconductor chip 20 can be electrically connected.

[0105] In one implementation, the first stack 100 can be stacked on the semiconductor chip 20. In another implementation, a second chip contact point 24 can be located on a top surface of the semiconductor chip 20. The second chip contact point 24 and the base contact point 170 can be connected by the base bump 190. In another implementation, the semiconductor chip 20 and the first stack 100 can be electrically connected to each other.

[0106] Referring to Fig. 13. According to some embodiments, a semiconductor package may also contain a third TSV 25.

[0107] In one implementation, the semiconductor chip 20 can contain a fourth semiconductor substrate 21 and a conduction layer 26. The third TSV 25 can pass through the fourth semiconductor substrate 21. In one implementation, the second chip contact point 24 can be in contact with the third TSV 25. In another implementation, the second chip contact point 24 can be in contact with the third TSV 25, which is exposed from or on the top side of the semiconductor chip 20 through the fourth semiconductor substrate 21.

[0108] In an implementation, an eleventh redundancy contact point 27, a twelfth redundancy contact point 175 and a third redundancy hump 95 can be formed.

[0109] The eleventh redundancy contact point 27 can be located on the top surface of the semiconductor chip 20. The eleventh redundancy contact point 27 can be spaced apart from the second chip contact point 24. In one implementation, the eleventh redundancy contact point 27 can be out of contact with the third TSV 25. The eleventh redundancy contact point 27 can be electrically connected to the second chip contact point 24. In one implementation, the second chip contact point 24 and the eleventh redundancy contact point 27 can be electrically connected by an eleventh connecting line 29. In one implementation, the eleventh connecting line 29 can extend along the top surface of the semiconductor chip 20.

[0110] The twelfth redundancy contact point 175 can be located on the underside of the first stack 100. The twelfth redundancy contact point 175 can be spaced apart from the base contact point 170. The twelfth redundancy contact point 175 can be electrically connected to the base contact point 170. In one implementation, the base contact point 170 and the twelfth redundancy contact point 175 can be electrically connected through the first semiconductor device layer 120.

[0111] The third redundancy hump 95 can be located between the eleventh redundancy contact point 27 and the twelfth redundancy contact point 175. The third redundancy hump 95 can have various shapes, e.g., a column structure, a sphere structure, or a solder layer. The third redundancy hump 95 can electrically connect the eleventh redundancy contact point 27 and the twelfth redundancy contact point 175.

[0112] Referring to Fig. 14 According to some embodiments, a semiconductor package may also contain an intermediate connector 40.

[0113] The intermediate connector 40 can be located between the substrate 10 and the first stack 100. In one implementation, the intermediate connector 40 can be stacked on top of the substrate 10. In another implementation, a first intermediate connector contact point 42 can be located on the underside of the intermediate connector 40. The substrate contact point 14 and the first intermediate connector contact point 42 can be connected by a fourth protrusion 48. In another implementation, the substrate 10 and the intermediate connector 40 can be electrically connected.

[0114] In one implementation, the first stack 100 can be stacked on the intermediate connector 40. In another implementation, a second intermediate connector contact point 43 can be located on the top side of the intermediate connector 40. The second intermediate connector contact point 43 and the base contact point 170 can be connected by the base hump 190. In another implementation, the intermediate connector 40 and the first stack 100 can be electrically connected to each other.

[0115] In one implementation, the first stack 100 and the semiconductor chip 20 can be stacked in series on top of the intermediate connector 40. The intermediate connector 40 can facilitate a connection between the substrate 10 and the first stack 100 or a connection between the semiconductor chip 20 and the first stack 100. In one implementation, the intermediate connector 40 can help reduce or prevent warping of the semiconductor package.

[0116] In one implementation, the intermediate connector 40 can contain a fifth semiconductor substrate 41, a second intermediate conductor insulating film 44, and second conductors 46 within the second intermediate conductor insulating film 44. The second conductors 46 can be stacked from a top surface of the fifth semiconductor substrate 41. In one implementation, some conductors of the second conductors 46 can connect the substrate 10 and the first stack 100, and some other conductors of the second conductors 46 can connect the semiconductor chip 20 and the second stack 200.

[0117] Referring to Fig. In some embodiments, a semiconductor package can also contain a fourth TSV 45.

[0118] The fourth TSV 45 can pass through the fifth semiconductor substrate 41. In one implementation, the first intermediate connector contact point 42 can be in contact with the fourth TSV 45. In another implementation, the first intermediate connector contact point 42 can be in contact with the fourth TSV 45, which is exposed from or on the underside of the intermediate connector 40 through the fifth semiconductor substrate 41.

[0119] In one implementation, the semiconductor package can contain a thirteenth redundancy contact point 15, a fourteenth redundancy contact point 43_1 and a fourth redundancy hump 49.

[0120] The thirteenth redundant contact point 15 can be located on the top surface of the substrate 10. The thirteenth redundant contact point 15 can be spaced apart from the substrate contact point 14. The thirteenth redundant contact point 15 can be electrically connected to the substrate contact point 14. In one implementation, the substrate contact point 14 and the thirteenth redundant contact point 15 can be electrically connected by a twelfth connecting line 16. The twelfth connecting line 16 can, for example, extend along the top surface of the substrate 10.

[0121] The fourteenth redundant contact point 43_1 can be located on the underside of the intermediate connector 40. The fourteenth redundant contact point 43_1 can be spaced apart from the first intermediate connector contact point 42. In one implementation, the fourteenth redundant contact point 43_1 can be out of contact with the fourth TSV 45. The fourteenth redundant contact point 43_1 can be electrically connected to the first intermediate connector contact point 42. In one implementation, the first intermediate connector contact point 42 and the fourteenth redundant contact point 43_1 can be electrically connected by a thirteenth connecting line 47. The thirteenth connecting line 47 can, for example, extend along the underside of the intermediate connector 40.

[0122] The fourth redundancy bump 49 can be located between the thirteenth redundancy contact point 15 and the fourteenth redundancy contact point 43_1. The fourth redundancy bump 49 can have various shapes, e.g., a column structure, a sphere structure, or a solder layer. The fourth redundancy bump 49 can electrically connect the thirteenth redundancy contact point 15 and the fourteenth redundancy contact point 43_1.

[0123] In summary and in retrospect, a semiconductor chip in which through-hole silicon vias (TSVs) are formed and a multi-chip semiconductor package in which a large number of semiconductor chips are stacked were considered.

[0124] One or more embodiments may provide a semiconductor package with through-hole silicon vias (TSVs).

[0125] One or more embodiments can provide a semiconductor package with improved product reliability.

Claims

[1] Semiconductor package, comprising: a first stack (100) containing a first semiconductor substrate (110); a multitude of through-silicon vias, TSVs (150) passing through the first semiconductor substrate (110); a second stack (200) on top of the first stack (100), wherein the second stack (200) contains a second surface (100U) facing a first surface of the first stack (100); a first contact point (180, 180a, 180b) on the first surface of the first stack (100), wherein the first contact point (180, 180a, 180b) is in contact with one or more of the plurality of TSVs (150); a second contact point (270) on the second surface (200L) of the second stack (200); a hump (28, 48, 190, 290, 390) connecting the first contact point (180, 180a, 180b) and the second contact point (270); a first redundancy contact point (185, 185a-e) on the first surface of the first stack (100), wherein the first redundancy contact point (185, 185a-e) is spaced apart from the first contact point (180, 180a, 180b) and is not in direct contact with the plurality of TSVs (150); a second redundancy contact point (275) on the second surface (200L) of the second stack, wherein the second redundancy contact point (275) is spaced apart from the second contact point (270); and a redundancy hump (49, 95, 195, 295) connecting the first redundancy contact point (185, 185a-e) and the second redundancy contact point (275), where: the first contact point (180, 180a, 180b) and the first redundancy contact point (185, 185a-e) are electrically connected to each other, and the second contact point (270) and the second redundancy contact point (275) are electrically connected to each other. [2] Semiconductor package according to claim 1, further comprising a connecting line (160) extending along the first surface of the first stack (100), wherein the connecting line (160) electrically connects the first contact point (180, 180a, 180b) and the first redundancy contact point (185, 185a-e). [3] Semiconductor package according to claim 2, wherein: the height of the first contact point (180, 180a, 180b) is greater than the height of the connecting line (160) as measured from the first surface of the first stack (100), and the height of the first redundancy contact point (185, 185a-e) is greater than the height of the connecting line (160) as measured from the first surface of the first stack (100). [4] Semiconductor package according to claim 2, wherein: the second stack (200) contains a second semiconductor substrate (210) and a semiconductor device layer (120, 220, 320) on the second semiconductor substrate (210), and the semiconductor device layer (120, 220, 320) electrically connects the second contact point (270) and the second redundancy contact point. [5] Semiconductor package according to claim 4, wherein: the semiconductor device layer (120, 220, 320) contains an inter-conductor insulating film (44, 222) and conductors stacked in the inter-conductor insulating film (44, 222), and a conductor stacked in the intermediate conductor insulating film (44, 222) which is closest to the second surface (100U), is in contact with the second contact point (270) and in contact with the second redundancy contact point (275). [6] Semiconductor package according to claim 2, further comprising a second connecting line (260) extending along the second surface (200L) of the second stack (200), wherein the second connecting line (260) electrically connects the second contact point (270) and the second redundancy contact point. [7] Semiconductor package according to claim 1, wherein the distance at which the first contact point (180, 180a, 180b) is spaced from the first redundancy contact point (185, 185a-e) is in a range of 3 µm to 8 µm. [8] Semiconductor package according to claim 1, wherein the width of the first contact point (180, 180a, 180b) is in a range of 15 µm to 30 µm. [9] Semiconductor package, comprising: a first stack (100) comprising a central region and a peripheral region around the central region, wherein the first stack (100) comprises a first semiconductor substrate (110); a multitude of through-silicon vias, TSVs (150) passing through the first semiconductor substrate (110); one or more first contact points (180, 180a, 180b) on a top side of the edge region of the first stack, wherein the one or more first contact points (180, 180a, 180b) are in contact with one or more of the plurality of TSVs (150); one or more first redundancy contact points (185, 185a-e) on the top of the edge region of the first stack (100), wherein the one or more first redundancy contact points are spaced apart from the one or more first contact points (180, 180a, 180b) and are not in direct contact with the plurality of TSVs (150); and one or more first connecting lines (160) extending along the top of the edge region of the first stack (100) to electrically connect the one or more first contact points and the one or more first redundancy connection surfaces. [10] Semiconductor package according to claim 9, wherein: the one or more first redundancy contact points (185, 185a-e) comprise / comprise a multitude of first redundancy contact points, and the number of multiple first redundancy contact points (185, 185a-e) electrically connected in a top view to a first contact point (180, 180a, 180b) near a center of the first stack (100) is less than the number of multiple first redundancy contact points electrically connected in a top view to another first contact point distal to a center of the first stack (100). [11] Semiconductor package according to claim 9, wherein: the first semiconductor substrate (110) contains an edge surface extending in a first direction and the one or more first contact points (180, 180a, 180b) and the one or more first redundancy contact points are arranged in the first direction. [12] Semiconductor package according to claim 9, wherein: the first semiconductor substrate (110) has a boundary surface (100S) extending in a first direction and the one or more first contact points (180, 180a, 180b) and the one or more first redundancy contact points are arranged in a second direction that intersects the first direction. [13] Semiconductor package according to claim 12, further comprising: a second redundancy contact point (275) on the top of the edge region of the first stack (100), wherein the second redundancy contact point (275) is spaced apart from the one or more first contact points (180, 180a, 180b) and the one or more first redundancy contact points and is not in direct contact with the plurality of TSVs (150); and a second connecting line (260) extending along the top of the first stack (100) of the edge region to electrically connect the one or more first contact points (180, 180a, 180b) and the second redundant contact point (275), wherein the one or more first contact points (180, 180a, 180b) and the second redundancy contact point (275) are arranged in the first direction. [14] Semiconductor package according to claim 12, further comprising: a third redundancy contact point (285) on the top of the edge region of the first stack (100), wherein the third redundancy contact point (285) is spaced apart from the one or more first contact points (180, 180a, 180b), the one or more first redundancy contact points and a second redundancy contact point (275) and is not in direct contact with the plurality of TSVs (150); and a third connecting line (165) extending along the top of the first stack (100) of the edge region to electrically connect the one or more first contact points (180, 180a, 180b) and the third redundant contact point (285), wherein the one or more first contact points (180, 180a, 180b) and the third redundancy contact point (285) are arranged in a third direction which differs from the first direction and the second direction. [15] Semiconductor package according to claim 9, wherein: the first semiconductor substrate (110) has a boundary surface (100S) extending in a first direction and the distance at which the edge region is spaced from the edge surface (100S) is 200 µm or less. [16] Semiconductor package according to claim 9, wherein the first connecting line (160) is in contact with a side surface of one or more first contact points (180, 180a, 180b) and a side surface of one or more first redundancy contact points (185, 185a-e). [17] Semiconductor package according to claim 9, wherein each first contact point (180, 180a, 180b) and each first redundancy contact point is in contact with a top surface of the first connecting line (160). [18] Semiconductor package, comprising: a first semiconductor chip comprising a first semiconductor substrate (110) and a first semiconductor device layer on a bottom side of the first semiconductor substrate (110); a second semiconductor chip comprising a second semiconductor substrate (210) and a second semiconductor device layer (220) on a bottom side of the second semiconductor substrate (210) on the first semiconductor chip; a multitude of first through-silicon vias, TSVs (150) passing through the first semiconductor substrate (110); a first contact point (180, 180a, 180b) on a top surface of the first semiconductor substrate (110), wherein the first contact point (180, 180a, 180b) is in contact with one or more of the plurality of first TSVs (150); a second contact point (270) on a bottom side of the second semiconductor device layer (220); a hump (28, 48, 190, 290, 390) connecting the first contact point (180, 180a, 180b) and the second contact point (270); a first redundancy contact point (185, 185a-e) on the top side of the first semiconductor substrate (110), wherein the first redundancy contact point (185, 185a-e) is spaced apart from the first contact point (180, 180a, 180b) and is not in direct contact with the plurality of first TSVs (150); a connecting line (160) extending along the top surface of the first semiconductor substrate and connecting the first contact point (180, 180a, 180b) and the first redundancy contact point (185, 185a-e); a second redundant contact point (275) on the underside of the second semiconductor device layer, wherein the second redundant contact point (275) is spaced apart from the second contact point; and a redundancy hump (49, 95, 195, 295) connecting the first redundancy contact point (185, 185a-e) and the second redundancy contact point (275), wherein the second semiconductor device layer (220) electrically connects the second contact point (270) and the second redundancy contact point (275). [19] Semiconductor package according to claim 18, wherein: the first semiconductor chip further includes a protective layer (130, 230) that covers the top of the first semiconductor substrate, and the multitude of first TSVs (150) penetrate the protective layer (130, 230). [20] Semiconductor package according to claim 18, further comprising a filler layer which is filled into a space between the first semiconductor chip and the second semiconductor chip.

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