METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Abstract

Procedure that includes the following: Deposition of a dielectric gate layer (112) on a channel region (68); Deposition of a first p-type exit work metal on the dielectric gate layer (112); Performing an aluminium treatment (118) of the first p-type exit work metal; after carrying out the aluminium treatment (118), carrying out a fluorine treatment (120) of the first p-type exit working metal; and After performing the fluorine treatment (120), a second p-type exit work metal is deposited on the first p-type exit work metal.

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as PCs, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers onto a semiconductor substrate. The various material layers are then structured using lithography to create circuit components and elements.

[0002] The semiconductor industry continues to improve the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area. However, reducing minimum feature sizes introduces additional problems that need to be addressed.

[0003] US 2020 / 0066535 A1 describes the formation of a gate structure of a device, such as in an exchange gate process, and the device formed thereby. In one embodiment, a method comprises conformally forming a gate dielectric layer on a fin extending from a substrate and along the sidewalls of gate spacers over the fin; conformally depositing a dummy layer over the gate dielectric layer during a deposition process using a silicon-containing precursor and a dopant gas containing fluorine, deuterium, or a combination thereof, wherein the dummy layer, as deposited, comprises a dopant of fluorine, deuterium, or a combination thereof; performing a thermal process to drive the dopant from the dummy layer into the gate dielectric layer; removing the dummy layer; and forming one or more metal-containing layers over the gate dielectric layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read together with the accompanying figures. It should be noted that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for the clarity of the discussion. Fig. Figure 1 shows an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional view, according to some embodiments. The Fig. Figures 2 to 22B are views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. Figure 23 is a flowchart of an example procedure for forming replacement gates for nano-FETs according to some embodiments. Fig. Figure 24 is a view of nano-FETs, in accordance with some other embodiments. The Fig. Figures 25A to 26 are views of FinFETs according to some embodiments. The Fig. 27 and Fig. Figure 28 shows views of devices according to some embodiments. The Fig. 29 and Fig. Figure 30 shows views of devices according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples of the implementation of various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. For example, the formation of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features are not in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself represent a relationship between the various designs and / or configurations discussed.

[0006] Furthermore, to simplify the description, spatially relative terms such as "under," "below," "below," "above," "above," and the like can be used to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative terms used here can be interpreted accordingly.

[0007] In various embodiments, gate structures for transistors are formed with a fluorine-treated work function metal layer (WFM). The fluorine treatment can, for example, involve fluorine soaking of the WFM layer, allowing fluorine to diffuse into an underlying gate dielectric (e.g., a high k-value gate dielectric). Prior to the fluorine treatment, the WFM layer undergoes an aluminum treatment to enhance the effectiveness of the fluorine treatment. As a result, the flat band voltage (VFB) of the resulting transistor can be increased toward a band edge of the WFM metal layer, the threshold voltage of the resulting transistor can be lowered, and the device performance can be improved.

[0008] The embodiments are described in a specific context, namely a chip with nano-FETs. However, various embodiments can be applied to chips that include other types of transistors (e.g., FinFETs, planar transistors, etc.) instead of or in combination with the nano-FETs.

[0009] Fig. Figure 1 shows an example of nano-FETs (e.g., nanowire FETs, nanosheet FETs, etc.) according to some embodiments. Fig. Figure 1 is a three-dimensional view in which some features of the nano-FETs have been omitted for illustrative purposes. The nano-FETs may be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate all-around field-effect transistors (GAAFETs), or similar.

[0010] The nanoFETs comprise nanostructures 66 (e.g., nanosheets, nanowires, or the like) over fins 62 on a substrate 50 (e.g., a semiconductor substrate), with the nanostructures 66 acting as channel regions for the nanoFETs. The nanostructures 66 can be p-type nanostructures, n-type nanostructures, or a combination thereof. Insulation regions 70, such as shallow trench isolation (STI) regions, are arranged between adjacent fins 62, which may protrude above and between adjacent isolation regions 70. Although the isolation regions 70 are described / illustrated as separate from the substrate 50, the term "substrate," as used here, can refer to the semiconductor substrate alone or a combination of the semiconductor substrate and the isolation regions.Furthermore, although a lower section of the fins 62 is depicted as a single, continuous material with the substrate 50, the lower section of the fins 62 and / or the substrate 50 can comprise a single material or a multitude of materials. In this context, the fins 62 refer to the section that extends over and between the adjacent insulation areas 70.

[0011] The gate dielectrics 122 are arranged over the upper surfaces of the fins 62 and along the upper surfaces, sidewalls, and lower surfaces of the nanostructures 66. Gate electrodes 124 are arranged over the gate dielectrics 122. Epitaxial source / drain regions 98 are arranged on the fins 62 on opposite sides of the gate dielectrics 122 and the gate electrodes 124. The epitaxial source / drain regions 98 can be shared by different fins 62. For example, adjacent epitaxial source / drain regions 98 can be electrically connected, for instance, by merging the epitaxial source / drain regions 98 through epitaxial growth or by coupling the epitaxial source / drain regions 98 with a common source / drain contact.

[0012] In Fig. Figure 1 also shows reference cross-sections that will be used in later figures. Cross-section AA' runs along a longitudinal axis of a gate electrode 124 and in a direction, e.g., perpendicular to a current flow direction between the epitaxial source / drain regions 98 of a nanoFET. Cross-section BB' runs along a longitudinal axis of a nanostructure 66 and in a direction of, for example, a current flow between the epitaxial source / drain regions 98 of the nanoFET. Cross-section CC' is parallel to cross-section AA' and extends through the epitaxial source / drain regions 98 of the nanoFETs. Subsequent figures refer to these reference cross-sections for clarification.

[0013] Some of the embodiments described here are discussed in the context of nanoFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices, such as planar FETs or fin field-effect transistors (FinFETs).

[0014] The Fig. Figures 2 to 22B show views of intermediate stages in the fabrication of nano-FETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5 and Fig. 6 are three-dimensional views that provide a similar three-dimensional view to Fig. Show 1. The Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14, Fig. 15, Fig. 16, Fig. 17, Fig. 18, Fig. 19, Fig. 20A, Fig. 21A and Fig. 22A shows the one in Fig. The reference cross-section A-A' shown in Figure 1, with the exception that two fins are shown. Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 20B, Fig. 21B and Fig. 22B show the one in Fig. 1 shown reference cross-section B-B'. The Fig. 9C and Fig. 9D shows the in Fig. 1 shown reference cross section C-C', where two fins are shown.

[0015] In Fig. Figure 2 shows a substrate 50 for the fabrication of nanoFETs. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or similar, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX), a silicon oxide layer, or similar. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise silicon, germanium, a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide, an alloy semiconductor including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide, combinations thereof or the like.

[0016] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form n-type devices, such as NMOS transistors, e.g., n-type nanoFETs, and the p-type region 50P can be used to form p-type devices, such as PMOS transistors, e.g., p-type nanoFETs. The n-type region 50N can be physically separated from the p-type region 50P (not shown separately), and any number of devices (e.g., other active devices, doped regions, insulating structures, etc.) can be placed between the n-type region 50N and the p-type region 50P. Although one n-type area 50N and one p-type area 50P are shown, any number of n-type areas 50N and p-type areas 50P can be provided.

[0017] Substrate 50 can be easily doped with a p-type or n-type impurity. Anti-punch-through (APT) implantation can be performed on an upper portion of substrate 50 to form an APT region. During APT implantation, dopants can be implanted into substrate 50. The dopants can have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type regions 50N and the p-type regions 50P. The APT region can extend below the source / drain regions in the nanoFETs. The APT region can be used to reduce leakage from the source / drain regions to substrate 50. In some embodiments, the doping concentration in the APT region can be in the range of approximately 10 18 cm -3 up to about 10 19 cm -3 lay.

[0018] A multilayer stack 52 is formed on top of the substrate 50. The multilayer stack 52 contains alternating layers of first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed from a first semiconductor material, and the second semiconductor layers 56 are formed from a second semiconductor material. The semiconductor materials can each be selected from the available semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 comprises three layers each of the first semiconductor layers 54 and the second semiconductor layers 56. It should be understood that the multilayer stack 52 can comprise any number of first semiconductor layers 54 and second semiconductor layers 56.

[0019] In the illustrated embodiment, and as will be described in more detail later, the first semiconductor layers 54 are removed and the second semiconductor layers 56 are structured to form channel regions for the nanoFETs in both the n-type region 50N and the p-type region 50P. The first semiconductor layers 54 are sacrificial (or dummy) layers that are removed in the subsequent processing to expose the upper and lower surfaces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material that exhibits high etch selectivity for the etching of the second semiconductor layers 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layers 56 is a material suitable for channel regions for both n-type and p-type nanoFETs, such as silicon.

[0020] In another embodiment (not shown separately), the first semiconductor layers 54 are structured to form channel regions for nanoFETs in one region (e.g., the p-type region 50P), and the second semiconductor layers 56 are structured to form channel regions for nanoFETs in another region (e.g., the n-type region 50N). The first semiconductor material of the first semiconductor layers 54 can be suitable for p-type nanoFETs, e.g., silicon-germanium (e.g., Si3). x Ge 1-x, where x can be in the range of 0 to 1), pure or essentially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layers 56 can be suitable for n-type nanoFETs, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material can exhibit high etch selectivity with respect to mutual etching, such that the first semiconductor layers 54 can be removed without removing the second semiconductor layers 56 in the n-type region 50N, and the second semiconductor layers 56 can be removed without removing the first semiconductor layers 54 in the p-type region 50P.

[0021] Each layer of the multilayer stack 52 can be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar. Each layer can have a small thickness, e.g., a thickness in the range of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers 56) are designed to be thinner than other layers (e.g., the first semiconductor layers 54).For example, in embodiments where the first semiconductor layers 54 are sacrificial (or dummy) layers and the second semiconductor layers 56 are structured to form channel regions for the nanoFETs, the first semiconductor layers 54 can have a first thickness T1 and the second semiconductor layers 56 a second thickness T2, where the second thickness T2 is approximately 30% to approximately 60% less than the first thickness T1. By forming the second semiconductor layers 56 with a smaller thickness, the channel regions can be formed with a higher density.

[0022] In Fig. In 3, trenches are structured into the substrate 50 and the multilayer stack 52 to form fins 62, first nanostructures 64, and second nanostructures 66. The fins 62 are semiconductor strips structured within the substrate 50. The first nanostructures 64 and the second nanostructures 66 comprise the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56, respectively. The trenches can be structured by any suitable etching method, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0023] The fins 62 and the nanostructures 64, 66 can be structured using any suitable method. For example, the fins 62 and the nanostructures 64, 66 can be structured using one or more photolithographic methods, including dual-structuring or multiple-structuring methods. In general, dual-structuring or multiple-structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, smaller spacing than those achievable with a single, direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used as masks to structure the fins 62 and the nanostructures 64, 66. In some embodiments, the mask (or another layer) can remain on the nanostructures 64, 66.

[0024] The fins 62 and the nanostructures 64, 66 can each have widths in a range of approximately 8 nm to approximately 40 nm. In the illustrated embodiment, the fins 62 and the nanostructures 64, 66 have essentially the same width in the n-type region 50N and in the p-type region 50P. In another embodiment, the fins 62 and the nanostructures 64, 66 are wider or narrower in one region (e.g., the n-type region 50N) than the fins 62 and the nanostructures 64, 66 in the other region (e.g., the p-type region 50P).

[0025] In Fig. 4. The STI regions 70 are formed above the substrate 50 and between adjacent fins 62. The STI regions 70 are arranged around at least one section of the fins 62 such that the nanostructures 64, 66 protrude between adjacent STI regions 70. In the illustrated embodiment, the upper surfaces of the STI regions 70 are coplanar (within process deviations) with the upper surfaces of the fins 62. In some embodiments, the upper surfaces of the STI regions 70 lie above or below the upper surfaces of the fins 62. The STI regions 70 separate the features of adjacent devices.

[0026] The STI areas 70 can be formed by any suitable method. For example, an insulating material can be formed over the substrate 50 and the nanostructures 64, 66 and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, or a combination thereof, and can be formed by a chemical vapor deposition (CVD) process, such as high-density plasma (HDP) CVD, flowable CVD (FCVD), or a combination thereof. Other insulating materials formed by any suitable method can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed. In one embodiment, the insulating material is formed such that excess insulating material covers the nanostructures 64, 66.Although the STI regions 70 are each shown as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a lining (not shown separately) can first be formed along the surfaces of the substrate 50, the fins 62, and the nanostructures 64, 66. A filler material, such as those described above, can then be formed over the lining.

[0027] Subsequently, an ablation process is applied to the insulation material to remove excess insulation material over the nanostructures 64, 66. In some embodiments, a planarization process such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or similar processes may be used. In embodiments where a mask remains on the nanostructures 64, 66, the planarization process may expose or remove the mask. After the planarization process, the top surfaces of the insulation material and the mask (if present) or the nanostructures 64, 66 are coplanar (within process variations). Accordingly, the top surfaces of the mask (if present) or the nanostructures 64, 66 are exposed through the insulation material. In the illustrated embodiment, no mask remains on the nanostructures 64, 66.The insulating material is then recessed to form the STI regions 70. The insulating material is recessed such that at least one section of the nanostructures 64, 66 protrudes between adjacent sections of the insulating material. Furthermore, the upper surfaces of the STI regions 70 can be flat, as shown, convex, concave (such as a depression), or a combination thereof. The upper surfaces of the STI regions 70 can be formed flat, convex, and / or concave by suitable etching. The insulating material can be recessed by a suitable etching method, e.g., a method that acts selectively on the insulating material (e.g., selectively etching the insulating material of the STI regions 70 at a faster rate than the materials of the fins 62 and the nanostructures 64, 66). For example, oxide removal can be carried out using dilute hydrofluoric acid (dHF).

[0028] The process described above is just one example of how the fins 62 and the nanostructures 64, 66 can be formed. In some embodiments, the fins 62 and / or the nanostructures 64, 66 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be deepened such that the epitaxial structures protrude from the dielectric layer to form the fins 62 and / or the nanostructures 64, 66. The epitaxial structures can include the previously described alternating semiconductor materials, such as the first semiconductor material and the second semiconductor material.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, which may eliminate the need for prior and / or subsequent implantations, although in situ and implantation doping can be used together.

[0029] Furthermore, suitable depressions (not shown separately) can be formed in the substrate 50, in the fins 62, and / or in the nanostructures 64, 66. In some embodiments, a p-type depression can be formed in the n-type region 50N and an n-type depression in the p-type region 50P. In some embodiments, a p-type depression or an n-type depression is formed in both the n-type region 50N and the p-type region 50P.

[0030] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be achieved using a mask (not shown separately), such as a photoresist. For example, a photoresist can be formed over the fins 62, the nanostructures 64 and 66, and the STI regions 70 in the n-type region 50N. The photoresist is then patterned to expose the p-type region 50P. The photoresist can be formed using a spin-depositing process and patterned using suitable photolithography techniques. Once the photoresist is patterned, an n-type contaminant is implanted into the p-type region 50P, and the photoresist can act as a mask to essentially prevent further implantation of n-type contaminants into the n-type region 50N.The n-type impurities may be phosphorus, arsenic, antimony or similar substances, occurring at concentrations in the range of approximately 10. 13 cm -3 up to about 10 14 cm -3 The photoresist can be implanted. After implantation, it can be removed, e.g., by a suitable ashing process.

[0031] Before or after implantation of the p-type region 50P, a mask (not shown separately), e.g., a photoresist, is formed over the fins 62, the nanostructures 64 and 66, and the STI regions 70 within the p-type region 50P. The photoresist is then patterned to expose the n-type region 50N. The photoresist can be formed using a spin-depositing process and patterned using suitable photolithography techniques. Once the photoresist is patterned, p-type impurities can be implanted into the n-type region 50N, and the photoresist can act as a mask to essentially prevent the implantation of p-type impurities into the p-type region 50P. The p-type impurities can be boron, boron fluoride, indium, or similar substances, introduced into the region at a concentration in the range of approximately 10 13 cm -3 up to about 10 14 cm -3The photoresist can be implanted. After implantation, it can be removed, e.g., by a suitable ashing process.

[0032] Following the implantation of the n-type region 50N and the p-type region 50P, an annealing process can be performed to repair the implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments where epitaxial structures for the fins 62 and / or the nanostructures 64, 66 are grown epitaxially, the grown materials can be doped in situ during growth, which may eliminate the need for implantation, although in situ and implantation doping can be used together.

[0033] In Fig. 5. A dielectric dummy layer 72 is formed on the fins 62 and the nanostructures 64, 66. The dielectric dummy layer 72 can be formed from a dielectric material such as silicon oxide, silicon nitride, a combination thereof, or the like, which can be deposited or thermally grown using suitable methods. A dummy gate layer 74 is formed over the dielectric dummy layer 72, and a mask layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 can be deposited over the dielectric dummy layer 72 and then planarized, e.g., by a CMP. The mask layer 76 can be deposited over the dummy gate layer 74. The dummy gate layer 74 can consist of a conductive or non-conductive material, such as...Amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), a metal, a metallic nitride, a metallic silicide, a metallic oxide, or the like, which can be deposited by physical vapor deposition (PVD), CVD, or the like. The dummy gate layer 74 can be formed from one or more materials exhibiting high etch selectivity for etching insulating materials, e.g., the STI regions 70 and / or the dielectric dummy layer 72. The mask layer 76 can be formed from a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single mask layer 76 are formed over the n-type region 50N and the p-type region 50P.In the illustrated embodiment, the dielectric dummy layer 72 covers the fins 62, the nanostructures 64, 66, and the STI regions 70, such that the dielectric dummy layer 72 extends over the STI regions 70 and between the dummy gate layer 74 and the STI regions 70. In another embodiment, the dielectric dummy layer 72 covers only the fins 62 and the nanostructures 64, 66.

[0034] In Fig. In step 6, the mask layer 76 is structured using suitable photolithography and etching techniques to form masks 86. The structure of the masks 86 is then transferred to the dummy gate layer 74 using a suitable etching technique to form dummy gates 84. The pattern of the masks 86 can optionally be further transferred to the dielectric dummy layer 72 using a suitable etching technique to form dummy dielectrics 82. The dummy gates 84 cover sections of the nanostructures 64, 66 that are exposed during subsequent processing to form channel regions. In particular, the dummy gates 84 extend along the sections of the nanostructures 66 that are to be structured to form channel regions 68. The structure of the masks 86 can be used to physically separate adjacent dummy gates 84.The dummy gates 84 can also have longitudinal directions that run essentially perpendicular (within process deviations) to the longitudinal directions of the fins 62. The masks 86 can optionally be removed after structuring, e.g., by a suitable etching technique.

[0035] The Fig. Figures 7A to 22B illustrate various additional steps in the manufacture of devices of this embodiment. Fig. 7A to 13B and the Fig. Figures 20A to 22B depict features in the n-type region 50N and the p-type region 50P. For example, the structures shown may be applicable to both the n-type region 50N and the p-type region 50P. Differences (if any) between the structures of the n-type region 50N and the p-type region 50P are described in the text accompanying each figure.

[0036] In the Fig. 7A and Fig. In 7B, gate spacers 90 are formed over the nanostructures 64, 66, on exposed sidewalls of the masks 86 (if present), the dummy gates 84, and the dummy dielectrics 82. The gate spacers 90 can be formed by conformal deposition of one or more dielectric materials and subsequent etching of the dielectric material(s). Acceptable dielectric materials include oxides such as silicon oxide or aluminum oxide, nitrides such as silicon nitride, carbides such as silicon carbide, combinations thereof such as silicon oxynitride, silicon oxycarbide, silicon carbonitride, or silicon oxycarbonitride, or similar materials. The dielectric materials can be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or similar processes. In the illustrated embodiment, the gate spacers 90 each comprise several layers, e.g.,a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layers 90A and the second spacer layers 90B are made of silicon oxycarbonitride (e.g. SiO₂). x NyC 1-x-y, where x and y lie in the range of 0 to 1). For example, the first spacer layers 90A can be formed from a similar or different composition of silicon oxycarbonitride than the second spacer layers 90B. To structure the dielectric material(s), a suitable etching process, such as a dry etching process, a wet etching process, or a combination thereof, can be carried out. The etching can be anisotropic. After etching, the dielectric material(s) have sections that remain on the sidewalls of the dummy gates 84 (thus forming the gate spacers 90). After etching, the gate spacers 90 can have straight sidewalls (as shown) or curved sidewalls (not shown separately). As described in more detail below, the dielectric material orThe dielectric materials may also have parts after etching that remain on the side walls of the fins 62 and / or the nanostructures 64, 66 (thus forming fin spacers).

[0037] Furthermore, implantations can be performed to form lightly doped source / drain regions (LDDs) (not shown separately). In embodiments with different device types, similar to the previously described implants for the wells, a mask (not shown separately), e.g., a photoresist, can be formed over the n-type region 50N while the p-type region 50P is exposed, and impurities of a suitable type (e.g., p-type) can be implanted into the fins 62 and / or the nanostructures 64, 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask (not shown separately), such as a photoresist, can be formed over the n-type region 50N while the p-type region 50P is exposed. B. a photoresist is formed over the p-type region 50P while the n-type region 50N is exposed, and impurities of the appropriate type (e.g. n-type) can be implanted into the fins 62 and / or the nanostructures 64, 66 exposed in the n-type region 50N.The mask can then be removed. The n-type contaminants can be any of the previously described n-type contaminants, and the p-type contaminants can be any of the previously described p-type contaminants. During implantation, the channel regions 68 remain covered by the dummy gates 84, so that the channel regions 68 remain essentially free of the contaminants implanted to form the LDD regions. The LDD regions can have a concentration of contaminants in the range of approximately 10. 15 cm -3 up to about 10 19 cm -3 exhibit. An annealing process can be used to repair implant damage and activate the implanted impurities.

[0038] It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other methods and procedures can also be used. For example, fewer or additional spacers can be used, a different sequence of steps can be employed, additional spacers can be formed and removed, and / or similar. Furthermore, the n-type and p-type devices can be formed with different structures and steps.

[0039] In the Fig. 8A and Fig. In 8B, source / drain depressions 94 are formed in the nanostructures 64, 66. In the illustrated embodiment, the source / drain depressions 94 extend through the nanostructures 64, 66 and into the fins 62. The source / drain depressions 94 can also extend into the substrate 50. In various embodiments, the source / drain depressions 94 can extend to a top surface of the substrate 50 without etching the substrate 50; the fins 62 can be etched such that the bottom surfaces of the source / drain depressions 94 are located below the top surfaces of the STI regions 70; or similar. The source / drain depressions 94 can be formed by etching the nanostructures 64, 66 using an anisotropic etching process, such as RIE, NBE, or similar.The gate spacers 90 and the dummy gates 84 together mask sections of the fins 62 and / or the nanostructures 64, 66 during the etching processes used to form the source / drain wells 94. A single etching process can be used to etch each of the nanostructures 64, 66, or multiple etching processes can be used to etch the nanostructures 64, 66. Timed etching processes can be used to stop the etching of the source / drain wells 94 after they have reached a desired depth.

[0040] Optionally, internal spacers 96 are formed on the sidewalls of the remaining sections of the first nanostructures 64, e.g., on the sidewalls exposed by the source / drain depressions 94. As will be described in more detail later, source / drain regions are subsequently formed in the source / drain depressions 94, and the first nanostructures 64 are then replaced by corresponding gate structures. The internal spacers 96 serve as insulating features between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the internal spacers 96 can be used to essentially prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as those used to remove the first nanostructures 64.

[0041] To form the internal spacers 96, the source / drain depressions 94 can, for example, be laterally extended. In particular, sections of the sidewalls of the first nanostructures 64, exposed by the source / drain depressions 94, can be deepened. Although the sidewalls of the first nanostructures 64 are shown as straight, they can be concave or convex. The sidewalls can be deepened by a suitable etching process, e.g., one that is selective for the material of the first nanostructures 64 (e.g., the material of the first nanostructures 64 etches selectively at a faster rate than the material of the second nanostructures 66). The etching can be isotropic.For example, if the second nanostructures 66 are made of silicon and the first nanostructures 64 are made of silicon-germanium, the etching process can be a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process can be a dry etching process using a fluorine-based gas, such as hydrogen fluoride (HF) gas. In some embodiments, the same etching process can be performed continuously to form both the source / drain depressions 94 and to recess the sidewalls of the first nanostructures 64. The internal spacers 96 can then be formed by conformal forming of an insulating material and subsequent etching of the insulating material.The insulating material can be silicon nitride or silicon oxynitride, although any suitable material, such as materials with a low dielectric constant (low k-value) with a k-value of less than approximately 3.5, can be used. The insulating material can be deposited by a conformal deposition process, such as ALD, CVD, or similar. The etching of the insulating material can be anisotropic. For example, the etching process can be a dry etching process, such as RIE, NBE, or similar. Although the outer sidewalls of the inner spacers 96 are shown as being flush with the sidewalls of the gate spacers 90, the outer sidewalls of the inner spacers 96 can extend beyond or be recessed from the sidewalls of the gate spacers 90. In other words, the inner spacers 96 can partially, completely, or excessively fill the sidewall recesses.Although the side walls of the inner spacers 96 are shown as straight, the side walls of the inner spacers 96 can be concave or convex.

[0042] In the Fig. 9A and Fig. In embodiment 9B, epitaxial source / drain regions 98 are formed in the source / drain recesses 94. The epitaxial source / drain regions 98 are configured in the source / drain recesses 94 such that each dummy gate 84 (and its corresponding channel regions 68) is positioned between adjacent pairs of epitaxial source / drain regions 98. In some embodiments, gate spacers 90 are used to separate the epitaxial source / drain regions 98 from the dummy gates 84, and inner spacers 96 are used to separate the epitaxial source / drain regions 98 from the first nanostructures 64 by a suitable lateral distance, so that the epitaxial source / drain regions 98 do not short-circuit with subsequently formed gates of the resulting nano-FETs.A material of the epitaxial source / drain regions 98 can be selected such that it exerts stresses in the respective channel regions 68 and thereby improves performance.

[0043] The epitaxial source / drain regions 98 in the n-type region 50N can be formed by masking the p-type region 50P. The epitaxial source / drain regions 98 in the n-type region 50N are then epitaxially grown in the source / drain depressions 94 in the n-type region 50N. The epitaxial source / drain regions 98 can comprise any suitable material appropriate for n-type nanoFETs. For example, the epitaxial source / drain regions 98 in the n-type region 50N can comprise materials that exert a tensile stress on the channel regions 68, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or similar materials. The epitaxial source / drain regions 98 in the n-type region 50N can have surfaces that are raised from the respective surfaces of the fins 62 and the nanostructures 64, 66, and can have facets.

[0044] The epitaxial source / drain regions 98 in the p-type region 50P can be formed by masking the n-type region 50N. The epitaxial source / drain regions 98 in the p-type region 50P are then epitaxially grown in the source / drain depressions 94 in the p-type region 50P. The epitaxial source / drain regions 98 can comprise any suitable material appropriate for p-type nanoFETs. For example, the epitaxial source / drain regions 98 in the p-type region 50P can comprise materials that exert a compressive stress on the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or similar materials. The epitaxial source / drain regions 98 in the p-type region 50P may have surfaces that stand out from the respective surfaces of the fins 62 and the nanostructures 64, 66, and may have facets.

[0045] The epitaxial source / drain regions 98, the nanostructures 64, 66 and / or the fins 62 can be implanted with dopants to form source / drain regions, similar to the previously described procedure for forming LDD regions, followed by annealing. The source / drain regions can accommodate an impurity concentration in the range of approximately 10 19 cm -3 up to about 10 21 cm -3 exhibiting the following characteristics: The n-type and / or p-type impurities for the source / drain regions can be any of the impurities described above. In some embodiments, the epitaxial source / drain regions 98 can be doped in situ during growth.

[0046] As a result of the epitaxial processes used to form the epitaxial source / drain regions 98, the upper surfaces of the epitaxial source / drain regions exhibit facets that extend laterally outward beyond the side walls of the fins 62 and the nanostructures 64, 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 98 to merge into one another, as shown in Fig. 9C is shown. In some embodiments, adjacent epitaxial source / drain regions 98 remain separated after completion of the epitaxial process, as shown in Fig. Figure 9D illustrates this. In the illustrated embodiments, the spacer etching used to form the gate spacers 90 is adapted such that fin spacers 92 are also formed on the sidewalls of the fins 62 and / or the nanostructures 64, 66. The fin spacers 92 are formed to cover a section of the sidewalls of the fins 62 that extend over the STI regions 70, thereby blocking epitaxial growth. In another embodiment, the spacer etching used to form the gate spacers 90 is adjusted so that no fin spacers are formed, allowing the epitaxial source / drain regions 98 to extend to the surface of the STI regions 70.

[0047] The epitaxial source / drain regions 98 can comprise one or more semiconductor material layers. For example, the epitaxial source / drain regions 98 can each comprise an intermediate layer 98A, a main layer 98B, and a final layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers can be used for the epitaxial source / drain regions 98. Each of the liner layer 98A, the main layer 98B, and the final layer 98C can be formed from different semiconductor materials and doped to different dopant concentrations. In some embodiments, the intermediate layer 98A can have a lower dopant concentration than the main layer 98B, and the final layer 98C can have a higher dopant concentration than the intermediate layer 98A and a lower concentration than the main layer 98B.In embodiments in which the epitaxial source / drain regions 98 comprise three semiconductor material layers, the liner layers 98A can be grown in the source / drain depressions 94, the main layers 98B can be grown on the liner layers 98A, and the termination layers 98C can be grown on the main layers 98B.

[0048] In the Fig. 10A and Fig. In 10B, a first ILD 104 is deposited over the epitaxial source / drain regions 98, the gate spacers 90, the masks 86 (if present), or the dummy gates 84. The first ILD 104 can consist of a dielectric material and be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or similar. Acceptable dielectric materials include phosphosilicate glass (PSG), boron silicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or similar. Other insulating materials formed by any suitable method may be used.

[0049] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first ILD 104 and the epitaxial source / drain regions 98, the gate spacers 90, and the masks 86 (if present) or the dummy gates 84. The CESL 102 can be formed from a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which exhibits high etch selectivity with respect to the etching of the first ILD 104. The CESL 102 can be formed by any suitable method, such as CVD, ALD, or the like.

[0050] In the Fig. 11A and Fig. In 11B, a removal process is performed to planarize the top surfaces of the first ILD 104 with the top surfaces of the masks 86 (if present) or the dummy gates 84. In some embodiments, a planarization process such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or similar processes may be used. The planarization process may also remove the masks 86 on the dummy gates 84 and sections of the gate spacers 90 along the sidewalls of the masks 86. After the planarization process, the top surfaces of the gate spacers 90, the first ILD 104, the CESL 102, and the masks 86 (if present) or the dummy gates 84 are coplanar (within process deviations). Accordingly, the top surfaces of the masks 86 (if present) or the dummy gates 84 are exposed through the first ILD 104.In the illustrated embodiment, the masks 86 remain, and the planarization process flattens the top surfaces of the first ILD 104 with the top surfaces of the masks 86.

[0051] In the Fig. 12A and Fig. In 12B, the masks 86 (if present) and the dummy gates 84 are removed in an etching process, creating recesses 110. Sections of the dummy dielectrics 82 in the recesses 110 are also removed. In some embodiments, the dummy gates 84 are removed by an anisotropic dry etching process. For example, the etching process may involve a dry etching process in which reactive gas(es) are used that selectively etch the dummy gates 84 at a faster rate than the first ILD 104 or the gate spacers 90. During removal, the dummy dielectrics 82 may be used as etch stop layers when the dummy gates 84 are etched. The dummy dielectrics 82 are then removed. Each recess 110 exposes and / or overlays sections of the channel regions 68. Sections of the second nanostructures 66, which act as the channel regions 68, are arranged between adjacent pairs of the epitaxial source / drain regions 98.

[0052] The remaining portions of the first nanostructures 64 are then removed to enlarge the recesses 110. These remaining portions can be removed by a suitable etching process that selectively etches the material of the first nanostructures 64 at a faster rate than the material of the second nanostructures 66. The etching can be isotropic. For example, if the first nanostructures 64 are silicon germanium and the second nanostructures 66 are silicon, the etching process can be a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the second nanostructures 66. As described in the Fig. As shown more clearly in Figures 14 to 19 (described in more detail below), the remaining sections of the second nanostructures can have 66 rounded corners.

[0053] In the Fig. 13A and Fig. In the recesses 110 of nanostructure 13B, a dielectric gate layer 112 is formed. A gate electrode layer 114 is formed on the gate dielectric layer 112. The gate dielectric layer 112 and the gate electrode layer 114 are layers for replacement gates and each encloses all (e.g., four) sides of the second nanostructure 66.

[0054] The dielectric gate layer 112 is arranged on the sidewalls and / or top surfaces of the fins 62, on the top surfaces, sidewalls, and bottom surfaces of the second nanostructures 66, and on the sidewalls of the gate spacers 90. The dielectric gate layer 112 can also be formed on the top surfaces of the first ILD 104 and the gate spacers 90. The dielectric gate layer 112 can comprise an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, combinations thereof, multiple layers thereof, or the like. The dielectric gate layer 112 can comprise a dielectric material with a k-value greater than approximately 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although in the Fig. 13A and Fig. Figure 13B shows a single-layer gate dielectric layer 112, the gate dielectric layer 112 can comprise an interface layer and a main layer, as described in more detail below.

[0055] The gate electrode layer 114 can comprise a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, multiple layers thereof, or similar materials. Although in the Fig. 13A and Fig. Figure 13B shows a single-layer gate electrode layer 114, the gate electrode layer 114 can, as described in more detail below, comprise any number of exit work tuning layers, any number of adhesion layers and a filler material.

[0056] The formation of the dielectric gate layers 112 in the n-type region 50N and in the p-type region 50P can occur simultaneously, so that the dielectric gate layers 112 in each region are formed from the same materials, and the formation of the gate electrode layers 114 can also occur simultaneously, so that the gate electrode layers 114 in each region are formed from the same materials. In some embodiments, the dielectric gate layers 112 in each region can be formed by different processes, so that the dielectric gate layers 112 consist of different materials and / or can have a different number of layers, and / or the gate electrode layers 114 in each region can be formed by different processes, so that the gate electrode layers 114 consist of different materials and / or can have a different number of layers.Various masking steps can be used to mask and expose suitable areas when different processes are employed. In the following description, the gate electrode layers 114 in the n-type region 50N and the gate electrode layers 114 in the p-type region 50P are formed separately.

[0057] The Fig. Figures 14 to 19 illustrate a process in which dielectric gate layers 112 and gate electrode layers 114 for replacement gates are formed in the recesses 110 in the p-type region 50P. Features in regions corresponding to a region 50R in Fig. 13A are similar, are shown. Fig. Figure 23 is a flowchart of an exemplary method 200 for forming the replacement gate layers in the p-type region 50P according to some embodiments. Fig. 14 to 19 are used in connection with Fig. 23 described. The gate electrode layers 114 comprise a WFM layer treated with fluorine. The treatment process involves soaking the WFM layer with an aluminum-containing precursor and subsequently soaking the WFM layer with a fluorine-containing precursor. As a result of the fluorine treatment, a flat-band voltage (VFB) of the resulting transistor can be increased toward a band edge of the metal of the WFM layer, a threshold voltage of the resulting transistor can be lowered, and the device performance can be improved. The n-type region 50N can be masked in the p-type region 50P, at least during the formation of the gate electrode layers 114.

[0058] In Fig. In steps 14 and 202 of process 200, the dielectric gate layer 112 is deposited in the recesses 110 of the p-type region 50P. The fabrication methods for the dielectric gate layer 112 can include molecular beam deposition (MBD), ALD, PECVD, and the like. The gate dielectric layer 112 envelops all (e.g., four) sides of the second nanostructures 66. In the illustrated embodiment, the gate dielectric layer 112 is multilayered and comprises a first gate dielectric layer 112A (e.g., an interface layer) and an overlying second gate dielectric layer 112B (e.g., a high-k dielectric layer). The first dielectric gate layer 112A can be formed from silicon oxide, and the second dielectric gate layer 112B from hafnium oxide.

[0059] In Fig. In steps 15 and 204 of process 200, a layer of a first conductive material 114A is conformally deposited on the gate dielectric layer 112 in the p-type region 50P. The first conductive material 114A is a p-type exit work metal (PWFM) such as titanium nitride, tantalum nitride, titanium silicon nitride, tungsten nitride, molybdenum nitride, or the like, which can be deposited by CVD, ALD, PECVD, PVD, or the like. Therefore, the layer of first conductive material 114A can be referred to as the exit work tuning layer. The first conductive material 114A can have a thickness in the range of about 1 nm to about 2 nm. The first conductive material 114A can be deposited such that it surrounds each of the second nanostructures 66. After the first conductive material 114A has been deposited, openings 116 can remain in the regions 50I between the second nanostructures 66.

[0060] In Fig. In steps 16 and 206 of process 200, a treatment process is performed on the exposed surfaces of the first conductive material 114A. This treatment process comprises an aluminum treatment 118 and a fluorine treatment 120. The fluorine treatment 120 introduces fluorine into the first conductive material 114A and (optionally) into the second dielectric gate layer 112B. As described in more detail below, the aluminum treatment 118 enhances the effectiveness of the fluorine treatment 120, resulting in more fluorine being introduced into the second dielectric gate layer 112B and / or the first conductive material 114A compared to other treatment processes.

[0061] In step 208 of the process 200, the aluminum treatment 118 is applied to the first conductive material 114A. In some embodiments, the aluminum treatment 118 is a deposition process (e.g., an ALD process, a CVD process, or the like) that involves flowing an aluminum-containing precursor over the surfaces of the first conductive material 114A. In particular, the aluminum treatment 118 can be carried out by placing the substrate 50 in a deposition chamber and adding the aluminum-containing precursor to the deposition chamber. In some embodiments, the aluminum-containing precursor is an organoaluminum such as triethylaluminum (TEA) (Al₂(C₂H₅)₆), trimethylaluminum (TMA) (Al₂(CH₃)₆), or the like. During the aluminium treatment 118, the aluminium dissociates from the aluminium-containing precursor and is introduced into the first conductive material 114A, while the other group (e.g. ethyl group, methyl group, etc.)), to which the aluminum is bound, from which the aluminum-containing precursor is dissociated and evacuated from the deposition chamber. As a result of the aluminum treatment 118, the first conductive material 114A can contain aluminum in a concentration in the range of about 0.5 at.% to about 25 at.%.

[0062] The aluminum treatment 118 can be carried out at a temperature in the range of approximately 250 °C to approximately 475 °C, for example, by maintaining the deposition chamber at a temperature within this range. Performing the aluminum treatment 118 at a temperature within this range introduces a desired amount of aluminum into the first conductive material 114A, creating a sufficient number of sites for fluorine binding. If the aluminum treatment 118 is performed at a temperature outside this range, the desired amount of aluminum may not be introduced into the first conductive material 114A. If the temperature of the aluminum treatment 118 is less than 250 °C, the aluminum-containing precursor does not dissociate properly and does not create a sufficient number of sites for fluorine binding in the first conductive material 114A.If the temperature of the aluminium treatment 118 is higher than 475 °C, the amount of aluminium that dissociates from the aluminium-containing precursor may be too large to be precisely controlled.

[0063] The aluminum treatment 118 can be performed for a duration ranging from approximately 1 second to approximately 15 minutes, for example, by allowing the aluminum-containing precursor to flow in the deposition chamber for a duration within this range. Performing the aluminum treatment 118 for a duration within this range introduces a desired amount of aluminum into the first conductive material 114A, creating a sufficient number of sites for fluorine binding. If the aluminum treatment 118 is performed for a duration outside this range, the desired amount of aluminum may not be introduced into the first conductive material 114A. If the aluminum treatment 118 is performed for less than approximately 1 second, an insufficient number of sites for fluorine binding will be created in the first conductive material 114A.If the aluminium treatment 118 is carried out for longer than about 15 minutes, an excessive amount of aluminium may be introduced into the device, which will undesirably change the threshold voltage of the resulting transistor.

[0064] In some embodiments, the aluminum treatment 118 is a deposition process in which a single chemical (e.g., TEA, TMA, or similar) is used without any other chemical that would initiate a reduction-oxidation reaction. Therefore, the aluminum treatment 118 does not deposit a continuous film on the first conductive material 114A. However, as described in more detail below, discrete pockets containing aluminum residues can be formed on the upper surface of the first conductive material 114A.

[0065] In other embodiments, no residues of the aluminium treatment 118 can form on the first conductive material 114A. Fig. Figure 24 shows, for example, an embodiment in which no aluminum residues are formed. Instead, the aluminum can diffuse into the first conductive material 114A.

[0066] In some embodiments, the aluminum treatment 118 does not lead to aluminum diffusion into the underlying dielectric gate layer 112, so that the underlying dielectric gate layer 112 (e.g., the second dielectric gate layer 112B) is free of aluminum. In another embodiment, the aluminum treatment 118 can still lead to aluminum diffusion into the underlying dielectric gate layer 112 (e.g., the second dielectric gate layer 112B), and aluminum can be detected in the second dielectric gate layer 112B by X-ray photoelectron spectroscopy analysis.

[0067] Fluorine readily binds to aluminum. Introducing aluminum into the second dielectric gate layer 112B and / or the first conductive material 114A during the aluminum treatment 118 increases the number of sites where fluorine can bind during the fluorine treatment 120. Thus, performing the aluminum treatment 118 increases the effectiveness of the fluorine treatment 120.

[0068] In step 210 of the process 200, the fluorine treatment 120 is applied to the first conductive material 114A. In some embodiments, the fluorine treatment 120 is a deposition process (e.g., an ALD process, a CVD process, or the like) that includes the flow of a fluorine-containing precursor over the surfaces of the first conductive material 114A. In particular, the fluorine treatment 120 can be carried out by placing the substrate 50 in a deposition chamber and adding the fluorine-containing precursor to the deposition chamber. In some embodiments, the fluorine-containing precursor is WF x , NF x , TiF x , TaF x , HfF xor the like, where x is an integer in the range of 1 to 6. For example, the fluorine-containing precursor can be WF6 and / or NF3. During the fluorine treatment 120, the fluorine dissociates from the fluorine-containing precursor and is incorporated into the first conductive material 114A, bonding with the aluminum that was previously incorporated into the first conductive material 114A. As a result of the fluorine treatment 120, the first conductive material 114A can contain fluorine in a concentration in the range of about 2.5 at% to about 30 at%.

[0069] The fluorine treatment 120 can be performed at a temperature in the range of approximately 250 °C to approximately 475 °C, for example, by maintaining the deposition chamber at a temperature within this range. Performing the fluorine treatment 120 at a temperature within this range causes the desired modification of the first conductive material 114A and / or its underlying layers. Performing the fluorine treatment 120 at a temperature outside this range may not have the desired effect on the first conductive material 114A and / or its underlying layers. If the temperature of the fluorine treatment 120 is less than 250 °C, the fluorine-containing precursor does not dissociate properly and does not cause the desired modification of the first conductive material 114A and / or its underlying layers.If the temperature of the fluorine treatment is greater than 475 °C, the amount of fluorine dissociated from the fluorine-containing precursor may be too large to be precisely controlled.

[0070] The fluorine treatment 120 can be performed for a duration ranging from approximately 1 second to approximately 15 minutes, for example, by allowing the fluorine-containing precursor to flow into the deposition chamber for a duration within this range. Performing the fluorine treatment 120 for a duration within this range sets the threshold voltage of the resulting transistor by a desired amount. If the fluorine treatment 120 is performed for a duration outside this range, the threshold voltage of the resulting transistor may not be set by the desired value. If the fluorine treatment 120 is performed for less than approximately 1 second, the amount of fluorine introduced by the treatment process may be insufficient to tune the threshold voltage of the resulting transistor.If the fluorine treatment 120 is performed for longer than about 15 minutes, an excessive amount of fluorine may be introduced into the device, leading to a reduction in the capacitance equivalent thickness (CET) (e.g., regrowth of the first dielectric gate layer 112A).

[0071] In some embodiments, the fluorine treatment 120 is a deposition process in which a single chemical (e.g., WF6, NF3, or similar) is used without any other chemical that would initiate a reduction-oxidation reaction. Therefore, the fluorine treatment 120 does not deposit a continuous film on the first conductive material 114A. In other embodiments, where the fluorine-containing precursor also contains a metal, discrete pockets with a residue of the metal can form on the upper surface of the first conductive material 114A. In embodiments where the fluorine-containing precursor used during the fluorine treatment 120 is WF6, the residue can be a tungsten residue formed on the first conductive material 114A.The treatment process can thus form a residue 114B consisting of one or more metals, including residual aluminum from the aluminum-containing precursor used during the aluminum treatment 118 (e.g., aluminum that did not bond with fluorine) and / or residual metal from the fluorine-containing precursor used during the fluorine treatment 120 (e.g., tungsten if the fluorine-containing precursor is WF6). Each pocket of residue 114B can be separate from other pockets of residue 114B, and a continuous film is not formed on the first conductive material 114A. The residue 114B can form on exposed surfaces of the first conductive material 114A, including in regions 50I of the gate structures between the second nanostructures 66.In some embodiments, where the residue 114B contains aluminum and tungsten residues and the second dielectric gate layer 112B contains hafnium oxide, the ratio of aluminum to hafnium in regions 50I may be less than about 0.1 (as in a range of about 0.005 to about 0.1) or less than about 0.005, and the ratio of tungsten to hafnium in regions 50I may be less than about 0.1 (as in a range of about 0.005 to about 0.1) or less than about 0.005. If the ratio of tungsten to hafnium or the ratio of aluminum to hafnium in regions 50I is greater than about 0.1, the resulting device may not have a desired threshold voltage (e.g., the threshold voltage may be too high).

[0072] In other embodiments where the fluorine-containing precursor does not include a metal (e.g., the fluorine-containing precursor is NF3), residues from the fluorine treatment 120 may not be formed on the first conductive material 114A. Fig. Figure 24 shows, for example, an embodiment in which no metal residue is formed and the fluorine-containing precursor used during the fluorine treatment 120 is NF3.

[0073] In some embodiments, the fluorine treatment 120 can further lead to fluorine diffusion into an underlying dielectric gate layer 112 (e.g., the second dielectric gate layer 112B), and fluorine can be observed in the second dielectric gate layer 112B by X-ray photoelectron spectroscopy analysis. For example, in embodiments where the second dielectric gate layer 112B contains hafnium oxide, the fluorine-to-hafnium ratio in regions 50I (e.g., in the second dielectric gate layer 112B) may be in the range of about 0.015 to about 0.2 as a result of the fluorine treatment 120. If the fluorine-to-hafnium ratio in regions 50I is less than about 0.015, the amount of fluorine may not be sufficient to set a threshold voltage of the resulting transistor.If the ratio of fluorine to hafnium in areas 50I is greater than approximately 0.2, an excessive amount of fluorine may have been introduced into the second dielectric gate layer 112B, leading to a loss of CET (e.g., regrowth of the first dielectric gate layer 112A). As a result of the fluorine treatment 120, the second dielectric gate layer 112B may contain fluorine in a concentration ranging from approximately 2.5 at.% to approximately 30 at.%.

[0074] As mentioned above, introducing aluminum into the first conductive material 114A during the aluminum treatment 118 increases the number of sites to which fluorine can bind during the fluorine treatment 120. Furthermore, Al-F bonds are more stable than Ti-F bonds, and thus the amount of fluorine introduced into the first conductive material 114A can remain more stable and decrease less over time than with other treatment methods. For example, in experimental data, embodiments in which a TEA treatment was performed prior to a WF6 treatment increased the fluorine concentration of the first conductive material 114A by up to 10.8 atomic percent, enabling a positive shift in the effective work function of more than 50 mV.

[0075] In some embodiments, the aluminum treatment 118 and the fluorine treatment 120 are carried out in situ, e.g., in the same deposition chamber, without interrupting the vacuum in the deposition chamber between the aluminum treatment 118 and the fluorine treatment 120. The treatment process may, for example, include: placing the substrate 50 in the deposition chamber; flowing the aluminum-containing precursor into the deposition chamber (thus performing the aluminum treatment 118); evacuating the aluminum-containing precursor from the deposition chamber; flowing the fluorine-containing precursor into the deposition chamber (thus performing the fluorine treatment 120); evacuating the fluorine-containing precursor from the deposition chamber; and removing the substrate 50 from the deposition chamber.In various embodiments, the aluminium treatment 118 and the fluorine treatment 120 are carried out at the same temperature and for the same duration; the aluminium treatment 118 and the fluorine treatment 120 are carried out at the same temperature and for different durations; the aluminium treatment 118 and the fluorine treatment 120 are carried out at different temperatures and for the same duration; or the aluminium treatment 118 and the fluorine treatment 120 are carried out at different temperatures and for different durations.

[0076] Accordingly, as previously described, in various embodiments a fluorine-treated WFM layer (e.g., the first conductive material 114A) is formed, and during the formation of the fluorine-treated WFM layer, fluorine can diffuse into an underlying dielectric gate layer 112 (e.g., the second dielectric gate layer 112B). As a result, the flat-band voltage (VFB) of the resulting transistor can be increased toward a band edge of the metal of the WFM layer, a threshold voltage of the resulting device can be reduced, and the device performance can be improved. In experimental data, for example, embodiment fluorine treatments using WF6 impregnation have resulted in a positive effective work function shift on a metal-oxide-semiconductor capacitor from about 15 mV to about 130 mV after formation gas annealing.

[0077] In Fig. In steps 17 and 212 of process 200, a layer of a second conductive material 114C is conformally deposited onto the residue 114B (if present) and / or the first conductive material 114A. The second conductive material 114C is a p-type exit work metal (PWFM) such as titanium nitride, tantalum nitride, titanium silicon nitride, tungsten nitride, molybdenum nitride, or the like, which can be deposited by CVD, ALD, PECVD, PVD, or the like. Therefore, the layer of the second conductive material 114C can be referred to as the exit work matching layer. The second conductive material 114C can have a thickness in the range of about 1 nm to about 2 nm. Since the second conductive material 114C is deposited after the aluminium treatment 118 and the fluorine treatment 120, the second conductive material 114C can be free of fluorine and aluminium or at least have a lower fluorine concentration of fluorine and aluminium than the first conductive material 114A.

[0078] In some embodiments, the first conductive material 114A differs from the second conductive material 114C. For example, the first conductive material 114A can be titanium nitride and the second conductive material 114C tantalum nitride. In some embodiments, the first conductive material 114A is the same as the second conductive material 114C. For example, the first conductive material 114A and the second conductive material 114C can both be titanium nitride.

[0079] The second conductive material 114C can fill a remaining part of the area 50I between the second nanostructures 66 (e.g., fill the openings 116, see Fig. 15 and Fig. 16) For example, the second conductive material 114C can be applied to the first conductive material 114A until they merge and converge, and in some embodiments an interface 114I can be formed by a first section of the second conductive material 114C (e.g., a section of the section of the second conductive material 114C around a second nanostructure 66) that contacts a second section of the second conductive material 114C (e.g., an adjacent section of the section of the second conductive material 114C around an adjacent second nanostructure 66) in the region 50I.

[0080] In Fig. In steps 18 and 214 of process 200, the remaining sections of the gate electrode layers 114 are deposited to fill the remaining sections of the recesses 110 in the p-type region 50P. In particular, a filler layer 114E is deposited on the second conductive material 114C. Optionally, an adhesive layer 114D is formed between the filler layer 114E and the second conductive material 114C. After completion of the formation, the gate electrode layers 114 in the p-type region 50P comprise the first conductive material 114A, the remainder 114B (if present), the second conductive material 114C, the adhesive layer 114D, and the filler layer 114E.

[0081] The adhesive layer 114D can be conformally deposited over the second conductive material 114C. The adhesive layer 114D can be formed from a conductive material such as titanium nitride, tantalum nitride, or similar, which can be deposited by CVD, ALD, PECVD, PVD, or similar processes. The adhesive layer 114D can alternatively be referred to as the bonding layer and improves the adhesion between the second conductive material 114C and the filler layer 114E.

[0082] The filler layer 114E is deposited over the adhesive layer 114D. In some embodiments, the filler layer 114E can be formed from a conductive material such as cobalt, ruthenium, aluminum, tungsten, combinations thereof, or the like, which can be deposited by CVD, ALD, PECVD, PVD, or the like. The filler layer 114E fills the remaining portions of the recesses 110 in the p-type region 50P.

[0083] In the p-type region 50P, the dielectric gate layers 112 (e.g., the first dielectric gate layer 112A and the second dielectric gate layer 112B) and the gate electrode layers 114 (e.g., the first conductive material 114A, the residue 114B (if present), the second conductive material 114C, the adhesive layer 114D, and the filler layer 114E) can each be formed on the upper surfaces, sidewalls, and lower surfaces of the second nanostructures 66. The residue 114B can be formed at an interface between the first conductive material 114A and the second conductive material 114C, and a metallic element of the residue 114B can differ from a metallic element of the first conductive material 114A and / or a metallic element of the second conductive material 114C.

[0084] Fig. Figure 19 shows the dielectric gate layers 112 and gate electrode layers 114 for substitute gates formed in the recesses 110 in the n-type region 50N. Features are shown in regions corresponding to a region 50R in Fig. 13A are similar. In some embodiments, the dielectric gate layers 112 in the n-type region 50N and in the p-type region 50P can be formed simultaneously. Furthermore, at least sections of the gate electrode layers 114 in the n-type region 50N can be formed either before or after the formation of the gate electrode layers 114 in the p-type region 50P (see Fig. 14 to 18), and at least sections of the gate electrode layers 114 in the n-type region 50N can be formed, while the p-type region 50P is masked. Thus, the gate electrode layers 114 in the n-type region 50N can comprise different materials than the gate electrode layers 114 in the p-type region 50P. For example, the gate electrode layers 114 in the n-type region 50N can include a layer of a third conductive material 114F. The third conductive material 114F is an n-type exit work metal (NWFM), such as titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, or similar materials, which can be deposited by CVD, ALD, PECVD, PVD, or similar processes. Therefore, the layer of the third conductive material 114F can be referred to as the exit work tuning layer.Since the third conductive material 114F is deposited after the aluminum treatment 118 and the fluorine treatment 120, the third conductive material 114F can be free of fluorine and aluminum, or at least have a lower fluorine and aluminum concentration than the first conductive material 114A. The gate electrode layers 114 in the n-type region 50N can also include an adhesive layer 114D and a filler layer 114E. The adhesive layer 114D in the n-type region 50N can (or may not) have the same material composition and be deposited simultaneously with the adhesive layer 114D in the p-type region 50P. The filler layer 114E in the n-type region 50N can (or may not) have the same material composition and be deposited simultaneously with the filler layer 114E in the p-type region 50P.

[0085] In some embodiments, the third conductive material 114F differs from the first conductive material 114A and the second conductive material 114C. For example, the first conductive material 114A and the second conductive material 114C can each be titanium nitride or tantalum nitride, while the third conductive material 114F is aluminum nitride.

[0086] In the Fig. 20A and Fig. In 20B, a removal process is performed to remove the excess portions of the materials of the dielectric gate layer 112 and the gate electrode layer 114 that are located above the upper surfaces of the first ILD 104 and the gate spacers 90, thereby forming the gate dielectric 122 and gate electrodes 124. In some embodiments, a planarization process such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like may be used. In the planarized state, the gate dielectric layer 112 has portions that remain in the recesses 110 (thus forming the gate dielectrics 122). In the planarized state, the gate electrode layer 114 has portions that remain in the recesses 110 (thus forming the gate electrodes 124). The top surfaces of the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122 (e.g.the first dielectric gate layers 112A and the second dielectric gate layers 112B, see . Fig. 18) and the gate electrodes 124 (e.g. the first conductive material 114A, the second conductive material 114C, the adhesive layer 114D, the filler layer 114E and the third conductive material 114F, see Fig. 18 and Fig. 19) are coplanar (within process variations). The gate dielectrics 122 and the gate electrodes 124 form substitute gates of the resulting nanoFETs. Each pair of a gate dielectric 122 and a gate electrode 124 can be collectively referred to as a “gate structure”. The gate structures extend along the top surfaces, side walls, and bottom surfaces of a channel region 68 of the second nanostructures 66.

[0087] In the Fig. 21A and Fig. In embodiment 21B, a second ILD 134 is deposited over the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. In some embodiments, the second ILD 134 is a flowable film formed by a flowable CVD process. In other embodiments, the second ILD 134 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, and can be deposited by any suitable process, such as CVD and PECVD.

[0088] In some embodiments, an etch stop layer (ESL) 132 is formed between the second ILD 134 and the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. The ESL 132 can comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which exhibits high etch selectivity with respect to the etching of the second ILD 134.

[0089] In the Fig. 22A and Fig. In 22B, gate contacts 142 and source / drain contacts 144 are formed to contact the gate electrodes 124 and the epitaxial source / drain regions 98, respectively. The gate contacts 142 are physically and electrically coupled to the gate electrodes 124, and the source / drain contacts 144 are physically and electrically coupled to the epitaxial source / drain regions 98.

[0090] To form the gate contacts 142 and the source / drain contacts 144, openings for the gate contacts 142 are formed, for example, by the second ILD 134 and the ESL 132, and openings for the source / drain contacts 144 are formed by the second ILD 134, the ESL 132, the first ILD 104, and the CESL 102. The openings can be formed using suitable photolithography and etching techniques. A lining (not shown separately), such as a diffusion barrier, an adhesive layer, or similar, and a conductive material are formed within the openings. The lining can comprise titanium, titanium nitride, tantalum, tantalum nitride, or similar materials. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or similar materials. A planarization process, such as... For example, a CMP can be performed to remove excess material from a surface of the second ILD 134.The remaining liner and the conductive material form the gate contacts 142 and the source / drain contacts 144 in the openings. The gate contacts 142 and the source / drain contacts 144 can be formed in different processes or in the same process. Although they are shown in the same cross-sections, the gate contacts 142 and the source / drain contacts 144 can be formed in different cross-sections, thus preventing short-circuiting of the contacts.

[0091] Optionally, metal-semiconductor alloy regions 146 are formed at the interface between the epitaxial source / drain regions 98 and the source / drain contacts 144. The metal-semiconductor alloy regions 146 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or similar. The metal-semiconductor alloy regions 146 can be formed upstream of the source / drain contact material(s) 144 by depositing a metal in the openings for the source / drain contacts 144 and then performing a thermal annealing process. The metal can be any metal that is able to interact with the semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.).) of the epitaxial source / drain regions 98 to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or similar. After thermal annealing, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the source / drain contact openings 144, e.g., from the surfaces of the metal-semiconductor alloy regions 146. The source / drain contact material(s) 144 can then be formed on the metal-semiconductor alloy regions 146.

[0092] Fig. Figure 24 shows a view of nano-FETs, according to some other embodiments. This embodiment is similar to the one shown for Fig. 18 described, except that the residue 114B is not formed between the first conductive material 114A and the second conductive material 114C. This can be achieved, for example, if all the aluminum of the aluminum-containing precursor used during the aluminum treatment 118 binds to fluorine during the fluorine treatment 120 (see Fig. 16) and / or if the fluorine-containing precursor used during the fluorine treatment 120 does not contain any metal. In embodiments where the fluorine-containing precursor is NF3 and all the aluminum binds to fluorine, the residue 114B, for example, is not formed.

[0093] As mentioned above, some embodiments consider aspects used in planar devices, e.g., in planar FETs or in fin field-effect transistors (FinFETs). Fig. Figures 25A to 26 are views of FinFETs according to some embodiments. Fig. 25A and Fig. 25B shows a similar view to the Fig. 22A and Fig. 22B, and Fig. 26 shows a similar view to Fig. 18, however, with FinFETs instead of Nano-FETs. In the illustrated embodiment, the fins 62 enclose the channel regions 68, and the gate structures extend along the side walls and top surfaces of the fins 62. Fig. Figure 26 shows an embodiment in which the gate structures comprise the residue 114B, but the residue 114B can be used in a similar way as before for Fig. Section 24 described above can be omitted.

[0094] Some implementations provide for the elimination of certain exit work coordination shifts. Fig. 27 and Fig. Figure 28 shows views of devices according to some embodiments. Fig. Figure 27 shows nano-FETs, in a similar view to Fig. 18, and Fig. Figure 28 shows FinFETs, in a similar view to Fig. 26. In these embodiments, the first conductive material 114A is treated, but the second conductive material 114C is omitted. The manufacturing complexity can be reduced by omitting the second conductive material 114C.

[0095] Some embodiments provide for the fluorine treatment of other exit work tuning layers. Fig. 29 and Fig. Figure 30 shows views of devices according to some embodiments. Fig. Figure 29 shows nano-FETs, in a similar view to Fig. 18, and Fig. Figure 30 shows FinFETs, in a similar view to Fig.26. In these embodiments, both the first conductive material 114A and the second conductive material 114C are included, but the second conductive material 114C is treated instead of the first conductive material 114A. Thus, the residue 114B can be formed on the second conductive material 114C instead of on the first conductive material 114A. Treating the second conductive material 114C instead of the first conductive material 114A can enable the formation of devices with other desired threshold voltages.

[0096] Several embodiments can offer advantages. Performing the fluorine treatment 120 forms a gate stack with a fluorine-treated WFM layer. The fluorine treatment can, for example, involve fluorine soaking of the WFM layer, allowing fluorine to diffuse into an underlying gate dielectric (e.g., a high k-value gate dielectric). Performing the aluminum treatment 118 increases the effectiveness of the fluorine treatment 120, resulting in more fluorine being introduced into the WFM layer. Consequently, the flat-band voltage of the resulting transistor can be increased toward a band edge of the metal in the WFM layer, the threshold voltage of the resulting transistor can be lowered, and the device performance can be improved.

[0097] In one embodiment, a method comprises: depositing a dielectric gate layer on a channel region; depositing a first p-type exit work metal on the dielectric gate layer; performing an aluminum treatment on the first p-type exit work metal; after performing the aluminum treatment, performing a fluorine treatment on the first p-type exit work metal; and after performing the fluorine treatment, depositing a second p-type exit work metal on the first p-type exit work metal. In some embodiments of the method, the aluminum treatment introduces aluminum into the first p-type exit work metal, the fluorine treatment introduces fluorine into the first p-type exit work metal, and the fluorine introduced during the fluorine treatment combines with the aluminum introduced during the aluminum treatment.In some embodiments of the process, the aluminum treatment is a first deposition process that exposes a surface of the first p-type exit work metal of an aluminum-containing precursor, and the fluorine treatment is a second deposition process that exposes the surface of the first p-type exit work metal of a fluorine-containing precursor. In some embodiments of the process, the fluorine-containing precursor is WF. x , NF x , TiF x , TaF xor HfF, and x is an integer in the range of 1 to 6. In some embodiments of the process, the aluminum-containing precursor is triethylaluminum or trimethylaluminum. In some embodiments of the process, the first deposition process and the second deposition process are carried out in the same deposition chamber. In some embodiments of the process, the first deposition process and the second deposition process are carried out at the same temperature. In some embodiments of the process, the first deposition process and the second deposition process are carried out at different temperatures. In some embodiments of the process, no aluminum diffuses into the dielectric gate layer during the aluminum treatment. In some embodiments of the process, fluorine diffuses into the dielectric gate layer during the fluorine treatment.

Claims

[1] Procedure comprising the following: Deposition of a dielectric gate layer (112) on a channel region (68); Deposition of a first p-type exit work metal on the dielectric gate layer (112); Performing an aluminium treatment (118) of the first p-type exit work metal; after carrying out the aluminium treatment (118), carrying out a fluorine treatment (120) of the first p-type exit working metal; and After performing the fluorine treatment (120), a second p-type exit work metal is deposited on the first p-type exit work metal. [2] Method according to claim 1, wherein the aluminium treatment introduces aluminium into the first p-type exit work metal (114A), wherein the fluorine treatment introduces fluorine into the first p-type exit work metal (114A), wherein the fluorine introduced during the fluorine treatment (120) binds to the aluminium introduced during the aluminium treatment (118). [3] Method according to claim 1 or 2, wherein the aluminium treatment (118) is a first deposition process which exposes a surface of the first p-type exit work metal to an aluminium-containing precursor, and wherein the fluorine treatment (120) is a second deposition process which exposes the surface of the first p-type exit work metal to a fluorine-containing precursor. [4] The method of claim 3, wherein the fluorine-containing precursor WF x , NF x , TiF x , TaF x or HfF x is, and where x is an integer in a range from 1 to 6. [5] Method according to claim 3 or 4, wherein the aluminium-containing precursor is triethylaluminium or trimethylaluminium. [6] Method according to any one of claims 3 to 5, wherein the first deposition process and the second deposition process are carried out in the same deposition chamber. [7] Method according to any one of claims 3 to 6, wherein the first deposition process and the second deposition process are carried out at the same temperature. [8] Method according to any one of claims 3 to 6, wherein the first deposition process and the second deposition process are carried out at different temperatures. [9] Method according to any one of claims 1 to 8, wherein no aluminium diffuses into the dielectric gate layer (112) during the aluminium treatment (118). [10] Method according to any one of claims 1 to 9, wherein during the fluorine treatment fluorine diffuses into the dielectric gate layer (112). [11] Method according to any of the preceding claims, wherein after the aluminium treatment and the fluorine treatment aluminium is present in a concentration of 0.5 at.% to 25 at.% in the first p-type exit metal and fluorine is present in a concentration of 2.5 at.% to 30 at.% in the first p-type exit metal. [12] A method according to any of the preceding claims for manufacturing a device comprising: the channel area as a first channel area (68); and a second channel area (68); and a gate structure arranged around the first channel area and the second channel area, the gate structure comprising: the dielectric gate layer (112), the first p-type exit work metal (114A) on the dielectric gate layer (112), the second p-type exit metal (114C), wherein the second p-type exit metal (114C) has a lower concentration of fluorine and a lower concentration of aluminum than the first p-type exit metal (114A); and a filler layer (114E) on the second p-type exit working metal. [13] Method according to claim 12, wherein a first region of the gate structure is arranged between the first channel region and the second channel region, and wherein the ratio of fluorine to aluminium in the first region of the gate structure is in a range of 0.005 to 0.

1. [14] Method according to claim 12 or 13, wherein the gate structure further comprises: Metal residues at an interface (114I) between the first p-type exit work metal and the second p-type exit work metal, wherein the metal residues comprise aluminium and tungsten. [15] Method according to claim 14, wherein a first region of the gate structure is arranged between the first channel region and the second channel region, and wherein the ratio of fluorine to tungsten in the first region of the gate structure is in the range of 0.005 to 0.

1. [16] Method according to claim 12, wherein the dielectric gate layer comprises fluorine and hafnium, and wherein a first region of the gate structure is arranged between the first channel region and the second channel region, and wherein the ratio of fluorine to hafnium in the first region of the gate structure is in the range of 0.015 to 0.

2. [17] Method according to any one of claims 1 to 11 for manufacturing a device comprising the following: the canal area (68); a boundary layer on the canal area (68); a dielectric gate layer (112) with a high k-value on the interface layer; a first exit work tuning layer (114A) on the dielectric gate layer (112) with a high k-value, wherein the first exit work tuning layer (114A) comprises the first p-type exit work metal (114A); a second exit work tuning layer (114C) on the first exit work tuning layer, wherein the second exit work tuning layer (114C) comprises the second p-type exit work metal (114C), wherein the second exit work tuning layer (114C) is free of fluorine and aluminium; a detention shift (114D) on the second exit work coordination shift (114C); and a filler layer (114E) on the adhesive layer (114D). [18] Method according to claim 17, wherein the high k-value dielectric gate layer (112) comprises fluorine and hafnium, wherein the high k-value dielectric gate layer (112) is free of aluminum. [19] Method according to claim 17 or 18, wherein the first exit work tuning layer and the second exit work tuning layer (114C) are titanium nitride. [20] Method according to claim 17 or 18, wherein the first exit work tuning layer is titanium nitride and the second exit work tuning layer (114C) is tantalum nitride.

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