TRANSISTOR GATE STRUCTURES AND METHOD FOR THEIR MANUFACTURING

Abstract

Device with: a first nanostructure (66); a second nanostructure (66); a dielectric gate layer (112) enclosing the first nanostructure (66) and the second nanostructure (66); a tungsten-free output work setting layer (114A) enclosing the dielectric gate layer (112) and made of a p-output work material; a tungsten-containing exit work setting layer (114B) enclosing the tungsten-free exit work setting layer (114A); and a filler layer (114E) on the tungsten-containing exit work adjustment layer (114B), wherein the tungsten-containing exit work adjustment layer (114B) comprises the following: a first layer (114B1) of fluorine-free tungsten enclosing the tungsten-free exit work setting layer (114A); and a second layer (114B2) of a second tungsten-containing material enclosing the first layer (114B1) of fluorine-free tungsten, wherein the second tungsten-containing material is different from the material of the first layer (114B1), wherein a region (50I) between the first nanostructure (66) and the second nanostructure (66) is completely filled with respective parts of the first layer (114B1), the tungsten-containing work function setting layer (114B), the tungsten-free work function setting layer (114A), and the dielectric gate layer (112).

Description

background

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, thus enabling the integration of more components in a given area. However, reducing the smallest feature size introduces further problems that need to be addressed.

[0003] US patent 2020 / 0328213 A1 describes methods for manufacturing semiconductor devices with gate structures featuring oxygen-blocking layers. German patent DE 102010795 A1 proposes various exit layer structures for transistor gate electrodes. German patent DE 102019107531 A1 discloses a CMOS device including a low-threshold PMOS metal gate. Brief description of the drawings

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. Rather, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of a nanostructured field-effect transistor (nano-FET) in a three-dimensional representation according to some embodiments. The Fig. Figures 2 to 20B are representations of intermediate steps in the fabrication of nano-FETs according to some embodiments. The Fig. 21A and Fig. Figure 21B shows representations of nano-FETs according to some embodiments. The Fig. 22A and Fig. Figures 22B are representations of nano-FETs according to some embodiments. The Fig. 23A and Fig. Figure 23B shows representations of nano-FETs according to some embodiments. Detailed description

[0005] The present invention provides devices with the features of claim 1 and 2, as well as a method with the features of claim 8. Exemplary embodiments are given in the dependent claims. The following description provides many different embodiments or examples for implementing various features of the invention and other examples. Specific examples of components and arrangements are described below. For example, the fabrication of a first element over or on a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact.Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention. This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0007] According to various embodiments, gate structures for p-devices feature work-function adjusting layers made of a tungsten-containing work-function material (WFM). The tungsten-containing WFM can be, for example, pure tungsten (e.g., fluorine-free tungsten), tungsten nitride, tungsten carbide, tungsten carbonitride, or the like, deposited by one of several deposition methods. Tungsten is suitable for adjusting the work function of p-devices. Advantageously, p-devices with work-function adjusting layers made of a tungsten-containing WFM can have a lower resistance than p-devices with work-function adjusting layers made of a WFM containing other metals (such as tantalum). This can improve device performance.

[0008] Embodiments are described in a specific context, namely in connection with a die featuring nanoFETs. However, various embodiments can also be used for dies that, in combination with the nanoFETs, feature other types of transistors, e.g., fin field-effect transistors (FinFETs), planar transistors, or the like.

[0009] Fig. Figure 1 shows an example of nano-FETs (e.g., nanowire FETs, nanolayer FETs, or the like) according to some embodiments. Fig. Figure 1 is a three-dimensional representation in which some structural elements of the nano-FETs have been omitted for clarity. The nano-FETs can be nanolayer field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAA-FETs), or the like.

[0010] The nanoFETs have nanostructures 66 (e.g., nanolayers, nanowires, or the like) mounted on fins 62 on a substrate 50 (e.g., a semiconductor substrate), with the nanostructures 66 acting as channel regions for the nanoFETs. The nanostructures 66 can be p-nanostructures, n-nanostructures, or a combination thereof. Insulation regions 70, such as STI regions (STI: shallow trench insulation), are arranged between adjacent fins 62 and can extend over and between adjacent insulation regions 70. Although the insulation regions 70 are described or depicted here as being separated from the substrate 50, the term "substrate" used here can refer to either the semiconductor substrate alone or a combination of the semiconductor substrate and the insulation regions.And although a lower part of the fins 62 is depicted as a single, continuous material with the substrate 50, the lower part of the fins 62 and / or the substrate 50 can consist of only one material or of multiple materials. In this context, the fins 62 refer to parts that extend over and between the adjacent insulation areas 70.

[0011] Gate dielectrics 122 are arranged on the upper surfaces of the fins 62 and along the upper, side, and lower surfaces of the nanostructures 66. Gate electrodes 124 are arranged above the gate dielectrics 122. Source / drain epitaxy regions 98 are arranged on the fins 62 on opposite sides of the gate dielectrics 122 and the gate electrodes 124. The source / drain epitaxy regions 98 can be shared by different fins 62. Adjacent source / drain epitaxy regions 98 can be electrically connected, for example, by joining them through epitaxial growth or by connecting them with the same source / drain contact.

[0012] Fig. Figure 1 also shows reference cross-sections that will be used in later figures. A cross-section A - A' runs along a longitudinal axis of a gate electrode 124 and in a direction that is, for example, perpendicular to the direction of current flow between the source / drain epitaxy regions 98 of a nanoFET. A cross-section B - B' runs along a longitudinal axis of a fin 62 and in a direction of, for example, current flow between the source / drain epitaxy regions 98 of the nanoFET. A cross-section C - C' is parallel to cross-section A - A' and passes through the source / drain epitaxy regions 98 of the nanoFETs. For clarity, subsequent figures refer to these reference cross-sections.

[0013] Some embodiments of the invention discussed here are related to nanoFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some examples consider aspects applicable to planar devices, such as planar FETs, or to FinFETs. For example, FinFETs may have fins on a substrate, with the fins acting as channel regions for the FinFETs. Similarly, planar FETs may have a substrate, with portions of the substrate acting as channel regions for the planar FETs.

[0014] The Fig. Figures 2 to 20B are representations of intermediate steps in the fabrication of nano-FETs according to some embodiments. Fig. 2 to 6 are three-dimensional representations that correspond to the three-dimensional representation of Fig. 1 are similar. Fig. 7A, Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A and Fig. 20A shows the reference cross-section A - A' of Fig. 1. The Fig. 7B, Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B and Fig. 20B show the reference cross-section B - B' of Fig. 1.

[0015] In Fig. 2. A substrate 50 is provided for fabricating nanoFETs. The substrate 50 can be a semiconductor substrate, such as a solid semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate comprises a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is fabricated on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of substrate 50 may comprise: silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenophosphide; combinations thereof; or the like.

[0016] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-nanoFETs, and the p-region 50P can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-nanoFETs. The n-region 50N can be physically separated from the p-region 50P (not shown separately), and countless device elements (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P. Although only one n-region 50N and one p-region 50P are shown, countless n-regions 50N and p-regions 50P can be provided.

[0017] Substrate 50 can be easily doped with a p-type or an n-type dopant. Anti-penetration therapy (APT) implantation can be performed on an upper portion of substrate 50 to create an APT region. During APT implantation, dopants can be implanted into substrate 50. The dopants can have a conductivity type opposite to that of source / drain regions subsequently created in each n-type region 50N and p-type region 50P. The APT region can extend below the source / drain regions in the nanoFETs. The APT region can be used to reduce leakage from the source / drain regions to substrate 50. In some embodiments, the doping concentration in the APT region can be approximately 10 18 cm -3 up to about 10 19 cm -3 be.

[0018] A multilayer stack 52 is fabricated on top of the substrate 50. The multilayer stack 52 comprises alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are made of a first semiconductor material, and the second semiconductor layers 56 are made of a second semiconductor material. The semiconductor materials can be selected from those suitable for the substrate 50. In the illustrated embodiment, the multilayer stack 52 comprises three first semiconductor layers 54 and three second semiconductor layers 56. It should be readily understood that the multilayer stack 52 can have an unlimited number of first semiconductor layers 54 and second semiconductor layers 56.

[0019] In the illustrated embodiment, and as will be explained in more detail later, the first semiconductor layers 54 are removed, and the second semiconductor layers 56 are patterned to create channel regions for the nanoFETs in the n-region 50N and the p-region 50P. The first semiconductor layers 54 are sacrificial (or dummy) layers that are removed during a subsequent processing step to expose the bottom and top surfaces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material that has high etch selectivity for the etching of the second semiconductor layers 56, such as silicon germanium. The second semiconductor material of the second semiconductor layers 56 is a material suitable for n- and p-type devices, such as silicon.

[0020] In another embodiment (not shown separately), the first semiconductor layers 54 are structured to create channel regions for nanoFETs in one region (e.g., the p-region 50P), and the second semiconductor layers 56 are structured to create channel regions for nanoFETs in another region (e.g., the n-region 50N). The first semiconductor material for the first semiconductor layers 54 can be a material suitable for p-type devices, such as silicon germanium (e.g., Si x Ge 1-x, where x can be 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material for the second semiconductor layers 56 can be a material suitable for n devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first and second semiconductor materials can have high etch selectivity with respect to mutual etching, such that the first semiconductor layers 54 can be removed without removing the second semiconductor layers 56 in the n region 50N, and the second semiconductor layers 56 can be removed without removing the first semiconductor layers 54 in the p region 50P.

[0021] The layers of the multilayer stack 52 can each be grown using a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), and they can be deposited using a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. The layers can each have a small thickness, such as a thickness of about 5 nm to about 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers 56) are produced such that they are thinner than other layers (e.g., the first semiconductor layers 54).For example, in embodiments where the first semiconductor layers 54 are sacrificial (or dummy) layers and the second semiconductor layers 56 are structured to create channel regions for the nanoFETs in the n-region 50N and the p-region 50P, the first semiconductor layers 54 can have a first thickness, and the second semiconductor layers 56 can have a second thickness, the second thickness being about 30% to about 60% smaller than the first thickness. By fabricating the second semiconductor layers 56 with a smaller thickness, the channel regions can be created with a higher density.

[0022] In Fig. In Step 3, trenches are structured in the substrate 50 and the multilayer stack 52 to fabricate fins 62, first nanostructures 64, and second nanostructures 66. The fins 62 are semiconductor strips structured in the substrate 50. The first nanostructures 64 and the second nanostructures 66 are the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56, respectively. The trenches can be structured using any suitable etching technique, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0023] The fins 62 and the nanostructures 64 and 66 can be structured using any suitable method. For example, the fins 62 and the nanostructures 64 and 66 can be structured using one or more photolithography processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, enabling the creation of structures with, for example, grid spacings smaller than those achievable with a single direct photolithography process. For example, in one embodiment, a sacrificial layer is produced over a substrate and then structured using a photolithography process. Spacers are produced along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can be used as masks for structuring the fins 62 and the nanostructures 64 and 66. In some embodiments, the mask (or other layer) can remain on the nanostructures 64 and 66.

[0024] The fins 62 and the nanostructures 64 and 66 can each have a width of approximately 8 nm to approximately 40 nm. In the illustrated embodiment, the fins 62 and the nanostructures 64 and 66 have essentially the same widths in the n-region 50N and the p-region 50P. In an alternative embodiment, the fins 62 and the nanostructures 64 and 66 are wider or narrower in one region (e.g., the n-region 50N) than the fins 62 and the nanostructures 64 and 66 in another region (e.g., the p-region 50P).

[0025] In Fig. 4. STI regions 70 are generated above the substrate 50 and between adjacent fins 62. The STI regions 70 are arranged around at least a portion of the fins 62 such that at least a portion of the nanostructures 64 and 66 protrudes between adjacent STI regions 70. In the illustrated embodiment, the top surfaces of the STI regions 70 are coplanar with the top surfaces of the fins 62 (within process variations). In some embodiments, the top surfaces of the STI regions 70 are located above or below the top surfaces of the fins 62. The STI regions 70 separate structural elements of adjacent devices.

[0026] The STI areas 70 can be generated using any suitable device. For example, an insulating material can be deposited over the substrate 50 and the nanostructures 64 and 66, and between adjacent fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, or the like, or a combination thereof, which can be deposited by a CVD process, such as high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD), or the like, or a combination thereof. Other insulating materials deposited by a suitable method can also be used. In some embodiments, the insulating material is silicon oxide deposited by an FCVD process. After the insulating material has been deposited, an annealing process can be carried out.In one embodiment, the insulating material is deposited such that excess insulating material covers the nanostructures 64 and 66. Although the STI regions 70 are each shown as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a coating (not shown individually) can first be produced along the surfaces of the substrate 50, the fins 62, and the nanostructures 64 and 66. Subsequently, a filler material (such as that described above) can be deposited over the coating.

[0027] A removal process is then performed on the insulating material to remove excess insulating material covering the nanostructures 64 and 66. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, a combination thereof, or the like, may be used. In embodiments where a mask remains on the nanostructures 64 and 66, the planarization process can expose or remove the mask. After the planarization process, the top surfaces of the insulating material and the mask (if present) or of the nanostructures 64 and 66 (within process variations) are coplanar. Accordingly, the top surfaces of the mask (if present) or of the nanostructures 64 and 66 are not covered by the insulating material. In the illustrated embodiment, the mask does not remain on the nanostructures 64 and 66.The insulating material is then recessed to create the STI regions 70. The recession is such that at least part of the nanostructures 64 and 66 protrudes between adjacent parts of the insulating material. Furthermore, the top surfaces of the STI regions 70 can have a flat surface as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI regions 70 can be created flat, convex, and / or concave by suitable etching. The insulating material can be recessed using a suitable etching process, such as one that is selective for the insulating material (e.g., one that selectively etches the insulating material of the STI regions 70 at a higher rate than the materials of the fins 62 and the nanostructures 64 and 66). For example, oxide removal using dilute hydrofluoric acid (dHF acid) can be performed.

[0028] The process described above is just one example of how the fins 62 and the nanostructures 64 and 66 can be fabricated. In some embodiments, the fins 62 and / or the nanostructures 64 and 66 can be fabricated using a mask and an epitaxial growth process. For example, a dielectric layer can be fabricated over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the epitaxial structures protrude from the dielectric layer and form the fins 62 and / or the nanostructures 64 and 66. The epitaxial structures can have the alternating semiconductor materials already described, such as the first and second semiconductor materials.In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thereby eliminating the need for prior and / or subsequent implantations, but in-situ and implantation doping can also be used together.

[0029] Furthermore, corresponding wells (not shown individually) can be created in the nanostructures 64 and 66, the fins 62, and / or the substrate 50. The wells can have a conductivity type opposite to that of source / drain regions subsequently created in the n-region 50N and the p-region 50P. In some embodiments, a p-well is created in the n-region 50N, and an n-well is created in the p-region 50P. In some embodiments, either a p-well or an n-well is created in the n-region 50N and the p-region 50P.

[0030] In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P can be implemented using a mask (not shown individually), such as a photoresist. For example, a photoresist can be fabricated over the fins 62, the nanostructures 64 and 66, and the STI regions 70 in the n-region 50N. The photoresist is then structured to expose the p-region 50P. The photoresist can be fabricated using a spin-deposition process and can be structured using suitable photolithography techniques. After the photoresist has been structured, implantation with an n-doping material is performed in the p-region 50P, with the photoresist acting as a mask to largely prevent the implantation of n-doping materials into the n-region 50N.The n-doping agents can be phosphorus, arsenic, antimony, or the like, in the range with a concentration of approximately 10. 13 cm -3 up to about 10 14 cm - 3 The photoresist can be implanted. After implantation, it can be removed, for example, using a suitable removal procedure.

[0031] Before or after implantation of the p-region 50P, a mask (not shown individually), such as a photoresist, is fabricated over the fins 62, the nanostructures 64 and 66, and the STI regions 70 within the p-region 50P. The photoresist is then patterned to expose the n-region 50N. The photoresist can be fabricated using a spin-coating technique and can be patterned using suitable photolithography techniques. After the photoresist has been patterned, implantation of a p-doping agent into the n-region 50N can be performed, with the photoresist acting as a mask to largely prevent p-doping agents from being implanted into the p-region 50P. The p-doping agents can be boron, boron fluoride, indium, or the like, introduced into the region at a concentration of approximately 10 13 cm -3 up to about 10 14 cm - 3The photoresist can be implanted. After implantation, it can be removed, for example, using a suitable removal procedure.

[0032] Following the implantation of the n-region 50N and the p-region 50P, a tempering process can be performed to repair implantation damage and activate the implanted p- and / or n-doping materials. In some embodiments where epitaxial structures for the fins 62 and / or the nanostructures 64 and 66 are grown epitaxially, the grown materials can be doped in situ during growth, thus eliminating the need for implantation. However, in-situ and implantation doping can also be used together.

[0033] In Fig. In step 5, a dielectric dummy layer 72 is fabricated on the fins 62 and the nanostructures 64 and 66. The dielectric dummy layer 72 can be made from a dielectric material, such as silicon oxide, silicon nitride, a combination thereof, or the like, which can be deposited or thermally grown using suitable methods. A dummy gate layer 74 is fabricated over the dielectric dummy layer 72, and a mask layer 76 is fabricated over the dummy gate layer 74. The dummy gate layer 74 can be deposited over the dielectric dummy layer 72 and subsequently planarized, for example, using CMP. The mask layer 76 can then be deposited over the dummy gate layer 74.The dummy gate layer 74 can be made of a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), a metal, a metal nitride, a metal silicide, a metal oxide, or the like, which can be deposited by physical vapor deposition (PVD), continuous vapor deposition (CVD), or the like. The dummy gate layer 74 can be made of one or more materials that have high etch selectivity with respect to insulating materials, e.g., the STI regions 70 and / or the dielectric dummy layer 72. The mask layer 76 can be made of a dielectric material, such as silicon nitride, silicon oxide nitride, or the like. In this example, only one dummy gate layer 74 and only one mask layer 76 are made across the n region 50N and the p region 50P.In the illustrated embodiment, the dielectric dummy layer 72 covers the fins 62, the nanostructures 64 and 66, and the STI regions 70, such that the dielectric dummy layer 72 extends over the STI regions 70 and between the dummy gate layer 74 and the STI regions 70. In an alternative embodiment, the dielectric dummy layer 72 covers only the fins 62 and the nanostructures 64 and 66.

[0034] In Fig. In step 6, the mask layer 76 is structured using suitable photolithography and etching techniques to fabricate masks 86. The structure of the masks 86 is then transferred to the dummy gate layer 74 using a suitable etching technique to fabricate dummy gates 84. Optionally, the structure of the masks 86 can also be transferred to the dielectric dummy layer 72 using a suitable etching technique to fabricate dummy gate dielectrics 82. The dummy gates 84 cover portions of the nanostructures 64 and 66 that are exposed during subsequent processing to form channel regions. In particular, the dummy gates 84 extend along the portions of the nanostructures 66 that are structured to generate channel regions 68. The structure of the masks 86 can be used to physically separate adjacent dummy gates 84.The dummy gates 84 can also have longitudinal directions that (within process variations) are essentially perpendicular to the longitudinal directions of the fins 62. The masks 86 can optionally be removed after structuring, for example, using a suitable etching process.

[0035] The Fig. Figures 7A to 20B show various further steps in the manufacture of exemplary devices. Fig. Figures 7A to 13B and 18A to 20B show structural elements in the n-domain 50N and the p-domain 50P. For example, the structures shown can be used for the n-domain 50N and the p-domain 50P. Differences (if any) between the structures of the n-domain 50N and the p-domain 50P are described in the text accompanying each figure. Fig. Figures 14A to 16B show structural elements in the p-region 50P. Fig. 17A and Fig. Figure 17B shows structural elements in the n-range 50N.

[0036] In the Fig. 7A and Fig. In 7B, gate spacers 90 are fabricated over the nanostructures 64 and 66, on exposed sidewalls of the masks 86 (if present), the dummy gates 84, and the dummy gate dielectrics 82. The gate spacers 90 can be fabricated by conformal deposition of one or more dielectric materials and subsequent etching of the dielectric materials. Suitable dielectric materials can be silicon oxide, silicon nitride, silicon oxide nitride, silicon oxide carbonitride, or the like, which can be deposited by a conformal deposition process such as CVD, plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulating materials deposited by a suitable process can also be used. In the illustrated embodiment, the gate spacers 90 each have multiple layers, e.g.,a first spacer layer 90A and a second spacer layer 90B. In some embodiments, the first spacer layer 90A and the second spacer layer 90B are made of silicon dioxide carbonitride (e.g. SiO₂). x N y C 1-x-y, where x and y are 0 to 1) are produced, wherein the first spacer layer 90A is made of silicon dioxide carbonitride with a composition similar to, or different from, that of the second spacer layer 90B. To structure the one or more dielectric materials, a suitable etching process, such as dry etching, wet etching, or the like, or a combination thereof, can be carried out. The etching can be anisotropic. After etching, the one or more dielectric materials have components that remain on the sidewalls of the dummy gates 84 (forming the gate spacers 90). As will be explained in more detail later, after etching, the one or more dielectric materials can also have components that remain on the sidewalls of the fins 62 and / or the nanostructures 64 and 66 (forming the fin spacers 92; see Fig. 9C and Fig. 9D). After etching, the fin spacers 92 and / or the gate spacers 90 can have straight side walls (as shown) or curved side walls (not shown individually).

[0037] Furthermore, implantations can be performed to create lightly doped source / drain regions (LDD regions) (not shown individually). In embodiments with different device types, similar to the implantations for the wells described above, a mask (not shown individually), such as a photoresist, can be fabricated over the n-region 50N while leaving the p-region 50P uncovered, and appropriate dopants (e.g., p-dopers) can be implanted into the fins 62 and / or the nanostructures 64 and 66 exposed in the p-region 50P. Subsequently, the mask can be removed. Then, a mask (not shown individually), such as a photoresist, can be fabricated over the p-region 50P while leaving the n-region 50N uncovered, and appropriate dopants (e.g.,n-Dopants can be implanted into the fins 62 and / or the nanostructures 64 and 66, which are exposed in the n-region 50N. Subsequently, the mask can be removed. The n-dopants can be any of the aforementioned n-dopants, and the p-dopants can be any of the aforementioned p-dopants. During implantation, the channel regions 68 remain covered by the dummy gates 84, so that the channel regions 68 remain essentially free of the dopants implanted to create the LDD regions. The LDD regions can have a dopant concentration of approximately 10. 15 cm -3 up to about 10 19 cm -3 To repair implant damage and activate the implanted dopants, a tempering process can be performed.

[0038] It should be noted that the foregoing invention generally describes a method for manufacturing spacers and LDD regions. Other processes and process sequences can also be used. For example, fewer or more spacers can be used, a different sequence of steps can be used, additional spacers can be manufactured and removed, and / or the like. Furthermore, n- and p-type devices can be manufactured using different structures and steps.

[0039] In the Fig. 8A and Fig. In 8B, source / drain recesses 94 are created in the nanostructures 64 and 66. In the illustrated embodiment, the source / drain recesses 94 extend through the nanostructures 64 and 66 and into the fins 62. The source / drain recesses 94 can also extend into the substrate 50. In various embodiments, the source / drain recesses 94 can extend to a top surface of the substrate 50 without etching the substrate 50; the fins 62 can be etched such that the undersides of the source / drain recesses 94 are located beneath the top surfaces of the STI regions 70; or the like. The source / drain recesses 94 can be created by etching the nanostructures 64 and 66 using anisotropic etching processes, such as RIE, NBE, or the like.The gate spacers 90 and the dummy gates 84 together mask parts of the fins 62 and / or the nanostructures 64 and 66 during the etching processes used to create the source / drain recesses 94. Only one etching process can be used to etch each of the nanostructures 64 and 66, or multiple etching processes can be used. Time-controlled etching processes can be used to stop the etching of the source / drain recesses 94 after a desired depth has been reached.

[0040] Optionally, internal spacers 96 can be fabricated on the sidewalls of the remaining portions of the first nanostructures 64, e.g., the sidewalls exposed by the source / drain recesses 94. As will be explained in more detail later, source / drain regions are subsequently created in the source / drain recesses 94, and the first nanostructures 64 are then replaced by corresponding gate structures. The internal spacers 96 act as insulating elements between the subsequently created source / drain regions and the subsequently fabricated gate structures. Furthermore, the internal spacers 96 can be used to largely prevent damage to the subsequently created source / drain regions from subsequent etching processes, such as those used to later remove the first nanostructures 64.

[0041] As an example of how to fabricate the internal spacers 96, the source / drain recesses 94 can be widened laterally. In particular, portions of the sidewalls of the first nanostructures 64, which have been exposed by the source / drain recesses 94, can be recessed. Although it has been shown that the sidewalls of the first nanostructures 64 are straight, the sidewalls can also be concave or convex. The sidewalls can be recessed using a suitable etching process, such as an etching process that is selective for the material of the first nanostructures 64 (e.g., one that etches the material of the first nanostructures 64 at a higher rate than the material of the second nanostructures 66). The etching can be isotropic.For example, if the second nanostructures 66 are made of silicon and the first nanostructures 64 are made of silicon germanium, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH₄OH), or the like. In another embodiment, the etching process can be a dry etching using a fluorine-based gas, such as hydrogen fluoride gas (HF gas). In some embodiments, the same etching process can be performed continuously to create the source / drain recesses 94 and to recess the sidewalls of the first nanostructures 64. The internal spacers 96 can then be produced by conformal deposition of an insulating material and subsequent etching of the insulating material.The insulating material can be silicon nitride or silicon oxide nitride, but any suitable material can be used, such as dielectric low-k materials with a k-value of less than approximately 3.5. The insulating material can be deposited using a conformal deposition process such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic. The etching process can be, for example, a dry etch such as RIE, NBE, or the like. Although it is shown that the outer sidewalls of the internal spacers 96 are flush with the sidewalls of the gate spacers 90, the outer sidewalls of the internal spacers 96 can also extend beyond the sidewalls of the gate spacers 90 or be recessed from them. In other words, the internal spacers 96 can partially or completely fill, or even overfill, the sidewall recesses.Furthermore, although the side walls of the internal spacers 96 are shown as straight side walls, they can also be concave or convex.

[0042] In the Fig. 9A and Fig. In 9B, source / drain epitaxy regions 98 are generated in the source / drain recesses 94. The source / drain epitaxy regions 98 are generated in the source / drain recesses 94 such that each dummy gate 84 (and corresponding channel regions 68) is arranged between respective adjacent pairs of source / drain epitaxy regions 98. In some embodiments, the gate spacers 90 and the internal spacers 96 are used to separate the source / drain epitaxy regions 98 from the dummy gates 84 or the first nanostructures 64 by a corresponding lateral distance, so that the source / drain epitaxy regions 98 do not bridge subsequently fabricated gate structures of the resulting nanoFETs by short circuit. The material for the source / drain epitaxy areas 98 can be selected such that a mechanical stress is introduced into the respective channel areas 68, thereby improving performance.

[0043] The source / drain epitaxy regions 98 in the n-region 50N can be generated by masking the p-region 50P. The source / drain epitaxy regions 98 in the n-region 50N are then grown epitaxially in the source / drain recesses 94 in the n-region 50N. The source / drain epitaxy regions 98 can be made of a material suitable for n-type devices. For example, the source / drain epitaxy regions 98 in the n-region 50N can be made of materials that introduce tensile stress into the channel regions 68, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The source / drain epitaxy regions 98 in the n-region 50N can also be referred to as "n-source / drain regions". The source / drain epitaxy regions 98 in the n-region 50N can have surfaces that are raised relative to the respective surfaces of the fins 62 and the nanostructures 64 and 66, and they can have chamfers.

[0044] The source / drain epitaxy regions 98 in the p-region 50P can be generated by masking the n-region 50N. The source / drain epitaxy regions 98 in the p-region 50P are then grown epitaxially in the source / drain recesses 94 in the p-region 50P. The source / drain epitaxy regions 98 in the p-region 50P can, for example, contain materials that introduce compressive stress into the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The source / drain epitaxy regions 98 in the p-region 50P can also be referred to as "p-source / drain regions". The source / drain epitaxy regions 98 in the p-region 50P can have surfaces that are raised relative to the respective surfaces of the fins 62 and the nanostructures 64 and 66, and they can have chamfers.

[0045] The source / drain epitaxy regions 98, the nanostructures 64 and 66, and / or the fins 62 can be implanted with dopants to create source / drain regions, similar to the process described above for creating LDD regions, and subsequently an annealing process can be performed. The source / drain regions can have a doping concentration of approximately 10 19 cm -3 up to about 10 21 cm -3 The n- and / or p-doping agents for the source / drain regions can be some of the aforementioned dopants. In some embodiments, the source / drain epitaxy regions 98 can be doped in situ during growth.

[0046] Through the epitaxy processes used to generate the source / drain epitaxy regions 98, the upper surfaces of the source / drain epitaxy regions 98 have chamfers that extend laterally outwards beyond the side walls of the fins 62 and the nanostructures 64 and 66. In some embodiments, these chamfers cause adjacent source / drain epitaxy regions 98 to merge, as shown in Fig. 9C is shown. In some embodiments, after completion of the epitaxy process, adjacent source / drain epitaxy regions 98 remain separated, as shown in Fig. Figure 9D shows the following embodiments. In these embodiments, the spacer etching used to fabricate the gate spacers 90 is modified to also produce fin spacers 92 on the sidewalls of the fins 62 and / or the nanostructures 64 and 66. The fin spacers 92 are fabricated to cover a portion of the sidewalls of the fins 62 and / or the nanostructures 64 and 66 that extend over the STI regions 70, thereby blocking epitaxial growth. In another embodiment, the spacer etching used to fabricate the gate spacers 90 is modified to prevent the formation of fin spacers, allowing the source / drain epitaxy regions 98 to extend to the surface of the STI regions 70.

[0047] The source / drain epitaxy regions 98 can have one or more semiconductor material layers. For example, the source / drain epitaxy regions 98 can each have a coating layer 98A, a main layer 98B, and a cover layer 98C (or more generally, a first semiconductor material layer, a second semiconductor material layer, and a third semiconductor material layer). Any number of semiconductor material layers can be used for the source / drain epitaxy regions 98. The coating layer 98A, the main layer 98B, and the cover layer 98C can each be made of different semiconductor materials and can be doped with different doping concentrations.In some embodiments, the coating layer 98A can have a lower doping concentration than the main layer 98B, and the top layer 98C can have a higher doping concentration than the coating layer 98A and a lower doping concentration than the main layer 98B. In embodiments where the source / drain epitaxy regions 98 have three semiconductor material layers, the coating layer 98A can be grown in the source / drain recesses 94, the main layer 98B can be grown on the coating layer 98A, and the top layer 98C can be grown on the main layer 98B.

[0048] In the Fig. 10A and Fig. In 10B, a first interlayer dielectric (ILD) 104 is deposited over the source / drain epitaxy regions 98, the gate spacers 90, the masks 86 (if present), or the dummy gates 84. The first ILD 104 can be made of a dielectric material that can be deposited by a suitable process such as CVD, PECVD, FCVD, or the like. Suitable dielectric materials include phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials deposited by a suitable process can also be used.

[0049] In some embodiments, a contact etch stop layer (CESL) 102 is produced between the first ILD 104 on the one hand and the source / drain epitaxy regions 98, the gate spacers 90, and the masks 86 (if present) or the dummy gates 84 on the other. The CESL 102 can be made of a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which has high etch selectivity with respect to the etching of the first ILD 104. The CESL 102 can be produced by a suitable method such as CVD, ALD, or the like.

[0050] In the Fig. 11A and Fig. In 11B, a removal process is performed to bring the top surface of the first ILD 104 to the same level as the top surfaces of the masks 86 (if present) or the dummy gates 84. In some embodiments, a planarization process, such as a CMP process, a back-etching process, a combination thereof, or the like, may be used. The planarization process may also remove the masks 86 on the dummy gates 84 as well as portions of the gate spacers 90 along the side walls of the masks 86. After the planarization process, the top surfaces of the gate spacers 90, the first ILD 104, the CESL 102, and the masks 86 (if present) or the dummy gates 84 are coplanar (within process variations). Accordingly, the top surfaces of the masks 86 (if present) or the dummy gates 84 are not covered by the first ILD 104.In the illustrated embodiment, the masks 86 remain in place, and the planarization process brings the top surfaces of the first ILD 104 to the same level as the top surfaces of the masks 86.

[0051] In the Fig. 12A and Fig. In 12B, the masks 86 (if present) and the dummy gates 84 are removed in an etching process, creating recesses 106. Portions of the dummy gate dielectrics 82 within the recesses 106 are also removed. In some embodiments, the dummy gates 84 are removed using an anisotropic dry etching process. For example, the etching process may be a dry etching process using one or more reactive gases that etch the dummy gates 84 at a higher rate than the first ILD 104 or the gate spacers 90. During removal, the dummy gate dielectrics 82 may be used as etch stop layers when the dummy gates 84 are etched. Then, the dummy gate dielectrics 82 are removed. Each recess 106 exposes and / or covers portions of the channel regions 68. Parts of the second nanostructures 66, which function as the channel regions 68, are arranged between adjacent pairs of the source / drain epitaxy regions 98.

[0052] The remaining portions of the first nanostructures 64 are then removed to widen the recesses 106, creating openings 108 in regions 501 between the second nanostructures 66. The remaining portions of the first nanostructures 64 can be removed by a suitable etching process that etches the material of the first nanostructures 64 at a higher rate than the material of the second nanostructures 66. The etching can be isotropic. For example, if the first nanostructures 64 are made of silicon germanium and the second nanostructures 66 are made of silicon, the etching process can be a wet etch using tetramethylammonium hydroxide (TMAH), hydrated ammonia (NH4OH), or the like. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portions of the second nanostructures 66. As described in the Fig. As 14A to 16B are more easily seen (which will be described in more detail later), the remaining parts of the second nanostructures may have 66 rounded corners.

[0053] In the Fig. 13A and Fig. In 13B, a dielectric gate layer 112 is fabricated in the recesses 106. A gate electrode layer 114 is fabricated on the dielectric gate layer 112. The dielectric gate layer 112 and the gate electrode layer 114 are layers for replacement gates, and they each enclose all (e.g., four) sides of the second nanostructures 66.

[0054] The dielectric gate layer 112 is arranged on the sidewalls and / or top surfaces of the fins 62, on the top surfaces, sidewalls, and bottom surfaces of the second nanostructures 66, and on the sidewalls of the gate spacers 90. The dielectric gate layer 112 can also be produced on the top surfaces of the first ILD 104 and the gate spacers 90. The dielectric gate layer 112 can comprise an oxide, such as silicon oxide, or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multilayers thereof, or the like. The dielectric gate layer 112 can comprise a dielectric material with a k-value greater than approximately 7.0, such as a metal oxide or a silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Fig. 13A and Fig. Although 13B is shown as a single-layer dielectric gate layer 112, as will be explained in more detail later, the dielectric gate layer 112 can have any number of interface layers and any number of main layers.

[0055] The gate electrode layer 114 can comprise a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multilayers thereof, or the like. In the Fig. 13A and Fig. Although 13B shows a single-layer gate electrode layer 114, as will be explained in more detail later, the gate electrode layer 114 according to the invention has a plurality of exit work setting layers and a filler material and can also have any number of barrier layers and any number of adhesive layers.

[0056] The fabrication of the dielectric gate layers 112 can be carried out simultaneously in the n-region 50N and the p-region 50P, so that the dielectric gate layers 112 in each region are made of the same materials, and the fabrication of the gate electrode layers 114 can also be carried out simultaneously, so that they are made of the same materials in each region. In some embodiments, the dielectric gate layers 112 in each region can be fabricated using different processes, so that they can be made of different materials and / or have a different number of layers each, and / or the gate electrode layers 114 in each region can be fabricated using different processes, so that they can be made of different materials and / or have a different number of layers each.Various masking steps can be used to mask or leave uncovered corresponding areas when different processes are employed. In the following description, at least parts of the gate electrode layers 114 in the n-region 50N and the gate electrode layers 114 in the p-region 50P are fabricated separately.

[0057] The Fig. Figures 14A to 16B show a process in which dielectric gate layers 112 and gate electrode layers 114 for replacement gates are produced in the recesses 106 in the p-region 50P. Fig. 14A, Fig. 15A and Fig. 16A show structural elements in an area of ​​50A from Fig. 13A. The Fig. 14B, Fig. 15B and Fig. 16B show structural elements in an area 50B of Fig. 13B. The gate electrode layers 114 in the p-region 50P have one or more work function adjustment layers made of a tungsten-containing material. Tungsten is suitable for adjusting the work function of the devices in the p-region 50P. Advantageously, by making the one or more work function layers from a tungsten-containing material, the gate electrode layers 114 in the p-region 50P can have a lower resistance than gate electrode layers with work function adjustment layers made of a material containing other metals (such as tantalum). This can improve device performance. The n-region 50N can be masked while parts of the gate electrode layers 114 are being made in the p-region 50P.

[0058] In the Fig. 14A and Fig. In 14B, a dielectric gate layer 112 is produced in the recesses 106. The dielectric gate layer 112 can also be produced on the top surfaces of the first ILD 104 and the gate spacers 90 (see Fig. 13B). Molecular beam deposition (MBD), ALD, PECVD, and the like can be used as fabrication methods for the dielectric gate layer 112. The dielectric gate layer 112 surrounds all (e.g., four) sides of the second nanostructures 66. The dielectric gate layer 112 fills portions of the regions 50I between the second nanostructures 66 in the p-region 50P (e.g., portions of the openings 108 in the p-region 50P). In the illustrated embodiment, the dielectric gate layer 112 is multilayered and comprises an interface layer 112A (or more generally, a first dielectric gate sublayer) and an overlying high-k dielectric layer 112B (or more generally, a second dielectric gate sublayer). The interface layer 112A can be made of silicon oxide, and the high-k dielectric layer 112B can be made of hafnium oxide.The dielectric gate layer 112 can have any suitable number and combination of sublayers.

[0059] In the Fig. 15A and Fig. According to the invention, a first work function adjustment layer 114A is produced on the dielectric gate layer 112 around the second nanostructures 66 in the p-region 50P. As will be explained in more detail later, the first work function adjustment layer 114A is omitted in some examples. In these cases, a second work function adjustment layer 114B is produced either on the first work function adjustment layer 114A (if present) or on the dielectric gate layer 112 around the second nanostructures 66 in the p-region 50P.

[0060] The first work function adjustment layer 114A (if present) is made from a p-work function material (PWFM) suitable for adjusting the work function of a device to a desired value depending on the application of the device to be manufactured, and it can be deposited by a suitable deposition process. In particular, the first work function adjustment layer 114A is made from a tungsten-free PWFM, such as titanium nitride (TiN), tantalum nitride (TaN), a combination thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. The first work function adjustment layer 114A can also be referred to as a "tungsten-free work function adjustment layer." The first work function adjustment layer 114A can be used or omitted depending on the desired work function of the resulting devices.The first work function adjustment layer 114A can have a thickness of approximately 0.5 nm to approximately 6.0 nm. In the illustrated embodiment, the first work function adjustment layer 114A is a single continuous layer of a tungsten-free PWFM. In other embodiments, the first work function adjustment layer 114A is a multilayer of tungsten-free PWFMs. The first work function adjustment layer 114A fills portions of the regions 50I between the second nanostructures 66 in the p-region 50P (e.g., portions of the openings 108 in the p-region 50P).

[0061] The second work function adjustment layer 114B is fabricated from a p-work function material (PWFM) with low resistivity and can be deposited using a suitable deposition method. Specifically, the second work function adjustment layer 114B is fabricated from a tungsten-containing PWFM, such as pure tungsten (e.g., fluorine-free tungsten), tungsten nitride, tungsten carbide, tungsten carbonitride, or the like, which can be deposited by ALD, CVD, PVD, or the like. The second work function adjustment layer 114B can also be referred to as a "tungsten-containing work function adjustment layer." The second work function adjustment layer 114B can have a thickness of approximately 0.5 nm to approximately 6.0 nm. In the example shown, the second work function adjustment layer 114B is a single, continuous layer of tungsten-containing PWFM.In embodiments according to the invention (which are referred to later in the . Fig. (described in sections 22A to 23B) the second work function adjustment layer 114B is a multilayer of tungsten-containing PWFMs. The material for the second work function adjustment layer 114B can also be used to adjust the work function of a device to a desired value (similar to the first work function adjustment layer 114A), but it has a lower resistivity than the material of the first work function adjustment layer 114A. By using PWFMs with a low resistivity, device performance can be improved.

[0062] In some embodiments, the second output work setting layer 114B is produced from fluorine-free tungsten deposited by an ALD process. Specifically, the second output work setting layer 114B can be produced by placing the substrate 50 in a deposition chamber and cyclically introducing different initial precursors into the deposition chamber. The initial precursors comprise one or more tungsten initial precursors and one or more precursors that react with the one or more tungsten initial precursors to form fluorine-free tungsten. Fluorine-free tungsten is tungsten that is free of fluorine, and it is deposited with a fluorine-free tungsten initial precursor, i.e., a tungsten initial precursor that is free of fluorine.By depositing tungsten with a fluorine-free tungsten precursor, the undesirable formation of corrosive byproducts during deposition is avoided, which can increase the production yield.

[0063] The first pulse of an ALD cycle is initiated by introducing a first precursor into the deposition chamber. The first precursor is a fluorine-free tungsten starting precursor. Suitable fluorine-free tungsten starting precursors include tungsten(V) chloride (WCl5) or similar compounds. The first precursor can be retained in the deposition chamber for a duration of approximately 0.2 s to approximately 5 s. The first precursor is then removed from the deposition chamber, for example, by a suitable evacuation method and / or by introducing an inert gas into the deposition chamber.

[0064] A second pulse of the ALD cycle is then performed by introducing a second precursor into the deposition chamber. The second precursor is a suitable precursor that reacts with the first precursor (e.g., the fluorine-free tungsten starting precursor) to deposit fluorine-free tungsten. If the first precursor is, for example, tungsten(V) chloride, the second precursor can be hydrogen (H₂) or the like. The second precursor can be retained in the deposition chamber for a duration of approximately 0.2 s to approximately 5 s. The second precursor is then removed from the deposition chamber, for example, by a suitable evacuation method and / or by introducing an inert gas into the deposition chamber.

[0065] Each ALD cycle results in the deposition of one atomic layer (occasionally referred to as a monolayer) of fluorine-free tungsten. If the first precursor is, for example, tungsten(V) chloride and the second precursor is hydrogen, they can react multiple times according to equations (1) and (2) below to form gas-phase byproducts (which are removed from the deposition chamber) and fluorine-free tungsten: WClX*+H2→W−H*+HCl W−H*+WCl5→W−WClX*+HCl

[0066] The ALD cycles are repeated until fluorine-free tungsten of the desired thickness (specified above) has been deposited. For example, the ALD cycles can be repeated approximately 1 to 500 times. Furthermore, the ALD process can be carried out at a temperature of approximately 300 °C to approximately 500 °C and at a pressure of approximately 0.67 hPa (0.5 Torr) to approximately 67 hPa (50 Torr), for example, by maintaining the deposition chamber at this temperature and pressure. By performing the ALD process with parameters within these ranges, the fluorine-free tungsten of the desired thickness (specified above) and quality can be deposited. If the ALD process is carried out with parameters outside these ranges, the fluorine-free tungsten cannot be deposited with the desired thickness or quality.

[0067] In some embodiments, the second work function setting layer 114B is produced from tungsten nitride deposited by ALD. The tungsten nitride can be deposited by a similar ALD process to that described above for the deposition of fluorine-free tungsten, except that other precursors may be used. For example, the first precursor may be a tungsten starting precursor (which may or may not be fluorine-free), and the second precursor may be a nitrogen starting precursor that reacts with the first precursor (e.g., the tungsten starting precursor) to deposit tungsten nitride. Tungsten starting precursors suitable for depositing tungsten nitride include bis(tert-butylimino)bis-(dimethylamido)tungsten [( t BuN)2(Me2N)2W] or the like. Nitrogen starting materials suitable for the deposition of tungsten nitride are ammonia (NH3) or the like.

[0068] The ALD cycles are repeated until tungsten nitride of the desired thickness (specified above) is deposited. For example, the ALD cycles can be repeated approximately 1 to 500 times. Furthermore, the ALD process can be carried out at a temperature of approximately 200 °C to approximately 450 °C and at a pressure of approximately 0.13 hPa (0.1 Torr) to approximately 80 hPa (60 Torr), for example, by maintaining the deposition chamber at this temperature and pressure. By performing the ALD process with parameters within these ranges, the tungsten nitride can be deposited with the desired thickness (specified above) and quality. If the ALD process is performed with parameters outside these ranges, the tungsten nitride cannot be deposited with the desired thickness or quality.

[0069] The second output function setting layer 114B fills the remaining portions of regions 50I between the second nanostructures 66 in the p-region 50P (e.g., the remaining portions of the openings 108 in the p-region 50P). Specifically, the second output function setting layer 114B is deposited onto the first output function setting layer 114A (if present) or the dielectric gate layer 112 until it is thick enough to fuse and connect. In embodiments where the first output function setting layer 114A is present, it may be thinner than the second output function setting layer 114B, which may prevent the first output function setting layer 114A from fusing and may promote the fusing of the second output function setting layer 114B. By contacting adjacent parts of the second exit work adjustment layer 114B (e.g.Interfaces 118 can form around the second nanostructures 66 in the p-region 50P. This results in the openings 108 in the p-region 50P being completely filled by respective parts of the dielectric gate layer 112, the first work function setting layer 114A (if present), and the second work function setting layer 114B. Specifically, respective parts of the dielectric gate layer 112 enclose respective second nanostructures 66 in the p-region 50P, respective parts of the first work function setting layer 114A enclose respective parts of the dielectric gate layer 112, and respective parts of the second work function setting layer 114B enclose respective parts of the first work function setting layer 114A, thereby completely filling the areas between the respective second nanostructures 66.If the second work function setting layer 114B is a single continuous layer of tungsten-free PWFM, the tungsten-free PWFM extends continuously between the respective portions of the first work function setting layer 114A (if present) or the respective portions of the dielectric gate layer 112. As explained above, the first work function setting layer 114A is a tungsten-free layer. There are no tungsten-containing layers between the second work function setting layer 114B and the second nanostructures 66 in the p-region 50P.

[0070] In the Fig. 16A and Fig. In step 16B, a filler layer 114E is deposited on the second output work setting layer 114B. Optionally, an adhesive layer 114D is produced between the filler layer 114E and the second output work setting layer 114B. After completion of the fabrication, the gate electrode layers 114 in the p-region 50P comprise the first output work setting layer 114A, the second output work setting layer 114B, the adhesive layer 114D, and the filler layer 114E.

[0071] The adhesive layer 114D comprises a material suitable for promoting adhesion and preventing diffusion. The adhesive layer 114D can be made, for example, from a metal or metal nitride such as titanium nitride, titanium aluminide, titanium aluminum nitride, silicon-doped titanium nitride, tantalum nitride, or the like, which can be deposited by ALD, CVD, PVD, or similar processes.

[0072] The filler layer 114E comprises a suitable material with a low resistivity. The filler layer 114E can be made, for example, from a metal such as tungsten, aluminum, cobalt, ruthenium, a combination thereof, or the like, which can be deposited by ALD, CVD, PVD, or the like. The filler layer 114E fills the remaining portions of the recesses 106.

[0073] The Fig. 17A and Fig. Figure 17B shows dielectric gate layers 112 and gate electrode layers 114 for replacement gates, which are manufactured in the recesses 106 in the n-range 50N. Fig. 17A shows structural elements in an area of ​​50A from Fig. 13A. Fig. 17B shows structural elements in an area 50B of Fig. 13B. In some embodiments, the dielectric gate layers 112 in the n-region 50N and the p-region 50P can be fabricated simultaneously. Furthermore, at least parts of the gate electrode layers 114 in the n-region 50N can be fabricated either before or after the fabrication of the gate electrode layers 114 in the p-region 50P, and at least parts of the gate electrode layers 114 in the n-region 50N can be fabricated while the p-region 50P is masked. This allows the gate electrode layers 114 in the n-region 50N to have different materials than the gate electrode layers 114 in the p-region 50P. For example, the gate electrode layers 114 in the n-region 50N can have a third exit-work setting layer 114C, an adhesive layer 114D, and a filler layer 114E.As will be explained in more detail later, the third output work adjustment layer 114C has a different material composition than the first output work adjustment layer 114A and the second output work adjustment layer 114B. The adhesive layer 114D in the n-region 50N may or may not have the same material composition as the adhesive layer 114D in the p-region 50P (and may be deposited simultaneously with it). The filler layer 114E in the n-region 50N may or may not have the same material composition as the filler layer 114E in the p-region 50P (and may be deposited simultaneously with it).

[0074] The third work function adjustment layer 114C is made from an n-work function material (NWFM) suitable for adjusting the work function of a device to a desired value depending on the application of the device to be manufactured, and it can be deposited by a suitable deposition process. In particular, the third work function adjustment layer 114C is made from a tungsten-free NWFM, such as titanium-aluminum, tantalum-aluminum carbide, tantalum-aluminum, tantalum carbide, combinations thereof, or the like, which can be deposited by ALD, PEALD, PVD, CVD, PECVD, or the like. The material of the third work function adjustment layer 114C is different from the material of the first work function adjustment layer 114A and the material of the second work function adjustment layer 114B.In some embodiments, the first exit work setting layer 114A can be made of titanium nitride, the second exit work setting layer 114B can be made of fluorine-free tungsten or tungsten nitride, and the third exit work setting layer 114C can be made of titanium-aluminium.

[0075] The material of the third output work adjustment layer 114C can also have a low resistivity (similar to the second output work adjustment layer 114B). The material of the third output work adjustment layer 114C can have a lower resistivity than the material of the first output work adjustment layer 114A. By using NWFMs with a low resistivity, device performance can be improved. The material of the third output work adjustment layer 114C can have a higher or lower resistivity than the material of the second output work adjustment layer 114B.In some embodiments, the material of the third output work setting layer 114C has a lower resistivity than the material of the first output work setting layer 114A and a higher resistivity than the material of the second output work setting layer 114B.

[0076] The third output function setting layer 114C fills the remaining portions of the regions 50I between the second nanostructures 66 in the n-region 50N (e.g., the remaining portions of the openings 108 in the n-region 50N). Specifically, the third output function setting layer 114C is deposited onto the dielectric gate layer 112 until it is thick enough to fuse and bond. Contact with adjacent portions of the third output function setting layer 114C (e.g., the portions around the second nanostructures 66 in the n-region 50N) can create interfaces 120. Respective parts of the dielectric gate layer 112 enclose respective second nanostructures 66 in the n-range 50\N, and respective parts of the third work function setting layer 114C enclose respective parts of the dielectric gate layer 112, thereby completely filling regions between the respective second nanostructures 66.

[0077] In the Fig. 18A and Fig. In 18B, a removal process is performed to remove excess portions of the materials of the dielectric gate layer 112 and the gate electrode layer 114 located above the top surfaces of the first ILD 104 and the gate spacers 90, resulting in gate dielectrics 122 and gate electrodes 124. In some embodiments, a planarization process, such as a CMP process, a back-etching process, a combination thereof, or the like, may be used. After planarization, the dielectric gate layer 112 has portions that remain in the recesses 106 (thus forming the gate dielectrics 122). After planarization, the gate electrode layer 114 has portions that remain in the recesses 106 (thus forming the gate electrodes 124). The top surfaces of the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122 (e.g., the interface layers 112A and the dielectric high-k layers 112B; see Fig. 14A to 17B) and the gate electrodes 124 [e.g., the work function setting layers 114A, 114B and 114C, the adhesive layer 114D (if present) and the filler layer 114E; see Fig. [14A to 17B] are coplanar (within process variations). The gate dielectrics 122 and the gate electrodes 124 form substitute gates of the resulting nano-FETs. Each pair of a gate dielectric 122 and a gate electrode 124 can be collectively referred to as a “gate structure”. The gate structures extend along the top, side, and bottom surfaces of a channel region 68 of the second nanostructures 66.

[0078] In the Fig. 19A and Fig. In embodiment 19B, a second ILD 134 is deposited over the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124. In some embodiments, the second ILD 134 is a flowable layer produced by a flowable CVD process. In other embodiments, the second ILD 134 is made from a dielectric material such as PSG, BSG, BPSG, USG, or the like, which can be deposited by a suitable process such as CVD, PECVD, or the like.

[0079] In some embodiments, an etch stop layer (ESL) 132 is produced between the second ILD 134 on the one hand and the gate spacers 90, the CESL 102, the first ILD 104, the gate dielectrics 122, and the gate electrodes 124 on the other. The ESL 132 can comprise a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride, or the like, which has high etch selectivity with respect to the etching of the second ILD 134.

[0080] In the Fig. 20A and Fig. In step 20B, gate contacts 142 and source / drain contacts 144 are manufactured to contact the gate electrodes 124 and the source / drain epitaxy regions 98, respectively. The gate contacts 142 are physically and electrically connected to the gate electrodes 124. The source / drain contacts 144 are physically and electrically connected to the source / drain epitaxy regions 98.

[0081] As an example of how to fabricate the gate contacts 142 and the source / drain contacts 144, openings for the gate contacts 142 are created by the second ILD 134 and the ESL 132, and openings for the source / drain contacts 144 are created by the second ILD 134, the ESL 132, the first ILD 104, and the CESL 102. The openings can be created using suitable photolithography and etching processes. A coating (not shown individually), such as a diffusion barrier layer, an adhesive layer, or the like, and a conductive material are deposited in the openings. The coating can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from a surface of the second ILD 134.The remaining coating and the conductive material form the gate contacts 142 and the source / drain contacts 144 in the openings. The gate contacts 142 and the source / drain contacts 144 can be manufactured in different processes or in the same process. Although it is shown that the gate contacts 142 and the source / drain contacts 144 are manufactured with the same cross-sections, it is understood that they can each be manufactured with different cross-sections.

[0082] Optionally, metal-semiconductor alloy regions 146 can be generated at the interfaces between the source / drain epitaxy regions 98 and the source / drain contacts 144. The metal-semiconductor alloy regions 146 can include: silicide regions made of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.); germanide regions made of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.); silicon germanide regions made of a metal silicide and a metal germanide; or the like. The metal-semiconductor alloy regions 146 can be generated prior to the deposition of the source / drain contact materials 144 by depositing a metal in the orifices for the source / drain contacts 144 and subsequently performing a thermal annealing process. The metal can be a metal that is compatible with semiconductor materials (e.g. silicon, silicon germanium, germanium, etc.).The source / drain epitaxy areas 98 can react with a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, another precious metal, another refractory metal, a rare-earth metal, or an alloy thereof. The metal can be deposited using a deposition process such as ALD, CVD, PVD, or the like. After the thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove residual metal from the openings for the source / drain contacts 144, such as from the surfaces of the metal-semiconductor alloy areas 146. The one or more materials for the source / drain contacts 144 can then be deposited onto the metal-semiconductor alloy areas 146.

[0083] The Fig. 21A and Fig. Figure 21B shows representations of nano-FETs according to some further embodiments. These non-inventional embodiments are described with reference to the Fig. 16A and Fig. The embodiment described in Figure 16B is similar, except that the first output work adjustment layer 114A is omitted. This results in the openings 108 in the p-region 50P being completely filled with respective portions of the dielectric gate layer 112 and the second output work adjustment layer 114B. In the illustrated embodiment, the second output work adjustment layer 114B is a single continuous layer of a tungsten-containing PWFM, such that the tungsten-containing PWFM extends continuously between the respective portions of the dielectric gate layer 112.

[0084] The Fig. Figures 22A to 23B are representations of nano-FETs according to some further embodiments. These embodiments are described with reference to the Fig. 21A and Fig. The embodiment described in 21B is similar, except that the second work function setting layer 114B is a multilayer of tungsten-containing PWFMs. Fig. Figures 22A to 23B show embodiments in which the first output work adjustment layer 114A is omitted, but it is understood that in embodiments according to the invention, the first output work adjustment layer 114A is used. In some embodiments, the second output work adjustment layer 114B is a double layer of tungsten-containing PWFMs, comprising a first output work adjustment sublayer 114B1 and a second output work adjustment sublayer 114B2 on the first output work adjustment sublayer 114B1, as shown in the Fig. 22A and Fig. 22B is shown. In some embodiments, the second output work adjustment layer 114B is a triple layer of tungsten-containing PWFMs, similar to the double layer, but also comprising a third output work adjustment sublayer 114B3 on top of the second output work adjustment sublayer 114B2, as shown in the Fig. 23A and Fig.Figure 23B shows that each of the sublayers is a single, continuous layer of a different tungsten-containing PWFM. The tungsten-containing material of the first work-of-flow-adjusting sublayer 114B1 may be the same as (or different from) the tungsten-containing material of the third work-of-flow-adjusting sublayer 114B3. In some embodiments, the first work-of-flow-adjusting sublayer 114B1 is fluorine-free tungsten, the second work-of-flow-adjusting sublayer 114B2 is tungsten nitride, and the third work-of-flow-adjusting sublayer 114B3 (if present) is fluorine-free tungsten. In some embodiments, the first work function setting sublayer 114B1 is tungsten nitride, the second work function setting sublayer 114B2 is fluorine-free tungsten, and the third work function setting sublayer 114B3 (if present) is tungsten nitride.

[0085] If the second output work adjustment layer 114B is a multilayer of tungsten-containing PWFMs, the sublayers of the tungsten-containing PWFMs are deposited in such a way that a lower sublayer of the second output work adjustment layer 114B (e.g., the first output work adjustment sublayer 114B1) fuses. For example, the lower sublayer of the second output work adjustment layer 114B may have a greater thickness than any of the upper sublayers of the second output work adjustment layer 114B [e.g., the third output work adjustment sublayer 114B3 (if present) and the second output work adjustment sublayer 114B2], which may prevent the upper sublayers from fusing and may promote the fusing of the lower sublayer.

[0086] In some embodiments, the use of tungsten-containing PWFMs is considered. While some of the embodiments described above use, for example, tungsten nitride for a tungsten-containing PWFM, tungsten carbides can also be used. In one embodiment, tungsten carbide and / or tungsten carbonitride can be used instead of (or in addition to) tungsten nitride.

[0087] Different embodiments can offer advantages. For example, tungsten is suitable for adjusting the work function of the devices in the p-range 50p. By fabricating the second work function adjustment layer 114B from a tungsten-containing PWFM, threshold voltages of the resulting devices can be set. Furthermore, tungsten-containing PWFMs can have a low resistivity. By fabricating the second work function adjustment layer 114B from a tungsten-containing PWFM, the gate electrodes 124 can have a lower resistivity in the p-range 50p than gate electrodes with work function adjustment layers fabricated from a PWFM containing other metals (such as tantalum). This can improve device performance.

Claims

[1] Device with: a first nanostructure (66); a second nanostructure (66); a dielectric gate layer (112) enclosing the first nanostructure (66) and the second nanostructure (66); a tungsten-free output work setting layer (114A) enclosing the dielectric gate layer (112) and made of a p-output work material; a tungsten-containing exit work setting layer (114B) enclosing the tungsten-free exit work setting layer (114A); and a filler layer (114E) on the tungsten-containing exit work adjustment layer (114B), wherein the tungsten-containing exit work adjustment layer (114B) comprises the following: a first layer (114B1) of fluorine-free tungsten enclosing the tungsten-free exit work setting layer (114A); and a second layer (114B2) of a second tungsten-containing material enclosing the first layer (114B1) of fluorine-free tungsten, wherein the second tungsten-containing material is different from the material of the first layer (114B1), wherein a region (50I) between the first nanostructure (66) and the second nanostructure (66) is completely filled with respective parts of the first layer (114B1), the tungsten-containing work function setting layer (114B), the tungsten-free work function setting layer (114A), and the dielectric gate layer (112). [2] Device with: a first nanostructure (66); a second nanostructure (66); a dielectric gate layer (112) enclosing the first nanostructure (66) and the second nanostructure (66); a tungsten-free output work setting layer (114A) enclosing the dielectric gate layer (112) and made of a p-output work material; a tungsten-containing work function setting layer (114B) enclosing the tungsten-free work function setting layer (114A), wherein a region (50I) between the first nanostructure (66) and the second nanostructure (66) is completely filled with respective parts of the tungsten-containing work function setting layer (114B), the tungsten-free work function setting layer (114A) and the dielectric gate layer (112); and a filler layer (114E) on the tungsten-containing exit work adjustment layer (114B), wherein the tungsten-containing exit work adjustment layer (114B) comprises the following: a first layer (114B1) of a first tungsten-containing material enclosing the tungsten-free exit work setting layer (114A); and a second layer (114B2) of a second tungsten-containing material enclosing the first layer (114B1) of the first tungsten-containing material, wherein the second tungsten-containing material is different from the first tungsten-containing material and the first layer (114B1) has a greater thickness than any of the overlying layers of the tungsten-containing output work adjustment layer (114B), wherein a first material of the tungsten-containing output work adjustment layer (114B) has a lower resistivity than a second material of the tungsten-free output work adjustment layer (114A). [3] Device according to claim 2, wherein the tungsten-containing exit work setting layer (114B) comprises fluorine-free tungsten. [4] Device according to any one of claims 1 to 3, wherein the tungsten-containing exit work setting layer (114B) comprises tungsten nitride, tungsten carbide or tungsten carbonitride. [5] Device according to one of the preceding claims, wherein the tungsten-containing exit work setting layer (114B) further comprises a third layer (114B3) of a tungsten-containing material enclosing the second layer (114B2), and the tungsten-containing material of the third layer (114B3) is different from the material of the second layer (114B1). [6] Device according to any of the preceding claims, further comprising an n-transistor having the following features: a canal area (68), a second dielectric gate layer (112) on the channel area (68), a second tungsten-free output function setting layer (114C) on the second dielectric gate layer (112), and a second filler layer (114E) on the tungsten-free exit working adjustment layer (114C). [7] Device according to claim 6, wherein the second tungsten-free exit work setting layer (114C) comprises titanium aluminum. [8] Procedure with the following steps: Fabricating a dielectric gate layer (112) with a first part (112A) enclosing a first nanostructure (66) and a second nanostructure; Deposition of a first tungsten-free exit material (114A) from a p-exit material on the first part (112A) of the dielectric gate layer (112); Deposition of a tungsten-containing working fluid (114B) on the first tungsten-free working fluid (114A), wherein the tungsten-containing working fluid (114B) has a lower resistivity than the first tungsten-free working fluid (114A); and Deposition of a filler layer (114E) on the tungsten-containing exit working material (114B), wherein the deposition of the tungsten-containing exit working material (114B) comprises the deposition of a multilayer of tungsten-containing exit working materials (114B1, 114B2), the multilayer comprising: a first layer (114B1) of a first tungsten-containing material on the first tungsten-free emerging working material (114A); and a second layer (114B2) of a second tungsten-containing material on the first layer (114B1) of the first tungsten-containing material, wherein the second tungsten-containing material is different from the first tungsten-containing material, wherein: the first layer (114B1) has a greater thickness than any of the overlying layers of the multilayer of tungsten-containing exit working materials (114B1, 114B2); and / or a region (50I) between the first nanostructure (66) and the second nanostructure (66) is completely filled with respective parts of the first layer (114B1) of the multilayer of tungsten-containing exit working materials (114B1, 114B2), the first tungsten-free exit working material (114A) and the dielectric gate layer (112), and the first layer is made of fluorine-free tungsten. [9] Method according to claim 8, wherein the separation of the tungsten-containing exit working material (114B) comprises: Deposition of fluorine-free tungsten using an ALD process, wherein the ALD process is carried out with tungsten(V) chloride and hydrogen at a temperature of 300 °C to 500 °C and a pressure of 0.67 hPa to 67 hPa. [10] Method according to claim 8, wherein the separation of the tungsten-containing exit working material (114B) comprises: Deposition of tungsten nitride using an ALD process, wherein the ALD process is carried out with bis(tert-butylimino)-bis-(dimethylamido)tungsten and ammonia at a temperature of 200 °C to 450 °C and a pressure of 0.13 hPa to 80 hPa. [11] Method according to claim 8, wherein the dielectric gate layer (112) has a second part (112B) enclosing a third nanostructure (66), the method further comprising: Deposition of a second tungsten-free exit material (114C) on the second part (112B) of the dielectric gate layer (112), wherein the second tungsten-free exit material (114C) is different from the first tungsten-free exit material (114A); and Deposition of the filler layer (114E) onto the second tungsten-free exit working material (114C). [12] The method of claim 11, further comprising: Growth of p-source / drain regions (98) on a substrate (50), wherein the first nanostructure (66) and the second nanostructure (66) are arranged between the p-source / drain regions (98); and Growth of n-source / drain regions (98) on the substrate (50), wherein the third nanostructure (66) is arranged between the n-source / drain regions (98). [13] Method according to claim 11 or 12, wherein the second tungsten-free exit working material (114C) has a lower specific resistance than the first tungsten-free exit working material (114A) and a higher specific resistance than the tungsten-containing exit working material (114B). [14] Method according to claim 11, 12 or 13, wherein the first tungsten-free exit working material (114A) comprises titanium nitride, the tungsten-containing exit working material (114B) comprises fluorine-free tungsten or tungsten nitride and the second tungsten-free exit working material (114C) comprises titanium aluminum. [15] Method according to any one of claims 8 to 14, wherein the first tungsten-free exit working material (114A) is deposited with a first thickness and the tungsten-containing exit working material (114B) is deposited with a second thickness, wherein the second thickness is greater than the first thickness.

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