Semiconductor device and manufacturing process

Abstract

Method for manufacturing a semiconductor device comprising the following steps: Exposing a source / drain region (82) through a first dielectric layer (88) and a second dielectric layer (87), wherein the source / drain region (82) is at least partially arranged in a semiconductor fin (52); after exposing the source / drain region (82) through the first dielectric layer (88) and the second dielectric layer (87), implanting (122) dopants into the second dielectric layer (87), wherein, in the implantation (122) of the dopants into the second dielectric layer (87), the dopants are also implanted along side walls of the first dielectric layer (88); after implanting (122) the dopants, recessing (129) the second dielectric layer (87) beneath the first dielectric layer (88); and Forming a silicide region (133) on the source / drain region (82), wherein the silicide region (133) is arranged in a direction perpendicular to the semiconductor fin (52) after the formation of the silicide region (133) between the source / drain region (82) and the first dielectric layer (88).

Description

BACKGROUND

[0001] Semiconductor devices are used in various electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing insulating or dielectric material layers, conductive material layers, and semiconductor material layers onto a semiconductor substrate. The different material layers are then structured by lithography to create circuit components and elements on the substrate.

[0002] The semiconductor industry is constantly improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the smallest feature size, so that more components can be integrated into a given area.

[0003] US 9985023B1 discloses a FinFET structure having a conductive contact connected to its S / D structure. The conductive contact has a first part and a second part. The second part extends from the first part to the S / D structure. The first part has a first width adjacent to the second part. The second part has a second width that is larger than the first width.

[0004] US 2009 / 0140350A1 discloses an anisotropic wet etching process for a masking material layer. Angled ion implantation of Ge, B, Ga, In, As, P, Sb, or inert atoms is performed, damaging implanted portions of the masking material layer, which can be selectively removed to undamaged portions of the masking material layer.

[0005] VAN OMMEN, AH, et al.: Etch Rate Modification of Si3N4 Layers by Ion Bombardment and Annealing. In: Journal of the Electrochemical Society, Vol. 133, No. 10, 1986, pp. 2140-2147, reveals that the etch rate of LPCVD-Si3N4 layers is increased by ion bombardment.

[0006] The invention is defined in the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figure 1 shows an example of a FinFET (FinFET: fin-like field-effect transistor) in a three-dimensional view according to some embodiments. The Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8A, Fig. 8B, Fig. 9A, Fig. 9B, Fig. 10A, Fig. 10B, Fig. 10C, Fig. 10D, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 14C, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 18C, Fig. 18D, Fig. Figures 19A, 19B, 20A and 20B are sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. DETAILED DESCRIPTION

[0008] The following description provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present invention. For example, the fabrication of a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are fabricated in direct contact, and it may also include embodiments in which additional elements can be fabricated between the first and second elements, such that the first and second elements are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in the various examples in the present invention.This repetition serves the purpose of simplicity and clarity and does not in itself prescribe any relationship between the various designs and / or configurations discussed.

[0009] Furthermore, spatially relative terms, such as "located below," "under," "lower," "located above," "upper," and the like, can be used here to simply describe the relationship of an element or structure to one or more other elements or structures depicted in the figures. These spatially relative terms are intended to encompass orientations of the device in use or operation beyond the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in a different orientation), and the spatially relative descriptors used here can be interpreted accordingly.

[0010] Embodiments are now described with reference to a specific embodiment in which a source / drain contact is generated for a fin-spray field-effect transistor (FinFET). However, the embodiments are not limited to this particular description, since the inventive concepts presented in the present application can be applied in many different embodiments.

[0011] Fig. Figure 1 shows an example of a FinFET in a three-dimensional view according to some embodiments. The FinFET has a fin 52 on a substrate 50 (e.g., a semiconductor substrate). Insulation regions 56 are arranged in the substrate 50, and the fin 52 extends between and over adjacent insulation regions 56. Although the insulation regions 56 are described / represented as regions separated from the substrate 50, the term "substrate" used here can refer to just the semiconductor substrate or to a semiconductor substrate with insulation regions. And although the fin 52 is shown as a single, continuous piece of the substrate 50, the fin 52 and / or the substrate 50 can consist of a single material or a plurality of materials. In this context, the fin 52 refers to the portion that extends between the adjacent insulation regions 56.

[0012] A dielectric gate layer 92 is arranged along the side walls and above a top surface of the fin 52, and a gate electrode 94 is arranged above the dielectric gate layer 92. Source / drain regions 82 are arranged on opposite sides of the fin 52 with respect to the dielectric gate layer 92 and the gate electrode 94. Fig. Figure 1 shows reference cross-sections that will be used in later figures. Cross-section AA runs along a longitudinal axis of the gate electrode 94 and in a direction that is, for example, perpendicular to the direction of current flow between the source / drain regions 82 of the FinFET. Cross-section BB is perpendicular to cross-section AA and runs along a longitudinal axis of the fin 52 and in a direction that is, for example, of current flow between the source / drain regions 82 of the FinFET. Cross-section CC is parallel to cross-section AA and passes through a source / drain region of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0013] Some embodiments presented here are discussed in connection with FinFETs fabricated using a gate-last process. Other embodiments may employ a gate-first process. Furthermore, some embodiments consider aspects used in planar devices such as planar FETs, nanostructured field-effect transistors (e.g., nanolayer, nanowire, gate-all-around, or similar field-effect transistors) (NSFETs), or the like.

[0014] The Fig. Figures 2 to 20B are sectional views of intermediate stages in the fabrication of FinFETs according to some embodiments. Fig. Figures 2 to 7 show the reference cross-section AA, which is in Fig. Figure 1 shows, except for the multiple fins / FinFETs. Fig. 8A, Fig. 9A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A and Fig. 15A are shown along the reference cross-section AA, which is in Fig. 1 is shown, and the Fig. 8B, Fig. 9B, Fig. 10B, Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 14C, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A and Fig. 20B are represented along a similar cross-section BB, which is in Fig. Figure 1 shows, except for the multiple fins / FinFETs. Fig. 10C and Fig. 10D are represented along the reference cross-section CC, which is in Fig. Figure 1 shows, except for the multiple fins / FinFETs.

[0015] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material fabricated on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a compound semiconductor, such as silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, such as silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0016] The substrate 50 has an n-region 50N and a p-region 50P. The n-region 50N can be used to fabricate n-type devices, such as NMOS transistors, e.g., n-FinFETs. The p-region 50P can be used to fabricate p-type devices, such as PMOS transistors, e.g., p-FinFETs. The n-region 50N can be physically separated from the p-region 50P (as shown by divider 51), and a number of device structure elements (e.g., other active devices, doped regions, isolation structures, etc.) can be placed between the n-region 50N and the p-region 50P.

[0017] In Fig. 3. Fins 52 are produced in the substrate 50. The fins 52 are semiconductor strips. In some embodiments, the fins 52 can be produced in the substrate 50 by etching grooves into the substrate 50. The etching can be carried out using any suitable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching process can be anisotropic.

[0018] The fins 52 can be structured using any suitable method. For example, the fins 52 can be structured using one or more photolithographic processes, such as dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithographic and self-aligning processes, enabling the creation of structures with grid spacings smaller than those achievable with a single direct photolithographic process. In one embodiment, for example, a sacrificial layer is produced over a substrate and then structured using a photolithographic process. Spacers are produced along the structured sacrificial layer using a self-aligning process. Subsequently, the sacrificial layer is removed, and the remaining spacers can then be used to structure the fins.In some embodiments, the mask (or other layer) can remain on the fins 52.

[0019] In Fig. In the embodiment shown, an insulating material 54 is produced above the substrate 50 and between adjacent fins 52. The insulating material 54 can be an oxide, such as silicon dioxide, a nitride, the like, or a combination thereof, and can be produced by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., CVD-based material deposition in a remote plasma system followed by post-curing to convert the material into another material, such as an oxide), the like, or a combination thereof. Other insulating materials deposited by a suitable method can also be used. In the embodiment shown, the insulating material 54 is silicon dioxide deposited by an FCVD process. After deposition of the insulating material, a tempering process can be carried out.In one embodiment, the insulating material 54 is deposited such that excess insulating material 54 covers the fins 52. Although the insulating material 54 is shown as a single layer, several layers can be used in some embodiments. For example, in some embodiments, a coating (not shown) can first be produced along a surface of the substrate 50 and the fins 52. Then, a filler material, such as one of those discussed above, can be deposited over the coating.

[0020] In Fig. In embodiment 5, a removal process is applied to the insulating material 54 to remove excess insulating material 54 above the fins 52. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process exposes the fins 52 so that the top surfaces of the fins 52 and the insulating material 54 are at the same level after the planarization process is completed. In embodiments where a mask remains on the fins 52, the planarization process may expose or remove the mask so that the top surfaces of the mask or the fins 52 and the insulating material 54 are at the same level after the planarization process is completed.

[0021] In Fig. 6. The insulating material 54 is recessed to create shallow trench insulation areas (STI areas) 56 (STI: Shallow Trench Insulation). The insulating material 54 is recessed such that the upper portions of the fins 52 protrude between adjacent STI areas 56 in the n-area 50N and in the p-area 50P. Furthermore, the top surfaces of the STI areas 56 can have a flat surface, as shown, a convex surface, a concave surface (such as dishing), or a combination thereof. The top surfaces of the STI areas 56 can be produced flat, convex, and / or concave by suitable etching. The STI areas 56 can be recessed using a suitable etching process, such as one that is selective for the insulating material 54 (e.g., etching the insulating material 54 at a higher rate than the fin material 52). For example, oxide removal can be carried out using dilute hydrofluoric acid (dHF).

[0022] Referring to the Fig. The process described in sections 2 to 6 is only one example of how the fins 52 can be produced. In some embodiments, the fins can be produced using an epitaxial growth process. For example, a dielectric layer can be produced over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be recessed such that the homoepitaxial structures protrude from the dielectric layer and form fins. In still other embodiments, heteroepitaxial structures can be used for the fins 52. For example, the fins 52 can be formed in Fig. 5, and a material different from that of the fins 52 can be epitaxially grown over the recessed fins 52. In these embodiments, the fins 52 can comprise the recessed material as well as the epitaxially grown material arranged over the recessed material. In yet another embodiment, a dielectric layer can be produced over a top surface of the substrate 50, and trenches can be etched through the dielectric layer. Heteroepitaxial structures can then be epitaxially grown in the trenches using a material different from that of the substrate 50, and the dielectric layer can be recessed such that the heteroepitaxial structures protrude from the dielectric layer and form the fins 52.In some embodiments where homoepitaxial or heteroepitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thus avoiding prior and subsequent implantations, although in-situ and implantation doping can also be used together.

[0023] Furthermore, it can be advantageous to epitaxially grow a material in the n-region 50N (e.g., an NMOS region) that differs from the material in the p-region 50P (e.g., a PMOS region). In various embodiments, upper parts of the fins 52 can be made of silicon germanium (Si₂). x Ge 1-x, where x can be in the range of 0 to 1), silicon carbide, pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. Materials available for fabricating the III-V compound semiconductor include, but are not limited to, indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, aluminum antimonide, aluminum phosphide, gallium phosphide, and the like.

[0024] Furthermore, suitable troughs (not shown) can be produced in the fins 52 and / or the substrate 50. In some embodiments, a p-trough can be produced in the n-region 50N, and an n-trough can be produced in the p-region 50P. In some embodiments, a p-trough or an n-trough is produced in both the n-region 50N and the p-region 50P.

[0025] In embodiments with different well types, the various implantation steps for the n-region 50N and the p-region 50P can be performed using a photoresist and / or other masks (not shown). For example, a photoresist can be fabricated over the fins 52 and the STI regions 56 in the n-region 50N. The photoresist is patterned to expose the p-region 50P of the substrate 50. The photoresist can be fabricated by a spin-coating process and patterned using suitable photolithographic techniques. After patterning the photoresist, n-dopers are implanted in the p-region 50P, and the photoresist can act as a mask to largely prevent further n-dopers from being implanted into the n-region 50N. The n-dopers can be phosphorus, arsenic, antimony, or the like, present in the region at concentrations equal to or less than 10⁻⁵.18 cm -3 , as between about 10 16 cm -3 and about 10 18 cm -3 The photoresist is implanted. After implantation, it is removed, for example, using a suitable removal process.

[0026] Following implantation in the p-region 50P, a photoresist is fabricated over the fins 52 and the STI regions 56 in the p-region 50P. The photoresist is patterned to expose the n-region 50N of the substrate 50. The photoresist can be fabricated by spin coating and patterned using suitable photolithographic techniques. After patterning the photoresist, p-dopers can be implanted in the n-region 50N, and the photoresist can act as a mask to largely prevent p-dopers from being implanted into the p-region 50P. The p-dopers can be boron, boron fluoride, indium, or the like, present in the region at a concentration of 10 or less. 18 cm -3 , as between about 10 16 cm -3 and about 10 18 cm -3The photoresist can be implanted. After implantation, it can be removed, for example with a suitable removal process.

[0027] Following the implantation of the n-region 50N and the p-region 50P, a tempering process can be performed to repair implantation damage and activate the implanted p- and / or n-doping materials. In some embodiments, the grown materials of epitaxial fins can be doped in situ during growth, thus avoiding implantation, although in-situ and implantation doping can also be used together.

[0028] In Fig. In step 7, a dielectric dummy layer 60 is produced on the fins 52. The dielectric dummy layer 60 can, for example, comprise silicon oxide, silicon nitride, a combination thereof, or the like, and can be deposited or thermally grown using suitable methods. A dummy gate layer 62 is produced over the dielectric dummy layer 60, and a mask layer 64 is produced over the dummy gate layer 62. The dummy gate layer 62 can be deposited over the dielectric dummy layer 60 and then planarized, for example, using CMP. The mask layer 64 can be deposited over the dummy gate layer 62.The dummy gate layer 62 can be made of a conductive or non-conductive material selected from the following group: amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and metals. The dummy gate layer 62 can be deposited by physical vapor deposition (PVD), chemical vapor deposition (CVD), sputtering, or other methods for depositing the selected material. The dummy gate layer 62 can be made of other materials that exhibit high etch selectivity for etching the insulating regions, such as the STI regions 56 and / or the dielectric dummy layer 60. The mask layer 64 can comprise one or more layers of, for example, silicon nitride, silicon oxide nitride, or the like.In this example, a single dummy gate layer 62 and a single mask layer 64 are produced across the n-region 50N and the p-region 50P. It should be noted that the dielectric dummy layer 60 is shown, for illustrative purposes only, to cover only the fins 52. In some embodiments, the dielectric dummy layer 60 can be deposited to cover the STI regions 56 by extending over the STI regions and between the dummy gate layer 62 and the STI regions 56.

[0029] The Fig. Figures 8A to 20B show various additional steps in the manufacture of devices according to embodiments. Fig. 8A to 20B show structural elements in both regions, the n-region 50N and the p-region 50P. For example, the ones in the Fig. The structures shown in Figures 8A to 20B can be applied to both the n-region 50N and the p-region 50P. Any differences (if any) between the structures of the n-region 50N and the p-region 50P are described in the accompanying text for each figure.

[0030] In the Fig. 8A and Fig. 8B can be used for mask layer 64 (see Fig. 7) can be structured using suitable photolithography and etching techniques to produce masks 74. The structure of the masks 74 can then be transferred to the dummy gate layer 62. In some embodiments (not shown), the structure of the masks 74 can also be transferred to the dielectric dummy layer 60 using a suitable etching method to produce dummy gates 72. The dummy gates 72 cover respective channel regions 58 of the fins 52. The structure of the masks 74 can be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The dummy gates 72 can also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of respective epitaxial fins 52.

[0031] In the Fig. 8A and Fig. Gate sealing spacers 80 can also be manufactured on exposed surfaces of the dummy gates 72, the masks 74, and / or the fins 52. The gate sealing spacers 80 can be manufactured by thermal oxidation or by deposition followed by anisotropic etching. The gate sealing spacers 80 can be made of silicon oxide, silicon nitride, silicon oxide nitride, or the like.

[0032] After the manufacture of the gate sealing spacers 80, implantations for lightly doped source / drain regions (LDD regions) (not explicitly shown) can be performed. In embodiments with different types of devices, similar to the previously described Fig. Following the implantation procedure discussed in section 6, a mask, such as a photoresist, can be fabricated over the n-region 50N while the p-region 50P is exposed, and dopants of a suitable type (e.g., p-dopers) can be implanted into the exposed fins 52 in the p-region 50P. The mask can then be removed. The n-dopers can be any of the previously discussed n-dopers, and the p-dopers can be any of the previously discussed p-dopers. The lightly doped source / drain regions can have a dopant concentration of approximately 10 15 cm -3 up to about 10 19 cm-3 exhibiting [unclear]. A tempering process can be performed to repair implant damage and activate the implanted dopants.

[0033] In the Fig. 9A and Fig. 9B Gate spacers 86 are manufactured on the gate gasket spacers 80 along the side walls of the dummy gates 72 and the masks 74. The gate spacers 86 can be manufactured by conformal deposition of an insulating material and subsequent anisotropic etching of the insulating material. The insulating material of the gate spacers 86 can be silicon oxide, silicon nitride, silicon oxide nitride, silicon carbonitride, a combination thereof, or the like.

[0034] It should be noted that the foregoing invention generally describes a process for manufacturing spacers and LDD areas. Other processes and sequences can be used. For example, fewer or additional spacers can be used, a different sequence of steps can be employed (e.g., the etching of the gate gasket spacers 80 before manufacturing the gate spacers 86 can be omitted, resulting in "L-shaped" gate gasket spacers, spacers can be manufactured and removed, and / or the like). Furthermore, the n- and p-devices can be manufactured using different structures and steps. For example, LDD areas for n-devices can be manufactured before manufacturing the gate gasket spacers 80, while the LDD areas for p-devices are manufactured after the gate gasket spacers 80 have been manufactured.

[0035] In the Fig. 10A and Fig. In 10B, epitaxial source / drain regions 82 are fabricated in the fins 52. The epitaxial source / drain regions 82 are fabricated in the fins 52 such that each dummy gate 72 is positioned between adjacent pairs of epitaxial source / drain regions 82. In some embodiments, the epitaxial source / drain regions 82 can extend into and even penetrate the fins 52. In some embodiments, gate spacers 86 are used to separate the epitaxial source / drain regions 82 from the dummy gates 72 by a suitable lateral distance, so that the epitaxial source / drain regions 82 do not short-circuit subsequently fabricated gates of the resulting FinFETs. A material of the epitaxial source / drain regions 82 can be selected to exert tension in the respective channel regions 58, thereby improving performance.

[0036] The epitaxial source / drain regions 82 in the n-region 50N can be fabricated by masking the p-region 50P and etching the source / drain regions of the fins 52 in the n-region 50N to form recesses in the fins 52. The epitaxial source / drain regions 82 in the n-region 50N are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can consist of any suitable material appropriate for n-FinFETs. For example, if the fin 52 is made of silicon, the epitaxial source / drain regions 82 in the n-region 50N can consist of materials that exert a tensile stress in the channel region 58, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 82 in the n-region 50N may have surfaces that are raised relative to the respective surfaces of the fins 52 and may have facets.

[0037] The epitaxial source / drain regions 82 in the p-region 50P can be fabricated by masking the n-region 50N and etching the source / drain regions of the fins 52 in the p-region 50P to form recesses in the fins 52. The epitaxial source / drain regions 82 in the p-region 50P are then epitaxially grown in the recesses. The epitaxial source / drain regions 82 can consist of any suitable material appropriate for p-FinFETs. For example, if the fin 52 is silicon, the epitaxial source / drain regions 82 in the p-region 50P can consist of materials that exert a compressive stress into the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium, germanium-tin, or the like. The epitaxial source / drain regions 82 in the p-region 50P may have surfaces that are raised relative to the respective surfaces of the fins 52 and may have facets.

[0038] Dopants can be implanted into the epitaxial source / drain regions 82 and / or the fins 52 to create source / drain regions, similar to the process discussed above for producing the lightly doped source / drain regions, and subsequently a annealing process can be performed. The source / drain regions can have a doping concentration of approximately 10 19 cm -3 and about 10 21 cm -3 exhibit. The n- and / or p-doping agents for source / drain regions can be any of the dopants discussed above. In some embodiments, the epitaxial source / drain regions 82 can be doped in situ during growth.

[0039] As a result of the epitaxial process used to create the epitaxial source / drain regions 82 in the n-region 50N and the p-region 50P, the top surfaces of the epitaxial source / drain regions exhibit facets that extend laterally outward beyond the side walls of the fins 52. In some embodiments, these facets cause adjacent source / drain regions 82 of the same FinFET to merge, as shown in Fig. 10C is shown. In other embodiments, adjacent source / drain regions 82 remain separated after the epitaxy process is complete, as shown in Fig. 10D is shown. In the Fig. 10C and Fig. In the embodiments shown in Figure 10D, gate spacers 86 are produced that cover part of the sidewalls of the fins 52 extending over the STI areas 56, thus blocking epitaxial growth. In some other embodiments, the spacer etching used to produce the gate spacers 86 can be adjusted to remove the spacer material, allowing the epitaxially grown area to extend onto the surface of the STI area 56.

[0040] In the Fig. 11A and Fig. In 11B, a first interlayer dielectric (ILD) 88 (ILD: interlayer dielectric) is deposited over the structure that is in the Fig. 10A and Fig. Figure 10B shows that the first ILD 88 can be fabricated from a dielectric material and can be deposited by any suitable process, such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable CVD (FCVD). Dielectric materials can be silicon dioxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials fabricated by a suitable process can be used. In some embodiments, a contact etch stop layer (CESL) 87 is fabricated between the first ILD 88 and the epitaxial source / drain regions 82, the masks 74, and the gate spacers 86.The CESL 87 may contain a dielectric material, such as silicon nitride, silicon oxide, silicon oxide nitride or the like, which has a lower etch rate than the material of the first ILD 88 located above it.

[0041] In the Fig. 12A and Fig. In 12B, a planarization process, such as a CMP, can be performed to bring the top surface of the first ILD 88 to the same level as the top surfaces of the dummy gates 72 or the masks 74. The planarization process can also remove the masks 74 on the dummy gates 72 and portions of the gate gasket spacers 80 and the gate spacers 86 along the side walls of the masks 74. After the planarization process, the top surfaces of the dummy gates 72, the gate gasket spacers 80, the gate spacers 86, and the first ILD 88 are at the same level. Accordingly, the top surfaces of the dummy gates 72 are exposed by the first ILD 88. In some embodiments, the masks 74 can remain, and in this case, the top surface of the first ILD 88 and the top surfaces of the masks 74 are brought to the same level by the planarization process.

[0042] In the Fig. 13A and Fig. In 13B, the dummy gates 72, and if present, the masks 74, are removed in one or more etching steps, forming recesses 90. Portions of the dielectric dummy layer 60 in the recesses 90 may also be removed. In some embodiments, only the dummy gates 72 are removed, and the dielectric dummy layer 60 remains and is exposed through the recesses 90. In some embodiments, the dielectric dummy layer 60 is removed from the recesses 90 in a first region of a die (e.g., in a core logic region) and remains in a second region of the die (e.g., in an input / output region). In some embodiments, the dummy gates 72 are removed using an anisotropic dry etching process.For example, the etching process can include a dry etching process using one or more reactive gases that selectively etches the dummy gates 72, leaving the first ILD 88 or the gate spacers 86 little or not etched at all. Each recess 90 exposes a channel region 58 of a respective fin 52 and / or is located above a channel region 58 of a respective fin 52. Each channel region 58 is positioned between adjacent pairs of the epitaxial source / drain regions 82. During removal, when the dummy gates 72 are etched, the dielectric dummy layer 60 can be used as an etch stop layer. After removal of the dummy gates 72, the dielectric dummy layer 60 can then be optionally removed.

[0043] In the Fig. 14A and Fig. 14B dielectric gate layers 92 and gate electrodes 94 for replacement gates are manufactured. Fig. Figure 14C shows a detailed view of area 89. Fig. 14B. Dielectric gate layers 92 are deposited in one or more layers in the recesses 90, for example, on the tops and side walls of the fins 52 and on side walls of the gate gasket spacers 80 / gate spacers 86. The dielectric gate layers 92 can also be produced on the top surface of the first ILD 88. In some embodiments, the dielectric gate layers 92 comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. In some embodiments, for example, the dielectric gate layers 92 comprise an interface layer of silicon oxide produced by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof.The dielectric gate layers 92 can have a dielectric layer with a k-value greater than approximately 7.0. The methods for producing the dielectric gate layers 92 can include molecular beam deposition (MBD), atomic layer deposition (ALD), PECVD, and the like. In embodiments where parts of the dielectric dummy layer 60 remain in the recesses 90, the dielectric gate layers 92 have a material of the dielectric dummy layer 60 (e.g., SiO2).

[0044] The gate electrodes 94 are deposited over the dielectric gate layers 92 and fill the remaining portions of the recesses 90. The gate electrodes 94 can be made of a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. Although, for example, a single-layer gate electrode 94 in Fig. As shown in Figure 14B, the gate electrode 94 can have any number of cover layers 94A, any number of exit work setting layers 94B and a filler material 94C, as shown in Figure 14B. Fig. As shown in Figure 14C, after filling the recesses 90, a planarization process, such as CMP, can be performed to remove the excess portions of the dielectric gate layers 92 and the material of the gate electrodes 94, the excess portions of which are located above the top of the first ILD 88. The remaining portions of the material of the gate electrodes 94 and the dielectric gate layers 92 consequently form substitute gates of the resulting FinFETs. The gate electrodes 94 and the dielectric gate layers 92 can be collectively referred to as the “gate stack.” The gate and the gate stack can extend along sidewalls of a channel region 58 of the fins 52.

[0045] The dielectric gate layers 92 in the n-region 50N and the p-region 50P can be fabricated simultaneously, so that the dielectric gate layers 92 in each region are made of the same materials, and the gate electrodes 94 can also be fabricated simultaneously, so that the gate electrodes 94 in each region are made of the same materials. In some embodiments, the dielectric gate layers 92 in each region can be fabricated using different processes, so that the dielectric gate layers 92 can be made of different materials, and / or the gate electrodes 94 in each region can be fabricated using different processes, so that the gate electrodes 94 can be made of different materials. Different masking steps can be used to mask and expose corresponding regions when different processes are used.

[0046] In the Fig. 15A and Fig. In embodiment 15B, a gate mask 96 is fabricated over the gate stack (with a dielectric gate layer 92 and a corresponding gate electrode 94), and the gate mask can also be arranged between opposing portions of the gate spacers 86. In some embodiments, fabricating the gate mask 96 includes recessing the gate stack, such that a recess is formed directly over the gate stack and between opposing portions of the gate spacers 86. A gate mask 96 with one or more layers of dielectric material, such as silicon nitride, silicon oxide nitride, or the like, is filled into the recess, followed by a planarization process to remove excess portions of the dielectric material extending over the first ILD 88.

[0047] In the Fig. 16A and Fig. 16B and with a more detailed examination of the structure in Fig. 15A are, according to some embodiments, source / drain contacts 112 (in finished form in the following) Fig. 19A-19B shown) produced by the first ILD 88 and the CESL 87, whereby Fig. 16B a close-up view of the area within the dotted line 111 in Fig. Figure 16A shows that in one embodiment, the process of fabricating the source / drain contacts 112 can begin by first fabricating source / drain contact openings 114 to expose the source / drain regions 82. In another embodiment, the fabrication of the source / drain contact openings 114 can begin by placing a hard mask 116 over the first ILD 88. The hard mask 116 can comprise a hard mask material such as silicon nitride, silicon oxide, combinations thereof, or the like, and can be deposited to a thickness between approximately 20 nm and approximately 100 nm. However, any suitable material and thickness can be used.

[0048] Once the hard mask 116 has been deposited, it can be patterned. In one embodiment, the hard mask 116 can be patterned using a photolithographic masking and etching process, wherein a photosensitive material is applied, exposed, and developed, and the developed photosensitive material is then used as a mask in an anisotropic etching process to pattern the hard mask 116 in the desired structure for the source / drain contact openings 114. The photosensitive material can then be removed, for example, by a peeling and / or stripping process.

[0049] After the hard mask 116 has been structured, it can be used to fabricate the source / drain contact openings 114 through the first ILD 88. In one embodiment, the source / drain contact openings 114 can be fabricated using an anisotropic etching process, such as a reactive ion etching process with etchants selective for the material of the first ILD 88, to etch away the material of the first ILD 88 until the etching process is stopped by the CESL 87. However, any suitable etching process can be used.

[0050] Once the CESL 87 has been exposed, another etching process can be performed to penetrate the CESL 87 and expose the underlying source / drain regions 82. In one embodiment, the penetration can be achieved using another anisotropic etching process, such as a reactive ion etching process with etchants selective for the CESL 87 material, to etch away the CESL 87 material until the source / drain region 82 is exposed. However, any suitable etching process can be used.

[0051] At the end of the breakthrough process for extending the source / drain contact openings 114 through the CESL 87, the source / drain contact openings 114 can exhibit several widths due to the different etching processes and their varying selectivities. For example, as the source / drain contact openings 114 extend through the first ILD 88, they have a first width W1 between approximately 20 nm and approximately 45 nm. Furthermore, as the CESL 87 extends the source / drain contact openings 114 through the CESL 87, they can have a second width W2, which is smaller than the first width W1, such that the second width W2 lies between approximately 16 nm and approximately 40 nm. However, any suitable width can be used.

[0052] Provided that the source / drain contact openings 114, when extending through the CESL 87, have a different (e.g., smaller) width than when extending through the first ILD 88, the CESL 87 can have extensions 118 that extend beyond the sidewalls of the first ILD 88, also referred to as "protruding and remaining dielectric layers on the lower sidewall" or "lower dielectric base layers." In some embodiments, the extensions 118 of the CESL 87 can have a third width W3 between about 4 nm and about 8 nm. However, any suitable width can be used.

[0053] The Fig. Figures 17A-17C show a first implantation process 122 with which the modification of the etch selectivity of the CESL 87 can be supported, so that the extensions 118 can be etched with a subsequent etching process (e.g. a subsequent cleaning process 129, which is described below with reference to the Fig. (described in sections 18A-18B) can be removed. In some embodiments, optional pre-cleaning can be performed by applying and subsequently removing a mixture of NF3 / NH3 (NSPE) and HF / NH3 (HPP). However, any suitable cleaning process can be used.

[0054] In one embodiment, the first implantation process 122 is performed to implant first dopants into the extensions 118 of the CESL 87. In one embodiment, the first dopants can be dopants that damage the material of the extensions 118 of the CESL 87 without significantly modifying the other properties of the material. Therefore, in one embodiment, the first dopants can be germanium, boron (B), arsenic (As), phosphorus (P), combinations thereof, or the like. However, any suitable dopant or combination thereof can be used.

[0055] In one embodiment, the first dopants can be introduced using a process such as a first implantation process (shown in Fig. Ions of the desired first dopants (17B, indicated by arrows 122) are implanted into the extensions 118 of CESL 87, thereby accelerating ions of the desired first dopants and directing them to the extensions 118 of CESL 87. The ion implantation process can utilize an accelerator system to accelerate ions of the desired first dopant with a first dose concentration. While the precise dose concentration used will depend at least partially on the extensions 118 of CESL 87 and the first dopants used, the accelerator system in one embodiment can therefore deliver an energy between approximately 500 eV and approximately 10 keV (e.g., 5.2 keV or 5.0 keV) along with a dose concentration of approximately 1 × 10 13 atoms / cm² 2 up to about 2 × 10 14 atoms / cm² 2 , such as 8.5 × 10 13 atoms / cm² 2 use.

[0056] Furthermore, the first dopants can be implanted perpendicular to the source / drain regions 201 or, alternatively, at an angle between approximately 0° and approximately 60° from the perpendicular to the extensions 118 of CESL 87, and at a temperature between approximately 100 °C and approximately 500 °C. In one embodiment, the first dopants can also be implanted at concentrations of up to approximately 1 × 10¹³ atoms / cm³. 2 and about 5E14 atoms / cm² 2 They can be implanted into the extensions 118 of the CESL 87. However, all suitable parameters can be used.

[0057] The first implantation process 122 can be performed with any suitable number of implantations. For example, in one embodiment, two separate implantations can be performed to implant the first dopants into each of the extensions 118, or more than two implantations can be used. In other embodiments, a single implantation can be performed, in which, for example, the substrate 50 is rotated during the single implantation. Any suitable number of implantations can be used.

[0058] The damage to the extensions 118 of CESL 87 caused by implanting the first dopants into these extensions helps to increase the etch rate in subsequent etching processes. In particular, the damage caused by the first implantation process 122 allows subsequent etching solutions to penetrate into the CESL 87 instead of remaining only on one surface. Therefore, the etching solutions remove material from the CESL 87 at a higher rate over a larger contact area than if the first implantation process 122 were omitted.

[0059] Furthermore, since in some embodiments the first implantation process 122 is performed at an angle, the first dopants actually encounter the extensions 118 of the CESL 87 and then move to a location that is actually beneath the first ILD 88. Therefore, the first implantation process 122 creates a first implantation area 124 in the extensions 118 of the CESL 87, which has a fourth width W4 between approximately 4 nm and approximately 8 nm, while the first implantation area 124 extends over a first distance D1 between approximately 1 nm and approximately 3 nm beneath the first ILD 88. However, any suitable width and distance can be used.

[0060] Furthermore, to simplify the implantation of the first dopants into the extensions 118 of the CESL 87, the first implantation process 122 additionally implants the first dopants into the sidewalls of the first ILD 88. Therefore, a second implantation area 127 can be created along the sidewalls of the first ILD 88, and this second implantation area 127 can have a fifth width W5 between approximately 1 nm and approximately 3 nm and can have a concentration of the first dopants between approximately 1E20 atoms / cm². 2 and about 1E21 atoms / cm² 2 exhibit. However, any suitable width and any suitable concentration can be used.

[0061] In embodiments where the first ILD 88 is an oxide material, such as silicon oxide, the first implantation process 122 also causes some oxygen atoms in the oxide to be displaced from the first ILD 88. Once the oxygen atoms have been displaced and are present in the surrounding atmosphere, they can then react with an exposed portion of the CESL 87, thereby oxidizing part of the CESL 87 material (e.g., silicon nitride). Such oxidation can further increase the reaction rate during subsequent processing.

[0062] Finally, during the first implantation process 122, some of the first dopants can be indirectly implanted into the source / drain region 82. In embodiments, for example, where the first implantation process 122 is performed with tilt IMP, some of the first dopants in the ambient atmosphere can diffuse into the source / drain region 82, e.g., via an indirect implantation process, while direct implantation into the source / drain region 82 may not occur. Therefore, there may be a third implantation region 128 located within the source / drain region 82. However, since this is an indirect implantation rather than a direct implantation, the depth and concentration of the third implantation region 128 are lower than the depth and concentration of either the first implantation region 124 or the second implantation region 127.

[0063] Fig. Figure 17C is a close-up view of box 125, marked with dashed lines. Fig. Figure 17B shows the extension 118 of CESL 87 after completion of the first implantation process 122, along with a first graph of the germanium concentration in the extensions 118 and a second graph of the germanium concentration in the second implantation area 126. As can be seen, the first dopants (e.g., germanium) are implanted into the extension 118 of CESL 87 by the first implantation process 122, so that there is a germanium concentration gradient there, with the germanium concentration increasing from one side of the extension 118 of CESL 87. However, any suitable concentration gradient can be used.

[0064] The Fig. 18A-18B show a cleaning process (in the Fig. 18A-18B (represented by the “X” symbols marked 129), which can be used after the first implantation process 122 to remove residual material and prepare the source / drain contact openings 114 for filling. In one embodiment, the cleaning process 129 can be a wet etching process using a wet etching solution, such as dilute hydrofluoric acid, NH3, NF3, combinations thereof, or the like. However, any suitable etching agent can be used.

[0065] In one embodiment, the wet etching solution can be brought into contact with both the first ILD 88 and the CESL 87. In another embodiment, the wet etching solution can be applied by immersion, spraying, puddle, combinations thereof, or the like. During the etching process, the wet etching solution can be maintained at a temperature between approximately 25 °C and 200 °C for a period of approximately 0.5 minutes to approximately 5 minutes. However, any suitable process conditions can be used.

[0066] During the cleaning process 129, the wet etching solution preferentially reacts with the material of CESL 87 above the material of the first ILD 88 and etches the material of CESL 87 above the material of the first ILD 88. In addition, the damage caused by the implantation of the first dopants (e.g. germanium) also increases the etch rate of the cleaning process 129 with respect to CESL 87, for example by more than three times compared to an etch rate that would occur if the first implantation process 122 had not been carried out.In one embodiment, for example, where CESL 87 is silicon nitride and the wet etchant is dilute hydrofluoric acid, the etch rate without the first implantation process 122 may be about 0.55 nm, while the use of the first implantation process 122 may increase this reaction rate to about 1.59 nm (even without significantly affecting the reaction rate of anisotropic etching processes).

[0067] Therefore, in addition to simply removing waste or material left over from previous etching processes, the cleaning process 129 also removes the material of CESL 87 beneath the first ILD 88. In some embodiments, the material of CESL 87 can be removed over a second section D2 between approximately 0.5 nm and approximately 3 nm. Thus, the remaining total amount of material of CESL 87 is reduced from approximately 8.3 nm to approximately 2.4 nm or even 1.9 nm. However, any suitable section can be used.

[0068] Although in some embodiments the first implantation area 124 can be completely removed, this is for illustrative purposes only and is not intended to be limiting. In particular, in other embodiments a portion of the first implantation area 124 may remain after the purification process 129 has been completed. In such an embodiment, the remaining portion of the first implantation area 124 in CESL 87 may have a germanium concentration of approximately 3 × 10 20 ions / cm² 2 and about 5 × 10 20 ions / cm² 2 exhibit. However, any suitable concentration can be used.

[0069] Fig. Figure 18C shows a possible chemical reaction mechanism between the material of CESL 87 and the wet etching solution when dilute hydrofluoric acid is used during the cleaning process 129 and the material of CESL 87 is silicon nitride. In this embodiment, there is a first reaction step 141, such as an initial protonation step, in which fluorine atoms and hydrogen atoms attack and remove one of the nitrogen atoms in the silicon nitride. Once one of the nitrogen atoms has been removed, a second reaction 143 takes place, such as a monomolecular nucleophilic substitution reaction (e.g., an SN1 reaction), whereby a fluorine atom replaces the previously removed nitrogen atom. In a third reaction step 145, a further protonation reaction takes place, and in a fourth reaction step 147, a bimolecular nucleophilic substitution reaction (e.g., an SN2 reaction) takes place, resulting in the removal of the silicon nitride.

[0070] Fig. Figure 18D shows a possible chemical reaction mechanism between the material of the first ILD 88 (e.g., silicon dioxide) and the wet etching solution (e.g., dilute hydrofluoric acid). In this embodiment, the silicon dioxide, which has a free lone pair of electrons, reacts with the dimer form of hydrofluoric acid (e.g., FHF), while the protonated form of silicon nitride, which does not have a free lone pair of electrons, does not react with the dimer form of hydrofluoric acid. Therefore, the material of the first ILD 88 reacts at a slower rate than the material of CESL 87.

[0071] By performing the first implantation process 122 prior to the wet etching of the cleaning process 129, the damage caused by the first implantation process 122 helps to increase the etching effectiveness during the cleaning process 129. The material damage allows the etching chemicals to penetrate the materials being etched, thereby increasing the surface area in contact with the etchants. Therefore, the cleaning process 129 can not only be used to remove additional waste, but it can also be used to enlarge the opening in preparation for subsequent steps.

[0072] The Fig. Figures 19A-19B show the preparation of a silicide area 133 and the filling of the opening with a conductive material, wherein Fig. 19B a large view of the one with the dotted line 111 in Fig. Figure 19A shows the area marked. In some embodiments, the silicide regions 133 are produced by first depositing a metal (not shown), such as titanium, nickel, cobalt, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or their alloys, which can react with the semiconductor materials of the underlying epitaxial source / drain regions 82 (e.g., silicon, silicon germanium, germanium) to form silicide or germanide regions, over the exposed portions of the epitaxial source / drain regions 82, and then performing a thermal annealing process. The unreacted portions of the deposited metal are then removed, for example, by an etching process. Although the silicide regions 133 are referred to as silicide regions, they can also be germanide regions or silicon germanide regions (e.g., regions containing both silicide and germanide).

[0073] In a particular embodiment, the silicide area 133 comprises a titanium silicide. In an embodiment where the first implantation process 122 is performed at an energy of 5.2 keV and the source / drain contact openings 114 have a width of approximately 42.94 nm, the titanium silicide can be manufactured to have a thickness between approximately 3.9 nm and approximately 5.4 nm, such as 4.8 nm. In an embodiment where the first implantation process 122 is performed at an energy of 5.0 keV and the source / drain contact openings 114 have a width of approximately 40.22 nm, the titanium silicide can also be manufactured to have a thickness between approximately 3.8 nm and approximately 6.7 nm, such as 5.3 nm. However, any suitable dimension can be used.

[0074] However, since the CESL 87 has been omitted to expose additional parts of the source / drain regions 82 located below the first ILD 88, the silicide regions 133 can also have a larger width, such as 43.2 nm (at an energy of about 5.2 keV) or about 43.1 nm (at an energy of about 5.0 keV), so that the silicide regions 133 are also produced between the source / drain regions 82 and the first ILD 88. In some embodiments, for example, the silicide regions 133 can extend over the second section D2 under the first ILD 88, and they can also be located under the second implantation region 126 of the first ILD 88, and an interface between the CESL 87 and the silicide regions 133 can extend vertically from under the second implantation region 126 of the first ILD 88 to the source / drain regions 82. However, any suitable section and arrangement can be used.

[0075] By omitting CESL 87 and creating the silicide zones 133 below the first ILD 88, the silicide zones 133 have a greater width than if CESL 87 had not been omitted. Increasing the width of the silicide zones 133 also enlarges the interface between the silicide zones 133 and the source / drain zones 82 located below them. Consequently, the total contact area between the silicide zones 133 and the source / drain zones 82 can be increased by the cleaning process 129, and the device's performance with respect to its parasitic resistance (Rp) can be improved.

[0076] Once the silicide regions 133 have been fabricated, the source / drain contact openings 114 are filled with a coating (not shown) and a conductive material. The coating may be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a surface of the first ILD 88. The remaining coating and conductive material form the source / drain contacts 112 in the openings in the shape of the first opening 114, such that the source / drain contacts 112 have a width smaller than the width of the silicide regions 133.

[0077] The Fig. Figures 20A-20B show the fabrication of a second ILD 108, which is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable layer deposited using a flowable CVD process. In other embodiments, the second ILD 108 is fabricated from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be deposited using a suitable process, such as CVD and PECVD.

[0078] The Fig.Figures 20A-20B also show the fabrication of gate contacts 110 and second source / drain contacts 113, which are produced by the second ILD 108 according to some embodiments. Openings for the second source / drain contacts 113 are created by the second ILD 108, and openings for the gate contacts 110 are created by the second ILD 108 and the gate mask 96. The openings can be produced by suitable photolithography and etching processes. A coating (not shown), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are produced in the openings. The coating can be titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like.To remove excess material from a surface of the second ILD 116, a planarization process, such as CMP, can be performed. The remaining coating and conductive material form the second source / drain contacts 113 and the gate contacts 110 in the openings. The second source / drain contacts 113 and the gate contacts 110 can be fabricated in different processes, or they can be fabricated in the same process. Although the second source / drain contacts 113 and the gate contacts 110 are shown as being fabricated in the same cross-sections, it should be understood that they can each be fabricated in different cross-sections to prevent short-circuiting of the contacts.

[0079] Because the material of CESL 87 is damaged by the implantation process prior to the cleaning process 129, a portion of the CESL 87 material can be removed during the cleaning process 129 without additional masking or etching processes. Therefore, the CESL 87 material can even be recessed beneath the sidewalls of the first ILD 88, allowing for the subsequent fabrication of the silicide regions 133 with a greater width than would otherwise be possible. Accordingly, a larger interface can lead to lower resistance and thus improved device performance.

[0080] The disclosed FinFET embodiments could also be applied to nanostructured devices (e.g., nanolayer, nanowire, gate-all-around, or similar field-effect transistors) (NSFETs) or the like. In one NSFET embodiment, the fins are replaced by nanostructures generated by structuring a stack of alternating channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are generated in a manner similar to the embodiments described above. After the dummy gate stacks have been removed, the sacrificial layers can be partially or completely removed in channel regions.The replacement gate structures are produced in a similar manner to the embodiments described above. These replacement gate structures can partially or completely fill openings left behind by the removal of the sacrificial layers, and they can partially or completely enclose the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source / drain regions can be produced in a similar manner to the embodiments described above. A nanostructure device can be produced as disclosed in U.S. patent application US 2016 / 0365414A1, which is incorporated into the present application by reference.

Claims

[1] Method for manufacturing a semiconductor device comprising the following steps: Exposing a source / drain region (82) through a first dielectric layer (88) and a second dielectric layer (87), wherein the source / drain region (82) is at least partially arranged in a semiconductor fin (52); after exposing the source / drain region (82) through the first dielectric layer (88) and the second dielectric layer (87), implanting (122) dopants into the second dielectric layer (87), wherein, in the implantation (122) of the dopants into the second dielectric layer (87), the dopants are also implanted along side walls of the first dielectric layer (88); after implanting (122) the dopants, recessing (129) the second dielectric layer (87) beneath the first dielectric layer (88); and Forming a silicide region (133) on the source / drain region (82), wherein the silicide region (133) is arranged in a direction perpendicular to the semiconductor fin (52) after the formation of the silicide region (133) between the source / drain region (82) and the first dielectric layer (88). [2] Method according to claim 1, wherein the recession (129) of the second dielectric layer (87) is carried out using a wet etching process (129). [3] Method according to claim 2, wherein the wet etching process (129) is carried out using hydrofluoric acid. [4] Method according to any of the preceding claims, wherein the implantation (122) of the dopants is carried out as an inclined implantation. [5] Method according to any of the preceding claims, wherein germanium is implanted during the implantation (122) of the dopants. [6] Method according to any of the preceding claims, wherein the second dielectric layer (87) has an extension (118) projecting from a side wall of the first dielectric layer (88). [7] Method for manufacturing a semiconductor device comprising the following steps: Etching of a first dielectric material (88) to create a first opening (114); Etching a second dielectric material (87) to extend the first opening (114) through the second dielectric material (87), wherein the first opening (114) has a first width (W1) through the first dielectric material (88) and a second width (W2) which is smaller than the first width through the second dielectric material (87); after etching the second dielectric material (87), recessing (129) of the second dielectric material (87) from a side wall of the first dielectric material (88) to create a recess; Producing a silicide (133) in the recess and in the first opening (114); and Filling a remainder of the first opening (114) with a conductive material, wherein the recession (129) of the second dielectric material (87) comprises the implantation (122) of a first dopant into the second dielectric material (87), wherein when implanting (122) the first dopant the first dopant is also implanted along side walls of the first dielectric material (88). [8] Method according to claim 7, wherein the first dopant comprises germanium. [9] Method according to claim 7 or 8, wherein the recession (129) of the second dielectric material (87) further comprises the application of a wet etching agent to the second dielectric material (87) after the implantation (122) of the first dopant. [10] Method according to claim 9, wherein the wet etching agent comprises hydrofluoric acid. [11] Method according to any one of claims 7 to 10, wherein the implantation (122) of the first dopant is carried out as an inclined implantation (122). [12] Semiconductor device with: a source / drain region (82) arranged in a semiconductor fin (52); a first dielectric material (88) over the semiconductor fin (52); a contact etch stop layer (87) arranged between the first dielectric material (88) and the semiconductor fin (52); and a conductive contact (112) extending through the first dielectric material (88) to make physical contact with a silicide region (133) above the source / drain region (82), wherein the silicide region (133) has a first width and the conductive contact has a second width adjacent to the silicide region (133) which is smaller than the first width, wherein the first dielectric material (88) has a first implantation area (126) which is arranged along a side wall of the first dielectric material (88) adjacent to the conductive contact (112), and wherein the contact etch stop layer (87) has a second implantation area (124) which is arranged along a side wall of the contact etch stop layer (87). [13] Semiconductor device according to claim 12, further comprising a third implantation area (128) arranged in the source / drain area (82), wherein the third implantation area (128), the second implantation area (124) and the first implantation area (126) have the same dopant. [14] Semiconductor device according to claim 12 or 13, wherein the silicide region (133) extends over a distance of about 0.5 nm to about 3 nm below the first dielectric material (88). [15] Semiconductor device according to any one of claims 12 to 14, wherein the second width is between about 20 nm and about 45 nm.

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