NANOSTRUCTURE FIELD-EFFECT TRANSISTOR DEVICE AND METHOD FOR FORMING THE SAME

Abstract

A method of forming a semiconductor device, the method comprising: Forming a fin structure (91) protruding above a substrate (50), the fin structure (91) comprising a fin (90) and a layer stack (92) overlying the fin (90), the layer stack (92) comprising alternating layers of a first semiconductor material (52) and a second semiconductor material (54); Forming a dummy gate structure (97, 102) over the fin structure (91); Forming openings (110) in the fin structure (91) on opposite sides of the dummy gate structure (97, 102), the openings (110) extending through the layer stack (92) into the fin (90); Forming a dielectric layer (107, 59) in bottom portions of the openings (110); and Forming source / drain regions (112) in the openings (110) on the dielectric layer (107, 59), wherein the source / drain regions (112) are separated from the fins (90) by the dielectric layer (107, 59), wherein forming the dielectric layer (107, 59) comprises: lining side walls and bottoms of the openings (110) with a dielectric material (107'); performing an implantation process to treat the dielectric material (107'); and after the implantation process, performing an etching process to remove sidewall portions of the dielectric material (107'), wherein after the etching process bottom portions of the dielectric material (107') remain and form the dielectric layer (107).

Description

BACKGROUNDSemiconductor devices are used in a variety of electronic applications, such as personal computers, cellular phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing layers of insulating or dielectric material, layers of conductive material, and semiconductor layers over a semiconductor substrate, and patterning the various layers using lithography to form circuit components and elements thereon.The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature sizes are reduced, additional challenges arise that should be addressed.The prior art relating to the subject matter of the invention can be found, for example, in U.S. Pat. No. 2020 / 0 044 061 A1, U.S. Pat. No. 2020 / 0 303 500 A1, U.S. Pat. No. 10 134 901 B1, U.S. Pat. No. 2019) / 0 109 040 A1 and U.S. Pat. No. 2020 / 0 044 087 A1.The invention provides a method according to claim 1, a method according to claim 3, a method according to claim 10 and a semiconductor device according to claim 15. Embodiments are set forth in the dependent claims.BRIEF DESCRIPTION OF THE DRAWINGSAspects of the present disclosure will be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features are not drawn to scale in accordance with common industry practice. Indeed, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased. FIG. 1 illustrates, in a three-dimensional view, an example of a nanostructure field effect transistor (NSFET) device, in accordance with some embodiments. FIGS. 2, 3A, 3B, 4A, 4B, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B are cross-sectional views of a nanostructure field effect transistor (NSFET) device in accordance with an embodiment at various stages of fabrication. FIGS. 17, 18 and 19A-19C are cross-sectional views of a nanostructure field effect transistor device at various stages of fabrication, according to another embodiment. FIGS. 20, 21, and 22A-22C are cross-sectional views of a nanostructure field effect transistor device at various stages of fabrication, according to another embodiment. FIGS. 23, 24 and 25A-25C are cross-sectional views of a nanostructure field effect transistor device at various stages of fabrication, in accordance with yet another embodiment. FIG. 26 is a flow diagram of a method of forming a semiconductor device in some embodiments.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments for implementing different features of the invention. In order to simplify the present disclosure, concrete examples of components and arrangements will be described below. These are of course merely exemplary embodiments. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact.Further, spatially relative terms such as "below," "below," "lower / r / s," "above," "upper / r / s," and the like may be used herein to simplify the description to describe the relationship of an element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The object may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptions used herein may also be interpreted accordingly. Throughout the discussion herein, the same reference number in different figures refers to the same or similar element formed by a same or similar formation process using a same or similar material / materials. Further, the figures with the same number but different letters (e.g., FIGS. 5A, 5B, and 5C ) illustrate the same semiconductor device at the same stage of manufacture but along different cross-sections.According to some embodiments, a dielectric layer is formed under source / drain regions located in a short channel device region of an n-type device region of a nanostructure field effect transistor (NSFET) device. The dielectric layer physically and electrically isolates the source / drain regions from the underlying fins, thereby reducing or preventing substrate leakage and / or well isolation leakage. In some embodiments, the dielectric layer is formed exclusively under the source / drain regions of the short channel device region in the n-type device region of the NSFET device. The dielectric layer is not formed in the p-type device region of the NSFET device, nor is the dielectric layer formed in a large channel device region or a receiving region of the n-type device region.FIG. 1 illustrates, in a three-dimensional view, an example of a nanostructure field effect transistor (NSFET) device, in accordance with some embodiments. The NSFET device includes semiconductor fins 90 (also referred to as fins) protruding above a substrate 50. Gate electrodes 122 (e.g., metal gates) are disposed over the fins, and source / drain regions 112 are formed on opposite sides of the gate electrodes 122. A plurality of nanosheets 54 are formed over the fins 90 and between source / drain regions 112. Isolation regions 96 are formed on opposing sides of the fins 90. A gate dielectric layer 120 is formed around the nanosheets 54. Gate electrodes 122 are present over and around the gate dielectric layer 120.FIG. 1 further illustrates reference cut planes used in subsequent figures. Cross-section A-A' is along a longitudinal axis of a gate electrode 122 and in a direction that is, for example, perpendicular to the direction of current flow between the source / drain regions 112 of an NSFET device. Cross-section B-B' is perpendicular to cross-section A-A' and is along a longitudinal axis of a fin and in a direction of, for example, current flow between the source / drain regions 112 of the NSFET device. The cross-section C-C' is parallel to the cross-section A-A' and extends through the source / drain regions 112. For clarity, subsequent figures refer to these reference cut planes.FIGS. 2, 3A, 3B, 4A, 4B, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B are cross-sectional views of a nanostructure field effect transistor (NSFET) device 100 in accordance with an embodiment at various stages of fabrication.In FIG. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, for example a bulk semiconductor, a semiconductor on insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or an n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a layer of a semiconductor material formed on an isolation layer. The isolation layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon substrate or a glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate 50 includes silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.A multilayer stack 64 is formed on the substrate 50. The multilayer stack 64 includes alternating layers of a first semiconductor material 52 and a second semiconductor material 54. In FIG. 2, the layers formed of the first semiconductor material 52 are labeled 52A, 52B, and 52C, and the layers formed of the second semiconductor material 54 are labeled 54A, 54B, and 54C. The number of layers formed by the first semiconductor material 52 and the second semiconductor material 54 illustrated in FIG. 2 is merely a non-limiting example. Further numbers of layers are also possible.In some embodiments, the first semiconductor material 52 is an epitaxial material suitable for forming channel regions of, e.g., p-type FETs, such as silicon germanium (Si x Ge 1-x, where x may be in the range of 0 to 1) and the second semiconductor material 54 is an epitaxial material suitable for forming channel regions of, e.g., n-type FETs, such as silicon. The multi-layer stacks 64 (may also be referred to as an epitaxial material stack) are patterned to form channel regions of NSFETs when subsequently processed. In particular, the multilayer stacks 64 are patterned to form horizontal nanostructures (e.g., nanosheets or nanowires), where the channel regions of the resulting NSFETs include multiple horizontal nanostructures.The multilayer stacks 64 may be formed by an epitaxial growth process that may be performed in a growth chamber. In some embodiments, during the epitaxial growth process, the deposition chamber is cyclically exposed to a first set of precursors for selectively growing the first semiconductor material 52 and then a second set of precursors for selectively growing the second semiconductor material 54. The first set of precursors includes a precursor for the first semiconductor material (e.g., silicon germanium) and the second set of precursors includes a precursor for the second semiconductor material (e.g., silicon). In some embodiments, the first set of precursors includes a silicon precursor (e.g., silane) and a germanium precursor (e.g., germane), and the second set of precursors includes the silicon precursor, but omits the germanium precursor. The epitaxial growth process may therefore include continuously permitting a flow of the silicon precursor into the growth chamber and subsequently cyclically: (1) permitting a flow of the germanium precursor into the growth chamber when the first semiconductor material 52 is grown; and (2) preventing the flow of the germanium precursor into the growth chamber when the second semiconductor material 54 is grown. The cyclic exposure may be repeated until a target number of layers are formed.FIGS. 3A, 3B, 4A, 4B, 5A-5C, 6A-6C, 7A-7C, 8A-8C, 9A-9C, 10A-10C, 11A-11C, 12A-12C, 13A, 13B, 14A, 14B, 15A, 15B, 16A, and 16B are cross-sectional views of the NSFET device 100 according to an embodiment at subsequent fabrication stages. FIGS. 3A, 4A, 5A, 6A, 7A, 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, and 16B are cross-sectional views taken along cross-section B-B' in FIGS. 1, 5B, 6B, 7B, 8B, 9B, 10B, 10B, and 10B, FIGS. 11B and 12B are cross-sectional views along cross-section C-C' in FIGS. 1, 3B, 4B, 5C, 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13B, 14B, and 15B are cross-sectional views along cross-section A-A' in FIG. 1. THE number of fins and the number of gate structures illustrated in the figures are non-limiting examples, and it should be understood that, further numbers of fins and further numbers of gate structures may also be formed. For simplicity, FIGS. 3A, 3B, 4A, 4B, 5A- 5C, 6A- 6C, 7A- 7C, 8A- 8C, 9A- 9C, 10A- 10C, 11A- 11C, 12A- 12C, 13A, 13B, 14A, 14B, 15A, and 15B illustrate the process steps to form n-type NSFETs in an n-type device region of the NSFET device 100. As will be readily understood by those skilled in the art, the same or similar processing steps may be performed to form p-type NSFETs in a p-type device region of the NSFET device 100. FIG. 16A illustrates NSFETs formed in an n-type device region of the NSFET device 100, and FIG. 16B illustrates NSFETs formed in a p-type device region of the NSFET device 100.In FIGS. 3A and 3B, protruding fin structures 91 are formed above the substrate 50. Each of the fin structures 91 includes a semiconductor fin 90 and a layer stack 92 overlying the semiconductor fin 90. The layer stack 92 and the semiconductor fin 90 may be formed by etching trenches in the multilayer stack 64 and the substrate 50, respectively.The fin structure 91 may be patterned by any suitable method. For example, the fin structure 91 may be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, in dual or multiple patterning processes, photolithography and self-aligned processes are combined, allowing for the fabrication of structures with smaller dimensions than is achievable using, for example, a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed and the remaining spacers may then be used to pattern, e.g., the fin structure 91. In some embodiments, the remaining spacers are used to pattern a mask 94, which is then used to pattern the fin pattern 91.The mask 94 may be a single layer mask or may be a multi-layer mask, such as a multi-layer mask including a first mask layer 94A and a second mask layer 94B. The first mask layer 94A and second mask layer 94B may each be formed of a dielectric material such as silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to suitable techniques. The first mask layer 94A and the second mask layer 94B are made of different materials having a high etching selectivity. For example, the first mask layer 94A may be made of silicon oxide and the second mask layer 94B may be made of silicon nitride. The mask 94 may be formed by patterning the first mask layer 94A and the second mask layer 94B using any acceptable etching process. The mask 94 may then be used as an etch mask to etch the substrate 50 and the multilayer stack 64. The etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or the like, or combinations thereof. In some embodiments, the etching is an anisotropic etching process. After the etching process, the patterned multilayer stack 64 forms the layer stacks 92, and the patterned substrate 50 forms the semiconductor fins 90, as illustrated in FIGS. 3A and 3B. Thus, in the illustrated embodiment, the layer stack 92 also includes alternating layers of the first semiconductor material 52 and the second semiconductor material 54, and the semiconductor fin 90 is formed of a same material (e.g., silicon) as the substrate 50.Next, in FIGS. 4A and 4B, shallow trench isolation (STI) regions 96 are formed over the substrate 50 and on opposite sides of the fin structure 91. As an example, an isolation material may be formed over the substrate 50 to form the STI regions 96. The isolation material may be an oxide such as silicon oxide, a nitride, or the like, or a combination thereof, and may be formed by high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., CVD-based material deposition in a remote post-cure plasma system for conversion to another material such as an oxide), or the like, or a combination thereof. Other insulation materials formed by any acceptable process may be used. In the illustrated embodiment, the isolation material is silicon oxide formed by an FCVD process. After the insulation material is formed, a anneal process may be performed.In an embodiment, the isolation material is formed such that excess isolation material covers the fin structure 91. In some embodiments, a liner is first formed along surfaces of the substrate 50 and the fin structure 91, and a fill material such as those discussed above is formed over the liner. In some embodiments, the liner is omitted.Next, a removal process is performed on the isolation material to remove excess isolation material from over the fin structure 91. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), an etch back process, combinations thereof, or the like, may be utilized. The planarization process exposes the layer stack 92 such that the top surfaces of the layer stacks 92 and the isolation material are the same height after the planarization process is completed. Next, the isolation material is recessed to form the STI regions 96. The isolation material is recessed such that the layer stacks 92 protrude from between adjacent STI regions 96. Upper portions of the semiconductor fins 90 may also protrude from between adjacent STI regions 96. Further, the top surfaces of the STI regions 96 may include a flat surface as illustrated, a convex surface, a concave surface (such as by recessing (dishing)), or a combination thereof. The top surfaces of the STI regions 96 may be formed flat, convex, and / or concave by appropriate etching. The STI regions 96 may be recessed using an acceptable etching process, such as one selective to the material of the insulating material (e.g., etches the material of the insulating material at a faster rate than the material of the semiconductor fins 90 and the layer stacks 92). For example, chemical oxide removal with a suitable etchant such as dilute hydrofluoric acid (dHF) may be used.Still referring to FIGS. 4A and 4B, a dummy dielectric layer 97 is formed over the layer stacks 92 and over the STI regions 96. The dummy dielectric layer 97 may be made of, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. In an embodiment, a layer of silicon is conformally formed over the layer stacks 92 and over the top surface of the STI regions 96, and a thermal oxidation process is performed to convert the deposited silicon layer to an oxide layer as the dummy dielectric layer 97.Next, in FIGS. 5A-5C, dummy gates 102 are formed over the fins 90 and over the layer stacks 92. To form dummy gates 102, a dummy gate layer may be formed over dummy dielectric layer 97. The dummy gate layer may be deposited over the dummy dielectric layer 97 and subsequently planarized, such as by CMP. The dummy gate layer may be made of a conductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), or the like. The dummy gate layer may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art. The dummy gate layer may be formed of other materials having high etch selectivity from the STI regions 96.Subsequently, masks 104 are formed on the dummy gate layer. The masks 104 may be formed of silicon nitride, silicon oxynitride, combinations thereof, or the like, and may be patterned using acceptable photolithography and etching techniques. In the illustrated embodiment, the mask 104 includes a first mask layer 104A (e.g., a silicon oxide layer) and a second mask layer 104B (e.g., a silicon nitride layer). Subsequently, the pattern of the masks 104 is transferred to the dummy gate layer by an acceptable etching technique to form the dummy gates 102 and then transferred to the dummy dielectric layer by an acceptable etching technique to form dummy gate dielectrics 97. The dummy gates 102 cover the respective channel regions of the layer stack 92 The structure of the masks 104 may be used to physically separate each of the dummy gates 102 from adjacent dummy gates. Dummy gate 102 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of fin 90. In some embodiments, dummy gate 102 and dummy gate dielectric 97 are collectively referred to as a dummy gate structure.Next, a gate spacer layer 108' is formed by conformally depositing an insulating material over the layer stacks 92, the STI regions 96, and the dummy gates 102. The insulating material may be made of silicon nitride, silicon carbonitride, a combination thereof, or the like. In some embodiments, the gate spacer layer 108' includes multiple sub-layers. For example, a first underlayer (sometimes referred to as a gate seal spacer layer) may be formed by thermal oxidation or deposition, and a second underlayer (sometimes referred to as a main gate spacer layer) may be conformally deposited on the first underlayer. FIGS. 5B and 5C illustrate cross-sectional views of the NSFET device 100 in FIG. 5A, respectively, but along cross-sections E-E' and F-F' in FIG. 5A, where cross-sections E-E' and F-F' correspond to cross-sections C-C' and A-A' in FIG. 1, respectively. Similarly, FIGS. 6B, 7B, 8B, 9B, 10B, 11B, and 12B illustrate cross-sectional views of the NSFET device 100 along cross-section E-E' in FIGS. 5A and 6C, 7C, 8C, 9C, 10C, 11C, 12C, 13B, 14B, and 15B illustrate cross-sectional views of the NSFET device 100 along cross-section F-F' in FIG. 5A.Next, in FIGS. 6A-6C, the gate spacer layer 108' is etched by an anisotropic etching process to form gate spacers 108. The anisotropic etching process may remove horizontal portions of the gate spacer layer 108 (e.g., portions over the STI regions 96 and the dummy gate 102), with remaining vertical portions of the gate spacer layer 108' (e.g., along sidewalls of the dummy gate 102 and the dummy gate dielectric 97) forming the gate spacers 108.After the formation of the gate spacers 108, an implantation may be performed for lightly doped source / drain (LDD) regions (not shown). Appropriate types of (e.g., p-type or n-type) impurities may be implanted into the exposed layer stacks 92 and / or the semiconductor fin 90. The n-type impurities may be any suitable n-type impurities such as phosphorus, arsenic, antimony, or the like, and the p-type impurities may be any p-type impurities such as boron, BF2, indium, or the like. The lightly doped source / drain regions may have an impurity concentration of from about 10 15 cm -3 to about 10 16 cm -3. An annealing process may be used to activate the implanted contaminants.Next, openings 110 (may also be referred to as recesses or source / drain openings) are formed in the layer stacks 92. The openings 110 may extend through the layer stacks 92 and into the semiconductor fin 90. The openings 110 may be formed by any acceptable etching technique, e.g., using the dummy gates 102 and the gate spacers 108 as an etch mask. The openings 110 expose end portions of the first semiconductor material 52 and end portions of the second semiconductor material 54.Referring still to FIGS. 6A-6C, after the openings 110 are formed, a selective etching process (e.g., a wet etching process using an etching chemical) is performed to remove end portions of the first semiconductor material 52 exposed by the openings 110 without substantially engaging the second semiconductor material 54. After a selective etching process, recesses 52R are formed in the first semiconductor material 52 at locations where the distal end portions were. Note that due to the recesses 52R, sidewalls of the first semiconductor material 52 are recessed from sidewalls 54S of the second semiconductor material 54, and thus the recesses 52R may also be referred to as sidewall recesses 52R.FIG. 6B illustrates the remaining portions of the gate spacer layer (labeled 108) on the top surface of the STI regions 96. In other embodiments, the remaining portions of the gate spacer layer 108 extend along sidewalls of the fins 90, but are not continuous between adjacent fins 90, and may thus expose portions of the top surface of the STI regions 96. In the example of FIG. 6B, the top surface of the fin 90, which corresponds to the top surface of a portion of the fin 90 directly below the opening 110 in FIG. 6A, is the same height as the top surface of the STI region 96, although the top surface of the fin 90 may also extend above or below the top surface of the STI region 96.Next, in FIGS. 7A-7C, a spacer film 55' is formed (e.g., conformal) over the structure of FIGS. 6A-6C. As illustrated in Figs. 7A-7C, the spacer film 55' extends along upper surfaces of the masks 104 and lines side walls and bottoms of the openings 110. Notably, the spacer film 55' fills (e.g., fills completely) the sidewall recesses 52R. The spacer film 55' may be, for example, silicon nitride (SiN), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), or the like, and may be formed by, for example, CVD, PVD, atomic layer deposition (ALD), or the like.Next, in FIGS. 8A-8C, a trimming process (also referred to as an inner spacer trimming process) is performed to remove (e.g., completely remove) portions of the spacer film 55' disposed outside the sidewall recess 52R, such as portions along the sidewalls and the bottoms of the openings 110 and portions along the top surface of the dummy gate 102. After the trimming process, portions of the spacer film 55' remain in the side wall recesses 52R to form the inner spacers 55.In some embodiments, the trimming process is a suitable etching process, such as a dry etching process or a wet etching process. In an example embodiment, a dry etching process is performed using a gas source including a mixture of CHF3and O 2, a mixture of CF 4 and O 2, a mixture of NF 3, CH 3 F, and CHF 3 or the like, to remove the portions of the spacer film 55' disposed outside the sidewall recesses 52R. Parameters of the dry etching process, such as the mixing ratio between gases in the gas source, the pressure and / or flow rates of the gases, are adjusted to adjust a lateral etching rate of the dry etching process. In the example of FIG. 8A, after the trimming process, sidewalls of the remaining portions of the spacer film 55' (or sidewalls of the inner spacers 55) are flush with sidewalls 54S of the second semiconductor material 54. In further embodiments, sidewalls of the inner spacers 55 may be recessed from the sidewalls 54S or may extend beyond the sidewalls 54S of the second semiconductor material 54 toward the openings 110.Next, in FIGS. 9A-9C, a dielectric material 107' is formed (e.g., conformal) over the dummy gate 102 and along the sidewalls and bottoms of the openings 110. Dielectric material 107' may be, for example, SiN, although other suitable material, such as SiCN, SiOCN, may also be used. A suitable formation method, such as ALD, PVD, CVD, may be used to form the dielectric material 107'.Next, an implantation process 130 (e.g., an ion implantation process) is performed to treat the dielectric material 107'. The implantation process 130 may be performed using a gas source comprising carbon (C), oxygen (O), germanium (Ge), or combinations thereof. In some embodiments, ion species, for example, C, O, Ge, or combinations thereof, are implanted into the dielectric material 107' to change the physical properties (e.g., hardness, etch rate) of the dielectric material 107'. It should be appreciated that the concentrations of the ion species implanted into the dielectric material 107' are non-uniform due to, e.g., the angle of the implantation process 130 and / or the aspect ratio of the openings 110. For example, the concentration of the implanted ion species at bottom portions of the dielectric material 107' (e.g., portions at the bottoms of the openings 110) is higher than the concentration of the implanted ion species at sidewall portions of the dielectric material 107' (e.g., portions along the sidewalls of the openings 110). In some embodiments, the bottom portions of the dielectric material 107' are implanted (e.g., doped) with the ion species and the sidewall portions of the dielectric material 107' are substantially free of the ion species, resulting in a large etch selectivity between the bottom portions and the sidewall portions of the dielectric material 107'. In some embodiments, the concentration of the implanted ion species in the dielectric material 107' gradually decreases from the bottom portions of the dielectric material 107' toward the sidewall portions of the dielectric material 107' (e.g., along the directions illustrated by arrows 131 in FIG. 10A ). In an example embodiment, the bottom portions of the dielectric material 107' have a lower etch rate than the sidewall portions of the dielectric material 107' as a result of the implantation process 130 in a subsequent etch process.In accordance with some embodiments, the dielectric material 107' is formed to have a thickness between about 1 nm and about 10 nm. In some embodiments, if the thickness of the dielectric material 107' is too small (e.g., less than about 1 nm), the subsequently formed dielectric layer 107 (see FIGS. 10A-10C ) may not provide enough electrical insulation to prevent or reduce leakage current. If the thickness is too large (e.g., greater than about 10 nm), the dielectric material 107' may coalesce along the sidewalls of the openings 110 and fill the openings 110, thus preventing the implantation process from reaching the bottom portions of the dielectric material 107', which in turn prevents the dielectric layer 107 (see FIGS. 10A-10C ) from being properly formed.Next, in FIGS. 10A-10C, a suitable etching process, such as a dry etch or wet etch, is performed to remove portions of the dielectric material 107' disposed along the sidewalls of the openings 110 and over the dummy gates 102. The etching process is stopped after the dielectric material 107' is removed from the sidewalls of the openings 110 and from over the dummy gates 102. Note that after the etching process is stopped, due to the etching selectivity between the bottom portions and the sidewall portions of the dielectric material 107', the bottom portions of the dielectric material 107' remain to form a dielectric layer 107 at the bottoms of the openings 110. In the example of FIG. 10A, the dielectric layer 107 extends continuously along the top surface of the fin 90 from a first inner spacer 55 (e.g., a lowermost inner spacer 55 below the left dummy gate 102) to a second inner spacer 55 (e.g., a lowermost inner spacer 55 below the right dummy gate 102). Note that the dielectric layer 107 contacts (e.g., physically contacts) the lowermost inner spacer 55, and the upper surface 107U of the dielectric layer 107 is lower (e.g., closer to the substrate 50) than the lowermost surface of the second semiconductor material 54 facing the substrate 50, allowing the subsequently formed source / drain regions 112 to be electrically connected to the second semiconductor material 54 (e.g., the channel regions of the NSFETs) without being blocked by the dielectric layer 107.FIG. 10B illustrates the dielectric layer 107 covering (e.g., contacting and extending along) the top surfaces of the fins 90 and extending continuously from a first fin 90 (e.g., the left fin 90) to an adjacent second fin 90 (e.g., the right fin 90).Next, in FIGS. 11A-11C, source / drain regions 112 are formed in the openings 110. In some embodiments, the source / drain regions 112 are formed of epitaxial material(s) and thus may also be referred to as epitaxial source / drain regions 112. In some embodiments, the epitaxial source / drain regions 112 are formed in the openings 110 to apply stress in the respective channel regions of the NSFET device that have been formed to increase mobility of the carriers, thereby improving device performance. The epitaxial source / drain regions 112 are formed such that each dummy gate 102 is disposed between adjacent pairs of the epitaxial source / drain regions 112. In some embodiments, the gate spacers 108 are used to separate the epitaxial source / drain regions 112 from the dummy gate 102 by an appropriate lateral distance such that the epitaxial source / drain regions 112 do not short the subsequently formed gates of the resulting NSFET device.In some embodiments, the epitaxial source / drain regions 112 are epitaxially grown in the openings 110. The epitaxial source / drain regions 112 may include any acceptable material, such as appropriate for n-type or p-type devices. For example, when forming n-type devices, the epitaxial source / drain regions 112 may include materials that exert tensile stress in the channel regions, such as silicon, SiC, SiCP, SiP, or the like. Likewise, when forming p-type devices, the epitaxial source / drain regions 112 may include materials that exert compressive stress in the channel regions, such as SiGe, SiGeB, Ge, GeSn, or the like. The epitaxial source / drain regions 112 may have surfaces raised from respective surfaces of the fins 90 and may have facets.The epitaxial source / drain regions 112 and / or the fins 90 may be implanted with dopants to form source / drain regions, similar to the process discussed above for forming lightly doped source / drain regions, followed by an anneal. The source / drain regions may have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3. The n- and / or p-type impurities for source / drain regions may be any of the impurities discussed above. In some embodiments, the epitaxial source / drain regions 112 may be in situ doped during growth.As a result of the epitaxy processes used to form the epitaxial source / drain regions 112, top surfaces of the epitaxial source / drain regions 112 have facets that extend laterally outward beyond the sidewalls of the fin 90. In some embodiments, after the epitaxy process is completed, adjacent epitaxial source / drain regions 112 disposed over adjacent fins 90 remain separated, as illustrated in FIG. 11B. In further embodiments, these facets cause adjacent epitaxial source / drain regions 112 disposed over adjacent fins 90 of a same NSFET to coalesce and form a continuous source / drain region 112 over adjacent fins 90.As illustrated in FIG. 11B, the dielectric layer 107 under the source / drain regions 112 separates (e.g., physically separates) the source / drain regions 112 from underlying fins 90. Similarly, as illustrated in FIG. 11A, the source / drain regions 112 are separated from the underlying fin 90 by the dielectric layer 107, as the dielectric layer 107 contacts (e.g., physically contacts) the sidewalls of the lowermost inner spacers 55.As feature sizes continue to shrink in advanced semiconductor fabrication processes, new challenges arise. For example, substrate leakage related to leakage current between adjacent source / drain regions 112 through substrate 50 (see dashed leakage path 133 in FIG. 11A ) may increase. Further, well isolation leakage related to leakage current between adjacent well regions may also increase. For a better understanding of the well isolation leakage path, assume that the fin 90 on the left side of FIG. 11B has an n-type well region and the fin 90 on the right side of FIG. 11B has a p-type well region, then the dashed line 135 in FIG. 11B illustrates a well isolation leakage path between an n-type well region (also referred to as a p-well) and a p-type well region (also referred to as a p-well). Note that in FIG. 11B, both fins 90 are present in an n-type device region and have p-type well regions, so there is no well isolation leakage between the fins 90 in FIG. 11B. Dashed line 135 is drawn to better understand well isolation leakage between two adjacent fins with different types of well regions.The present disclosure isolates (e.g., electrically isolates) the source / drain regions 112 from the underlying fins 90 by forming the dielectric layer 107 under the source / drain regions 112, thus blocking the substrate leakage paths and well isolation leakage paths, which in turn prevents or reduces substrate leakage and well isolation leakage and improves device performance.Next, in FIGS. 12A-12C, a contact etch stop layer (CESL) 116 is formed (e.g., conformal) over the source / drain regions 112 and over the dummy gate 102, and an interlayer dielectric (ILD) 114 is subsequently deposited over the CESL 116. The CESL 116 is formed of a material having an etch rate different from the ILD 114 and may be formed of silicon nitride using PECVD, although other dielectric materials such as silicon oxide, silicon oxynitride, combinations thereof, or the like, and alternative techniques for forming the CESL 116, such as low pressure CVD (LPCVD), PVD, or the like, could be used.The ILD 114 may be formed of a dielectric material and may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Dielectric materials for the ILD 114 may include silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron doped phosphosilicate glass (BPSG), undoped silicon glass (USG), or the like. Other dielectric materials formed by any acceptable process may be used.The cross-sectional view of FIG. 12B remains the same for the subsequent processing steps illustrated in FIGS. 13A, 13B, 14A, 14B, 15A, and 15B is therefore not repeated.Next, in FIGS. 13A and 13B, the dummy gates 102 are removed. To remove the dummy gates 102, a planarization process such as CMP may be performed to level the top surfaces of the ILD 114 and the CESL 116 with the top surfaces of the dummy gates 102 and gate spacers 108. The planarization process may also remove the masks 104 (see FIG. 12A ) on the dummy gates 102 and portions of the gate spacers 108 along sidewalls of the masks 104. After the planarization process, top surfaces of dummy gates 102, gate spacers 108, and ILD 114 are equal in height. Accordingly, the top surfaces of the dummy gates 102 are exposed at the top surface of the ILD 114.After the planarization process, dummy gates 102 are removed in an etch step(s) such that recesses 103 (may also be referred to as openings 103) are formed between gate spacers 108. In some embodiments, the dummy gates 102 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reaction gas(s) that selectively etch the dummy gates 102 without etching the ILD 114 or the gate spacers 108. The recesses 103 expose the channel regions of the NSFET device 100. The channel regions are disposed between adjacent pairs of the epitaxial source / drain regions 112. In the course of removing the dummy gates 102, the dummy gate dielectric 97 may be used as an etch stop layer when the dummy gates 102 are etched. Thereafter, the dummy gate dielectric 97 may be removed after the removal of the dummy gates 102. After the dummy gates 102 are removed, the first semiconductor material 52 and the second semiconductor material 54 that were disposed under (e.g., directly under) the dummy gates 102 are exposed by the recesses 103.Next, in FIGS. 14A and 14B, the first semiconductor material 52 is removed to release the second semiconductor material 54. After the first semiconductor material 52 is removed, the second semiconductor material 54 forms a plurality of nanostructures 54 that extend horizontally (e.g., parallel to a top major surface of the substrate 50). In some embodiments, the nanostructures 54 may also be referred to as nanosheets or nanowires, and the NSFET device 100 may also be referred to as a gate all around (GAA) device, depending on, e.g., the dimension of the nanostructure 54. As illustrated in FIGS. 14A and 14B, gaps 53 (e.g., voids) are formed between the nanostructures 54 by the removal of the first semiconductor material 52.In some embodiments, the first semiconductor material 52 is removed by a selective etching process using an etchant that is selective to (e.g., has a higher etch rate for) the first semiconductor material 52, such that the first semiconductor material 52 is removed without substantially impacting the second semiconductor material 54. In an embodiment, an isotropic etch process is performed to remove the first semiconductor material 52. The isotropic etching process may be performed using an etching gas and optionally a carrier gas. In some embodiments, the etching gas comprises HF, a mixture of F 2 and HF, or the like, and the carrier gas may be an inert gas such as Ar, He, N 2, combinations thereof, or the like. In some embodiments, an etchant such as dissolved ozone in deionized water (DIO) is used to selectively remove the first semiconductor material 52.In the illustrated embodiment, the upper surface 107U of the dielectric layer 107 is lower (e.g., closer to the substrate 50) than a lower surface of a lowermost nanostructure 54 facing the substrate 50. This feature ensures that the dielectric layer 107 does not interfere with (e.g., block or partially block) the electrical connection between the source / drain regions 112 and the nanostructure 54. Otherwise, the electrical resistance between the source / drain regions 112 and the nanostructures 54 may be negatively affected (e.g., increased).Next, in FIGS. 15A and 15B, a gate dielectric layer 120 is formed (e.g., conformally) in the recesses 103 and in the gaps 53. The gate dielectric layer 120 wraps around the nanostructures 54, lines sidewalls of the inner spacers 55 and sidewalls of the gate spacers 108, and extends along the top surfaces and sidewalls of the fins 90. In some embodiments, the gate dielectric layer 120 includes a high-k dielectric material, and in these embodiments, the gate dielectric layer 120 may have a dielectric constant of greater than about 7.0, and may include a metal oxide or silicate of Hf, Al, Zr, La, Mg, Ba, Ti, or Pb, or combinations thereof. The formation methods of the gate dielectric layer 120 may include molecular-beam deposition (MBD), ALD, PECVD, or the like.Next, a gate electrode material (e.g., an electrically conductive material) is formed in the recesses 103 and the gaps 53 to form the gate electrodes 122. The gate electrode material fills the remaining portions of the recesses 103 and the gaps 53. the gate electrode material may be a metal-containing material such as Cu, Al, W, the like, combinations thereof, or multilayers thereof, and may be formed by electroplating, electroless plating, or other suitable method, for example. After the gate electrode material is formed, a planarization process such as CMP may be performed to remove the excess portions of the gate dielectric layer 120 and the gate electrode material, the excess portions being over the top surface of the ILD 114. The remaining portions of the gate electrode material and the gate dielectric layer 120 therefore form replacement gates of the resulting NSFET device 100. The gate electrode 122 and the corresponding gate dielectric layer 120 may be collectively referred to as a gate stack 123, a replacement gate structure 123, or a metal gate structure 123. Each gate structure 123 extends over and around the corresponding nanostructures 54.Although the gate electrode 122 is illustrated as a single layer in the example of FIGS. 15A and 15B, one skilled in the art will readily appreciate that the gate electrode 122 may have a multilayer structure and may include a plurality of layers such as a barrier layer, a work function layer, a seed layer, and a fill metal.For example, a barrier layer may be conformally formed over the gate dielectric layer 120. The barrier layer may comprise an electrically conductive material such as titanium nitride, although other materials such as tantalum nitride, titanium, tantalum, or the like may alternatively be used. A work function layer may be formed over the barrier layer. Exemplary p-type work function materials (may also be referred to as p-type work function metals) include TiN, TaN, Ru, Mo, Al, WN, ZrSi 2, MoSi 2, TaSi 2, NiSi 2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function materials (may also be referred to as n-type work function metals) include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. A work function value is associated with a material composition of the work function layer, and thus the work function layer is selected to adjust its work function value, such that a target threshold voltage V TH is achieved in the device to be formed. Next, a seed layer may be formed over the work function layer. The seed layer may be formed of tungsten, copper, or copper alloys, although other suitable materials may alternatively be used. Once the seed layer has been formed, the fill metal may be formed on the seed layer filling the openings 103 and the gaps 53. The fill metal may comprise tungsten, although other suitable materials such as aluminum, copper, tungsten nitride, ruthenium, silver, gold, rhodium, molybdenum, nickel, cobalt, cadmium, zinc, alloys thereof, combinations thereof, and the like may alternatively be utilized.FIGS. 15A and 15B illustrate NSFETs formed in a first device region (see, e.g., 210 in FIG. 16A ) of an n-type device region of the NSFET device 100. The n-type device region of the NSFET device 100 may include other regions, such as a second device region 230 and a receiving region 220, as illustrated in FIG. 16A. Further, processing steps similar to those illustrated above for forming the NSFETs of FIGS. 15A and 15B may be performed to form p-type NSFETs in a p-type device region of the NSFET device 100, as illustrated in FIG. 16B. In other words, FIGS. 16A and 16B illustrate the n-type device region and the p-type device region of the NSFET device 100, respectively. Details are discussed below.Referring now to FIG. 16A, which illustrates an n-type device region of the NSFET device 100, further including a first device region 210, a second device region 230, and a receiving region 220. In an embodiment, the NSFETs of FIGS. 15A and 15B are formed in the first device region 210, where the NSFETs have a channel length Lg 1 between, e.g., about 5 nm and about 30 nm, and a contacted poly pitch (CPP) in a range between, e.g., about 20 nm and about 70 nm. The CPP of the first device region 210 may be calculated as the sum of the channel length Lg 1 and a width SW 1 of the source / drain region 112 in the first device region 210. Due to the short channel length Lg 1, the first device region 210 may also be referred to as a short channel region. The second device region 230 corresponds to a device region having NSFETs with a channel length Lg2between, e.g., 30 nm and about 150 nm and a CPP greater than about 70 nm, where the CPP of the second device region 230 is calculated as the sum of Lg2and a width SW2of the source / drain region 112 in the second device region 230. The second device region 230 may also be referred to as a large channel region. In the illustrated embodiment, the width SW 2 of the source / drain region 112 in the second device region 230 is greater than the width SW 1 of the source / drain region 112 in the first device region 210.FIG. 16A further illustrates a receiving region 220, wherein the source / drain regions in the receiving region 220 are labeled as source / drain regions 113 to distinguish from the source / drain regions 112 in the first device region 210 and the second device region 230. In particular, the source / drain regions 112 in the first device region 210 and in the second device region 230 are doped with n-type dopant(s) to form the n-type NSFETs. In contrast, the source / drain regions 113 in the receiving region 220 are doped with p-type dopant(s) to form the receiving region 220. Note that the fins 90 in the first device region 210, the second device region 230, and the receiving region 220 are doped with p-type dopant(s) to form p-wells in the fins 90. In some embodiments, the fins 90 in the first device region 210, the second device region 230, and the receiving region 220 are the same fin. In other words, the first device region 210, the second device region 230, and the receiving region 220 are formed in the same fin 90. In further embodiments, the first device region 210, the second device region 230, and the receiving region 220 are formed in different fins 90 located in the n-type device region of the NSFET device 100.FIG. 16B illustrates the p-type device region of the NSFET device 100, which further includes a first device region 240, a second device region 260, and a receiving region 250. Note that to form p-type NSFETs in the p-type device region, the second semiconductor material 54 is selectively removed after the dummy gates 102 and the dummy gate dielectric 97 are removed, and the first semiconductor material 52 remains and forms nanostructures 52 suitable for forming p-type NSFETs, as illustrated in FIG. 16B. Further, the inner spacers 55 are formed by replacing end portions of the second semiconductor material 54. One skilled in the art will also recognize that the fins 90 in the p-type device region are doped with n-type dopant(s) to form n-wells. The source / drain regions in the first device region 240 and the second device region 260 are labeled as source / drain regions 113 to indicate that p-type dopant(s) are added to form the source / drain regions for p-type NSFETs, and the source / drain region in the receiving region 250 is labeled as source / drain regions 112 to indicate that n-type dopant(s) are added to form the receiving region.In some embodiments, the channel length Lg 3 and the width SW 3 of the first device region 240 of the p-type device region are the same or similar to Lg 1 and SW 1 of the first device region 210 of the n-type device region, respectively. Similarly, the channel length Lg 4 and the width SW 4 of the second device region 260 of the p-type device region 260 are the same or similar to Lg 2 and SW 2 of the second device region 230 of the n-type device region, respectively. In some embodiments, the fins 90 in the first device region 240, the second device region 260, and the receiving region 250 are the same fin. In other words, the first device region 240, the second device region 260, and the receiving region 250 are formed in the same fin 90. In further embodiments, the first device region 240, the second device region 260, and the receiving region 250 are formed in different fins 90 located in the p-type device region of the NSFET device 100.Note that in the illustrated embodiment of FIGS. 16A and 16B, the dielectric layer 107 is formed only under the source / drain regions 112 in the first device region 210 of the n-type device region. The dielectric layer 107 is not formed in the p-type device region (e.g., 240, 250, and 260), nor is the dielectric layer 107 formed in the second device region 230 or the n-type device region 220. In some embodiments, the source / drain regions 113 of the p-type device region of FIG. 16B must grow from the fin 90 to form high-quality epitaxial semiconductor material to effectively provide voltage at the channel regions of the NSFETs, while the source / drain regions 112 in the n-type device region of FIG. 16A are little or not affected in voltage. Thus, the dielectric layer 107 is not formed under the source / drain region 113 in the p-type device regions but is formed under the source / drain regions 112 in the first device region 210 of the n-type device region (e.g., a small channel region). Further, the second device region 230 (e.g., a larger channel region) of the n-type device region in FIG. 16A has a large CPP (e.g., a large source / drain width SW 2) and may require epitaxial growth from the fin 90 to form large volumes of epitaxial material than the source / drain regions 112. In other words, if the dielectric layer 107 was formed under the source / drain regions 112 of the second device region 230, the dielectric layer 107 would cover the bottoms of the openings 110 and prevent epitaxial growth from the fins 90, and epitaxial growth of the source / drain regions 112 from the sidewalls of the second semiconductor material 54 may not be sufficient (e.g., may not have a sufficiently large volume) to fill the source / drain openings 110. In addition, epitaxial growth in the source / drain openings 110 from the fin 90 may also be necessary to provide access to the stress of the substrate 50 in the receiving regions 220 and 250, and thus no dielectric layer 170 is formed at the bottoms of the openings 110 in the receiving regions (e.g., to prevent blocking access to the substrate stress). It should be appreciated that forming the dielectric layer 107 below the source / drain regions 112 of the n-type device region is sufficient to prevent or reduce well isolation leakage between the fin 90 including the device region 210 (e.g., a fin having a p-type well) and an adjacent fin 90 including the p-type device region (e.g., a fin having an n-type well).As will be readily understood by those skilled in the art, additional processing may be performed to complete fabrication of the NSFET device 100, therefore details may not be repeated herein. For example, a second ILD may be deposited over the ILD 114. Further, gate contacts and source / drain contacts may be formed that extend through the second ILD and / or the ILD 114 to electrically couple the gate electrode 122 and the source / drain regions 112 / 113. Further, interconnect structures including conductive features (e.g., vias, metal lines) formed in a plurality of dielectric layers may be formed over the second ILD to interconnect the electronic components (e.g., transistors) to form functional circuits.In addition to the embodiment disclosed above, other embodiments to form a dielectric layer under the source / drain regions 112 of the short channel region (e.g., 210) in the n-type device region are possible Additional embodiments (e.g., 100A, 100B, 100C) are discussed below. It should be noted that the additional embodiments (e.g., 100A, 100B, 100C) exclusively illustrate cross-sectional views of portions of the NSFET device in the first device region 210 (e.g., a short channel region in an n-type device region), and other device regions (e.g., 220, 230, 240, 250, 260) are the same or similar to those disclosed above, therefore details are not repeated.FIGS. 17, 18 and 19A-19C are cross-sectional views of a nanostructure field effect transistor (NSFET) device 100A at various fabrication stages, according to another embodiment. In some embodiments, the processing of FIG. 17 follows the processing of FIGS. 8A-8C.As illustrated in FIG. 17, after the inner spacers 55 in FIG. 8A are formed, a semiconductor material 141 (e.g., silicon) is formed in the openings 110 by, e.g., an epitaxial growth process. An upper surface 141U of the semiconductor material 141 is higher (e.g., further from the substrate 50) than a lowermost surface of the inner spacers 55 facing the substrate 50. In other words, the semiconductor material 141 contacts (e.g., physically contacts) sidewalls of the lowermost inner spacers 55, and extends continuously from a first lowermost inner spacer 55 (e.g., a lowermost inner spacer 55 below the dummy gate 102 on the left side of FIG. 17 ) to a laterally adjacent second lowermost inner spacer 55 (e.g., a lowermost inner spacer 55 below the dummy gate 102 on the right side of FIG. 17 ).Next, an implantation process 140 (e.g., an ion implantation process) is performed to treat the semiconductor material 141. The implantation process 140 may use a gas source comprising fluorine (F), germanium (Ge), oxygen (O) or argon (Ar) such that ion species of F, Ge, O or Ar are implanted into the semiconductor material 141. After the implantation process 140, as illustrated in FIG. 17, an upper layer of the semiconductor material 141 is converted into a treated layer 143 (e.g., semiconductor material 141 doped with ion species of F, Ge, O, or Ar) having physical properties (e.g., hardness, etch rate) different from the semiconductor material 141.Next, in FIG. 18, an oxidation process is performed to convert an upper layer of the treated layer 143 into a dielectric layer 145 (e.g., an oxide layer such as a silicon oxide layer). In an embodiment, a furnace oxidation process is performed using a gas source comprising hydrogen (H 2) and oxygen (O 2) to form the dielectric layer 145. It should be appreciated that due to the ion species doped (e.g., implanted) into the dielectric layer 145, the dielectric layer 145 has improved physical properties (e.g., harder and / or with a lower etch rate) to resist a subsequent etch process. In some embodiments, a thickness of the dielectric layer 145 is between about 1 nm and about 10 nm. The dielectric layer 145 serves the same or similar functions as the dielectric layer 107 of FIG. 16A. Note that the top surface 145U of the dielectric layer 145 is lower (e.g., closer to the substrate 50) than a lowermost surface of the second semiconductor material 54 facing the substrate 50, which allows the subsequently formed source / drain regions 112 to electrically connect to the second semiconductor material 54 (e.g., the channel regions of the NFFETs) without being blocked by the dielectric layer 145.In addition to converting the top layer of the treated layer 143 to the dielectric layer 145, the oxidation process may also oxidize other exposed materials (e.g., 54, 55). In preparation for epitaxially growing the source / drain regions 112 (see FIG. 19 ), in order to clean the openings 110, an etching process may be performed to remove the oxides (e.g., oxides of the second semiconductor material 54 and oxides of the inner spacers 55) from, e.g., the sidewalls of the openings 110. The dielectric layer 145 with its implanted ion species has a much lower etch rate for the etch process. Due to the etch selectivity provided by the implantation process, the etching process removes the oxides from the sidewalls of the openings 110 without substantially engaging the dielectric layer 145.Next, in FIGS. 19A-19C, source / drain regions 112 are formed in the openings 110 on the dielectric layer 145, the dummy gates 102 are removed, the first semiconductor material 52 is removed to form the nanostructures 54, and the metal gate structure (e.g., 120 and 122) is formed following the same or similar processing steps discussed above for the NSFET device 100, therefore details are not repeated.FIG. 19B illustrates the cross-sectional view of the NSFET device 100A along cross-section E-E' in FIG. 19A, and FIG. 19C illustrates the cross-sectional view along cross-section F-F' in FIG. 19A. As illustrated in FIG. 19B, the dielectric layer 145 physically separates and electrically isolates the source / drain regions 112 from the underlying fins 90 to prevent or reduce substrate leakage and / or well isolation leakage.FIGS. 20, 21, and 22A- 22C are cross-sectional views of a nanostructure field effect transistor (NSFET) device 100B at various fabrication stages, according to another embodiment. In some embodiments, the processing of FIG. 20 follows the processing of FIGS. 8A-8C.As illustrated in FIG. 20, after the inner spacers 55 in FIG. 8A are formed, a semiconductor material 151 such as silicon germanium is formed in the openings 110 by, for example, an epitaxial growth process. An upper surface 151U of the semiconductor material 151 is higher (e.g., further from the substrate 50) than a lowermost surface of the inner spacers 55 facing the substrate 50. In other words, the semiconductor material 151 contacts (e.g., physically contacts) sidewalls of the lowermost inner spacers 55, and extends continuously from a first lowermost inner spacer 55 (e.g., a lowermost inner spacer 55 below the dummy gate 102 on the left side of FIG. 20 ) to a laterally adjacent second lowermost inner spacer 55 (e.g., a lowermost inner spacer 55 below the dummy gate 102 on the right side of FIG. 20 ).Next, in FIG. 21, an oxidation process is performed to convert an upper layer of the semiconductor material 151 into a dielectric layer 153 (e.g., an oxide of silicon germanium or silicon germanium oxide). In an embodiment, a furnace oxidation process is performed using a gas source comprising hydrogen (H 2) and oxygen (O 2) to form the dielectric layer 153. In some embodiments, a thickness of the dielectric layer 153 is between about 1 nm and about 10 nm. Dielectric layer 153 serves the same or similar functions as dielectric layer 107 of FIG. 16A. In some embodiments, the oxidation process converts all of the semiconductor material 151 into the dielectric layer 153, and thus no semiconductor material 151 remains under the dielectric layer 153. Note that the implantation process 140 for the NSFET device 100A is not performed in this embodiment because the oxide of the semiconductor material 151 (e.g., SiGeO) is different from, e.g., the oxide of the second semiconductor material 54 (e.g., SiO), and thus already provides etch selectivity for the subsequent etch process to clean the openings 110. Note that the upper surface 153U of the dielectric layer 153 is lower (e.g., closer to the substrate 50) than a lowermost surface of the second semiconductor material 54 facing the substrate 50, allowing the subsequently formed source / drain regions 112 to electrically connect to the second semiconductor material 54 (e.g., the channel regions of the NFFETs) without being blocked by the dielectric layer 153.Next, in FIGS. 22A-22C, source / drain regions 112 are formed in the openings 110 on the dielectric layer 153, the dummy gates 102 are removed, the first semiconductor material 52 is removed to form the nanostructures 54, and the metal gate structure (e.g., 120 and 122) is formed following the same or similar processing steps as discussed above for the NSFET device 100, therefore details are not repeated.FIG. 22B illustrates the cross-sectional view of the NSFET device 100B along cross-section E-E' in FIG. 22A, and FIG. 22C illustrates the cross-sectional view along cross-section F-F' in FIG. 22A. As illustrated in FIG. 22B, the dielectric layer 153 physically separates and electrically isolates the source / drain regions 112 from the underlying fins 90 to prevent or reduce substrate leakage and / or well isolation leakage.FIGS. 23, 24 and 25A-25C are cross-sectional views of a nanostructure field effect transistor (NSFET) device 100C at various fabrication stages, in accordance with yet another embodiment not in accordance with the invention. In some embodiments, the processing of FIG. 23 follows the processing of FIGS. 7A-7C.As illustrated in FIG. 23, after the spacer film 55' is formed, a protective material 58 is formed on the spacer film 55' at the bottoms of the openings 110. The protective material 58 may be, for example, a photoresist material, a bottom anti-reflective coating (BARC), or the like. An upper surface 58U of the protective material 58 is higher (e.g., further from the substrate 50) than a lowermost surface of the inner spacers 55 facing the substrate 50. In other words, the protective material 58 contacts (e.g., physically contacts) sidewalls of the lowermost inner spacers 55.Next, in FIG. 24, a trimming process similar to the trimming process of FIG. 8A is performed to remove portions of the spacer film 55' disposed outside the side wall recesses 52R, such as portions along the side walls of the openings 110. Note that portions of the spacer film 58' disposed below the top surface 58U of the protective material 58 are shielded from the trimming process, therefore remain after the trimming process to form a dielectric layer 59. After the trimming process, the protective material 58 is removed by a suitable removal process such as ashing. In some embodiments, the shape of the dielectric layer 59 may be controlled, e.g., by varying the depth of the protective material 58 and / or the thickness of the spacer film 55'.As illustrated in FIG. 24, the dielectric layer 59 contacts (e.g., physically contacts) sidewalls of the lowermost inner spacers 55, and extends continuously from a first lowermost inner spacer 55 (e.g., a lowermost inner spacer 55 below the dummy gate 102 on the left side of FIG. 24 ) to a laterally adjacent second lowermost inner spacer 55 (e.g., a lowermost inner spacer 55 below the dummy gate 102 on the right side of FIG. 24 ). In some non-inventive embodiments, a thickness of the dielectric layer 59 is between about 1 nm and about 10 nm. In the example of FIG. 24, the dielectric layer 59 has a same material composition as the inner spacers 55 (e.g., SiN, SiCN, SiOCN). The dielectric layer 59 serves the same or similar functions as the dielectric layer 107 of FIG. 16A. Note that the top surface 59U of the dielectric layer 59 is lower (e.g., closer to the substrate 50) than a lowermost surface of the second semiconductor material 54 facing the substrate 50, allowing the subsequently formed source / drain regions 112 to electrically connect to the second semiconductor material 54 (e.g., the channel regions of the NFFETs) without being blocked by the dielectric layer 59.Next, in FIGS. 25A-25C, source / drain regions 112 are formed in the openings 110 on the dielectric layer 59, the dummy gates 102 are removed, the first semiconductor material 52 is removed to form the nanostructures 54, and the metal gate structure (e.g., 120 and 122) is formed following the same or similar processing steps discussed above for the NSFET device 100, therefore details are not repeated.FIG. 25B illustrates the cross-sectional view of the NSFET device 100C along cross-section E-E' in FIG. 25A, and FIG. 25C illustrates the cross-sectional view along cross-section F-F' in FIG. 25A. As illustrated in FIG. 25B, the dielectric layer 59 physically separates and electrically isolates the source / drain regions 112 from the underlying fins 90 to prevent or reduce substrate leakage and / or well isolation leakage.FIG. 26 illustrates a flow diagram of a method of fabricating a semiconductor device, in accordance with some embodiments. It should be understood that the embodiment method shown in FIG. 26 is merely an example of many possible embodiment methods. Many variations, alternatives and modifications will occur to those skilled in the art. For example, as illustrated in FIG. 26, various steps may be added, removed, replaced, rearranged, or repeated.Referring to FIG. 26, at block 1010, a fin structure is formed protruding above a substrate, the fin structure including a fin and a layer stack overlying the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material. At block 1020, a dummy gate structure is formed over the fin structure. At block 1030, openings are formed in the fin structure on opposite sides of the dummy gate structure, the openings extending into the fin through the layer stack. At block 1040, a dielectric layer is formed in bottom portions of the openings. At block 1050, source / drain regions are formed in the openings on the dielectric layer, the source / drain regions being separated from the fin by the dielectric layer.Embodiments may achieve advantages. For example, by forming the dielectric layer under the source / drain regions 112 of the short channel regions in the n-type device region, substrate leakage and well isolation leakage are reduced or prevented and device performance is improved. By not forming the dielectric layer under the source / drain regions 113 of the p-type device region, high quality epitaxial source / drain regions are grown on the fin to apply stress to the channel regions of the p-type NSFETs. Furthermore, by not forming the dielectric layer under the long channel region source / drain regions 112 in the n-type device region, large volumes of the epitaxial source / drain regions are grown on the fin to fill the source / drain openings. In addition, the dielectric layer is not formed in receiving regions in order to allow easy access to the substrate voltage. The embodiments disclosed herein achieve advantages (e.g., reducing substrate leakage and well isolation leakage) for NSFETs in short channel regions of the n-type device regions while avoiding problems that the dielectric layer may cause in other device regions.According to an embodiment, a method of forming a semiconductor device includes: forming a fin structure protruding above a substrate, the fin structure including a fin and a layer stack overlying the fin, the layer stack including alternating layers of a first semiconductor material and a second semiconductor material; forming a dummy gate structure over the fin structure; forming openings in the fin structure on opposite sides of the dummy gate structure, the openings extending through the layer stack into the fin; forming a dielectric layer in bottom portions of the openings; and forming source / drain regions in the openings on the dielectric layer, the source / drain regions being separated from the fin by the dielectric layer. In one embodiment, a bottom surface of the source / drain regions facing the substrate contacts and extends along a top surface of the dielectric layer that faces away from the substrate. In an embodiment, the first semiconductor material in the layer stack contacts the fin, wherein a top surface of the dielectric layer is closer to the substrate than a bottom surface of the second semiconductor material facing the substrate. In an embodiment, forming the dielectric layer includes: lining sidewalls and bottoms of the openings with a dielectric material; performing an implantation process to treat the dielectric material; and performing an etching process after the implantation process to remove sidewall portions of the dielectric material, wherein after the etching process, bottom portions of the dielectric material remain and form the dielectric layer. In an embodiment, after the implantation process, a first concentration of an ion species in the bottom portions of the dielectric material is higher than a second concentration of the ion species in the sidewall portions of the dielectric material. In an embodiment, forming the dielectric layer includes: epitaxially growing a semiconductor material in the bottom portions of the openings; and performing an oxidation process to convert an upper layer of the semiconductor material into an oxide of the semiconductor material, wherein the oxide of the semiconductor material forms the dielectric layer. In an embodiment, after epitaxially growing the semiconductor material and before performing the oxidation process, the method further includes performing an implantation process to treat the semiconductor material. In an embodiment, after forming the source / drain regions, the method further includes: forming an interlayer dielectric (ILD) layer over the source / drain regions around the dummy gate structure; removing the dummy gate structure to expose the first semiconductor material and the second semiconductor material under the dummy gate structure; and performing an etching process to selectively remove the exposed first semiconductor material, wherein after the etching process, the exposed second semiconductor material forms nanostructures. In one embodiment, the nanostructures are nanowires or nanosheets. In an embodiment, after the nanostructures are formed, the method further includes: forming a gate dielectric material around the nanostructures; and forming a conductive material around the gate dielectric material.According to an embodiment, a method of forming a semiconductor device includes: forming a first gate structure and a second gate structure over a first fin structure, the first fin structure comprising a fin protruding above a substrate and comprising a layer stack over the fin, the layer stack comprising alternating layers of a first semiconductor material and a second semiconductor material; forming a first opening in the first fin structure between the first gate structure and the second gate structure, the first opening extending through the layer stack into the fin; replacing end portions of the first semiconductor material exposed by the first opening with inner spacers; forming a dielectric layer along a bottom of the first opening, the dielectric layer continuously extending from a first inner spacer under the first gate structure to a second inner spacer under the second gate structure; and forming a first source / drain region in the first opening on the dielectric layer. In an embodiment, the first inner spacer is a first lowermost inner spacer below the first gate structure and the second inner spacer is a second lowermost inner spacer below the second gate structure. In an embodiment, after forming the dielectric layer, sidewalls of the second semiconductor material opposing the first opening are free of the dielectric layer. In an embodiment, the first fin structure is in an n-type device region of the semiconductor device, the first gate structure, the second gate structure, the first opening, and the first source / drain region being formed in a first region of the n-type device region, the first source / drain region comprising an n-type dopant, the method further comprising: forming a third gate structure and a fourth gate structure over the first fin structure in a second region of the n-type device region; forming a second opening in the first fin structure between the third gate structure and the fourth gate structure, the second opening extending through the layer stack into the fin; forming a second source / drain region in the second opening, the second source / drain region comprising p-type dopant and physically contacting the fin. In an embodiment, the first fin structure is in an n-type device region of the semiconductor device, the first source / drain region comprising an n-type dopant, the method further comprising: forming a third gate structure and a fourth gate structure over a second fin structure, the second fin structure being in a p-type device region of the semiconductor device, the second fin structure comprising a second fin protruding above the substrate and comprising the layer stack over the second fin; forming a second opening in the second fin structure between the third gate structure and the fourth gate structure, the second opening extending through the layer stack into the second fin; and forming a second source / drain region in the second opening, the second source / drain region comprising a p-type dopant and physically contacting the second fin.According to an embodiment, a semiconductor device includes: a fin protruding above a substrate; a gate structure above the fin; source / drain regions above the fin on opposite sides of the gate structure, the source / drain regions extending into the fin; a dielectric layer below the source / drain regions, the dielectric layer being disposed between and separating the source / drain region and the fin; and channel layers below the gate structure and between the source / drain regions, the channel layers being parallel to each other, opposite ends of each of the channel layers contacting the source / drain regions. In one embodiment, a bottom surface of the source / drain regions facing the substrate contacts and extends along a top surface of the dielectric layer that faces away from the substrate. In an embodiment, the upper surface of the dielectric layer is closer to the substrate than a lowermost surface of the channel layers facing the substrate.

Claims

A method of forming a semiconductor device, the method comprising: forming a fin structure (91) protruding above a substrate (50), the fin structure (91) comprising a fin (90) and a layer stack (92) overlying the fin (90), the layer stack (92) comprising alternating layers of a first semiconductor material (52) and a second semiconductor material (54); forming a dummy gate structure (97, 102) over the fin structure (91); forming openings (110) in the fin structure (91) on opposite sides of the dummy gate structure (97, 102), the openings (110) extending through the layer stack (92) into the fin (90); forming a dielectric layer (107, 59) in bottom portions of the openings (110); and forming source / drain regions (112) in the openings (110) on the dielectric layer (107, 59), the source / drain regions (112) being separated from the fins (90) by the dielectric layer (107, 59), wherein forming the dielectric layer (107, 59) comprises: lining sidewalls and bottoms of the openings (110) with a dielectric material (107'); performing an implantation process to treat the dielectric material (107'); and after the implantation process, performing an etching process to remove sidewall portions of the dielectric material (107'), wherein after the etching process, bottom portions of the dielectric material (107') remain and form the dielectric layer (107).The method of claim 1, wherein after the implantation process, a first concentration of an ion species in the bottom portions of the dielectric material (107') is higher than a second concentration of the ion species in the sidewall portions of the dielectric material (107').A method of forming a semiconductor device, the method comprising: forming a fin structure (91) protruding above a substrate (50), the fin structure (91) comprising a fin (90) and a layer stack (92) overlying the fin (90), the layer stack (92) comprising alternating layers of a first semiconductor material (52) and a second semiconductor material (54); forming a dummy gate structure (97, 102) over the fin structure (91); forming openings (110) in the fin structure (91) on opposite sides of the dummy gate structure (97, 102), the openings (110) extending through the layer stack (92) into the fin (90); forming a dielectric layer (145) in bottom portions of the openings (110); and forming source / drain regions (112) in the openings (110) on the dielectric layer (145), the source / drain regions (112) being separated from the fins (90) by the dielectric layer (145), wherein forming the dielectric layer (145) comprises: epitaxially growing a semiconductor material (141) in the bottom portions of the openings (110); and performing an oxidation process to convert an upper layer of the semiconductor material (141) into an oxide of the semiconductor material (141), the oxide of the semiconductor material (141) forming the dielectric layer (145).The method of claim 3, further comprising, after epitaxially growing the semiconductor material (141) and before performing the oxidation process: performing an implantation process to treat the semiconductor material (141).The method of any of the preceding claims 1 to 4, wherein a bottom surface of the source / drain regions (112) facing the substrate (50) contacts and extends along a top surface of the dielectric layer (107, 145, 59) facing away from the substrate (50).The method of any of the preceding claims 1 to 5, wherein the first semiconductor material (52) in the layer stack (92) contacts the fin (90), wherein the upper surface of the dielectric layer (107, 145, 59) is closer to the substrate (50) than a lowermost surface of the second semiconductor material (54) facing the substrate (50).The method of any of the preceding claims 1 to 6, further comprising, after forming the source / drain regions (112): forming an interlayer dielectric, hereinafter referred to as ILD, over the source / drain regions (112) around the dummy gate structure (97, 102); removing the dummy gate structure (97, 102) to expose the first semiconductor material (52) and the second semiconductor material (54) under the dummy gate structure (97, 102); and performing an etching process to selectively remove the exposed first semiconductor material (52), wherein after the etching process the exposed second semiconductor material (54) form nanostructures.The method of claim 7, wherein the nanostructures are nanowires or nanosheets.The method of claim 7 or 8, further comprising, after the nanostructures are formed: forming a gate dielectric material (120) around the nanostructures; and forming an electrically conductive material (122) around the gate dielectric material (120).A method of forming a semiconductor device, the method comprising: forming a first gate structure and a second gate structure over a first fin structure (91), the first fin structure (91) comprising a fin (90) protruding above a substrate (50) and comprising a layer stack (92) over the fin (90), the layer stack (92) comprising alternating layers of a first semiconductor material (52) and a second semiconductor material (54); forming a first opening (110) in the first fin structure (91) between the first gate structure and the second gate structure, the first opening (110) extending through the layer stack (92) into the fin (90); replacing end portions of the first semiconductor material (52) exposed by the first opening (110) with inner spacers (55); forming a dielectric layer (107, 145, 59) along a bottom of the first opening (110), the dielectric layer (107, 145, 59) extending continuously from a first inner spacer (55) below the first gate structure to a second inner spacer (55) below the second gate structure; and forming a first source / drain region (112) in the first opening (110) on the dielectric layer (107, 145, 59), the dielectric layer (107, 145, 59) being doped with either ion species of oxygen, germanium or a combination thereof or ion species of fluorine, germanium, oxygen or argon.The method of claim 10, wherein the first inner spacer (55) is a first lowermost inner spacer below the first gate structure and the second inner spacer (55) is a second lowermost inner spacer below the second gate structure.The method of claim 11, wherein after forming the dielectric layer (107, 145, 59), sidewalls of the second semiconductor material (54) facing the first opening (110) are free of the dielectric layer (107, 145, 59).The method of any of the preceding claims 10 to 12, wherein the first fin structure (91) is in an n-type device region of the semiconductor device, the first gate structure, the second gate structure, the first opening (110), and the first source / drain region (112) being formed in a first region of the n-type device region, the first source / drain region (112) comprising an n-type dopant, the method further comprising: forming a third gate structure and a fourth gate structure over the first fin structure (91) in a second region of the n-type device region; forming a second opening in the first fin structure (91) between the third gate structure and the fourth gate structure, the second opening extending through the layer stack (92) into the fin (90); and forming a second source / drain region in the second opening, the second source / drain region comprising a p-type dopant and physically contacting the fin (90).The method of any of the preceding claims 10 to 13, wherein the first fin structure (91) is in an n-type device region of the semiconductor device, the first source / drain region (112) comprising an n-type dopant, the method further comprising: forming a third gate structure and a fourth gate structure over a second fin structure, the second fin structure being in a p-type device region of the semiconductor device, the second fin structure comprising a second fin protruding above the substrate (50) and comprising the layer stack (92) over the second fin; forming a second opening in the second fin structure between the third gate structure and the fourth gate structure, the second opening extending through the layer stack (92) into the second fin; and forming a second source / drain region in the second opening, the second source / drain region comprising a p-type dopant and physically contacting the second fin.A semiconductor device comprising: a fin (90) protruding above a substrate (50); a gate structure (120, 122) over the fin (90); source / drain regions (112) over the fin (90) on opposite sides of the gate structure (120, 122), the source / drain regions (112) extending into the fin (90); a dielectric layer (107, 145, 59) under the source / drain regions (112), the dielectric layer (107, 145, 59) being disposed between and separating the source / drain region (112) and the fin (90); and channel layers (54, 93) under the gate structure (120, 122) and between the source / drain regions (112), the channel layers (54, 93) being parallel to each other, opposite ends of each of the channel layers (54, 93) contacting the source / drain regions (112), the dielectric layer (107, 145, 59) being doped with either ion species of oxygen, germanium or a combination thereof or ion species of fluorine, germanium, oxygen or argon.The semiconductor device of claim 15, wherein a bottom surface of the source / drain regions (112) facing the substrate (50) contacts a top surface of the dielectric layer (107, 145, 59) facing away from and extending along the substrate (50).The semiconductor device according to claim 16, wherein the upper surface of the dielectric layer (107, 145, 59) is closer to the substrate (50) than a lowermost surface of the channel layers (54, 93) facing the substrate (50).

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