semiconductor device

Abstract

Semiconductor device comprising: - a circuit board (16, 36, 56, 66, 76) having a first circuit structure (16B, 36B, 36H, 36G, 36J) and a second circuit structure (16E, 36D); and - a semiconductor element (18) arranged on an upper surface of the first circuit structure (16B, 36B, 36H, 36G, 36J), wherein: - in the semiconductor element (18) - a drain electrode (18A) is arranged on its upper surface and - a gate electrode (18B) and a source electrode (18C) are arranged on its lower surface, - the gate electrode (18B) and the source electrode (18C) are bonded to the upper surface of the first circuit structure (16B, 36B, 36H, 36G, 36J) via a first bonding material (14B), - the drain electrode (18A) is bonded to an upper surface of the second circuit structure (16E, 36D) via a metal component (20, 110) connected to the upper surface of the semiconductor element (18), - the printed circuit board (36, 56, 66, 76) comprises: - an insulating substrate (36A), - a wiring layer (36B, 36G, 36J) formed on an upper surface of the insulating substrate (36A), and - an insulating layer (36C) partially disposed on an upper surface of the wiring layer (36B, 36G, 36J), - the first circuit structure (36B, 36H, 36G, 36J) is part of the wiring layers (36B, 36G, 36J) which are exposed at a plurality of locations without being covered by the insulating layers (36C), and - the second circuit structure (36D) is arranged on an upper surface of the insulating layer (36C).

Description

Field of the invention

[0001] The technique disclosed in the specification of the present application relates to a semiconductor device. Description of the background technology

[0002] In a conventional semiconductor device, for example, a drain electrode of a semiconductor element is bonded to a circuit pattern on the upper surface of an insulating substrate with solder or the like, and a source electrode and a gate electrode of the semiconductor element are connected to a metal terminal or the like via a metal wire made of Al or Cu or the like.

[0003] Meanwhile, in order to reduce manufacturing costs, a reduction in the size of a semiconductor element is underway, and the areas to which the metal wires of the gate electrode and the source electrode are to be bonded are becoming smaller.

[0004] As the bonding areas of the gate electrode and source electrode metal wires decrease, the number of metal wires to be connected to the source electrode decreases, so the amount of heat generated by each metal wire increases. Consequently, in many cases, the temperature of the semiconductor element rises due to heat transfer from the metal wire.

[0005] For example, the technique disclosed in Japanese Patent Application Laid-Open No. JP 2017-123358 A is a technique to cope with such a problem, in which the heat radiation efficiency is improved in a lateral semiconductor element such as a GaN high electron mobility transistor (HEMT). SUMMARY

[0006] However, the technique disclosed in Japanese Patent Application Laid-Open No. 2017-123358 A relates to a lateral semiconductor element in which a source electrode and a drain electrode are arranged in a direction parallel to a substrate, which has posed a problem that the technique is not applicable to other semiconductor elements such as a vertical semiconductor element in which a source electrode and a drain electrode are arranged in a direction perpendicular to a substrate.

[0007] JP 2014-170799 A relates to a semiconductor device capable of reducing wire-induced current limitation, an increase in on-resistance, and an increase in inductance even when a semiconductor chip is miniaturized. This semiconductor device includes a substrate having a main surface on which first, second, and third wiring patterns are formed, and a vertical transistor chip having a gate electrode and a source electrode on one surface and a drain electrode on a back surface. The transistor chip is mounted on the first and second wiring patterns of the substrate so as to face the main surface of the substrate, and therefore, the gate electrode and the source electrode are connected to the first and second wiring patterns, respectively, and the drain electrode of the transistor chip is connected to the third wiring pattern of the substrate via a wire.

[0008] JP 2013-073945 A discloses an electrode terminal with a wiring view enabling the assembly of a small switching element without using wire bonding, a wiring structure, a semiconductor device, and a manufacturing method for the semiconductor device. A switching element is disposed in an electrode terminal with a wiring layer, in which a source electrode and a gate electrode are formed on a first main surface. The electrode terminal with the wiring layer includes a first conductor connected to a source electrode, a wiring layer in which a gate terminal connected to the gate electrode and a connecting part are provided, and a third electrode terminal connected to the connecting part. The wiring layer is connected to a first electrode terminal to be integrated therewith.

[0009] JP 2019-080016 A discloses means for efficiently transferring heat generated by a heat-generating component mounted on a circuit board that is sealed and housed in a case. In a circuit board housing case, a heat-generating component is soldered to a surface of a circuit board that is sealed and clamped by a storage portion of a metal base member and a clamping pressure portion of a resin cover member. A heat transfer layer is connected to a front-side heat transfer layer and a back-side heat transfer layer through plated layers of a plurality of through-holes.The heat transfer layer, on both surfaces of which a thin film insulating layer is applied, with a graphite layer of high thermal conductivity as an intermediate layer, is pressed to the storage section via the circuit board to transfer heat to the base member, and heat dissipation is also carried out from a back side of the heat transfer layer to a bottom side of the base member.

[0010] A technique disclosed in the present specification is a technique for suppressing a temperature rise of a semiconductor element due to heat generation of a metal wire or the like.

[0011] The object underlying the invention is achieved in a semiconductor device according to the invention with the features of claim 1. Advantageous further developments are the subject of the respective dependent claims.

[0012] A first aspect of the technique related to the semiconductor element disclosed in the present specification includes a circuit board having a first circuit pattern and a second circuit pattern, and a semiconductor element disposed on an upper surface of the first circuit pattern, wherein, in the semiconductor element, a drain electrode is disposed on the upper surface thereof and a gate electrode and a source electrode are disposed on the lower surface thereof, the gate electrode and the source electrode are bonded to the upper surface of the first circuit pattern via a first bonding material, and the drain electrode is bonded to an upper surface of the second circuit pattern via a metal member bonded to the upper surface of the semiconductor element.The circuit board includes an insulating substrate, a wiring layer formed on an upper surface of the insulating substrate, and an insulating layer partially disposed on an upper surface of the wiring layer. The first circuit pattern is part of the wiring layers exposed at a plurality of locations without being covered by the insulating layers. The second circuit pattern is disposed on an upper surface of the insulating layer.

[0013] According to the first aspect of the technique disclosed in the present specification, the temperature rise of the semiconductor element is suppressed.

[0014] These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present specification or patent application when taken in conjunction with the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device for explaining the background art of the present invention according to Embodiment 1; Fig. 2 is a cross-sectional view schematically illustrating a modification example of a configuration of the semiconductor device according to Embodiment 1 of the present invention; Fig. 3 is a cross-sectional view schematically illustrating a structural example for explaining the technical background of the present invention, in which a metal wire is connected to a gate electrode and a source electrode, respectively; Fig. 4 is a plan view schematically illustrating a structural example for explaining the technical background of the present invention when the metal wire is connected to the gate electrode and the source electrode, respectively; Fig. 5 is a plan view schematically illustrating a configuration example of the semiconductor device according to Embodiment 1 of the present invention; Fig. 6 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to Embodiment 2 of the present invention; Fig. 7 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to Embodiment 3 of the present invention; Fig. 8 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to an embodiment 4 of the present invention; and Fig. 9 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to Embodiment 5 of the present invention. DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0015] Hereinafter, embodiments of the invention and their technical background will be described with reference to the accompanying drawings. Although detailed features and the like are also described in the following embodiments for the purpose of explaining the technique, the features are examples, and not all of them are necessary essential features for realizing the embodiments.

[0016] It should be noted that the drawings are schematically illustrated, and therefore, the configuration is appropriately omitted or simplified to facilitate description. The interrelationship between sizes and positions in configurations and the like illustrated in the respective drawings are also not necessarily described precisely and may be changed as necessary. Furthermore, hatching may be indicated in the drawings, such as plan views other than cross-sectional views, to facilitate understanding of the contents of the embodiments.

[0017] Furthermore, in the following description, the same components are designated by the same reference numerals, and their names and functions are also similar. Accordingly, detailed descriptions of these components are omitted to avoid redundancy.

[0018] If the following description also describes that a particular component is “provided with”, “contains” or “has”, this does not, unless otherwise stated, imply that the presence of other components is excluded.

[0019] In the following description, even though ordinal numbers such as "first" and "second" may be used, these terms are used to facilitate understanding of the contents of embodiments and are not used to define the order determined by such ordinal numbers.

[0020] In addition, in the following description, even if terms indicating specific positions or directions such as "upper", "lower", "left", "right", "side", "bottom", "front" and "rear" may be used, these terms are for promoting understanding of the contents of embodiments and do not refer to the positions or directions at the time of implementation.

[0021] Furthermore, in the description described below, when "the upper surface of..." or "the lower surface of..." is described, the description includes such a state in which other components are formed on the upper surface or the lower surface of a component in question in addition to the upper surface itself or the lower surface itself of the component in question. That is, for example, when the description is made as "the component B arranged on the upper surface of the component A," the description does not exclude the interposition of another component C between the component A and the component B. <Ausführungsform 1>

[0022] Hereinafter, a semiconductor device according to Embodiment 1 will be described.

[0023] Furthermore, in the following description, the expression “A and B are electrically connected” indicates that a current can flow in either direction between configuration A and configuration B. <Konfiguration einer Halbleitervorrichtung>

[0024] Fig. 1 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device for explaining the background art of the present invention according to Embodiment 1.

[0025] When the Fig. 1 for explaining the technical background of the present invention, the semiconductor device comprises at least a circuit board 16 and a semiconductor element 18 bonded to the upper surface of the circuit board 16 via a conductive bonding material 14B.

[0026] Here, the circuit board 16 includes an insulating substrate 16A, a circuit pattern 16B and a circuit pattern 16E formed on the upper surface of the insulating substrate 16A, and a circuit pattern 16C formed on the lower surface of the insulating substrate 16A.

[0027] Further, a semiconductor element 18 is a field-effect transistor including a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), an insulated-gate bipolar transistor (IGBT), a high electron mobility transistor (HEMT), or the like. The semiconductor element 18 has a drain electrode 18A disposed on the upper surface and a gate electrode 18B disposed on the lower surface, which is connected to the circuit pattern 16B via the bonding material 14B, and a source electrode 18C disposed on the lower surface, which is connected to the circuit pattern 16B via the bonding material 14B. Further, the semiconductor element 18 is made of, for example, Si.When an IGBT is used as the semiconductor element 18, the source electrode in the above description is replaced by an emitter electrode of the IGBT, and the drain electrode in the above description is replaced by a collector electrode of the IGBT.

[0028] Furthermore, the semiconductor device may further include a base plate 12 bonded to the lower surface of the circuit board 16 via the conductive bonding material 14A, a metal wire 20 connecting the drain electrode 18A and the circuit pattern 16E, a metal terminal 24 further connected to the circuit pattern 16E via the metal wire 20, a case 26 accommodating these components, and a sealing material 22 such as gel or epoxy resin filled in the case 26. The lower surface of the base plate 12 is exposed to the outside below the case 26.

[0029] The drain electrode 18A is formed on the upper surface of the semiconductor element 18, to which the metal wire 20 is connected. With this configuration, an area where the metal wire is bonded is made larger than in a case where the metal wire 20 is connected to the surface on which the gate electrode 18B and the source electrode 18C are formed, which is the upper surface.

[0030] Accordingly, the number of metal wires 20 to be wired on the surface increases; therefore, the amount of heat generated by each metal wire 20 is suppressed. Furthermore, the degree of freedom regarding the wiring position of the metal wires 20 is increased. As a result, even if the outer diameter of the semiconductor element 18 is reduced, the temperature rise of the semiconductor element 18 due to the heat of the metal wires 20 is suppressed.

[0031] The source electrode 18C is further connected to the circuit pattern 16B via the bonding material 14B; therefore, the temperature rise of the semiconductor element 18 is suppressed more than in the case where the source electrode 18C is connected by the metal wire 20.

[0032] Fig. 2 is a cross-sectional view schematically illustrating a modification example of a configuration of an apparatus according to Embodiment 1 of the present invention.

[0033] When the Fig. 2, the semiconductor device according to the invention comprises at least one circuit board 36 and a semiconductor element 18 bonded to the upper surface of the circuit board 36 via a conductive bonding material 14B.

[0034] Here, the circuit board 36 includes an insulating substrate 36A, a wiring layer 36B formed on the upper surface of the insulating substrate 36A, an insulating layer 36C partially formed on the upper layer of the wiring layer 36B, a circuit pattern 36D formed on the upper layer of the insulating layer 36C, and a circuit pattern 36E formed on the lower layer of the insulating substrate 36A. The wiring layer 36B and the circuit pattern 36D are electrically connected via an interconnection layer 36F.

[0035] The semiconductor element 18 includes the drain electrode 18A arranged on the upper surface, the gate electrode 18B connected to the wiring layer 36B (i.e., the circuit pattern on the upper surface of the circuit board 36) exposed from the insulating layer 36C via the bonding material 14B, and the source electrode 18C connected to the wiring layer 36B (i.e., the circuit pattern on the upper surface of the circuit board 36) exposed from the insulating layer 36C via the bonding material 14B.

[0036] Furthermore, the semiconductor device may further include a base plate 12 bonded to the lower surface of the circuit board 36 via the conductive bonding material 14A, a metal wire 20 connecting the drain electrode 18A and the circuit pattern 36D, a metal terminal 24 further connected to the metal wire 20 and the circuit pattern 36D, a housing 26, and a sealing material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

[0037] Here, the comparison is made between the structure in which a metal wire is connected to each of the gate electrode 18B and the source electrode 18C and the semiconductor device according to Embodiment 1.

[0038] Fig. 3 is a cross-sectional view schematically illustrating a structural example for explaining the technical background of the present invention, in which a metal wire is connected to a gate electrode and a source electrode, respectively.

[0039] When the Fig. 3 for explaining the technical background of the present invention, the semiconductor device comprises at least one circuit board 46 and a semiconductor element 18 bonded to the upper surface of the circuit board 46 via a conductive bonding material 14B.

[0040] Here, the circuit board 46 includes an insulating substrate 16A, a circuit pattern 16D formed on the upper surface of the insulating substrate 16A, and a circuit pattern 16C formed on the lower surface of the insulating substrate 16A.

[0041] Furthermore, the semiconductor element 18 includes the drain electrode 18A, which is connected to the circuit structure 16D via the bonding material 14B, the gate electrode 18B and the source electrode 18C.

[0042] Furthermore, the semiconductor device may further include a base plate 12 bonded to the lower surface of the circuit board 46 via the conductive bonding material 14A, a metal wire 20B connecting a gate electrode 18B and a circuit pattern 16D, a metal wire 20A connecting a source electrode 18C and a circuit pattern 16D, a metal terminal 24 further connected to the metal wire 20A or the metal wire 20B and the circuit pattern 16D, a case 26 accommodating these components, and a sealing material 22 such as gel or epoxy resin filled in the case 26. The lower surface of the base plate 12 is exposed to the outside below the case 26.

[0043] Fig. 4 is a plan view schematically illustrating a structural example for explaining the technical background of the present invention, in which a metal wire is connected to each of the gate electrode 18B and the source electrode 18C.

[0044] As in Fig. As illustrated in FIG. 4, the metal wire 20B connected to the gate electrode 18B and the metal wire 20A connected to the source electrode 18C are each laid as wiring for controlling a plurality of semiconductor elements 18. This increases the area required for bonding the wiring. Furthermore, the degree of freedom of the wiring is reduced.

[0045] Fig. 5 is a plan view schematically illustrating a configuration example of the semiconductor device according to Embodiment 1 of the present invention.

[0046] As in Fig. 5, the metal wire 20 connected to the drain electrode 18B is laid as wiring for controlling a plurality of semiconductor elements 18. On the other hand, the wiring layer 36B connected to the gate electrode 18B and the source electrode 18C serves as wiring for controlling a plurality of semiconductor elements 18 in the layer structure of the circuit board 36.

[0047] Therefore, in the Fig. 5, the reduction in the amount of wiring to be laid, which serves as the metal wire 20 for connection, is ensured. Therefore, even if the outer diameter of the semiconductor element 18 is reduced and a large number of semiconductor elements 18 are arranged in parallel, appropriate wiring can be performed with a high degree of freedom without increasing the outer diameter of the semiconductor device. As a result, the downsizing of the semiconductor device is realized. <Ausführungsform 2>

[0048] A semiconductor device according to an embodiment 2 of the present invention will be described. In the following description, components similar to those described in the above embodiment are illustrated by the same reference numerals, and detailed descriptions thereof will be omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0049] Fig. 6 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to Embodiment 2 of the present invention.

[0050] When the Fig. 6, the semiconductor device according to the invention comprises at least one circuit board 56 and a semiconductor element 18 bonded to the upper surface of the circuit board 56 via a conductive bonding material 14B.

[0051] Here, the circuit board 56 includes an insulating substrate 36A, a wiring layer 36G formed on the upper layer of the insulating substrate 36A, an insulating layer 36C partially formed on the upper layer of the wiring layer 36G, a circuit pattern 36D formed on the upper layer of the insulating layer 36C, and a circuit pattern 36E formed on the lower layer of the insulating substrate 36A. The wiring layer 36G includes a through-hole plating layer 36H, which is a plating layer formed on the inner wall of a through-hole at a position where a gate electrode 18B and a source electrode 18C are bonded to the wiring layer 36G via the bonding material 14B. The wiring layer 36G and the circuit structure 36D are electrically connected via a connection layer 36F.Further, the plating layer 36H of a through-hole may be disposed at a portion where the wiring layer 36G is bonded to the gate electrode 18B or a portion where the wiring layer 36G is bonded to the source electrode 18C.

[0052] The semiconductor element 18 includes a drain electrode 18A, the gate electrode 18B connected via the bonding material 14B to the plating layer 36H of a through-hole exposed from the insulating layer 36C and further to the wiring layer 36G, and the source electrode 18C connected via the bonding material 14B to the plating layer 36H of a through-hole exposed from the insulating layer 36C and further to the wiring layer 36G.

[0053] Furthermore, the semiconductor device may further include a base plate 12 bonded to the lower surface of the circuit board 56 via a conductive bonding material 14A, a metal wire 20 connecting the drain electrode 18A and the circuit pattern 36D, a metal terminal 24 further connected to the metal wire 20 and the circuit pattern 36D, a housing 26, and a sealing material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

[0054] In Fig. 6, each of the gate electrode 18B and the source electrode 18C is connected to the through-hole plating layer 36H and further to the wiring layer 36G via the bonding material 14B. Therefore, when the semiconductor element 18 and the circuit board 56 are bonded, the bonding material 14B penetrates into the through-hole of the through-hole plating layer 36H. Therefore, the bonding area between the bonding material 14B and the through-hole plating layer 36H increases, making it possible to stabilize the bonding process. Furthermore, suppression of heat generation in the wiring of the semiconductor element 18 is ensured; therefore, the reliability of the semiconductor element is improved. <Ausführungsform 3>

[0055] A semiconductor device according to an embodiment 3 of the present invention will be described. In the following description, components similar to those described in the above embodiments will be illustrated with the same reference numerals, and detailed descriptions thereof will be omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0056] Fig. 7 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to Embodiment 3 of the present invention.

[0057] When the Fig. In the example illustrated in Fig. 7, the semiconductor device according to the invention comprises at least one circuit board 66 and a semiconductor element 18 bonded to the upper surface of the circuit board 66 via a conductive bonding material 14B.

[0058] Here, the circuit board 66 includes an insulating substrate 36A, a wiring layer 36G formed on the upper layer of the insulating substrate 36A, an insulating layer 36C partially formed on the upper layer of the wiring layer 36G, and a circuit pattern 36D formed on the upper layer of the insulating layer 36C. The wiring layer 36G has a through-hole plating layer 36H disposed at a position where a gate electrode 18B and a source electrode 18C are bonded to the wiring layer 36G via the bonding material 14B. The wiring layer 36G and the circuit pattern 36D are electrically connected via an interconnection layer 36F.

[0059] The semiconductor element 18 includes a drain electrode 18A, the gate electrode 18B connected via the bonding material 14B to the plating layer 36H of a through-hole exposed from the insulating layer 36C and further to the wiring layer 36G, and the source electrode 18C connected via the bonding material 14B to the plating layer 36H of a through-hole exposed from the insulating layer 36C and further to the wiring layer 36G.

[0060] Furthermore, the semiconductor device may further include a base plate 12 bonded to the lower surface of a circuit board 66 via a heat dissipation film 100, a metal wire 20 connecting the drain electrode 18A and the circuit pattern 36D, a metal terminal 24 further connected to the metal wire 20 and the circuit pattern 36D, a housing 26, and a sealing material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

[0061] The dissipation film 100 includes a polyethylene terephthalate (PET) film 102A adhered to the lower side of the insulating substrate 36A via an acrylic adhesive 101A, a graphite film 103 disposed on the lower surface of the PET film 102A, a PET film 102B disposed on the lower surface of the graphite film 103, and an acrylic adhesive 101B adhered to the lower surface of the PET film 102B. The base plate 12 adheres to the lower surface of the acrylic adhesive 101B.

[0062] According to the Fig. According to the inventive structure illustrated in FIG. 7, the heat dissipation property of the semiconductor element 18 is improved. Therefore, even if the outer diameter of the semiconductor element 18 is reduced, deterioration of the heat dissipation property of the semiconductor element 18 is suppressed by dissipating the heat generated in the semiconductor element 18 through the graphite foil 103. <Ausführungsform 4>

[0063] A semiconductor device according to an embodiment 4 of the present invention will be described. In the following description, components similar to those described in the above embodiments will be illustrated with the same reference numerals, and detailed descriptions thereof will be omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0064] Fig. 8 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to Embodiment 4 of the present invention.

[0065] When the Fig. In the example illustrated in Figure 8, the semiconductor device according to the invention comprises at least one circuit board 66 and one semiconductor element 18.

[0066] Furthermore, the semiconductor device may include a base plate 12 bonded to the lower surface of the circuit board 66 via a heat dissipation film 100, a metal block 110 connecting a drain electrode 18A and a circuit pattern 36D via a bonding material 14C, a metal terminal 24 connected to the circuit pattern 36D with a metal wire 20, a housing 26, and a sealing material 22. The lower surface of the base plate 12 is exposed to the outside below the housing 26.

[0067] The dissipation film 100 includes an acrylic adhesive 101A, a PET film 102A, a graphite film 103, a PET film 102B, and an acrylic adhesive 101B. The base plate 12 adheres to the lower surface of the acrylic adhesive 101B.

[0068] According to the Fig. In the structure illustrated in Figure 8, the metal block 110 connected to the drain electrode 18A and the circuit pattern 36D has a larger bonding area than the metal wire; therefore, the heat dissipation property of the semiconductor element 18 is improved. As a result, a design that increases the current density of the semiconductor element 18 is realized. <Ausführungsform 5>

[0069] A semiconductor device according to an embodiment 5 of the present invention will be described. In the following description, components similar to those described in the above embodiments are illustrated with the same reference numerals, and detailed descriptions thereof will be omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0070] Fig. 9 is a cross-sectional view schematically illustrating a configuration example of a semiconductor device according to Embodiment 5 of the present invention.

[0071] When the Fig. In the example illustrated in Fig. 9, the semiconductor device according to the invention comprises at least one circuit board 76 and a semiconductor element 18 bonded to the upper surface of the circuit board 76 via a conductive bonding material 14B.

[0072] Here, the circuit board 76 includes an insulating substrate 76A, a wiring layer 36J formed on the upper surface of the insulating substrate 36A, an insulating layer 36C partially formed on the upper layer of the wiring layer 36J, and a circuit pattern 36D formed on the upper layer of the insulating layer 36C. The wiring layer 36J includes a through-hole plating layer 36H disposed at a position where a gate electrode 18B and the source electrode 18C are bonded to the wiring layer 36J via the bonding material 14B. The wiring layer 36J and the circuit pattern 36D are electrically connected via an interconnection layer 36F.

[0073] The semiconductor element 18 includes a drain electrode 18A, the gate electrode 18B connected via the bonding material 14B to the plating layer 36H of a through-hole exposed from the insulating layer 36C and further to the wiring layer 36J, and the source electrode 18C connected via the bonding material 14B to the plating layer 36H of a through-hole exposed from the insulating layer 36C and further to the wiring layer 36J.

[0074] Furthermore, the semiconductor device may further include a base plate 12 bonded to the lower surface of a circuit board 76 via a heat dissipation film 100, a metal block 110 connecting the drain electrode 18A and the circuit pattern 36D via a bonding material 14C, a metal terminal 24A connected to the wiring layer 36J exposed on the insulating layer 36C side via a bonding material 14D, a case 26A, and a sealing material 22. The lower surface of the base plate 12 is exposed to the outside below the case 26A.

[0075] The dissipation film 100 includes an acrylic adhesive 101A, a PET film 102A, a graphite film 103, a PET film 102B, and an acrylic adhesive 101B. The base plate 12 adheres to the lower surface of the acrylic adhesive 101B.

[0076] According to the Fig.In the structure illustrated in Figure 9, the metal terminal 24A and the wiring layer 36J are connected via the bonding material 14D; therefore, the need to form a structure for connecting the metal wires is eliminated. Therefore, a large area for mounting the semiconductor element 18 is ensured, and downsizing of the semiconductor device is implemented. <Ausführungsform 6>

[0077] A semiconductor device according to Embodiment 6 will be described. In the following description, components similar to those described in the above embodiments are illustrated with the same reference numerals, and detailed descriptions thereof will be omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0078] The semiconductor device described in an embodiment 6 may have a circuit board with Tj=175°C or higher, and the peel strength at 175°C or higher is 70% or more of the peel strength at room temperature.

[0079] By arranging a circuit board made of a resin material having heat resistance as described above, the reliability of the semiconductor device in a high temperature environment is improved. <Ausführungsform 7>

[0080] A semiconductor device according to Embodiment 7 will be described. In the following description, components similar to those described in the above embodiments are illustrated with the same reference numerals, and detailed descriptions thereof will be omitted where appropriate. <Konfiguration einer Halbleitervorrichtung>

[0081] The semiconductor device described in Embodiment 7 may include a semiconductor element 18 made of silicon carbide (SiC). Silicon carbide (SiC) is a type of wide band gap semiconductor here. Wide band gap semiconductors typically refer to semiconductors with a forbidden band gap of approximately 2 eV or higher, and known wide band gap semiconductors include a Group 3 nitride such as gallium nitride (GaN), a Group 2 oxide such as zinc oxide (ZnO), a Group 2 chalcogenide such as zinc selenide, diamond, and silicon carbide.

[0082] When the semiconductor element disposed in the semiconductor device is made of SiC, downsizing and multiple parallelization of the semiconductor elements are realized due to the property of SiC being capable of operating at a higher temperature than that of Si or the like. As a result, downsizing of the semiconductor device is implemented. <Durch die oben beschriebenen Ausführungsformen erzeugte Effekte>

[0083] Next, an example of the effects produced by the above-described embodiments will be described. Although the following description describes the effects based on the specific configuration illustrated in the above-described embodiments, the specific configuration may be replaced with another specific embodiment, the example of which is illustrated in the present description, to the extent that the same effects are produced.

[0084] Furthermore, the replacement may be performed across a plurality of embodiments. That is, the respective configurations illustrated in the examples in different embodiments may be combined to achieve the same effects.

[0085] According to the embodiments described above, the semiconductor devices include the circuit board and the semiconductor element 18. Here, the circuit board corresponds, for example, to any of the circuit board 16, the circuit board 36, the circuit board 56, the circuit board 66, the circuit board 76, and the like (for convenience, any of these may correspond to the circuit board described hereinafter). The circuit board 16 has a first circuit pattern and a second circuit pattern on its upper surface. Here, the first circuit pattern corresponds, for example, to any of the circuit pattern 16B, the wiring layer 36B, the plating layer 36H of a through hole, the wiring layer 36G, and the wiring layer 36J, and the like (for convenience, any of these may correspond to the first circuit pattern described hereinafter).The second circuit pattern also corresponds, for example, to any of the circuit pattern 16E and the circuit pattern 36D, and the like (for convenience, any of these may correspond to the second circuit pattern described hereinafter). The semiconductor element 18 is arranged on the upper surface of the circuit pattern 16B. The drain electrode 18A is arranged on the upper surface of the semiconductor element 18. The semiconductor element 18 further has the gate electrode 18B and the source electrode 18C arranged on its lower surface. The gate electrode 18B and the source electrode 18C are bonded to the upper surface of the circuit pattern 16B via a first bonding material. Here, the first bonding material corresponds, for example, to the bonding material 14B or the like.The drain electrode 18A is bonded to the upper surface of the second circuit pattern via a metal member connected to the upper surface of the semiconductor element 18. Here, the metal member corresponds, for example, to any of the metal wire 20 and the metal block 110, and the like (for convenience, any of these may correspond to the metal member described hereinafter). The second circuit pattern also corresponds, for example, to any of the circuit pattern 16E and the circuit pattern 36D, and the like (for convenience, any of these may correspond to the second circuit pattern described hereinafter).

[0086] According to such a configuration, the temperature rise of the semiconductor element 18 is suppressed. Specifically, since the drain electrode 18A is formed on the upper surface of the semiconductor element 18 to which the metal wire 20 (or the metal block 110) is connected, an area where the metal wire is bonded is made larger than in a case where the metal wire 20 is connected to the surface on which the gate electrode 18B and the source electrode 18C are formed. Accordingly, the number of metal wires 20 to be wired (or the metal block 110 can be connected) on the surface increases; therefore, the amount of heat generated by each metal wire 20 (or the metal block 110) is suppressed. Furthermore, the degree of freedom regarding the wiring position of the metal wires 20 is increased.As a result, even if the outer diameter of the semiconductor element 18 is reduced to improve yield (i.e., the area of ​​the source electrode is reduced), the temperature rise of the semiconductor element 18 due to the heat of the metal wires 20 is suppressed. The source electrode 18C is further connected to the circuit pattern 16B via the bonding material 14B; therefore, the temperature rise of the semiconductor element 18 is suppressed more than that in the case where the source electrode 18C is connected by the metal wire 20. Therefore, the temperature rise of the wiring on the upper and lower surfaces of the semiconductor element 18 is suppressed, and as a result, the temperature rise of the semiconductor element 18 is suppressed.

[0087] It should be particularly noted that even if the other configurations illustrated herein are optionally added to the above-described configurations, that is, even if configurations other than the above configurations are optionally added to the description of the present application, the same effects can be produced.

[0088] According to the embodiments described above, the circuit board 36 further includes the insulating substrate 36A, the wiring layer disposed on the upper surface of the insulating substrate 36A, and the insulating layer 36C partially disposed on the upper surface of the wiring layer. Here, the wiring layer corresponds, for example, to any one of the wiring layer 36B, the wiring layer 36G, and the wiring layer 36J, and the like (for convenience, any of these may correspond to the wiring layer described hereinafter). The first circuit pattern is part of the wiring layers 36B exposed at a plurality of locations without being covered by the insulating layers 36C. The second circuit pattern is further the circuit pattern 36D disposed on the upper layer of the insulating layer 36C.According to such a configuration, the reduction in the amount of wiring to be laid, which serves as the metal wire 20 for connection, is ensured. Therefore, even if the outer diameter of the semiconductor element 18 is reduced and a large number of semiconductor elements 18 are arranged in parallel, appropriate wiring can be performed with a high degree of freedom without increasing the outer diameter of the semiconductor device. As a result, the downsizing of the semiconductor device is realized.

[0089] According to the embodiments described above, the wiring layer 36G further includes a through-hole plating layer 36H disposed at a position where at least one of the gate electrode 18B and the source electrode 18C is bonded to the wiring layer 36G via the bonding material 14B. According to such a configuration, when the semiconductor element 18 and the circuit board 56 are bonded, the bonding material 14B penetrates into the through-hole of the through-hole plating layer 36H. Therefore, the bonding area between the bonding material 14B and the through-hole plating layer 36H increases, making it possible to stabilize the bonding process. Furthermore, suppression of heat generation in the wiring of the semiconductor element 18 is ensured; therefore, the reliability of the semiconductor element is improved.

[0090] Moreover, according to the embodiments described above, the wiring layer 36J is exposed from the side surface of the insulating substrate 36A. The semiconductor device includes the metal terminal 24A bonded to the wiring layer 36J exposed from the side surface of the insulating substrate 36A via a second bonding material. Here, the second bonding material corresponds to, for example, the bonding material 14D or the like. According to such a configuration, the metal terminal 24A and the wiring layer 36J are connected via the bonding material 14D; therefore, the need to form a structure for connecting the metal wires is eliminated. Therefore, a large area for mounting the semiconductor element 18 is ensured, and downsizing of the semiconductor device is realized.

[0091] Furthermore, according to the embodiments described above, the semiconductor device includes the heat dissipation sheet 100 adhered to the lower surface of the circuit board 66 (or the circuit board 76), and the base plate 12 adhered to the lower surface of the heat dissipation sheet 100. The heat dissipation sheet 100 includes the first PET film, the graphite sheet 103, and the second PET film. Here, the first PET film corresponds to, for example, PET film 102A. The second PET film also corresponds to, for example, PET film 102B. The PET film 102A adheres to the lower surface of the circuit board 66 (or the circuit board 76) via a first adhesive. Here, the first adhesive corresponds to, for example, acrylic adhesive 101A. The graphite sheet 103 is disposed on the lower surface of the PET film 102A. The PET film 103B is disposed on the lower surface of the graphite sheet 103.Furthermore, the PET film 102B adheres to the upper surface of the base plate 12 via the second adhesive. Here, the second adhesive corresponds to, for example, the acrylic adhesive 101B. According to such a configuration, the heat dissipation property of the semiconductor element 18 is improved. Therefore, even if the outer diameter of the semiconductor element 18 is reduced, deterioration of the heat dissipation property of the semiconductor element 18 is suppressed by dissipating the heat generated in the semiconductor element 18 through the graphite foil 103.

[0092] Furthermore, according to the above-described embodiments, the printed circuit board 16 has a peel strength at 175°C or higher that is 70% or more of the peel strength at room temperature. According to such a configuration, the reliability of the semiconductor device in a high-temperature environment is improved.

[0093] Furthermore, according to the embodiments described above, the semiconductor element is made of SiC. According to such a configuration, downsizing and multi-parallelization of the semiconductor elements are realized due to the property of SiC being capable of operating at a higher temperature than that of Si or the like. As a result, downsizing of the semiconductor device is realized.

[0094] Further, according to the embodiments described above, the metal member is the metal wire 20. According to such a configuration, since the drain electrode 18A is formed on the upper surface of the semiconductor element 18, to which the metal wire 20 is connected, an area where the metal wire is bonded is made larger than in a case where the metal wire 20 is connected to the surface on which the gate electrode 18B and the source electrode 18C are formed. Accordingly, the number of metal wires 20 to be wired on the surface increases; therefore, the amount of heat generated by each metal wire 20 is suppressed.

[0095] Moreover, according to the embodiments described above, the metal component is the metal block 110. According to such a configuration, the metal block 110 connected to the drain electrode 18A and the circuit pattern 36D has a larger bonding area than the metal wire; therefore, the heat dissipation property of the semiconductor element 18 is improved. As a result, a design that increases the current density of the semiconductor element 18 is realized.

Claims

[1] A semiconductor device comprising: - a circuit board (16, 36, 56, 66, 76) having a first circuit structure (16B, 36B, 36H, 36G, 36J) and a second circuit structure (16E, 36D); and - a semiconductor element (18) arranged on an upper surface of the first circuit structure (16B, 36B, 36H, 36G, 36J), wherein: - in the semiconductor element (18) - a drain electrode (18A) is arranged on its upper surface and - a gate electrode (18B) and a source electrode (18C) are arranged on its lower surface, - the gate electrode (18B) and the source electrode (18C) are bonded to the upper surface of the first circuit structure (16B, 36B, 36H, 36G, 36J) via a first bonding material (14B), - the drain electrode (18A) is bonded to an upper surface of the second circuit structure (16E, 36D) via a metal component (20, 110) connected to the upper surface of the semiconductor element (18), - the printed circuit board (36, 56, 66, 76) comprises: - an insulating substrate (36A), - a wiring layer (36B, 36G, 36J) formed on an upper surface of the insulating substrate (36A), and - an insulating layer (36C) partially disposed on an upper surface of the wiring layer (36B, 36G, 36J), - the first circuit structure (36B, 36H, 36G, 36J) is part of the wiring layers (36B, 36G, 36J) which are exposed at a plurality of locations without being covered by the insulating layers (36C), and - the second circuit structure (36D) is arranged on an upper surface of the insulating layer (36C). [2] The semiconductor device according to claim 1, wherein the wiring layer (36G) has a plating layer (36H) at a position where the wiring layer (36G) is bonded to at least one of the gate electrode (18B) and the source electrode (18C) via the first bonding material (14B). [3] A semiconductor device according to any one of the preceding claims, wherein: - the wiring layer (36J) is exposed from a side surface of the insulating substrate (36A) and - the semiconductor device further comprises a metal terminal (24A) connected via a second bonding material (14D) to the wiring layer (36J) exposed from the side surface of the insulating substrate (36A). [4] A semiconductor device according to any one of the preceding claims, further comprising: - a heat dissipation film (100) adhered to a lower surface of the circuit board (66, 76), and - a base plate (12) adhered to a lower surface of the heat dissipation film (100), the heat dissipation film (100) comprising: - a first PET film (102A) adhered to the lower surface of the circuit board (66, 76) via a first adhesive (101A), - a graphite foil (103) arranged on a lower surface of the first PET film (102A), and - a second PET film (102B) disposed on a lower surface of the graphite foil (103) and attached to an upper surface of the base plate (12) via the second adhesive (101B). [5] A semiconductor device according to any one of the preceding claims, wherein the circuit board (16, 36, 56, 66, 76) has a peel strength at 175°C or higher which is 70% or more of the peel strength at room temperature. [6] A semiconductor device according to any one of the preceding claims, wherein the semiconductor element (18) is made of SiC. [7] A semiconductor device according to any one of the preceding claims, wherein the metal component comprises a metal wire (20). [8] A semiconductor device according to any one of claims 1 to 6, wherein the metal component comprises a metal block (110).

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