3D storage array contact structures and methods for their fabrication

Abstract

Storage array device comprising: a stack of transistors (204) over a semiconductor substrate (50), wherein the stack of transistors (204) comprises a first thin-film transistor (204) over a second thin-film transistor (204), wherein the first thin-film transistor (204) comprises: a first storage film (90) along a first word line (54); and a first channel region (92), a first source line (108) and a first bit line (106), wherein the first storage film (90) is arranged between the first channel region (92) and the first word line (54); the second thin-film transistor (204) has: a second storage film (90) along a second word line (54); and a second channel region (92) along the first source line (108) and the first bit line (106), wherein the second storage film (90) is arranged between the second channel region (92) and the second word line (54); a first stairwell via (110) which is electrically connected to the first word line (54), wherein the first stairwell via (110) has a first width that is uniform from top to bottom; and a second stairwell via (110) which is electrically connected to the second word line (54), wherein the second stairwell via (110) has a second width that is uniform from top to bottom, the second width being greater than the first width.

Description

BACKGROUND

[0001] Semiconductor memory is used in integrated circuits for electronic applications, including radios, televisions, mobile phones, and personal computing devices. Semiconductor memory comprises two main categories: volatile memory and non-volatile memory. Volatile memory includes random-access memory (RAM), which can be further divided into two subcategories: static random-access memory (SRAM) and dynamic random-access memory (DRAM). SRAM and DRAM are both volatile because they lose the information they store when they are not powered.

[0002] On the other hand, data can be stored on non-volatile memory. One type of non-volatile semiconductor memory is ferroelectric random-access memory (FeRAM or FRAM). Advantages of FeRAM include its fast read / write speeds and small size.

[0003] US 2020 / 0185411A1 discloses a memory array device comprising a stack of transistors on a semiconductor substrate and a stepped contact structure. Each transistor has a word line, and the stepped contact structure features stepped vias that are electrically connected to the respective word line and have the same width.

[0004] Karouta, F.: A practical approach to reactive ion etching. In: Journal of Physics D: Applied Physics, 47, 2014, 233501, describes the effects of etching stress that occur at different etching depths.

[0005] US 2014 / 0264718A1 discloses a storage device with vias on a stepped structure, wherein the width of a via at its upper end is greater the longer the via is and thus the deeper the via extends to establish contact with a conductive layer of the stepped structure. The width at the lower end of each via is identical.

[0006] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of this revelation are best understood from the following detailed description when read in conjunction with the accompanying figures. It should be noted that, in accordance with industry practice, various features are not drawn to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. 1A, Fig. 1B and Fig. Figure 1C illustrates a perspective view, a circuit diagram, and a top view of a storage array according to some embodiments. Fig. 2, Fig. 3A, Fig. 3B, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11, Fig. 12A, Fig. 12B, Fig. 13, Fig. 14, Fig. 15, Fig. 16, Fig. 17A, Fig. 17B, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20, Fig. 21, Fig. 22, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 24A, Fig. 24B, Fig. 24C, Fig. 25A, Fig. 25B, Fig. 25°C, Fig. 26A, Fig. 26B, Fig. 26C, Fig. 27A, Fig. 27B and Fig. 27C illustrates different views on the fabrication of a storage array according to some embodiments. Fig. 28A and Fig. Figure 28B illustrates a perspective view of a storage array and an adjacent stair contact structure, as well as a top-down view of the stair contact structure according to some embodiments. Fig. 29, Fig. 30 and Fig. Figure 31 illustrates different views of the manufacture of the stair contact structure according to some embodiments. Fig. 32A, Fig. 32B, Fig. 32C and Fig. Figure 32D illustrates various views of the formation of conductor tracks to the word lines, source lines and bit lines of the memory array and to conductive vias in a redistribution structure according to some embodiments. Fig. 33, Fig. 34 and Fig. Figure 35 illustrates different views of a memory array according to some embodiments. Fig. Figure 36 illustrates a stair contact structure according to some other embodiments. Fig. Figure 37 illustrates a staircase contact structure according to some other embodiments. DETAILED DESCRIPTION

[0008] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify this disclosure. For example, the formation of a first element or a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and it may also include embodiments in which further elements may be formed between the first and second elements, so that the first and second elements need not be in direct contact. Furthermore, this disclosure may repeat reference numbers and / or letters of the various examples. This repetition is for the sake of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and / or configurations discussed.

[0009] Furthermore, spatially relative terms such as "below," "underneath," "lower," "above," "upper," and the like may be used herein for a simpler description of the relationship of one element or feature to one or more other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass various orientations of the device in use or operation, in addition to the orientation shown in the figures. The device may be oriented differently (rotated by 90 degrees or in another orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0010] Various embodiments represent a 3D stacked memory array with multiple vertical stacked memory cells. Each memory cell comprises a thin-film transistor (TFT) having a word line region serving as a gate electrode, a bit line region serving as a first source / drain electrode, and a source line region serving as a second source / drain electrode. Each TFT further comprises an insulating storage film (e.g., as a gate dielectric) and an oxide semiconductor channel region (OS channel region).

[0011] In some embodiments, a contact staircase structure is formed from a stack of conductive layers separated by dielectric layers. The staircase structure provides word lines for the memory array, and conductive vias are formed that extend downwards and are electrically connected to each of the conductive layers. The conductive vias can vary in width. For example, the width of the conductive vias can increase as the vias are further away from the transistor area of ​​the memory array. An etching stress effect (e.g.,Wider critical dimensions of the stair vias are used for deeper etch depths, and narrow critical dimensions for shallow etch depths. This prevents over-etching of the openings and word line short circuits of the upper layer for the stair vias due to a large difference in step heights between the upper and lower layers. Material savings (e.g., mask materials), lower manufacturing costs, and simplified processes can be achieved for the fabrication of a 3D stacked storage array device with reliable word line contacting.

[0012] Fig. 1A, Fig. 1B and Fig. Figure 1C illustrates examples of a memory array according to some embodiments. Fig. Figure 1A illustrates an example of a section of the memory array 200 in a three-dimensional view; Fig. Figure 1B illustrates a circuit diagram of the memory array 200; and Fig. Figure 1C illustrates a top view of the memory array 200 according to some embodiments. The memory array 200 comprises multiple memory cells 202, which can be arranged in a row-and-column grid. The memory cells 202 can further be stacked vertically to provide a three-dimensional memory array, thereby increasing the device density. The memory array 200 can be located in the back-end-of-line (BEOL) of a semiconductor die. For example, the memory array can be located in the interconnect layers of the semiconductor die, such as above one or more active devices (e.g., transistors) formed on a semiconductor substrate.

[0013] In some embodiments, the memory array 200 is a flash memory array, such as a NOR flash memory array or the like. Each memory cell 202 can comprise a thin-film transistor (TFT) 204 with an insulating storage film 90 as a gate dielectric. In some embodiments, a gate of each TFT 204 is electrically coupled to a corresponding word line (e.g., conductor track 72), a first source / drain region of each TFT 204 is electrically coupled to a corresponding bit line (e.g., conductor track 106), and a second source / drain region of each TFT 204 is electrically coupled to a corresponding source line (e.g., conductor track 108) that electrically connects the second source / drain region to ground.The memory cells 202 in an equal vertical column of the memory array 200 can share a common bit line (BL) 116A and a common source line (SL) 116B, while the memory cells 202 in an equal horizontal row of the memory array 200 can share a common word line (WL) 116C.

[0014] The memory array 200 comprises several vertically stacked conductor tracks 72 (e.g., word lines) with dielectric layers 52, arranged between adjacent conductor tracks 72. The conductor tracks 72 extend in one direction parallel to a main surface of an underlying substrate (in Fig. 1A and Fig. (1B not explicitly illustrated). The conductor tracks 72 can have a stair configuration such that lower conductor tracks 72 are longer than upper conductor tracks 72 and extend laterally beyond their endpoints. For example, in Fig. Figure 1A illustrates several stacked layers of conductor tracks 72, wherein the uppermost conductor tracks 72 are the shortest and the lowermost conductor tracks 72 are the longest. The respective lengths of the conductor tracks 72 can increase in one direction towards the underlying substrate. In this way, a section of each of the conductor tracks 72 can be accessible from above the memory array 200, and conductive contacts can be made on an exposed section of each of the conductor tracks 72.

[0015] The memory array 200 further comprises several of the conductor tracks 106 (e.g., common bit lines 116A) and the conductor tracks 108 (e.g., common source lines 116B). The conductor tracks 106 and 108 can each extend in one direction perpendicular to the conductor tracks 72. A dielectric 98 is arranged between adjacent conductor tracks 106 and the conductor tracks 108 and insulates them. In some embodiments, at least one portion of the dielectric 98 is a hydrogen-deficient material formed using a hydrogen-containing precursor introduced at a reduced flow rate. For example, at least portions of the dielectric 98 (e.g., dielectric 98A) that are in physical contact with an oxide semiconductor layer (OS layer) 92 (described below) can have a relatively low hydrogen concentration, such as less than 3 atomic percent (at%). The low hydrogen concentration (e.g.(in the above area) hydrogen diffusion into the OS layer 92 can be reduced, thereby reducing defects and improving the stability of the device. For example, by reducing hydrogen diffusion with the dielectric 98, the threshold voltage curve (V. thThe -curve) of the TFTs 204 is shifted in a positive bias direction, which, according to one embodiment, increases the stability of the TFTs 204. A relatively low hydrogen concentration in the dielectric 98 can be achieved, for example, by reducing the flow rate of the hydrogen-containing precursor(s) used to deposit the dielectric 98. In embodiments where the dielectric 98 comprises silicon oxide, silicon nitride, or the like, the dielectric 98 can, for example, be deposited by a process with a relatively low SiH4 precursor flow rate to suppress the diffusion of Ho or H+ into the dielectric 98 and the OS layer 92.

[0016] Pairs of conductor tracks 106 and 108, together with an intersecting conductor track 72, define the boundary of each memory cell 202, and a dielectric 102 is arranged between adjacent pairs of conductor tracks 106 and 108 and insulates them. In some embodiments, the conductor tracks 108 are electrically coupled to ground. Even if Fig. Figure 1A illustrates a specific placement of the conductor tracks 106 with respect to the conductor tracks 108; it should be noted that the placement of the conductor tracks 106 and 108 may be reversed in other embodiments.

[0017] As discussed above, the memory array 200 can also include an oxide semiconductor layer (OS layer) 92. The OS layer 92 can provide channel regions for the TFTs 204 of the memory cells 202. For example, if a suitable voltage (e.g., higher than a respective threshold voltage (V)) is applied, the memory cells 202 can be activated. thWhen a current is applied to a corresponding TFT 204 via corresponding conductor tracks 72, a region of the OS layer 92 that intersects the conductor tracks 72 can allow current to flow from the conductor tracks 106 to the conductor tracks 108 (e.g., in the direction indicated by arrow 206). The OS layer 92 can have a relatively low hydrogen concentration, such as in the range of approximately 10²⁻² to approximately 10²⁻² atoms per cubic centimeter, as measured by time-of-flight secondary ion mass spectrometry (ToF-SIMS) analysis. Therefore, the stability of the TFTs 204 can be improved compared to TFTs with OS layers exhibiting a higher hydrogen concentration.

[0018] A storage film 90 is arranged between the conductor tracks 72 and the OS layer 92, and the storage film 90 can provide gate dielectrics for the TFTs 204. In some embodiments, the storage film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. Accordingly, the storage array 200 can also be referred to as a ferroelectric direct-access memory array (FERAM array). Alternatively, the storage film 90 can have a multilayer structure, including a SiN layer. x between two SiO x -layers (e.g., of an ONO structure), another ferroelectric material, another type of storage layer (e.g., capable of storing a bit), or the like.

[0019] In embodiments where the storage film 90 comprises a ferroelectric material, the storage film 90 can be polarized in one of two different directions, and the polarization direction can be changed by applying a suitable voltage difference across the storage film 90 and generating a suitable electric field. The polarization can be relatively localized (e.g., generally encompassing each boundary of the memory cells 202), and a continuous region of the storage film 90 can extend across multiple memory cells 202. Depending on the polarization direction of a particular region of the storage film 90, a threshold voltage of a corresponding TFT 204 varies, and a digital value (e.g., 0 or 1) can be stored.For example, if a region of the memory film 90 has a first electrical polarization direction, the corresponding TFT 204 can have a relatively low threshold voltage, and if the region of the memory film 90 has a second electrical polarization direction, the corresponding TFT 204 can have a relatively high threshold voltage. The difference between the two threshold voltages can be referred to as the threshold voltage shift. A larger threshold voltage shift makes it easier (e.g., less error-prone) to read the digital value stored in the corresponding memory cell 202.

[0020] To perform a write operation on a memory cell 202 in such embodiments, a write voltage is applied across a section of the memory film 90 corresponding to the memory cell 202. The write voltage can be applied, for example, by applying suitable voltages to the corresponding conductor tracks 72 (e.g., the word line) and the corresponding conductor tracks 106 / 108 (e.g., the bit line / source line). By applying the write voltage across the section of the memory film 90, the polarization direction of the region of the memory film 90 can be changed. This allows the corresponding threshold voltage of the corresponding TFT 204 to be switched from a low threshold voltage to a high threshold voltage or vice versa, and a digital value can be stored in the memory cell 202. Since the conductor tracks 72 intersect the conductor tracks 106 and 108, individual memory cells 202 can be selected for the write operation.

[0021] In such embodiments, to perform a read operation on memory cell 202, a read voltage (a voltage between the low and high threshold voltages) is applied to the corresponding conductor tracks 72 (e.g., the word line). Depending on the polarization direction of the corresponding region of the memory film 90, the TFT 204 of memory cell 202 may be switched on, but this is not required. Therefore, conductor track 106 may be discharged through conductor track 108 (e.g., a source line coupled to ground), but this is not required, and the digital value stored in memory cell 202 can be determined. Since conductor tracks 72 intersect conductor tracks 106 and 108, individual memory cells 202 can be selected for the read operation.

[0022] Fig. Figure 1A further illustrates reference cross-sections of the memory array 200, which are used in later figures. Cross-section BB' runs along a longitudinal axis of the conductor tracks 72 and in a direction, for example, parallel to the direction of the current flux of the TFTs 204. Cross-section CC' is perpendicular to cross-section BB' and parallel to a longitudinal axis of the conductor tracks 72. Cross-section CC' extends through the conductor tracks 106. Cross-section DD' is parallel to cross-section CC' and extends through the dielectric 102. For clarity, subsequent figures refer to these reference cross-sections.

[0023] In Fig. 2. A substrate 50 is provided. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type dopant) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like. The insulating layer is provided on a substrate, usually a silicon or glass substrate. Other substrates, such as a multilayer or gradient substrate, may also be used.In some embodiments, the semiconductor material of the substrate 50 may comprise silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; or combinations thereof.

[0024] Fig. Figure 2 further illustrates circuits that can be formed on the substrate 50. The circuits include active devices (e.g., transistors) on an upper surface of the substrate 50. The transistors can comprise gate dielectric layers 203 over upper surfaces of the substrate 50 and gate electrodes 205 over the gate dielectric layers 203. Source / drain regions 207 are arranged in the substrate 50 on opposite sides of the gate dielectric layers 203 and the gate electrodes 205. Gate spacers 208 are formed by the gate electrodes 205 at suitable lateral distances along side walls of the gate dielectric layers 203 and separate from the source / drain regions 207. In some embodiments, the transistors can be planar field-effect transistors (FETs), fin field-effect transistors (finFETs), nanofield-effect transistors (nanoFETs), or the like.

[0025] A first ILD 210 surrounds and insulates the source / drain regions 207, the gate dielectric layers 203, and the gate electrodes 205, and a second ILD 212 is located above the first ILD 210. Source / drain contacts 214 extend through the second ILD 212 and the first ILD 210 and are electrically coupled to the source / drain regions 207, and gate contacts 216 extend through the second ILD 212 and are electrically coupled to the gate electrodes 205. An interconnect structure 220, comprising one or more stacked dielectric layers 224 and conductive features 222 formed in one or more dielectric layers 224, is located above the second ILD 212, the source / drain contacts 214, and the gate contacts 216. Fig. Figure 2 illustrates two stacked dielectric layers 224. It should be noted that the interconnect structure 220 can comprise any number of dielectric layers 224 in which conductive features 222 are arranged. The interconnect structure 220 can be electrically connected to the gate contacts 216 and the source / drain contacts 214 to form functional circuits. In some embodiments, the functional circuits formed by the interconnect structure 220 can include logic circuits, memory circuits, sense amplifiers, controllers, input / output circuits, image sensor circuits, the like, or combinations thereof. Fig. In addition to the two transistors formed on the substrate 50, other active devices (e.g. diodes or the like) and / or passive devices (e.g. capacitors, resistors or the like) can be formed as a section of the functional circuits.

[0026] In the Fig. 3A and Fig. 3B will be a multilayer stack 58 above the interconnect structure 220 of Fig. 2. The substrate 50, the transistors, the ILDs, and the interconnect structure 220 can be omitted from subsequent drawings for the sake of simplicity and clarity. Although the multilayer stack 58 is illustrated as contacting the dielectric layers 224 of the interconnect structure 220, any number of intermediate layers can be arranged between the substrate 50 and the multilayer stack 58. For example, one or more additional interconnect layers with conductive features in insulating layers (e.g., dielectric layers with a low k-value) can be arranged between the substrate 50 and the multilayer stack 58. In some embodiments, the conductive features can be structured to provide power, ground, and / or signal lines to the active devices on the substrate 50 and / or the storage array 200 (see Fig. 1A and Fig. 1B).

[0027] The multilayer stack 58 comprises alternating layers of conductive layers 54A to C (collectively referred to as conductive layers 54) and dielectric layers 52A to D (collectively referred to as dielectric layers 52). The conductive layers 54 may be structured in subsequent steps to define the conductor tracks 54 (e.g., word lines). The conductive layers 54 may comprise a conductive material, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, and the dielectric layers 52 may comprise an insulating material, such as silicon oxide, silicon nitride, silicon oxynitride, combinations thereof, or the like.The conductive layers 54 and dielectric layers 52 can each be formed, for example, using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), or the like. Even if... Fig. 3A and Fig. Figure 3B illustrates a specific number of conductive layers 54 and dielectric layers 52; other embodiments may include a different number of conductive layers 54 and dielectric layers 52. Furthermore, the multilayer stack 58 may comprise any number of suitable types of material layers, and the number and arrangement of the material layers may be based on a desired device to be formed in the multilayer stack 58.

[0028] Fig. Figures 4 to 12B are views of intermediate stages in the manufacture of a staircase structure 68 of the storage array 200 according to some embodiments. Fig. Figures 4 to 11 and 12B are illustrated along reference cross-section BB', which is shown in Fig. 1 is illustrated. Fig. 12A is illustrated in a three-dimensional view.

[0029] In Fig. 4 A photoresist 56 is formed over the multilayer stack 58. As discussed above, 54C, the multilayer stack 58 can comprise alternating layers of the conductive layers 54 (labeled 54A, 54B and 54C) and the dielectric layers 52 (labeled 52A, 52B, 52C and 52D). The photoresist 56 can be formed using a spin-on technique.

[0030] In Fig. The photoresist 56 is structured to expose the multilayer stack 58 in regions 60, while masking the remaining sections of the multilayer stack 58. For example, a top layer of the multilayer stack 58 (e.g., dielectric layer 52D) can be exposed in regions 60. The photoresist 56 can be structured using acceptable photolithography techniques.

[0031] In Fig. 6. The exposed sections of the multilayer stack 58 in regions 60 are etched using the photoresist 56 as a mask. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The etching can remove sections of the dielectric layer 52D and the conductive layer 54C in regions 60 to define openings 61. Since the dielectric layer 52D and the conductive layer 54C have different material compositions, the etchants used to remove the exposed sections of these layers can be different. In some embodiments, the conductive layer 54C acts as an etch stop layer when etching the dielectric layer 52D and the dielectric layer 52C acts as an etch stop layer when etching the conductive layer 54C.This allows sections of the dielectric layer 52D and the conductive layer 54C to be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 can be enlarged to a desired depth. Alternatively, a timed etching process can be used to stop the etching of the openings 61 after they reach a desired depth. In the resulting structure, the dielectric layer 52C is exposed in regions 60.

[0032] In Fig. 7. The photoresist 56 is cut to expose further sections of the multilayer stack 58. The photoresist can be cut using appropriate photolithography techniques. As a result of the cutting, the width of the photoresist 56 is reduced, and sections of the multilayer stack 58 in regions 60 and 62 can be exposed. For example, a top surface of the dielectric layer 52C in region 60 and a top surface of the dielectric layer 52D in region 62 can be exposed.

[0033] In Fig. Sections of the dielectric layer 52D, the conductive layer 54C, and the conductive layer 54B in regions 60 and 62 are removed by acceptable etching processes using the photoresist 56 as a mask. The etching can be any acceptable process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The etching can extend the openings 61 further into the multilayer stack 58. Because the dielectric layers 52D / 52C and the conductive layers 54C / 54B have different material compositions, the etchants used to remove exposed sections of the layers can differ.In some embodiments, the conductive layer 54C acts as an etch stop layer when etching the dielectric layer 52D; the dielectric layer 52C acts as an etch stop layer when etching the conductive layer 54C; the conductive layer 54B acts as an etch stop layer when etching the dielectric layer 52C; and the dielectric layer 52B acts as an etch stop layer when etching the conductive layer 54B. This allows sections of the dielectric layer 52D / 52C and the conductive layers 54B / 54C to be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 can be enlarged to a desired depth. Furthermore, during the etching process, unetched sections of the conductive layers 54 and dielectric layers 52 act as a mask for underlying layers and due to a previous structure of the dielectric layer 52D and conductive layer 54C (see . Fig. 7) can be transferred to the underlying dielectric layer 52C and conductive layer 54B. In the resulting structure, the dielectric layer 52B is exposed in regions 60 and the dielectric layer 52C in regions 62.

[0034] In Fig. 9. The photoresist 56 is cut to expose further sections of the multilayer stack 58. The photoresist can be cut using appropriate photolithography techniques. As a result of the cutting, the width of the photoresist 56 is reduced, and sections of the multilayer stack 58 in regions 60, 62, and 64 can be exposed. For example, a top surface of dielectric layer 52B can be exposed in region 60, a top surface of dielectric layer 52C can be exposed in region 62, and a top surface of dielectric layer 52D can be exposed in region 64.

[0035] In Fig. 10. Sections of the dielectric layers 52D, 52C, and 52B in regions 60, 62, and 64 are removed by acceptable etching processes using the photoresist 56 as a mask. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The etching can extend the openings 61 further into the multilayer stack 58. In some embodiments, the conductive layer 54C acts as an etch stop layer when etching the dielectric layer 52D; the conductive layer 54B acts as an etch stop layer when etching the dielectric layer 52C; and the conductive layer 54A acts as an etch stop layer when etching the dielectric layer 52B.Therefore, sections of the dielectric layers 52D, 52C, and 52B can be selectively removed without removing the remaining layers of the multilayer stack 58, and the openings 61 can be extended to a desired depth. Furthermore, each of the conductive layers 54 acts as a mask for the underlying layers during the etching processes, so that a prior structure of the conductive layers 54C / 54B (see . Fig. 9) can be transferred to the underlying dielectric layers 52C / 52B. In the resulting structure, the conductive layer 54A is exposed in regions 60; the dielectric layer 54B is exposed in regions 62; and the conductive layer 54C is exposed in regions 64.

[0036] In Fig. 11 The photoresist 56 can be removed, for example by an acceptable ash or wet stripping process. This forms a step structure 68. The step structure 68 comprises a stack of alternating conductive layers 54 and dielectric layers 52. Lower conductive layers 54 are wider and extend laterally past upper conductive layers 54, with the width of each conductive layer 54 increasing in one direction towards the substrate 50. For example, conductor 54A can be longer than conductor 54B; conductor 54B can be longer than conductor 54C; and conductor 54C can be longer than conductor 54D. Therefore, in subsequent processing steps, conductive contacts can be made from the step contact structures 68 to each of the conductive layers 54.

[0037] In Fig. In step 12A, an intermediate metal dielectric (IMD) 70 is deposited over the multilayer stack 58. The IMD 70 can be formed from a dielectric and can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectrics can include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped silicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by an acceptable process can be used. The IMD 70 extends along the sidewalls of the conductive layers 54 as well as the sidewalls of the dielectric layers 52. Furthermore, the IMD 70 can contact the top surfaces of each of the dielectric layers 52.

[0038] As further in Fig. As illustrated in Figure 12A, a removal process is then applied to the IMD 70 to remove excess dielectric material above the multilayer stack 58. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), etching, combinations thereof, or the like, can be used. According to some embodiments, the planarization process exposes the multilayer stack 58 openly, so that the upper surfaces of the multilayer stack 58 and the IMD 70 are flat after completion of the planarization process. In other embodiments, the planarization process planes the IMD 70 to a desired height above a top layer (e.g., dielectric layer 52D) of the multilayer stack 58.

[0039] Fig. Figure 12B is a perspective view of the stair structure 68, according to some embodiments. In particular, in Fig. Figure 12B illustrates the staircase contact structures 68, which are formed from a multilayer stack 58 comprising four of the dielectric layers 52 and five of the conductor tracks 54. It also illustrates Fig. 12B a note according to some embodiments. Although embodiments of the stair structures 68 have been illustrated to include a certain number of conductor tracks 54 and dielectric layers 52, it is understood that the stair contact structures 68 can be formed to include any other suitable material layer and any number of conductor tracks 54 and dielectric layers 52.

[0040] Fig. Figures 13 to 17B are views of intermediate stages in the fabrication of the memory array 200 using the multilayer stack 58. Fig. 3A according to some embodiments. In Fig. At steps 13 to 17B, the multilayer stack 58 is formed, and trenches are created in the multilayer stack 58, thereby defining the conductor tracks 72. The conductor tracks 72 can correspond to word lines in the memory array 200, and the conductor tracks 72 can also provide gate electrodes for the resulting TFTs of the memory array 200. Fig. 17A is illustrated in a three-dimensional view. Fig. Figures 13 to 16 and 17B are illustrated along reference cross-section CC', which is shown in Fig. 1A is illustrated.

[0041] In Fig. A hard mask 80 and a photoresist 82 are deposited over the multilayer stack 58. The hard mask 80 can, for example, comprise silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The photoresist 82 can, for example, be formed using a spin-on technique.

[0042] In Fig. 14. The photoresist 82 is structured to form trenches 86. The photoresists can be structured using appropriate photolithography techniques. For example, the photoresist 82 is exposed for structuring. After the exposure process, the photoresist 82 can be developed to reveal exposed or unexposed sections of the photoresist, depending on whether a negative or positive resist is used, thereby defining a structure of the trenches 86.

[0043] In Fig. 15 A structure of the photoresist 82 is transferred to the hard mask 80 using an acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. Thus, grooves 86 are formed that extend through the hard mask 80. The photoresist 82 can be removed, for example, by an ash removal process.

[0044] In Fig. 16 A structure of the hard mask 80 is transferred to the multilayer stack 58 using one or more acceptable etching processes, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching processes can be anisotropic. Thus, trenches 86 extend through the multilayer stack 58, and the conductive traces 72 (e.g., word lines) are formed from the conductive layers 54. By etching trenches 86 through the conductive layers 54, adjacent conductive traces 72 can be separated from one another.

[0045] The following can be found in Fig. 17A and Fig. 17B the hard mask 80 can then be removed by an acceptable process, such as a wet etching process, a dry etching process, a planarization process, combinations thereof, or the like. Due to the stepped shape of the multilayer stack 58 (see e.g. Fig. 12A), the conductor tracks 72 can have different lengths, which increase in one direction towards the substrate 50. For example, the conductor tracks 72A can be longer than the conductor tracks 72B; and the conductor tracks 72B can be longer than the conductor tracks 72C.

[0046] Fig. Figures 18A to 23C illustrate the formation and structuring of channel regions for the TFTs 204 (see Fig. 1A) in the trenches 86. Fig. 18A, Fig. 19A and Fig. 23A are illustrated in a three-dimensional view. In Fig. 18B, Fig. 19B, Fig. 20, Fig. 21, Fig. 22A, Fig. 22B and Fig. 23B are cross-sectional views along line CC' from Fig. 1A provided. Fig. Figure 23C illustrates a corresponding top view of the TFT structure.

[0047] In Fig. 18A and Fig. 18B is a storage film 90 compliant in the trenches 86 deposited. In Fig. In 18A, the storage film 90 was omitted from the undersides of the trenches 86 and over the upper surfaces of the multilayer stack 58 for reasons of optical clarity. The storage film 90 can be made of a material capable of storing a bit, such as a material capable of switching between two different polarization directions by applying a suitable voltage difference across the storage film 90. For example, the polarization of the storage film 90 can change due to an electric field resulting from the application of the voltage difference.

[0048] For example, the storage film 90 can be a dielectric with a high k-value, such as a hafnium-based (HF-based) dielectric or the like. In some embodiments, the storage film 90 comprises a ferroelectric material, such as hafnium oxide, hafnium zirconium oxide, silicon-doped hafnium oxide, or the like. In other embodiments, the storage film 90 can have a multilayer structure comprising a layer of SiN x includes between two SiO x-layers (e.g., of an ONO structure). In other embodiments, the storage film 90 may comprise a different ferroelectric material or a different type of storage material. The storage film 90 may be deposited by CVD, PVD, ALD, PECVD, or the like to extend along sidewalls and a lower surface of the trenches 86. After the storage film 90 has been deposited, an annealing step (e.g., at a temperature range of approximately 300 °C to 600 °C) may be performed to achieve a desired crystalline phase, improve film quality, and reduce film-related defects / impurities in the storage film 90. In some embodiments, the annealing step may further be below 400 °C to meet a BEOL heat budget and reduce defects that may lead to other features from high-temperature annealing processes.

[0049] In Fig. 19A and Fig. In 19B, the OS layer 92 is compliantly deposited in the trenches 86 above the storage film 90. Fig. In Figure 19A, the OS layer 92 and the storage film 90 on the undersides of the trenches 86 and over the upper surfaces of the multilayer stack 58 have been omitted for reasons of optical clarity. The OS layer 92 comprises a material suitable for providing a channel region for a TFT (e.g., TFTs 204, see Figure 19A). Fig. 1A). In some embodiments, OS layer 92 comprises an indium-containing material, such as In x Ga y Zn zMO, where M can be Ti, Al, Ag, Si, Sn, or the like. X, Y, and Z can each be a value between 0 and 1. In other embodiments, a different semiconductor material can be used for the OS layer 92. The OS layer 92 can be deposited by CVD, PVD, ALD, PECVD, or the like. The OS layer 92 can extend along sidewalls and a lower surface of the grooves 86 above the storage film 90. After deposition of the OS layer 92, an annealing step (e.g., in a temperature range between approximately 300°C and approximately 450°C) can be performed in an oxygen-containing environment to activate the charge carriers of the OS layer 92.

[0050] In Fig. 20 A dielectric 98A is deposited on the side walls and a lower surface of the trenches 86 and above the OS layer 92. The dielectric 98A can, for example, comprise silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like.

[0051] In Fig. 21. Lower sections of the dielectric 98A in the trenches 86 are removed, for example, using a combination of photolithography and etching. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic.

[0052] The following can be seen, as well as through Fig. Figure 21 illustrates how the dielectric 98A can be used as an etching mask to etch through a lower section of the OS layer 92 in the trenches 86. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. Etching the OS layer 92 can expose sections of the storage film 90 on a lower surface of the trenches 86. Thus, sections of the OS layer 92 on opposite side walls of the trenches 86 can be separated from each other, which reduces the insulation between the storage cells 202 of the storage array 200 (see Figure 21). Fig. 1A) improved.

[0053] In Fig. 22 An additional dielectric 98B can be deposited to fill the remaining sections of the trenches 86. The dielectric 98B can, for example, comprise silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. In some embodiments, the dielectric 98B can have the same material composition and be formed using the same process as the dielectric 98A. Alternatively, the dielectric 98B can have a different material composition and / or be formed by a different process than the dielectric 98A.

[0054] The following figures illustrate, for easier illustration, the further processing based on the embodiment of Fig. 22 (e.g., if dielectric 98B and dielectric 98A have the same material composition). Dielectric 98B and dielectric 98A may hereinafter be referred to collectively as dielectric 98. It is understood that a similar processing procedure can also be applied to embodiments in which dielectric 98B and dielectric 98A have different material compositions.

[0055] In Fig. In steps 23A to 23C, a removal process is then applied to the dielectric 98, the OS layer 92, and the storage film 90 to remove excess material above the multilayer stack 58. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a re-etching process, combinations thereof, or the like, may be used. The planarization process exposes the multilayer stack 58 such that the top surface of the multilayer stack 58 is flat after completion of the planarization process. Fig. 23C illustrates a corresponding top view of the structure, which is in Fig. 23A is illustrated.

[0056] Fig. Figures 24A to 27C illustrate intermediate steps in the fabrication of the conductor tracks 106 and 108 (e.g., source lines and bit lines) in the memory array 200. The conductor tracks 106 and 108 can extend along one direction perpendicular to the conductor tracks 54, so that individual cells of the memory array 200 can be selected for read and write operations. Fig. Figures 24A to 27C illustrate a 3D view with end “A”; figures with end “B” illustrate a top view; and figures with end “C” illustrate a corresponding cross-sectional view parallel to line CC’. Fig. 1A.

[0057] In Fig. 24A, Fig. 24B and Fig. 24C are trenches 100 structured through the OS layer 92 and the dielectric 98 (including the dielectric 98A and the dielectric 98B). Fig. 24C illustrates a cross-sectional view of line CC' in Fig. 24B. The structuring of the trenches 100 can be carried out, for example, by a combination of photolithography and etching. The trenches 100 can be arranged between opposite side walls of the storage film 90, and the trenches 100 can be physically separate adjacent stacked storage cells in the storage array 200 (see Fig. 1A).

[0058] In Fig. 25A, Fig. 25B and Fig. 25C is a dielectric 102 deposited in the trenches 100 and fills them. Fig. 25C illustrates a cross-sectional view of line CC' in Fig. 25B. The dielectric 102 may, for example, comprise silicon oxide, silicon nitride, silicon oxynitride, or the like, which may be deposited by CVD, PVD, ALD, PECVD, or the like. The dielectric 102 may extend along sidewalls and a lower surface of the trenches 100 above the OS layer 92. After deposition, a planarization process (e.g., CMP, back-etching, or the like) may be performed to remove excess portions of the dielectric 102. In the resulting structure, the upper surfaces of the multilayer stack 58, the storage film 90, the OS layer 92, and the dielectric 102 may be substantially planar (e.g., within process variations). In some embodiments, the materials of the dielectrics 98 and 102 may be selected such that they can be selectively etched relative to each other. For example, in some embodiments the dielectric 98 is an oxide and the dielectric 102 is a nitride.In some embodiments, the dielectric 98 is a nitride and the dielectric 102 is an oxide. Other materials are possible.

[0059] In Fig. 26A, Fig. 26B and Fig. 26C, trenches 104 are structured for the conductor tracks 106 and 108. Fig. 26C illustrates a cross-sectional view of line CC' in Fig. 26B. The trenches 104 are formed, for example, by structuring the dielectric 98 (including dielectric 98A and dielectric 98B) using a combination of photolithography and etching.

[0060] For example, a photoresist 120 can be deposited over the multilayer stack 58, the dielectric 98, the dielectric 102, the OS layer 92, and the storage film 90. The photoresist 120 can be formed, for example, using a spin-on technique. The photoresist 120 is structured to define apertures 122. Each of the apertures 122 can overlap a corresponding region of the dielectric 102, and each of the apertures 122 can furthermore partially expose two separate regions of the dielectric 98. For example, each aperture 122 can expose one region of the dielectric 102; partially expose a first region of the dielectric 98; and partially expose a second region of the dielectric 98, which is separated from the first region of the dielectric 98 by the region of the dielectric 102 exposed through the aperture 122.Each of the openings 122 can define a structure of a conductor track 106 and an adjacent conductor track 108, separated by the dielectric 102. The photoresists can be structured using appropriate photolithography techniques. For example, the photoresist 120 is exposed for structuring. After the exposure process, the photoresist 120 can be developed to reveal exposed or unexposed sections of the photoresist, depending on whether a negative or positive resist is used, thereby defining a structure of the mold openings 122.

[0061] Subsequently, sections of the dielectric 98 exposed through the openings 122 can be removed, for example, by etching. The etching can be any acceptable etching process, such as wet or dry etching, reactive ion etching (RIE), neutral beam etching (NBE), the like, or a combination thereof. The etching can be anisotropic. The etching process can use an etchant that etches the dielectric 98 without substantially etching the dielectric 102. Therefore, although the openings 122 expose the dielectric 102, the dielectric 102 may not be substantially removed. A structure of the trenches 104 can correspond to the conductor tracks 106 and 108 (see Fig. 27A, Fig. 27B and Fig. 27C). For example, a section of the dielectric 98 can remain between each pair of the grooves 104, and the dielectric 102 can be arranged between adjacent pairs of the grooves 104. After the grooves 104 have been structured, the photoresist 120 can be removed, for example, by ashing.

[0062] In Fig. 27A, Fig. 27B and Fig. 27C the trenches 104 are filled with a conductive material to form the conductor tracks 106 and 108. Fig. 27C illustrates a cross-sectional view of line CC' in Fig. 27B. The conductor tracks 106 and 108 can each comprise a conductive material, such as copper, titanium, titanium nitride, tantalum, tantalum nitride, tungsten, ruthenium, aluminum, combinations thereof, or the like, each formed, for example, by CVD, ALD, PVD, PECVD, or the like. After the conductor tracks 106 and 108 have been deposited, planarization (e.g., CMP, back-etching, or the like) can be performed to remove excess portions of the conductive material and thus form the conductor tracks 106 and 108. In the resulting structure, the top surfaces of the multilayer stack 58, the storage film 90, the OS layer 92, the conductor tracks 106, and the conductor tracks 108 can be substantially planar (e.g., within process variations). Traces 106 can correspond to bit lines in the memory array, and traces 108 can correspond to source lines in the memory array 200. Even if Fig. Figure 27C illustrates a cross-sectional view showing only the conductor tracks 106; a cross-sectional view of the conductor tracks 108 may be similar.

[0063] Stacked TFTs 204 can be formed in the memory array 200. Each TFT 204 comprises a gate electrode (e.g., a section of a corresponding conductor 54), a gate dielectric (e.g., a section of a corresponding storage film 90), a channel region (e.g., a section of a corresponding OS layer 92), and source and drain electrodes (e.g., sections of corresponding conductors 106 and 108). The dielectric 102 insulates adjacent TFTs 204 in the same column and on the same vertical plane. The TFTs 204 can be arranged in an array of vertically stacked rows and columns.

[0064] In the Fig. 28A and Fig. 28B are staircase vias 110 to the conductor tracks 54 (e.g. word lines WL) and source / bit line contacts 112 and 114 to the conductor tracks 106 and 108 (e.g. source lines SL and bit lines BL) are made. Fig. Figure 28A illustrates a perspective view of the memory array 200 and two of the step contact structures 68 adjacent to the memory array 200, according to some embodiments. In some embodiments, the step contact structures 68 are formed on opposite sides of the transistor stack region 1201 of the memory array 200. Fig. Figure 28B illustrates a top view of the stair contact structure 68 in Fig. 28A.

[0065] In the illustrated embodiment, the multilayer stack 58 comprises six of the conductor tracks 54, separated by seven of the dielectric layers 52, which can be formed by repeating the steps described above. In some embodiments, the stepped shape of the multilayer stack 58 can provide a surface on each of the conductor tracks 54 that can contact the stepped vias 110.

[0066] As also through the perspective view of Fig. As illustrated in Figure 28A, source / bit line contacts 112 and 114 can also be formed with the conductor tracks 106 and 108, respectively. The source / bit line contacts 112 and 114 can be formed with any of the materials and techniques suitable for forming the staircase vias 110.

[0067] In the illustrated embodiment, the IMD 70 is in comparison to the staircase vias 110 in Fig. 28A shown in cutout; however, the planes of the stepped vias 110 and the IMD 70 can be coplanar. In other embodiments, the IMD 70 can be formed coplanar with the storage array 200 and an optional dielectric layer 120 (see Fig. 29) can be formed above the IMD 70 and the memory array 200. In such embodiments, the openings for the staircase vias 110 are formed by the optional dielectric layer and the IMD 70, and the openings for the source / bit line contacts 112 and 114 are formed by the optional dielectric layer.

[0068] In some embodiments, the size of the vias 110 increases with the height of the vias 110 from the topmost conductor track 54 to the bottommost conductor track 54. For example, the diameter of the vias 110 at their top face can increase with increasing distance from the transistor stack region 120. Thus, the diameters of the vias 110 closest to the transistor stack region 1201 are smaller than the diameters of the vias 110 furthest from the transistor stack region 1201. In the Fig. 28A and Fig. In 28B, the vias 110 closest to the transistor stack region 1201 can have a first height H1, and the vias 110 furthest from the transistor stack region 1201 can have an nth height H(n). The nth height H(n) is greater than the first height H1. Furthermore, the vias 110 closest to the transistor stack region 1201 can have a first diameter W(o), and the vias 110 furthest from the transistor stack region 1201 can have an nth diameter W(n). The nth diameter W(n) is larger than the first diameter W(o).

[0069] Furthermore, the source / bit line contacts 112 and 114 can be formed in any suitable size (e.g., height and diameter) used for the stepped vias 110. Although the source / bit line contacts 112 and 114 are illustrated as being of the same size (e.g., first height H1 and first width W(o)), their sizes can also be different. Fig. Figure 28B further illustrates the section line EE' through the stair vias 110 of the stair contact structure 68.

[0070] Fig. Figures 29-31 illustrate intermediate steps in the formation of the stair vias 110 according to some embodiments. Fig. 29, Fig. 30 to Fig. Figure 31 illustrates cross-sectional views of the stair contact structure 68 along line EE' of the Fig. 28B.

[0071] In particular, it illustrates Fig. 29. The formation of openings 2901 through the IMD 70 at desired locations of the stair vias 110 according to some embodiments. In some embodiments, the shape of the stair structures 68 can provide a surface on each of the conductor tracks 54 that can contact the stair vias 110. The formation of the stair vias 110 can include structuring openings in the IMD 70 and the dielectric layers 52 to expose sections of the conductor tracks 54, for example, by a combination of photolithography and etching. In some embodiments, the openings 2901 can be structured such that they have substantially vertical sidewalls. In such embodiments, the widths of the openings 2901 can be uniform from the top surfaces of the openings to the bottom surfaces of the openings. In other embodiments, the openings 2901 can be structured such that they have angled sidewalls.In such embodiments, the widths of the openings 2901 on the upper surfaces of the openings can be larger than the widths on the undersides of the openings.

[0072] After the openings 2901 are formed, the extensions Ext1 to Ext(n) of the conductor tracks 54 are exposed. The extensions Ext1 to Ext(n) can refer to a section of one of the conductor tracks 54 that extends beyond an overlying dielectric layer 52 and / or a layer of conductor tracks 54 above it. In some embodiments, the extensions Ext1 to Ext(n) are of the same length. In other embodiments, the extensions Ext1 to Ext(n) can have different lengths. Fig. Figure 29 further illustrates the center lines CL1 to CL(n) of the openings 2901, which in the illustrated embodiment can be aligned with the centers of the extensions Ext1 to Ext(n). According to some embodiments, the openings 2901 can have different widths (e.g., W(0) to W(n) and H1 to H(n)), and each of the openings 2901 is centered over an associated extension (e.g., Ext1 to Ext(n)) of the conductor tracks 54.

[0073] Now illustrated with a view to Fig. Figure 30 shows an etching stress effect of the openings 2901 according to some embodiments. In some embodiments, a first opening can be located at a first distance D1 from the transistor stack region 1201, and the remaining openings are formed at positions along a line up to a second distance D2 from the first opening. In some embodiments, the openings 2901 are formed at positions along the line at regular intervals P1. In other embodiments, the openings 2901 can be formed at any suitable positions along the line between the first distance D1 and the second distance D2.

[0074] In particular, it illustrates Fig. 30. A correlation between a desired width and a desired depth of the openings 2901 as a result of etching processes used to structure the openings 2901, according to some embodiments. For example, if the second spacing D2 increases, the width of the openings 2901 increases (e.g., W(o) to W(n)) and the etch depths (e.g., H1 to H(n)) of the openings 2901 also increase, where n is a positive integer. According to some embodiments, the widths (e.g., W(o) to W(n)) of the openings 2901 can range from about 10 nm to about 500 nm. In some embodiments, the heights (e.g., H1 to H(n)) of the openings 2901 can range from about 50 nm to about 5,000 nm. However, any suitable widths and heights can be used for the openings 2901.Due to the etching effect, openings 2901 of different widths can be structured in a single structuring step, since the openings 2901 extend to different depths.

[0075] Now illustrated with a view to Fig. Figure 31 shows the formation of the stair-step vias 110 in the openings 2901 according to some embodiments. The formation of the stair-step vias 110 may include the formation of a lining (not shown), such as a diffusion barrier, an adhesion layer, or the like, and the formation of a conductive material in the openings. The lining may comprise titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, may be performed to remove excess material from a face of the IMD 120. The remaining lining and the conductive material form the stair-step vias 110 in the openings 2901.In some embodiments, the IMD 120 can be omitted and the planarization process flattens the upper surfaces of the stair vias 110 and the IMD 70.

[0076] Furthermore, it illustrates Fig. 31, that the center lines CL1 to CL(n) of the stair vias 110 can be centered over the extensions of the conductor tracks 54 according to some embodiments. Furthermore, according to some embodiments, the first stair via 110 is located at a first distance D1 from the transistor stack region 1201. According to some embodiments, the widths (e.g., W(0) to W(n)) of the stair vias 110 can increase as the second distance D2 from the first stair via 110 increases. Any suitable distances can be used for the first distance D1 and the second distance D2. In the illustrated embodiment, the stair vias 110 are planarized with the IMD 120. Thus, according to some embodiments, the upper surfaces of the stair vias 110 are exposed in a coplanar area of ​​the IMD 120.

[0077] In the Fig. 32A, Fig. 32B, Fig. 32C and Fig. 32D Formation of common bit lines 116A, common source lines 116B and common word lines 116C to the source / bit line contacts 112 and 114 or the staircase vias 110. Fig. Figure 32D illustrates that the staircase vias 110 and the source / bit line contacts 112 and 114 can be electrically connected to common bit lines 116A, common source lines 116B, and common word lines 116C, respectively, which connect the memory array to an underlying / overlying circuit arrangement (e.g., control circuit arrangement) and / or signal, power, and ground lines for the semiconductor die. For example, the common bit lines 116A, the common source lines 116B, and the common word lines 116C can be encased by one or more dielectric layers 3201 (in the Fig. 28C and Fig. 28D) are guided and connected to conductive vias 118 extending through the IMD 70 to electrically connect the common word lines 116C to the underlying circuit arrangement of the interconnect structure 220 and the active devices on the substrate 50, as shown in Fig. Figure 28C illustrates this. Other conductive vias 118 can be formed by the IMD 70 to electrically connect the common bit lines 116A and the common source lines 116B to the underlying circuit arrangement of the interconnect structure 220. In alternative embodiments, routing and / or power lines to and from the memory array can be provided by an interconnect structure formed above the memory array 200, alongside or instead of the interconnect structure 220. Accordingly, the memory array 200 can be terminated.

[0078] Although the embodiments of Fig. While Figures 2 to 32C illustrate a specific structure for conductor tracks 106 and 108, other configurations are also possible. In these embodiments, for example, conductor tracks 106 and 108 have a stepped structure. In some embodiments, conductor tracks 106 and 108 in the same row of the array are all aligned with each other.

[0079] Fig. 33 illustrates a view from above, and Fig. Figure 34 illustrates a cross-sectional view of line CC' alone. Fig. 33. Fig. Figure 35 illustrates a cross-sectional view of line DD' alone. Fig. 33. In the Fig. 33, Fig. 34 and Fig. 35 denote identical reference digits, identical elements that undergo the same processes as the elements of the Fig. 2 to 32CV can be formed.

[0080] With regard to Fig. Figure 36 now illustrates the stair contact structures 68 according to a different embodiment. Fig. 36 is similar to Fig. 31, except that each of the stair vias 110 is spaced a third distance D3 along the extensions Ext1 to Ext(n) of the conductor tracks 54, instead of being centered along the extensions. Thus, the distance of a stair via to the word line (e.g., the third distance D3) for each of the stair vias 110 in the illustrated embodiment of Fig. 36 equal. A uniform distance between the stair-step via and the word line ensures a reliable contact connection during the fabrication of the stair-step contact structures 68 and for the operation of the storage array device 200. After the stair-step contact structures 68 have been formed according to the illustrated embodiment, the storage array device 200 can be operated as described in the Fig. Items 32A to 35 will be discussed and further processed.

[0081] Fig. Figure 37 further illustrates the stair contact structures 68 according to another embodiment. Fig. 37 is similar to Fig. 31, except that the widths (e.g., W(0) to W(n)) of the stair vias 110 are proportional to the first width W(0), where n is a positive integer and W(n) is between about 10 nm and about 500 nm. The ratio W(n) / W(0) of a stair via can, for example, be between about 1:1 and about 50:1. However, any suitable ratio can be used. In some embodiments, the nth width W(n) increases as the second distance D2 from the first stair via 110 increases. According to some embodiments, the nth width W(n) = [W(0) + W(0)*n], where n is a positive integer and W(n) is a width between about 10 nm and 500 nm. However, any suitable width can be used. In such embodiments, the openings 2901 (in Fig. 30) with the desired widths and at the desired locations of the stair vias 110. After the stair contact structures 68 have been formed according to the illustrated embodiment, the storage array device 200 can be assembled as shown in the illustration. Fig. Items 32A to 35 will be discussed and further processed.

[0082] Various embodiments offer a 3D stacked memory array with vertically stacked memory cells. Each memory cell comprises a TFT with a memory film, gate dielectric, and an oxide semiconductor channel region. The TFT includes source / drain electrodes, which also serve as source and bit lines in the memory array. A dielectric is positioned between adjacent source / drain electrodes, isolating them.

[0083] In some embodiments, a contact staircase structure is formed from a stack of conductive layers separated by dielectric layers. The contact staircase structure provides word line contacts for a stacked memory array. The upper conductive layers provide word line contacts for the upper memory cells of the stacked memory array, and the lower conductive layers provide word line contacts for the lower memory cells of the stacked memory array. Thus, the step heights of the lower conductive layers are greater than the step heights of the upper conductive layers. An etching stress effect (e.g.,Wider critical dimensions of the stair vias are used for deeper etch depths, and narrow critical dimensions for shallow etch depths. This prevents over-etching of the openings and word line short circuits of the upper layer for the stair vias due to a large difference in step heights between the upper and lower layers. Material savings (e.g., mask materials), lower manufacturing costs, and simplified processes can be achieved for the fabrication of a 3D stacked storage array device with reliable word line contacting.

[0084] According to one embodiment, a memory array device comprises: a stack of transistors over a semiconductor substrate, wherein the stack of transistors comprises a first thin-film transistor over a second thin-film transistor, the first thin-film transistor comprising: a first storage film along a first word line; and a first channel region, a first source line, and a first bit line, wherein the first storage film is arranged between the first channel region and the first word line; the second thin-film transistor comprising: a second storage film along a second word line; and a second channel region along the first source line and the first bit line, wherein the second storage film is arranged between the second channel region and the second word line; a first stairwell via electrically connected to the first word line.wherein the first stairwell via has a first width; and a second stairwell via which is electrically connected to the second word line, wherein the second stairwell via has a second width, the second width being greater than the first width. In one embodiment, the first stairwell via is located at a first distance from the stack of transistors, and wherein the second stairwell via is located at a second distance from the stack of transistors, the second distance being greater than the first distance. In one embodiment, the first stairwell via is centered on a first extension of the first word line, and wherein the second stairwell via is centered on a second extension of the second word line, the first extension of the first word line being a segment of the first word line.which extends over a third word line above the first word line, and wherein the second extension of the second word line is a segment of the second word line extending over the first word line. In one embodiment, the first stair via is located at a third distance along a first extension of the first word line, and wherein the second stair via is located at the third distance along a second extension of the second word line, wherein the first extension of the first word line is a segment of the first word line extending over a third word line above the first word line, and wherein the second extension of the second word line is a segment of the second word line,which extends over the first word line. In one embodiment, the first width is in a range of 10 nm to 500 nm. In another embodiment, the ratio of the second width to the first width is in a range of 1:1 to 50:1. In another embodiment, the first stair via and the second stair via are encompassed by multiple stair vias, wherein the width of an nth stair via of the multiple stair vias is equal to an nth width W(n), where the nth width W(n) = [W(o) + W(o)*n], and where W(o) is the first width and n is a positive integer.

[0085] According to another embodiment, a device comprises: a semiconductor substrate; a word line stack; a first stepped via connected to a first word line of the word line stack, the first stepped via having a first width and a first height; a second stepped via connected to a second word line of the word line stack, the first word line being arranged above the second word line, the second stepped via having a second width and a second height, the second width being greater than the first width and the second height being greater than the first height; and a memory cell stack, the memory cell stack comprising: a first thin-film transistor, wherein a section of the first word line provides a gate electrode of the first thin-film transistor; and a second thin-film transistor.wherein the first thin-film transistor is arranged above the second thin-film transistor and wherein a section of the second word line provides a gate electrode of the second thin-film transistor. In one embodiment, the first stepped via is located at a first distance from the memory cell stack and the second stepped via is located at a second distance from the memory cell stack, the second distance being greater than the first distance. In one embodiment, the first width is between about 10 nm and about 500 nm. In one embodiment, the ratio of the second width to the first width is between about 1:1 and about 50:1. In one embodiment, the first stepped via is centered over a first extension of the first word line and the second stepped via is centered over a second extension of the second word line.wherein the first extension of the first word line is a section of the first word line extending beyond a third word line of the word line stack, the third word line being arranged above the first word line, and wherein the second extension of the second word line is a section of the second word line extending beyond the first word line. In one embodiment, the first step via is located at a third distance along a first extension of the first word line, and the second step via is located at the third distance along a second extension of the second word line, wherein the first extension of the first word line is a section of the first word line extending beyond a third word line of the word line stack, the third word line being arranged above the first word line.and wherein the second extension of the second word line is a section of the second word line that extends beyond the first word line. In one embodiment, a total of n stair vias are connected to the word line stack, wherein the width of an nth stair via is equal to an nth width W(n), where the nth width W(n) = [W(o) + W(o)*n], and where W(o) is the first width, and where n is a positive integer between 1 and 50.

[0086] In a further embodiment, a method comprises: forming a stack of memory cells in a first region of a multilayer stack of conductive layers, wherein a section of a first conductive layer is a gate electrode of a first memory cell in the stack of memory cells and a section of a second conductive layer is a gate electrode of a second memory cell in the stack of memory cells; forming a conductive step structure in a second region of the multilayer stack of conductive layers; forming a dielectric layer over the conductive step structure; exposing the first conductive layer by forming a first opening through the dielectric layer, wherein the first opening has a first width and is arranged at a first distance from the first region; exposing the second conductive layer by forming a second opening through the dielectric layer.wherein the second opening has a second width and is arranged at a second distance from the first region, the second width being greater than the first width and the second distance being greater than the first distance; forming a first conductive via in the first opening; and forming a second conductive via in the second opening. In one embodiment, the first width is between about 10 nm and about 500 nm. In one embodiment, the ratio of the second width to the first width is between about 1:1 and about 50:1. In one embodiment, the multilayer stack of conductive layers comprises a total of n conductive layers, wherein the method further comprises exposing an nth conductive layer by forming an nth opening through the dielectric layer, wherein a width of the nth opening is equal to the sum of the first width and a product of the first width and n.where n is a positive integer between 1 and 50. In one embodiment, the first opening is centered over a first extension of the first conductive layer, and the second opening is centered over a second extension of the second conductive layer, wherein the first extension of the first conductive layer is a portion of the first conductive layer extending over a third conductive layer above the first conductive layer, and wherein the second extension of the second conductive layer is a portion of the second conductive layer extending over the first conductive layer. In another embodiment, the first opening is located at a third distance along a first extension of the first conductive layer, and the second opening is located at the third distance along a second extension of the second conductive layer.wherein the first extension of the first conductive layer is a section of the first conductive layer extending over a third conductive layer above the first conductive layer, and wherein the second extension of the second conductive layer is a section of the second conductive layer extending over the first conductive layer.

Claims

[1] Storage array device comprising: a stack of transistors (204) over a semiconductor substrate (50), wherein the stack of transistors (204) comprises a first thin-film transistor (204) over a second thin-film transistor (204), wherein the first thin-film transistor (204) comprises: a first storage film (90) along a first word line (54); and a first channel region (92), a first source line (108) and a first bit line (106), wherein the first storage film (90) is arranged between the first channel region (92) and the first word line (54); the second thin-film transistor (204) has: a second storage film (90) along a second word line (54); and a second channel region (92) along the first source line (108) and the first bit line (106), wherein the second storage film (90) is arranged between the second channel region (92) and the second word line (54); a first stairwell via (110) which is electrically connected to the first word line (54), wherein the first stairwell via (110) has a first width that is uniform from top to bottom; and a second stairwell via (110) which is electrically connected to the second word line (54), wherein the second stairwell via (110) has a second width that is uniform from top to bottom, the second width being greater than the first width. [2] Storage array device according to claim 1, wherein the first via (110) is located at a first distance from the stack of transistors (204) and wherein the second via (110) is located at a second distance from the stack of transistors (204), the second distance being greater than the first distance. [3] Storage array device according to claim 2, wherein the first staircase via (110) is centered on a first extension of the first word line (54), wherein the second staircase via (110) is centered on a second extension of the second word line (54), wherein the first extension of the first word line (54) is a section of the first word line (54) extending beyond a third word line (54) above the first word line (54), and wherein the second extension of the second word line (54) is a section of the second word line (54) extending beyond the first word line (54). [4] Storage array device according to claim 2, wherein the first staircase via (110) is arranged at a third distance along a first extension of the first word line (54) and wherein the second staircase via (110) is arranged at the third distance along a second extension of the second word line (54), wherein the first extension of the first word line (54) is a section of the first word line (54) extending beyond a third word line (54) above the first word line (54), and wherein the second extension of the second word line (54) is a section of the second word line (54) extending beyond the first word line (54). [5] Storage array device according to any one of claims 2 to 4, wherein the first width is in a range of 10 nm to 500 nm. [6] Storage array device according to claim 5, wherein the ratio of the second width to the first width is in a range of 1:1 to 50:

1. [7] Storage array device according to claim 5 or 6, wherein the first stair via (110) and the second stair via (110) are comprised in multiple stair vias (110), wherein a width of an nth stair via (110) of the multiple stair vias (110) is equal to an nth width W(n), wherein the nth width W(n) = [W(o) + W(o)*n], and wherein W(o) is the first width and n is a positive integer. [8] Device comprising: a semiconductor substrate (50); a word-lead stack (54); a first stair via (110) connected to a first word line (54) of the word line stack, wherein the first stair via (110) has a first width and height that is uniform from top to bottom; a second stair via (110) connected to a second word line (54) of the word line stack, wherein the first word line (54) is arranged above the second word line (54), wherein the second stair via (110) has a second width and a second height that are uniform from top to bottom, wherein the second width is greater than the first width and the second height is greater than the first height; and a memory cell stack, wherein the memory cell stack has: a first thin-film transistor (204), wherein a section of the first word line (54) provides a gate electrode of the first thin-film transistor (204); and a second thin-film transistor (204), wherein the first thin-film transistor (204) is arranged above the second thin-film transistor (204) and wherein a section of the second word line (54) provides a gate electrode of the second thin-film transistor (204). [9] Device according to claim 8, wherein the first staircase via (110) is arranged at a first distance from the memory cell stack and the second staircase via (110) is arranged at a second distance from the memory cell stack, wherein the second distance is greater than the first distance. [10] Device according to claim 9, wherein the first width is between about 10 nm and about 500 nm. [11] Device according to claim 10, wherein the ratio of the second width to the first width is between about 1:1 and about 50:

1. [12] Device according to claim 10 or 11, wherein the first staircase via (110) is centered over a first extension of the first word line (54) and the second staircase via (110) is centered over a second extension of the second word line (54), wherein the first extension of the first word line (54) is a section of the first word line (54) extending beyond a third word line (54) of the word line stack, wherein the third word line (54) is arranged above the first word line (54), and wherein the second extension of the second word line (54) is a section of the second word line (54) extending beyond the first word line (54). [13] Device according to claim 10 or 11, wherein the first stair via (110) is arranged at a third distance along a first extension of the first word line (54) and the second stair via (110) is arranged at the third distance along a second extension of the second word line (54), wherein the first extension of the first word line is a section of the first word line extending beyond a third word line (54) of the word line stack, wherein the third word line (54) is arranged above the first word line (54), and wherein the second extension of the second word line (54) is a section of the second word line (54) extending beyond the first word line (54). [14] Device according to any one of claims 10 to 13, wherein a total of n stair vias (110) are connected to the word line stack, wherein a width of an nth stair via (110) is equal to an nth width W(n), wherein the nth width W(n) = [W(o) + W(o)*n], and wherein W(o) is the first width, and wherein n is a positive integer between 1 and 50. [15] Procedures, including: Forming a stack of memory cells (202) in a first region (1201) of a multilayer stack of conductive layers (54), wherein a section of a first conductive layer is a gate electrode of a first memory cell (202) in the stack of memory cells (202) and a section of a second conductive layer (54) is a gate electrode of a second memory cell (202) in the stack of memory cells (202); Forming a conductive staircase structure (68) in a second area (1203) of the multilayer stack of conductive layers (54); Forming a dielectric layer (70) over the conductive step structure (68); Exposing the first conductive layer (54) by forming a first opening (2901) through the dielectric layer (70), wherein the first opening (2901) has a first width that is uniform from top to bottom and is arranged at a first distance from the first region (1201); Exposing the second conductive layer (54) by forming a second opening (2901) through the dielectric layer (70), wherein the second opening (2901) has a second width that is uniform from top to bottom and is arranged at a second distance from the first region (1201), wherein the second width is greater than the first width and the second distance is greater than the first distance; Forming a first conductive via (110) in the first opening (2901); and Forming a second conductive via (110) in the second opening (2901). [16] Method according to claim 15, wherein the first width is a width between about 10 nm and about 500 nm. [17] Method according to claim 16, wherein the ratio of the second width to the first width is between about 1:1 and about 50:

1. [18] Method according to claim 16 or 17, wherein the multilayer stack of conductive layers (54) comprises a total of n conductive layers (54), wherein the method further comprises exposing an nth conductive layer (54) by forming an nth opening (2901) through the dielectric layer (70), wherein a width of the nth opening (2901) is equal to a sum of the first width and a product of the first width and n, where n is a positive integer between 1 and 50. [19] Method according to any one of claims 16 to 18, wherein the first opening (2901) is centered over a first extension of the first conductive layer (54) and the second opening (2901) is centered over a second extension of the second conductive layer (54), wherein the first extension of the first conductive layer (54) is a section of the first conductive layer (54) extending over a third conductive layer (54) above the first conductive layer (54), and wherein the second extension of the second conductive layer (54) is a section of the second conductive layer (54) extending over the first conductive layer (54). [20] Method according to any one of claims 16 to 18, wherein the first opening (2901) is arranged at a third distance along a first extension of the first conductive layer (54) and the second opening (2901) is arranged at the third distance along a second extension of the second conductive layer (54), wherein the first extension of the first conductive layer (54) is a section of the first conductive layer (54) extending over a third conductive layer (54) above the first conductive layer (54), and wherein the second extension of the second conductive layer (54) is a section of the second conductive layer (54) extending over the first conductive layer (54).

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