Semiconductor device and method for its manufacture

Abstract

Semiconductor device with: a first semiconductor chip (201) connected to an interposer (101); an encapsulation material (303) that encapsulates the first semiconductor chip (201); and a first lid (501) that is in physical contact with both the first semiconductor chip (201) and the encapsulation material (303), wherein the first lid (501) crosses an interface between the first semiconductor chip (201) and the encapsulation material (303), wherein the first cover (501) overlaps the first semiconductor chip (201) by a first overlap length and by a first overlap width, and the first overlap length is less than a length of the first semiconductor chip (201) and the first overlap width is less than a width of the first semiconductor chip (201).

Description

BACKGROUND

[0001] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of a wide variety of electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). This improvement in integration density is largely attributable to the repeated reduction of the minimum feature size (e.g., shrinking the semiconductor process node towards the sub-20nm node), which allows more components to be integrated into a given area. As the demand for miniaturization, higher speed and bandwidth, as well as lower power consumption and latency, has increased recently, a need has arisen for smaller and more innovative packaging techniques for semiconductor chips.

[0002] With the further advancement of semiconductor technologies, stacked and bonded semiconductor devices have emerged as an effective alternative for further reducing the physical size of a semiconductor device. In a stacked semiconductor device, active circuits such as logic, memory, and processor circuits are at least partially fabricated on separate substrates and then physically and electrically connected to form a functional device. Sophisticated techniques are used for such bonding processes, and improvements are desirable.

[0003] From US patent 2021 / 0066151A1, a semiconductor device is known which has a first semiconductor chip connected to an interposer; an encapsulation material encapsulating the first semiconductor chip; and a first lid in physical contact with both the first semiconductor chip and the encapsulation material, wherein the first lid crosses an interface between the first semiconductor chip and the encapsulation material.

[0004] The publication US 2021 / 0 118 756 A1 shows in Fig. 5 A semiconductor device with a substrate 502 on which chips 510 are arranged and surrounded by an encapsulation layer 580. A thermal interface material 540 is located on the entire surface of the chips 510, on which a heat spreader 520 is arranged in direct contact. Both the thermal interface material 540 and the heat spreader 520 overlap the entire surface of the chips 510.

[0005] Further prior art relating to the subject matter of the invention can be found, for example, in publications US 2015 / 0179607A1 and US 2020 / 0075436A1.

[0006] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of this disclosure are best understood from the following detailed description when read together with the accompanying figures. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased to enhance the clarity of the description. Fig. Figure 1 shows an interposer connected to a substrate, according to some embodiments. Fig. Figure 2 shows the placement of a first semiconductor chip and a second semiconductor chip on the interposer according to some embodiments. Fig. Figure 3 illustrates an encapsulation of the first semiconductor chip and the second semiconductor chip with an encapsulation material, according to some embodiments. Fig. Figure 4 illustrates a dilution of the encapsulating agent according to some embodiments. The Fig. Figures 5A-5C show the placement of covers according to some embodiments. Fig. Figure 6 illustrates a first annealing process according to some embodiments. The Fig. Figures 7A-7B show the attachment of a ring according to some embodiments. In the Fig. Figures 8A-8B show a second annealing process according to some embodiments. Fig. Figure 9 illustrates the attachment of the ring before the attachment of the lids, according to some embodiments. Fig. Figure 10 illustrates the placement of the lids after the placement of the ring, according to some embodiments. Fig. Figure 11 illustrates an arrangement of the lid and ring before annealing according to some embodiments. Fig. Figure 12 illustrates a third annealing process according to some embodiments. In the Fig. Figures 13A-13G show different shapes and arrangements for the covers according to some embodiments. Fig. Figure 14 illustrates the placement of a lid according to some embodiments. Fig. Figure 15 illustrates the use of a thermal interface material according to some embodiments. Fig. Figure 16 shows an embodiment in which the ring and the lids are coplanar, according to some embodiments. Fig. Figure 17 shows an embodiment in which the cover is placed on the first semiconductor chip, according to some embodiments. DETAILED DESCRIPTION

[0008] The following disclosure includes many different embodiments or examples of the implementation of various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, only examples and are not to be understood as limiting. For example, the embodiment of a first feature above or on top of a second feature in the following description may include embodiments in which the first and second features are in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, so that the first and second features do not have to be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself represent a relationship between the various designs and / or configurations discussed.

[0009] Furthermore, to simplify the description, spatially relative terms such as "below," "under," "below," "above," "above," and the like can be used to describe the relationship of one element or feature to another, as illustrated in the figures. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also other orientations of the device during use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative terms used here can be interpreted accordingly.

[0010] Embodiments are now described in relation to one or more specific embodiments in which corner regions of a semiconductor structure are reinforced with corner covers.

[0011] In Fig. Figure 1 shows the formation of an interposer 101 and the placement of the interposer 101 on a substrate 103. In one embodiment, the interposer 101 can be formed as an organic interposer with a first redistribution layer comprising a series of conductive layers (e.g., two, three, or four conductive layers) embedded in a series of dielectric layers (e.g., four or five dielectric layers). These dielectric layers are used not only to provide a conductive guide for signals but can also be used to provide structures such as integrated inductors or capacitors. In one embodiment, a first series of dielectric layers is formed, for example, over a support substrate (in Fig. (1 not shown separately), and the first of the series of dielectric layers can consist of a material such as polybenzoxazole (PBO), although any suitable material, such as polyimide or a polyimide derivative, can be used. The first of the series of dielectric layers can be applied, for example, by a spin-coating process, using any suitable method.

[0012] Once the first series of dielectric layers has been formed, openings can be created through it by removing portions of the layer. These openings can be formed using a suitable photolithographic mask and an etching process, although any suitable process or processes can be used to structure the first series of dielectric layers.

[0013] Once the first series of dielectric layers has been formed and structured, a first series of conductive layers is formed over the first series of dielectric layers and through the openings formed in the first series of dielectric layers. In one embodiment, the first series of conductive layers can be formed by first forming a seed layer of a titanium-copper alloy by a suitable formation process such as CVD or sputtering. A photoresist can then be formed to cover the seed layer, and the photoresist can then be structured to expose the portions of the seed layer that are located where the first series of conductive layers is to be placed.

[0014] After the photoresist has been shaped and structured, a conductive material, such as copper, can be formed on the seed layer by a deposition process, such as plating. The conductive material can be formed with a thickness between approximately 1 µm and approximately 10 µm, e.g., approximately 5 µm. Although the materials and processes described are suitable for forming the conductive material, these materials are only examples. Any other suitable material, such as AlCu or Au, and any other suitable fabrication process, such as CVD or PVD, can be used to form the first of the series of conductive layers. After the conductive material has been formed, the photoresist can be removed by a suitable removal process, such as ashing. Additionally, after the photoresist has been removed, the parts of the seed layer that were covered by the photoresist can be, for example,removed by a suitable etching process using the conductive material as a mask.

[0015] Once the first series of conductive layers has been formed, a second series of dielectric layers and a second series of conductive layers can be formed by repeating steps similar to those of the first series of dielectric layers and the first series of conductive layers. These steps can be repeated indefinitely to electrically connect each series of conductive layers to an underlying series of conductive layers, and they can be repeated indefinitely until a topmost series of conductive layers and a topmost series of dielectric layers have been formed.In one embodiment, the deposition and structuring of the series of conductive layers and the series of dielectric layers can be continued until the first redistribution layer has a desired number of layers, although any suitable number of individual layers can be used.

[0016] Once the desired number of conductive and dielectric layers have been formed, the support substrate is removed, and underbump metallizations and first external connections 105 can be formed to establish an electrical connection with the first of the conductive layers. In one embodiment, the underbump metallization layers can comprise three layers of conductive materials, such as a layer of titanium, a layer of copper, and a layer of nickel, formed by processes such as plating, sputtering, vapor deposition, PECVD processes, combinations of these processes, or the like. However, a person skilled in the art will recognize that there are many suitable arrangements of materials and layers, such as a chromium / chromium-copper alloy / copper / gold arrangement, a titanium / titanium tungsten / copper arrangement, or a copper / nickel / gold arrangement, that are suitable for forming the underbump metallization layers.All suitable materials or material layers that can be used for the underbump metallization layers are fully included within the scope of the embodiments.

[0017] In one embodiment, the first external connections 105 can be a ball grid array (BGA) comprising a eutectic material, such as solder, although any suitable material can be used. In another embodiment, where the first external connections 105 are solder bumps, they can be formed using a ball-drop process, such as a direct ball-drop process. In another embodiment, the solder bumps can be formed by first forming a tin layer by any suitable method, such as evaporation, electroplating, printing, or solder transfer, and then reflowing to bring the material into the desired bump shape with a height between about 20 µm and about 200 µm. However, any suitable method and dimensions can be used.

[0018] After the first external connections 105 have been formed, the interposer 101 can be placed on the substrate 103. The substrate 103 can comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. In general, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon-germanium, SOI, silicon-germanium on insulator (SGOI), or combinations thereof. Additionally, the substrate 103 can be part of a semiconductor wafer at this point in the process (the complete wafer of which is shown in the diagram). Fig. (not shown in 1), which will be separated in a later step.

[0019] However, the substrate 103 is not limited to the embodiments described above. In other embodiments, the substrate 103 may, for example, comprise multilayer substrates, gradient substrates, or substrates with hybrid orientation, or be a glass substrate, a ceramic substrate, a polymer substrate, a printed circuit board such as a laminate substrate formed as a stack of several thin layers (or laminates) of a polymer material such as bismaleimide triazine (BT), FR-4, ABF, and the like, or any other substrate that provides suitable protective and / or interconnect functionality. These and all other suitable materials may alternatively be used for the substrate 103.

[0020] In one embodiment, the interposer 101 is placed on the substrate 103, for example, by a pick-and-place process. After placement, a reflow process can be performed to physically and electrically connect the interposer 101 to the substrate 103 using the first external terminals 105. However, any suitable method for placing, connecting, and bonding the interposer 101 to the substrate 103 can be used.

[0021] After joining, a first underfill 107 can be applied between the interposer 101 and the substrate 103. In one embodiment, the first underfill 107 is a protective material used to protect the interposer 101 and the substrate 103 from operational and environmental influences, such as stresses caused by heat generation during operation. The first underfill 107 can be introduced by a capillary injection method or formed in the space between the interposer 101 and the substrate 103 by other means and can, for example, consist of a liquid epoxy that is distributed between the interposer 101 and the substrate 103 and then cured.

[0022] Fig. Figure 2 illustrates that after connecting the interposer 101 to the substrate 103, a first semiconductor chip 201 and a second semiconductor chip 203 are connected to the interposer 101 to form a chip-on-wafer device. In one embodiment, the first semiconductor chip 201 and the second semiconductor chip 203 can each be system-on-chip components, such as logic components, designed to work together to provide a desired functionality. However, any suitable functionality or combination of functionalities, such as logic chips, CPU chips, memory chips, input / output chips, combinations thereof, or the like, can be used, and all such types are intended to be fully included within the scope of the embodiments.

[0023] In one embodiment, the first semiconductor chip 201 and the second semiconductor chip 203 are placed on the interposer 101 after their fabrication, for example, using a pick-and-place process, to bring the second external terminals 205 of the first semiconductor chip 201 and the second semiconductor chip 203 into contact with conductive parts of the interposer 101. In one embodiment, the second external terminals 205 can be similar to the first external terminals 105, for example, by being made of a solder material. After placement, and in one embodiment where the second external terminals 205 are solder balls, a reflow process can be used to connect the first semiconductor chip 201 and the second semiconductor chip 203 to the interposer 101. However, any suitable terminal and method can be used.

[0024] Fig. Figure 3 illustrates that once the first semiconductor chip 201 and the second semiconductor chip 203 are in place, a second underfill 301 can be placed and an encapsulating agent 303 can be used to encapsulate the first semiconductor chip 201, the second semiconductor chip 203, and part of the interposer 101. In one embodiment, the second underfill 301 can be similar to the first underfill 107, which is described above in relation to Fig. As described in section 1. For example, the second underfill 301 can be a liquid epoxy introduced by capillary action. However, any suitable material and placement method can be used.

[0025] With regard to the second underfill 301, the second underfill 301 is not only dispensed between the interposer 101 and the first semiconductor chip 201 and between the interposer 101 and the second semiconductor chip 203. Furthermore, the second underfill 301 can be distributed such that it is located between the first semiconductor chip 201 and the second semiconductor chip 203. In some embodiments, the second underfill 301 fills the entire area between the first semiconductor chip 201 and the second semiconductor chip 203, while in other embodiments, the second underfill 301 fills a portion of the area between the first semiconductor chip 201 and the second semiconductor chip 203. Any suitable distribution can be used.

[0026] Once the second underfill 301 has been applied, the potting compound 303 is arranged to encapsulate the first semiconductor chip 201, the second semiconductor chip 203, and the second underfill 301. The encapsulation can be carried out in a mold (in Fig. 3 (not shown) which can be carried out, comprising an upper mold section and a lower mold section that is separable from the upper mold section. When the upper mold section is lowered to adjoin the lower mold section, a mold cavity can be formed for the first semiconductor chip 201 and the second semiconductor chip 203.

[0027] During the encapsulation process, the upper mold part can be positioned next to the lower mold part, thereby enclosing the first semiconductor chip 201 and the second semiconductor chip 203 within the mold cavity. Once enclosed, the upper and lower mold parts can form an airtight seal to control the inflow and outflow of gases from the mold cavity. After sealing, an encapsulation material 303 can be introduced into the mold cavity. The encapsulation material 303 can be a molding compound resin such as polyimide, PPS, PEEK, PES, a heat-resistant crystalline resin, combinations thereof, or similar materials. The encapsulation compound 303 can be introduced into the mold cavity before the upper and lower mold parts are aligned, or it can be injected into the mold cavity through an injection port.

[0028] Once the potting compound 303 has been introduced into the mold cavity, encapsulating the first semiconductor chip 201 and the second semiconductor chip 203, the potting compound 303 can be cured to provide optimal protection. While the exact curing process depends at least partially on the specific material chosen for the potting compound 303, in an embodiment where molding compound is chosen as the potting compound 303, curing could be achieved by a process such as heating the potting compound 303 to between approximately 100 °C and approximately 130 °C, such as 125 °C, for approximately 60 seconds to approximately 3000 seconds, such as 600 seconds. Additionally, initiators and / or catalysts can be included in the potting compound 303 to better control the curing process.

[0029] The curing process described above is merely an example and is not intended to limit the current embodiments, as a person skilled in the art will recognize. Other curing processes, such as irradiation or even curing the encapsulation compound 303 at ambient temperature, can also be used. Any suitable curing method can be employed, and all such methods are intended to be fully included within the scope of the embodiments described herein.

[0030] Fig. Figure 4 illustrates that after the encapsulation 303 is applied, the encapsulation 303 can be thinned to expose the first semiconductor chip 201 and the second semiconductor chip 203, creating a first surface 401 that comprises the encapsulation 303, the first semiconductor chip 201, and the second semiconductor chip 203, respectively. The thinning can be performed, for example, by a mechanical grinding or chemical-mechanical polishing (CMP) process, in which chemical etchants and abrasives are used to react and grind away the encapsulation material 303, the first semiconductor chip 201, and the second semiconductor chip 203 until the first semiconductor chip 201 and the second semiconductor chip 203 are exposed. In this way, both the first semiconductor chip 201 and the second semiconductor chip 203 can have a flat surface that is also planar with the encapsulation material 303.

[0031] The CMP process described above, although presented as an exemplary embodiment, is not intended to be limiting to the embodiments. Any other suitable removal process may be used to thin the encapsulation 303, the first semiconductor chip 201, and the second semiconductor chip 203. For example, a series of chemical etchings may be used. This process, and any other suitable process, may be used to thin the encapsulation 303, the first semiconductor chip 201, and the second semiconductor chip 203, and all such processes are intended to be fully included within the scope of the embodiments.

[0032] The Fig. Figures 5A-5C illustrate the placement of lids 501 or islands on the first surface 401 (e.g., the surface encompassing the encapsulation material 303, the first semiconductor chip 201, and the second semiconductor chip 203) along the corners of a first intersection between the first semiconductor chip 201 and the encapsulation material 303, and along the corners of a second intersection between the second semiconductor chip 203 and the encapsulation material 303. With respect to these figures, Fig. 5B a top view of the cross-section in Fig. Structure shown in 5A. Additionally, it shows Fig. 5C an enlarged close-up view of the section marked by the dashed line labeled 503 in Fig. 5B is shown.

[0033] In one embodiment, the covers 501 are attached to provide additional structural support during the heating processes between the encapsulation 303 and the first semiconductor chip 201 and the second semiconductor chip 203. As such, the covers 501 can be made of a substrate material having a first coefficient of thermal expansion that is lower than the second coefficient of thermal expansion of the encapsulation material 303. In a particular embodiment, the covers 501 can be made of a metal such as copper, stainless steel (e.g., SUS304, SUS430, etc.), combinations thereof, or similar materials. However, any suitable material can be used.

[0034] In one embodiment, the covers 501 can be positioned, for example, using a pick-and-place method, such that the covers 501 cross and cover parts of one or more interfaces between the underlying structures (e.g., cover parts of the interfaces between the encapsulation 303 and the first semiconductor chip 201). In this way, the encapsulation 303, the first semiconductor chip 201, and the covers 501 share a single interface.

[0035] Additionally, the covers 501 can be attached to the underlying structures (e.g., the first semiconductor chip 201 and the encapsulation 303) using a thermal interface material (TIM) (in the Fig. (5A-5C not shown separately). In one embodiment, the thermal interface material can be a viscous silicone compound similar to the mechanical properties of a grease or gel (e.g., 993-TC), wherein the thermal interface material can have a thermal conductivity (i.e., a “k-value”) in watts per meter-kelvin (W / mK) between about 1 W / mK and about 10 W / mK, such as about 4 W / mK. In other embodiments, the thermal interface material is a metal-based thermal paste containing silver, nickel, or aluminum particles suspended in the silicone grease. In still other embodiments, non-electrically conductive ceramic-based pastes filled with ceramic powders such as beryllium oxide, aluminum nitride, aluminum oxide, or zinc oxide can be used.

[0036] In embodiments where a gel or paste consistency is not desired, the thermal interface material may be a hard, solid material instead of a paste with a consistency similar to that of gels or greases. In this embodiment, the thermal interface material may be a thin sheet of a thermally conductive, solid material. In a particular embodiment, the solid thermal interface material may be a thin sheet of indium, nickel, silver, aluminum, combinations and alloys of these materials, or similar materials, or another thermally conductive solid material (e.g., X23-8018-33). Any suitably thermally conductive material (e.g., 8099-HB) may also be used, and all such materials are fully intended to be included within the scope of the embodiments.

[0037] The covers 501 can be placed in a corner of the encapsulation 303 such that the covers 501 cover at least part of the intersection between the first semiconductor chip 201 and the encapsulation 303. In this embodiment, each of the covers 501 can be aligned with the encapsulation 303 along at least two edges of the encapsulation 303. However, any suitable placement can be used.

[0038] In some embodiments, the lids 501 can have the shape of a square with a first thickness T1, a first width W1, and a first length L1. In one embodiment, the first thickness T1 can be between about 50 µm and about 500 µm. However, any suitable thickness can be used.

[0039] The first width W1 can be smaller than the width of the first semiconductor chip 201 (see Fig. 5C). For example, the first width W1 can be between approximately 3 mm and approximately 4 mm. However, any suitable width can be used.

[0040] Additionally, the first length L1 can be smaller than the length of the first semiconductor chip 291. For example, the first length L1 can be between approximately 3 mm and approximately 4 mm. However, any suitable dimensions can be used.

[0041] In addition, in this embodiment the covers 501 can overlap the first semiconductor chip 201 by a first overlap length L O and a first overlap width W O overlap. In one embodiment, the first overlap length L O be smaller than the length of the first semiconductor chip 201, e.g. between about 2 mm and about 3 mm, and the first overlap width W OIt can be smaller than the width of the first semiconductor chip 201, e.g., between about 2 mm and about 3 mm. However, any suitable length and width can be used.

[0042] As shown, in this embodiment, the covers 501 can cover a portion of the encapsulation material 303 extending away from the first semiconductor chip 201. In one embodiment, this portion of the encapsulation means 303 can extend over a first distance D1, which may be smaller than the length of the first semiconductor chip 201, and in particular embodiments, the first distance D1 can be less than about one-third of the length of the first semiconductor chip 201. For example, the first distance D1 can be between about 400 µm and about 1000 µm. However, any suitable dimension can be used.

[0043] Similarly, the covers 501 on a second side of the first semiconductor chip 201 can cover another section of the encapsulation 303 extending away from the first semiconductor chip 201. In one embodiment, this section of the encapsulation 303 can extend over a second gap D2, which may be smaller than the width of the first semiconductor chip 201, and in particular embodiments, the second gap D2 can be less than about one-third the width of the first semiconductor chip 201. For example, the second gap D2 can be between about 400 µm and about 1000 µm. However, any suitable dimension can be used.

[0044] The described placement of the lids 501 allows them to help protect and support the underlying structures during subsequent processing. Specifically, the use of a material with a lower coefficient of thermal expansion, combined with the described placement of the lids 501, helps to limit and suppress any expansion of the encapsulation material 303 during subsequent processing and operations where heat may be applied and / or generated. Thus, the presence of the lids 501 reduces stress at the corner.

[0045] Fig. Figure 6 shows a first annealing process (in Fig. 6 (represented by the wavy lines labeled 601), which can be used for curing or further curing the first underfill 107, the second underfill 301, and the encapsulating agent 303. In one embodiment, the first curing process 601 can be an oven curing process, wherein the structure is placed in an oven and surrounded by an inert environment. In one embodiment, the inert environment can be an inert gas such as argon, neon, or the like, or an environment that does not react with the exposed surfaces. Once the structure is in the oven, the oven uses heating elements to raise the temperature of the inert environment and thus raise the temperature of the encapsulating agent 303 and other structures.

[0046] In one embodiment, the first annealing process 601 can raise the temperature to a value between approximately -55 °C and approximately 260 °C. Furthermore, the first annealing process 601 can be carried out for a time between approximately 60 seconds and approximately 3600 seconds. However, any suitable time and temperature can be used.

[0047] Although a furnace annealing process is described above as one embodiment of the first annealing process 601, this is for illustrative purposes only and is in no way intended to be restrictive. Rather, any suitable annealing process, such as thermal rapid annealing, flash annealing, laser annealing, combinations thereof, or similar processes, can also be used. Any suitable annealing process can be used, and all such processes are to be fully included within the scope of the embodiments.

[0048] The Fig. Figures 7A-7B illustrate that after completion of the first annealing process 601, a ring 701, e.g., a stiffening ring, is placed on the substrate 103. In these figures, Fig. 7B an isometric view of the in Fig. The structure shown in cross-section along line BB' is visible in Figure 7A. In one embodiment, the ring 701 is used to provide additional support to the substrate 103 during subsequent manufacturing and use.

[0049] In one embodiment, the ring 701 can be positioned such that it is laterally separated from the encapsulation 303 by a third gap D3 and extends to enclose the encapsulation 303, forming a cavity. In one embodiment, the third gap D3 can be between approximately 3 mm and approximately 10 mm. While the lateral distance between the ring 701 and the encapsulation material 303 can be equidistant around each side of the encapsulation material 303 in some embodiments, in other embodiments the lateral distance around each side of the encapsulation material 303 can be different. However, all suitable dimensions and / or combinations of dimensions can be used.

[0050] In one embodiment, the ring 701 can be made of a metal such as copper, although any other suitable metal, such as aluminum or the like, can also be used. Similarly, dielectric materials, such as silicone, can also be used. Additionally, the ring 701 can be attached using an adhesive (not shown separately), such as epoxy, glue, polymer material, solder paste, thermal adhesive, or the like, and can be made of a thermally conductive material and / or contain thermally conductive particles. However, any suitable material and any suitable method of attachment can be used.

[0051] In one embodiment, the ring 701 can be placed on the substrate 103 and can have a third width W3 between about 1 mm and about 30 mm. Additionally, the ring 701 can have a second thickness T2 between about 0.1 mm and about 3 mm, which is greater than the combined thickness of the interposer 101, the encapsulating agent 303, and the lids 501, so that the ring 701 extends over the lids 501 by a fourth distance D4 between about 0 mm and about 2.9 mm. However, any suitable dimensions can be used.

[0052] The Fig. Figures 8A-8B illustrate that after the ring 701 is placed, a second annealing process (in Fig. 8A (shown by the wavy lines labeled 801) can be carried out to harden the device. In these figures, in Fig. 8B an isometric view of the in Fig. 8A can be seen in cross-section along line BB' of the structure shown. In one embodiment, the second annealing process 801 can be compared to the one described above with reference to Fig. The first annealing process 601 described in section 6 may be similar, for example, by being a furnace annealing process. However, the second annealing process 801 can be carried out at a temperature between about -55 °C and about 260 °C for a time between about 60 seconds and about 3600 seconds, although any suitable temperature and annealing process may be used.

[0053] By placing the lids 501 onto the encapsulation 303 and the first semiconductor chip 201 (or the second semiconductor chip 203), the lids 501 help to limit and reduce the stresses that can build up when the encapsulation 303 is heated. Because the lids 501 have a lower coefficient of thermal expansion than the adjacent materials, they can help to limit the expansion of the surrounding material. This limitation of expansion helps to prevent stress buildup and the formation of defects within the structure, thus contributing to increased efficiency and yield.

[0054] Fig. Figure 9 shows another embodiment in which the ring 701 is placed on the substrate 103 before the covers 501 are placed on it. In this embodiment, after the encapsulation compound 303 has been thinned to expose the first semiconductor chip 201 and the second semiconductor chip 203, the ring 701 is placed on the substrate 103 as described above. Fig. The ring 701 is positioned as described in section 7. It can be attached, for example, with a suitable adhesive, although any method for attaching the ring 701 can be used.

[0055] In Fig. Figure 9 further illustrates that the first annealing process 601 is carried out after the ring 701 is placed and before the covers 501 are placed. In one embodiment, the first annealing process 601 can be carried out as above with respect to Fig. The process described in section 6 can be carried out. However, any other suitable annealing process can also be used.

[0056] In another embodiment, the second annealing process 801 is carried out after the ring 701 has been placed and before the covers 501 have been placed, instead of the first annealing process 601. As such, either of the described annealing processes can be used once the ring 701 has been placed and before the covers 501 have been placed.

[0057] After a first annealing process 601 or a second annealing process 801, the lids 501 can be, as in Fig. Figure 10 shows the encapsulation material 303, the first semiconductor chip 201, and the second semiconductor chip 203 being placed on it. In one embodiment, the covers 501 can be positioned as above with respect to Fig. The lids 501 can be placed as described in section 5. For example, the lids 501 can be placed at the corners of the encapsulation 303 using a pick-and-place method. However, any other suitable method for placing the lids 501 can also be used.

[0058] In Fig. Figure 10 further illustrates that after placing the lids 501, the second of the first annealing process 601 or the second annealing process 801 (e.g., the annealing process that was not carried out before placing the lids 501) can be performed. For example, if the first annealing process 601 was previously performed, the second annealing process 801 can be carried out as described above. Fig. 8A is described. As a further example, if the second annealing process 801 has been carried out previously, the first annealing process 601 is carried out. However, any suitable annealing process can be used.

[0059] By rearranging the process steps (e.g., placement of the lids 501, placement of the ring 701, first annealing process 601, second annealing process 801, etc.), the manufacturing process can be modified while retaining the benefits of reduced stress. In particular, the lids 501 can still be used to limit the expansion of the encapsulation 303 (and other adjacent materials). However, a more flexible manufacturing process can be achieved.

[0060] Fig. Figure 11 shows another embodiment in which both the ring 701 and the covers 501 are used. In this embodiment, however, instead of the first annealing process 601 and the second annealing process 801, a single third annealing process 1201 (in Fig. 11 not shown, but further below in relation to Fig. 12 shown and discussed) used to cure the encapsulation material 303.

[0061] In this embodiment, the covers 501 are placed on the encapsulation 303 and the ring 701 on the substrate 103 before an annealing process is used to cure the structure, including the encapsulation 303. For example, the covers 501 can be arranged as above with respect to Fig. 5 described, and the ring 701 can be placed as above in relation to Fig. They can be placed as described in section 7. However, any suitable method can be used.

[0062] Fig. Figure 12 illustrates that after placing the two lids 501 and the ring 701, the third annealing process 1201 (in Fig. 12 (represented by the wavy lines labeled 1201). In one embodiment, the third annealing process 1201 can be an annealing process similar to either the first annealing process 601 or the second annealing process 801, e.g., a furnace annealing process. However, in one embodiment, the third annealing process 1201 can be carried out at a temperature between about -55 °C and about 260 °C. Furthermore, the third annealing process 1201 can be carried out for a time between about 60 seconds and about 3600 seconds. However, any suitable time and temperature can be used.

[0063] By placing the ring 701 and the lid 501 before any annealing processes, the use of two annealing processes (e.g., the first annealing process 601 and the second annealing process 801) can be combined into a single annealing process (e.g., the third annealing process 1201). In this way, the manufacturing process can be simplified while retaining the advantages of the encapsulation material 303, the lid 501, and the ring 701.

[0064] The Fig. 13A-13G show other embodiments which are used for the lid 501 instead of the one above with respect to the Fig. The square embodiment described in Figures 5A-5C can be used. Each of these embodiments shows that the covers 501 can have any suitable shape and size, as long as the covers 501 cover parts of both the first semiconductor chip 201 (or the second semiconductor chip 203) and the encapsulating means 303 at one corner, even if no specific point needs to be covered.

[0065] First, let's consider Fig. In this embodiment, the cover 501 has the shape of a triangle. Furthermore, the triangle is arranged such that two sides of the triangle are aligned with two sides of the encapsulation material 303, while the cover 501 nevertheless extends at least partially over a portion of the first semiconductor chip 201. However, any suitable placement can be used.

[0066] Fig. Figure 13B shows an embodiment in which the lid 501 is placed in a corner region but does not cover the exact corner of either the first semiconductor chip 201 or the encapsulation 303. In this embodiment, the lid 501 can be shaped as an “L”, with opposite, short ends of the “L” shape oriented with different sides of the encapsulation material 303, while longer ends of the “L” shape extend at least partially over the first semiconductor chip 201. By using the “L” shape, the lid 501 can still restrict the expansion of the encapsulation material 303 without covering the corner region. However, any suitable placement can be used.

[0067] Fig. Figure 13C shows an embodiment in which the lid 501 has the shape of a quarter circle. In this embodiment, the straight sides of the lid 501 are aligned with the side walls of the encapsulation means 303 and also cover the corner region of the encapsulation means 303. Additionally, a curved side of the lid 501 extends over the encapsulation 303 and also extends over at least a portion of the first semiconductor chip 201. However, any suitable placement can be used.

[0068] In Fig. Figure 13D shows an embodiment in which the cover 501 is a polygon. In this embodiment, the polygon has five or more sides (one five-sided embodiment is shown), and each side is straight. In such an embodiment, two of the sides of the cover 501 can be aligned with the underlying encapsulation material 303, and three or more sides can extend such that they are at least partially located over the first semiconductor chip 201. Additionally, one or more of the straight sides are located completely over the first semiconductor chip 201. However, any suitable number of sides and any suitable position can be used.

[0069] Fig. Figure 13E shows another embodiment in which the lid 501 has an “L” shape. In this embodiment, however, the “L” shape covers the corners of both the first semiconductor chip 201 and the encapsulation material 303. Thus, the long sides of the “L” shape can be aligned with the sides of the encapsulation 303, while the short sides extend so that they are at least partially located over the first semiconductor chip 201. However, any suitable location can be used.

[0070] Fig. Figure 13F shows another embodiment in which the lid 501 has the “L” shape, as above in relation to Fig. 13B described. In this embodiment, however, the lid 501 is divided into several different “L” shapes, each of the several different “L” shapes being separated from the others by a first gap. However, any suitable number of “L” shapes can be separated by any suitable distance.

[0071] Fig. Figure 13G shows an embodiment in which the cover 501 is a full circle instead of a quarter circle. In this embodiment, the cover 501 has several points located above an edge of the encapsulation 303, but the corner of the encapsulation 303 remains uncovered. Furthermore, the cover 501 curves further away from the edges of the encapsulation 303 and extends at least partially over the first semiconductor chip 201. However, any suitable placement can be used.

[0072] Fig. Figure 14 illustrates the placement of an optional second cover 1401 over the first semiconductor chip 201 and the second semiconductor chip 203. In one embodiment, the second cover 1401 can be used for heat dissipation and can be, for example, a heat exchanger, a vapor chamber cover, a combination thereof, or the like. In some embodiments, the second cover 1401 can be made of copper, aluminum, other metals, alloys, combinations thereof, or other materials with high electrical and / or thermal conductivities.

[0073] Additionally, the second lid 1401 can be sealed to the ring 701. For example, the second lid 1401 can be sealed to the ring 701 using a heat-clamping method, applying pressure and heat to seal the second lid 1401 to the ring 701. However, any suitable method can be used to seal the second lid 1401.

[0074] Fig. Figure 15 shows a further embodiment in which a thermal interface material 1501 is used to bridge the gap between the first semiconductor chip 201 and the second semiconductor chip 203 and the second cover 1401, thereby improving heat transfer. In one embodiment, the thermal interface material 1501 can be a viscous silicone compound with mechanical properties similar to a grease or gel, wherein the thermal interface material 1501 can have a thermal conductivity (i.e., a “k-value”) in watts per meter-kelvin (W / mK) between about 1 W / mK and about 10 W / mK, such as about 4 W / mK. In other embodiments, the thermal interface material 1501 is a metal-based thermal paste containing silver, nickel, or aluminum particles suspended in the silicone grease.In other embodiments, non-electrically conductive, ceramic-based pastes filled with ceramic powders such as beryllium oxide, aluminum nitride, aluminum oxide or zinc oxide can be used.

[0075] In embodiments where a gel or paste consistency is not desired, the thermal interface material 1501 can be a solid material instead of a paste with a consistency similar to that of gels or fats. In this embodiment, the thermal interface material 1501 can be a thin layer of a thermally conductive solid material that is sprayed or otherwise applied to the first semiconductor chip 201 and the second semiconductor chip 203. In a particular embodiment, the solid thermal interface material 1501 can be a thin sheet of indium, nickel, silver, aluminum, combinations and alloys of these materials, or similar or other thermally conductive solid material. Any suitably thermally conductive material can also be used, and all such materials and methods of application are fully intended to be included within the scope of the embodiments.

[0076] Additionally, in Fig. Figure 15 illustrates the use of an adhesive 1503 to bond the ring 701 to both the second cover 1401 and the substrate 103. In some embodiments, the adhesive 1503 is a metal-based thermal paste containing silver, nickel, or aluminum particles suspended in the silicone grease. In other embodiments, non-electrically conductive ceramic-based pastes filled with ceramic powders such as beryllium oxide, aluminum nitride, aluminum oxide, or zinc oxide can be used. In other embodiments, the adhesive 1503 can be a solid material instead of a paste with a consistency similar to that of gels or greases. In this embodiment, the adhesive 1503 can be a thin film of a thermally conductive, solid material.In a particular embodiment, the adhesive 1503, which is solid, can be a thin sheet of indium, nickel, silver, aluminum, combinations and alloys of these materials, or similar or any other thermally conductive solid material. Any suitable thermally conductive material can also be used, and all such materials are fully intended to be included within the scope of the embodiments.

[0077] Fig. Figure 16 shows a further embodiment in which the covers 501 are at the same level as the tops of the ring 701. Whereas in the embodiments described above, the top of the covers 501 can be at a different level than the ring 701 (e.g., separated by the fourth gap D4, as in Figure 16). Fig. (7A shown above), in this embodiment the top surface of the covers 501 is at the same height as the top surface of the ring 701. As such, the covers 501 are coplanar with the top surfaces of the ring 701.

[0078] Fig. Figure 16 additionally shows the placement of the second cover 1401 on the ring 701, as above in relation to Fig. 14 described. In this embodiment, however, because the lids 501 are coplanar with the ring 701, the second lid 1401 is also in physical contact with the lids 501. When the second lid 1401 is sealed with the ring 701, the second lid 1401 is additionally sealed with the lids 501.

[0079] Fig. Figure 17 shows another embodiment in which the second cover 1401 is used. In this embodiment, however, the second cover 1401 is not glued over the ring 701 and the covers 501, but rather onto the first semiconductor chip 201 and the second semiconductor chip 203 in order to increase heat dissipation from the first semiconductor chip 201 and the second semiconductor chip 203. In this embodiment, the second cover 1401 can be bonded with an adhesive (in Fig. (17 not shown separately) or glued using a heat clamping method as described above. However, any suitable method may be used to bond the second cover 1401.

[0080] In this embodiment, however, the second cover 1401 is dimensioned such that it fits between the covers 501, which are also attached to the first semiconductor chip 201 and the second semiconductor chip 203, since it is connected to the first semiconductor chip 201 and the second semiconductor chip 203. However, any suitable dimensions can be used.

[0081] By using the lids 501, as described above, stresses occurring at the corners of the encapsulation 303 can be reduced or eliminated. Specifically, because the coefficient of thermal expansion (CTE) of the lids 501 (e.g., metal) is lower than the CTE of the encapsulation material 303 (e.g., polymer), the expansion of the encapsulation material 303 is suppressed by the lids 501 when heated. Such stress reduction further reduces cracking and delamination, resulting in higher yields during the manufacturing process.

[0082] In one embodiment, a semiconductor device comprises: a first semiconductor chip connected to an interposer; an encapsulation encapsulating the first semiconductor chip; and a first lid in physical contact with both the first semiconductor chip and the encapsulation, the first lid intersecting an interface between the first semiconductor chip and the encapsulation. In another embodiment, the semiconductor device further comprises a second lid in physical contact with a second semiconductor chip and the encapsulation, the second semiconductor chip being different from the first semiconductor chip and the second lid being located in a different corner of the encapsulation than the first lid. In another embodiment, the semiconductor device further comprises a substrate connected to the interposer. In another embodiment, the semiconductor device further comprises a ring attached to the substrate.In one embodiment, the first cover comprises a metal. In one embodiment, the first cover is square. In one embodiment, the first cover is triangular.

[0083] According to another embodiment, a semiconductor device comprises: an interposer; an encapsulation over the interposer; and a first island material supporting both the encapsulation and a first semiconductor chip, the first island material being located in a first corner of the encapsulation, the first island material, the encapsulation, and the first semiconductor chip sharing a first single interface. In one embodiment, the first island material comprises a metal. In another embodiment, the semiconductor device further comprises a second island material supporting both the encapsulation and the first semiconductor chip, the second island material being separate from the first island material. In another embodiment, the semiconductor device further comprises a ring that is separate from the encapsulation. In another embodiment, the interposer is bonded to a substrate.In one embodiment, the semiconductor device further comprises a second semiconductor chip that is embedded in the encapsulation.

[0084] According to a further embodiment, a method for manufacturing a semiconductor device comprises the following steps: bonding a first semiconductor device to an interposer; encapsulating the first semiconductor device with an encapsulation material to form a first surface, the first surface comprising the encapsulation material and the first semiconductor device; attaching a first cover to a first corner of the first surface; and bonding a second cover to a second corner of the first surface, the second corner being different from the first corner. In one embodiment, bonding the first cover involves bonding a metal. In another embodiment, encapsulating the first semiconductor device encapsulates a second semiconductor device with the first semiconductor device, the first surface continuing to include the second semiconductor device.In one embodiment, the method further comprises bonding a third lid to a third corner of the first surface. In another embodiment, the method further comprises: placing a ring around the encapsulation element; and annealing the encapsulation element between placing the ring and bonding the first lid. In another embodiment, the method further comprises: placing a ring around the encapsulation material; and annealing the encapsulation material after placing the ring and bonding the first lid, with no annealing taking place between placing the ring and bonding the first lid.

Claims

[1] Semiconductor device with: a first semiconductor chip (201) connected to an interposer (101); an encapsulation material (303) that encapsulates the first semiconductor chip (201); and a first lid (501) that is in physical contact with both the first semiconductor chip (201) and the encapsulation material (303), wherein the first lid (501) crosses an interface between the first semiconductor chip (201) and the encapsulation material (303), wherein the first cover (501) overlaps the first semiconductor chip (201) by a first overlap length and by a first overlap width, and the first overlap length is less than a length of the first semiconductor chip (201) and the first overlap width is less than a width of the first semiconductor chip (201). [2] Semiconductor device according to claim 1, further comprising a second lid (501) which is in physical contact with a second semiconductor chip (203) and the encapsulation (303), wherein the second semiconductor chip (203) differs from the first semiconductor chip (201) and the second lid (501) is arranged in a different corner of the encapsulation (303) than the first lid (501). [3] Semiconductor device according to claim 1 or 2, further comprising a substrate (103) connected to the interposer (101). [4] Semiconductor device according to claim 3, further comprising a ring (701) attached to the substrate (103). [5] Semiconductor device according to one of the preceding claims, wherein the first cover (501) comprises a metal. [6] Semiconductor device according to any one of the preceding claims 1 to 5, wherein the first lid (501) is square in shape. [7] Semiconductor device according to any one of the preceding claims 1 to 5, wherein the first cover (501) is triangular in shape. [8] Semiconductor device with: an Interposer (101); an encapsulation (303) over the interposer (101); and a first island material (501) that carries both the encapsulation (303) and a first semiconductor chip (201), wherein the first island material (501) is arranged in a first corner of the encapsulation (303), wherein the first island material (501), the encapsulation (303) and the first semiconductor chip (201) share a first single interface, wherein the first island material (501) overlaps the first semiconductor chip (201) by a first overlap length and by a first overlap width, and the first overlap length is less than a length of the first semiconductor chip (201) and the first overlap width is less than a width of the first semiconductor chip (201). [9] Semiconductor device according to claim 8, wherein the first island material (501) comprises a metal. [10] Semiconductor device according to claim 8 or 9, further comprising a second island material (501) which carries both the encapsulation material (303) and the first semiconductor chip (201), wherein the second island material (501) is separated from the first island material (501). [11] Semiconductor device according to any one of the preceding claims 8 to 10, further comprising a ring (701) separated from the encapsulation (303). [12] Semiconductor device according to any one of the preceding claims 8 to 11, wherein the interposer (101) is bonded to a substrate (103). [13] Semiconductor device according to any one of the preceding claims 8 to 13, further comprising a second semiconductor chip (203) embedded in the encapsulation (303). [14] Semiconductor device according to claim 13, further comprising a second island material (501) supporting both the encapsulation (303) and the second semiconductor chip (203), wherein the second island material (501) is arranged in a second corner of the encapsulation (303), wherein the second island material (501), the encapsulation (303) and the second semiconductor chip (203) share a second single interface. [15] Method for manufacturing a semiconductor device, the method comprising: Bonding of a first semiconductor device (201) to an interposer (101); Encapsulating the first semiconductor device (201) with an encapsulation material (303) to form a first surface, wherein the first surface comprises the encapsulation material (303) and the first semiconductor device (201); Attaching a first cover (501) to a first corner of the first surface; and Attaching a second cover (501) to a second corner of the first surface, wherein the second corner is different from the first corner, wherein the first cover (501) overlaps the first semiconductor device (201) by a first overlap length and by a first overlap width and the second cover (501) overlaps the first semiconductor device (201) by a second overlap length and by a second overlap width, wherein the first overlap length and the second overlap length are less than a length of the first semiconductor device (201) and wherein the first overlap width and the second overlap width are less than a width of the first semiconductor device (201). [16] Method according to claim 15, wherein the application of the first cover (501) involves bonding a metal. [17] Method according to claim 15 or 16, wherein the encapsulation of the first semiconductor device (201) encapsulates a second semiconductor device (203) with the first semiconductor device (201), wherein the first surface further comprises the second semiconductor device (203). [18] Method according to claim 17, further comprising bonding a third lid (501) to a third corner of the first surface. [19] Method according to any one of the preceding claims 15 to 18, further comprising: Attaching a ring (701) around the encapsulation material (303); and Annealing of the encapsulation material (303) between the application of the ring (701) and the application of the first cover (501). [20] Method according to any one of the preceding claims 15 to 18, further comprising: Attaching a ring (701) around the encapsulation material (303); and Annealing of the encapsulation material (303) after the application of the ring (701) and the application of the first lid (501), wherein no annealing takes place between the application of the ring (701) and the application of the first lid (501).

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