Three-dimensional ferroelectric direct access storage devices and methods for training

Abstract

Method for forming a ferroelectric direct access memory device, FeRAM device, wherein the method comprises: Forming a layer stack (202) over a substrate (50), wherein the layer stack (202) comprises alternating layers of a first dielectric material (201) and a word line material, WL material (203); Forming first trenches (206) extending vertically through the layer stack (202) from an upper surface of the layer stack (202) away from the substrate (50) to a lower surface of the layer stack (202) facing the substrate (50), Lining the undersides and side walls of the first trenches (206) with a ferroelectric material (205), Formation of a channel material (207) in the first trenches (206) over the ferroelectric material (205), Filling the first trenches (206) with a second dielectric material (213), after filling the first trenches (206), forming second trenches (212) extending vertically through the layer stack (202), with the second trenches (212) being nested with the first trenches (206), Lining the undersides and side walls of the second trenches (212) with the ferroelectric material (205), Formation of the channel material (207) in the second trenches (212) above the ferroelectric material (205), Filling the second trenches (212) with the second dielectric material (213), and after filling the second trenches (212), forming source lines, SLs (218S), and bit lines, BLs (218B), in the first trenches (206) and the second trenches (212), the SLs (218S) and BLs (218B) extending vertically through the layer stack (202), wherein the WL material (203) is an electrically conductive material and the channel material (207) is a semiconductor oxide, wherein the channel material (207) comprises indium tungsten oxide.

Description

BACKGROUND

[0001] Semiconductor memory is used in integrated circuits for electronic applications, such as radios, televisions, mobile phones, and personal computers. Semiconductor memory falls into two main categories: volatile and non-volatile. Volatile memory includes random-access memory (RAM), which can be further divided into two subcategories: static random-access memory (SRAM) and dynamic random-access memory (DRAM). Both SRAM and DRAM are volatile because they lose their stored information when power is not supplied.

[0002] On the other hand, non-volatile memory can retain data stored within it even without a power supply. One type of non-volatile semiconductor memory is ferroelectric random-access memory (FeRAM or FRAM). Advantages of FeRAM include its fast read / write speeds and small size.

[0003] Prior art relating to the subject matter of the invention can be found, for example, in US 2020 / 0 185 411 A1, WO 2019 / 152 226 A1, US 2015 / 0 243 674 A1, DE 10 2020 130 890 A1, CN 1 11 354 734 A, US 2020 / 0 075 617 A1 and US 2014 / 0 264 525 A1.

[0004] The invention is defined by the main claim and the dependent claims. Further embodiments of the invention are described by the dependent claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] For a more complete understanding of the present invention and its advantages, reference is now made to the following descriptions in conjunction with the accompanying drawings. These show: Fig. 1 a cross-sectional view of a semiconductor device with integrated memory devices in one embodiment; Fig. 2-8, 9A, 9B, 10, 11, 12A-12E and 13 different views of a three-dimensional (3D) ferroelectric direct access memory device (FeRAM device) at different stages of manufacture in one embodiment; Fig. 14 a top view of a three-dimensional (3D) ferroelectric direct access memory device (FeRAM) in another embodiment; Fig. 15 a top view of a three-dimensional (3D) ferroelectric direct access memory device (FeRAM) in yet another embodiment; and Fig. 16 a flowchart of a method for forming a three-dimensional (3D) ferroelectric direct access memory device (FeRAM device) in some embodiments; DETAILED DESCRIPTION OF EXAMPLES OF EXECUTION

[0006] The following disclosure provides many different embodiments, or examples, for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, forming a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features can be formed between the first and second features, so that the first and second features may not be in direct contact.

[0007] Furthermore, terms relating to spatial relativity, such as "below," "under," "lower," "above," "upper," and the like, may be used herein for the convenience of discussion to describe the relationship of one element or feature to another element or feature (or other elements or features), as illustrated in the figures. The terms relating to spatial relativity are intended to encompass various orientations of the apparatus used or operated in addition to the orientation illustrated in the figures. The apparatus may be oriented in a different way (rotated by 90 degrees or otherwise), and the terms relating to spatial relativity used herein may likewise be interpreted accordingly.Throughout the discussion, unless otherwise specified, identical or similar reference symbols in different figures refer to the same or a similar element formed by the same or a similar process using the same or a similar material (materials).

[0008] In some embodiments, an LEDLED (litho-etch-dep-litho-etch-dep) method for forming high-density memory arrays in a ferroelectric random-access memory (FeRAM) device is disclosed. The LEDLED method comprises forming multiple first trenches in a layer stack over a substrate, wherein the layer stack comprises alternating layers of a first dielectric material and a word line (WL) material. The multiple first trenches are then filled by successively forming a ferroelectric material, a channel material, and a second dielectric material within the multiple first trenches. After the multiple first trenches are filled, multiple second trenches are formed in the layer stack, the multiple second trenches being nested with the multiple first trenches.The multiple second trenches are then filled with the ferroelectric material, the channel material, and the second dielectric material. Next, source lines (SLs) and bit lines (BLs) are formed in the multiple first and multiple second trenches. Compared to a reference method in which the multiple first and multiple second trenches are formed simultaneously, the LEDLED method allows the multiple first and multiple second trenches to be formed closer together for a higher integration density, while avoiding a fin structure collapse problem that occurs in the reference method.

[0009] Fig. Figure 1 shows a cross-sectional view of a semiconductor device 100 with integrated memory devices 123 (e.g., 123A and 123B) in one embodiment. In the illustrated embodiment, the semiconductor device 100 is a Fin field-effect transistor (FinFET) device with three-dimensional (3D) ferroelectric direct-access memory devices (FeRAM) 123, which are integrated in the back-end-of-line (BEOL) processing of semiconductor manufacturing. To avoid overcrowding, details of the memory devices 123 are shown in Figure 1. Fig. Figure 1 is not shown, but is shown in subsequent figures. It should be noted that FinFET is used here as a non-limiting example; the FeRAM devices 123 can be integrated in BEOL processing with any suitable device, such as planar devices or gate-all-around (GAA) devices.

[0010] As in Fig. As shown in Figure 1, the semiconductor device 100 has 100 different regions for forming various types of circuits. For example, the semiconductor device 100 may have a first region 110 for forming logic circuits, and may have a second region 120, for example, for forming peripheral circuits, input / output (I / O) circuits, ESD (electrostatic discharge) circuits, and / or analog circuits. Other regions for forming other types of circuits are possible and are fully included within the scope of this disclosure.

[0011] The semiconductor device 100 comprises a substrate 101. The substrate 101 can be a bulk substrate, such as doped or undoped silicon, or an active layer of a SOI substrate (semiconductor on an insulator). The substrate 101 can also comprise other semiconductor materials, such as germanium, a compound semiconductor comprising silicon carbide, gallium arsenic, gallium phosphide, gallium nitride, indium phosphide, indium arsenide, and / or indium antimonide, an alloy semiconductor comprising SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP, or combinations thereof. Other substrates, such as multilayer or gradient substrates, can also be used.

[0012] Electrical components, such as transistors, resistors, capacitors, inductors, diodes, or the like, are formed in or on substrate 101 in the front-end-of-line (FEOL) processing of semiconductor manufacturing. For example, Fig. Semiconductor fins 103 (also called fins) are formed such that they protrude above the substrate 101. Insulation regions 105, such as STI regions (shallow trench insulation), are formed between or around the semiconductor fins 103. Gate electrodes 109 are formed over the semiconductor fins 103. Gate spacers 111 are formed along the sidewalls of the gate electrodes 109. Source / drain regions 107, such as epitaxial source / drain regions, are formed on opposite sides of the gate electrodes 109. Contacts 113, such as gate contacts and source / drain contacts, are formed over their respective underlying electrically conductive features (e.g., gate electrodes 109 or source / drain regions 107) and electrically coupled to them. One or more dielectric layers 117, such asA dielectric intermediate layer (ILD) is formed over the substrate 101 and around the semiconductor fins 103 and the gate electrodes 109. Other electrically conductive features, such as interconnect structures with conductive traces 115 and vias 114, can also be formed in one or more of the dielectric layers 117. The FinFETs in . Fig. 1 can be formed using any suitable method known per se or used in the prior art; details are not repeated here. For the sake of simplicity, the substrate 101, the electrical components (e.g., FinFETs) formed in or on the substrate 101, the contacts 113, conductive features 115 / 114, and the one or more dielectric layers 117 are collectively referred to as substrate 50.

[0013] With further reference to Fig. 1. A dielectric layer 119, which may be an etch stop layer (ESL), is formed over one or more dielectric layers 117. In one embodiment, the dielectric layer 119 is formed from silicon nitride using plasma-enhanced physical vapor deposition (PECVD), although other dielectric materials, such as nitride, carbide, combinations thereof, or the like, and alternative techniques for forming the dielectric layer 119, such as low-pressure chemical vapor deposition (LPCVD), photovoltaics (PVD), or the like, may alternatively be used. In some embodiments, the dielectric layer 119 is omitted. Next, a dielectric layer 121 is formed over the dielectric layer 119. The dielectric layer 121 may be any suitable dielectric material, such as silicon oxide, silicon nitride, or the like, formed using a suitable method, such as…a PVD, a CVD, or the like. One or more storage devices 123A, each comprising several storage cells, are formed in the dielectric layer 121 and coupled to electrically conductive features (e.g., vias 124 and conductive lines 125) in the dielectric layer 121. Various embodiments of the storage devices 123A or 123B are shown in . Fig. 1 (e.g. 3D FeRAM devices 200, 200A and 200B) are discussed in detail below.

[0014] Fig. Figure 1 further shows a second layer of storage devices 123B formed above the storage devices 123A. The storage devices 123A and 123B can have the same or a similar structure and can be collectively referred to as storage devices 123. The example of Fig. Figure 1 shows two layers of storage devices 123 as a non-limiting example. Other numbers of layers of storage devices 123, such as one layer, three layers, or more, are also possible and are said to be fully included within the scope of this disclosure. The one or more layers of storage devices 123 are formed in a storage region 130 of the semiconductor device 100 and can be formed in the back-end-of-line (BEOL) processing of the semiconductor fabrication. The storage devices 123 can be formed in the BEOL processing at any suitable positions within the semiconductor device 100, such as (directly above) the first region 110, above the second region 120, or above several regions.

[0015] In the example of Fig. 1. The memory devices 123 occupy part but not the entire area of ​​the memory region 130 of the semiconductor device 100, since other features, such as conductive traces 125 and vias 124, can be formed in other areas of the memory region 130 for connection with conductive features above and below the memory region 130. To form the memory devices 123A or 123B, in some embodiments a mask layer, such as a structured photoresist layer, is formed that covers some areas of the memory region 130, while the memory devices 123A or 123B are formed in other areas of the memory region 130 that are exposed by the mask layer. After the memory devices 123 have been formed, the mask layer is then removed.

[0016] With further reference to Fig. 1. After the storage area 130 has been formed, an interconnect structure 140, comprising the dielectric layer 121 and the electrically conductive features (e.g., vias 124 and conductive traces 125), is formed in the dielectric layer 121 above the storage area 130. The interconnect structure 140 can electrically connect the electrical components formed in / on the substrate 101 to form functional circuits. The interconnect structure 140 can also electrically couple the storage devices 123 to the components formed in / on the substrate 101, and / or couple the storage devices 123 to conductive paths formed above the interconnect structure 140 for connection to an external circuit or device. The formation of an interconnect structure is known in the prior art, therefore details are not repeated here.

[0017] In some embodiments, the storage devices 123 are electrically coupled to the electrical components (e.g., transistors) formed on the substrate 50, e.g., by the vias 124 and conductive lines 125, and in some embodiments are controlled by functional circuits of the semiconductor device 100 or accessed by them (e.g., written to or read from them). Additionally or alternatively, in some embodiments, the storage devices 123 are electrically coupled to conductive paths formed above an upper metal layer of the interconnect structure 140, in which case the storage devices 123 can be directly controlled or accessed by an external circuit (e.g., another semiconductor device) without the involvement of the functional circuits of the semiconductor device 100. Although additional metal layers (e.g.,the interconnect structure 140) via the storage devices 123 in the example of . Fig. 1. The storage devices 123 can be formed in an upper (e.g., top) metal layer of the semiconductor device 100; these and other modifications are to be fully included within the scope of this disclosure.

[0018] Fig. Figures 2-8, 9A, 9B, 10, 11, 12A-12E, and 13 show different views (e.g., a perspective view, a cross-sectional view, a top view) of a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) at various stages of fabrication in one embodiment. For the sake of simplicity, a 3D FeRAM device may also be referred to as a 3D memory device or simply a memory device in this discussion. The 3D memory device 200 is a three-dimensional memory device made of a ferroelectric material. The 3D memory device 200 may be referred to as memory device 123A and / or 123B in Fig. 1. It should be noted that, for the sake of simplicity, not all features of the 3D storage device 200 are shown in the figures, and the figures may only show a section of the 3D storage device 200.

[0019] Now, reference is made to Fig. Figure 2 shows a perspective view of the storage device 200 at an early stage of fabrication. A layer stack 202 is formed over the substrate 50. The layer stack 202 has alternating layers of a dielectric material 201 and an electrically conductive material 203. Each layer of the dielectric material 201 in the layer stack 202 can also be referred to as a dielectric layer 201, and each layer of the electrically conductive material 203 in the layer stack 202 can also be referred to as an electrically conductive layer 203. As will be discussed below, the electrically conductive material 203 is used to form word lines (WLs) of the 3D storage device 200 and can therefore also be referred to as a word line material 203.

[0020] To form the layer stack 202, in some embodiments the dielectric layer 201 is first formed by depositing a suitable dielectric material, such as silicon oxide, silicon nitride, or the like, onto the substrate 500 using a suitable deposition method, such as PVD, CVD, atomic layer deposition (ALD), or the like. Next, the electrically conductive layer 203 is formed over the dielectric layer 201. In some embodiments, the electrically conductive layer 203 is formed from an electrically conductive material, such as a metal or a metal-containing material. Examples of materials for the electrically conductive layer 203 include Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt, or the like. The electrically conductive layer 203 can be formed, for example, by PVD, CVD, ALD, combinations thereof, or the like.The preceding deposition processes are repeated until a predetermined number of layers are formed in the layer stack 202. In the illustrated embodiment, the topmost layer of the layer stack 202 is a dielectric layer 201, which can be referred to as the topmost dielectric layer 201T of the layer stack 202. It should be noted that the number of layers in the layer stack 202 can be any suitable number and is not limited to the number shown in the illustration. Fig. The second example shown is limited.

[0021] Next, in Fig. Three first trenches 206 (which can also be referred to as openings, recesses, or fissures) are formed in the layer stack 202 and extend through the layer stack 202 to expose the substrate 50. The first trenches 206 can be formed, for example, using photolithographic and etching techniques. In the illustrated embodiment, the first trenches 206 extend from a lower surface of the layer stack 202, which faces the substrate 50, to an upper surface of the layer stack 202, which is farther from the substrate 50. In the example of Fig. 3. The first trenches 206 extend continuously between opposite side walls of the layer stack 202, so that the first trenches cut through the layer stack 202 and divide the layer stack 202 into several slices (e.g., fin-shaped structures) that are separated from each other (e.g., spaced apart). It should be noted that Fig. Figure 3, for the sake of simplicity, shows only one of the first trenches 206. With preliminary reference to Fig. 9B shows Fig. 9B several first trenches 206 nested with several second trenches 212 formed in the layer stack 202 in a subsequent processing step, wherein the first trenches 206 and the second trenches 212 are filled with other materials (e.g. 205, 207, 209, 211, 213) to form the 3D storage device 200, the details of which will be discussed below.

[0022] Next, in Fig. 4. A ferroelectric material 205 is formed in the first trenches 206 along the side walls and bottom surfaces of the first trenches 206 (e.g., conforming). The ferroelectric material 205 can also be formed over the top surface of the layer stack 202. Next, a channel material 207 is formed over the ferroelectric material 205 (e.g., conforming). Next, a cover layer 209 (e.g., conforming) is formed over the channel material 207, and an oxide liner 211 is formed over the cover layer 209 (e.g., conforming).

[0023] In some embodiments, the ferroelectric material 205 BaTiO3, PbTiO3, PbZrO3, LiNbO3, NaNbO3, KNbO3, KTaO3, BiScO3, BiFeO3, Hf 1-x He x O, Hf 1-x La x O, Hf 1-x Y x O, Hf 1-x Gd x O, Hf 1-x Al x O, Hf 1-x Zr x O, Hf 1-x Ti x O, Hf 1-x Ta xO, AlScN, the like, combinations thereof, or multiple layers thereof, and can be formed using a suitable formation process, such as PVD, CVD, ALD, or the like. The ferroelectric material 205 can also be referred to as a ferroelectric film.

[0024] In some embodiments, the channel material 207 is a semiconductor material, such as amorphous silicon (a-Si), polysilicon (Poly-Si), a semiconductor oxide (e.g., indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin oxide (ITO), or indium tungsten oxide (IWO)), or the like. The channel material 207 can be formed, for example, by PVD, CVD, ALD, combinations thereof, or the like.

[0025] In some embodiments, the cover layer 209 is formed from a dielectric material. The cover layer 209 acts as a protective layer for the channel material 207 and prevents impurities, such as H, Cl, or F, from diffusing into the channel material 207 during subsequent processing (e.g., a subsequent etching process). In one embodiment, the cover layer 209 is formed from a high-k dielectric material with a dielectric constant (e.g., k-value) greater than approximately 7.0 or even higher. Examples of high-k dielectric materials include HfO₂, TiO₂, HfZrO, Ta₂O₃, HfSiO₄, ZrO₂, ZrSiO₂, and other suitable materials. The high-k dielectric material of the cover layer 209 can be formed by atomic layer deposition (ALD) and / or other suitable methods.

[0026] In some embodiments, the dielectric constant K capthe covering layer 209 (e.g. of a dielectric material) is higher than the dielectric constant K fer of the ferroelectric material 205 (e.g. K cap > K fer ), to enable reliable switching of the direction of the electrical polarization of the ferroelectric material 205. As will be discussed in more detail below, the electrical polarization direction of the ferroelectric material 205 is used to store the digital information (e.g., a bit of 0 or 1) of each memory cell of the 3D storage device 200. The electrical polarization direction of the ferroelectric material 205 is switched by an electric field applied to the ferroelectric material 205, the electric field being proportional to a voltage applied across the ferroelectric material 205. With preliminary reference to Fig. During operation (e.g. a write operation) of a memory cell 225 of the 3D storage device 200, a voltage V is applied. total e.g., applied between a word line (WL) 203 and a respective source line (SL) 218. The voltage V total is shared by the various material layers between the WL 203 and the SL 218, such as the ferroelectric material 205, the channel material 207, and the cover layer 209 in the example of 12C. In other words, part of the voltage V is total A voltage is applied to each layer (e.g., 205, 207, or 209) of the material between WL 203 and SL 218. Since the voltage applied to each material layer is inversely proportional to its dielectric constant, it can be advantageous to determine the dielectric constant K. cap to select the cover layer 209 such that it is higher than the dielectric constant K ferof the ferroelectric material 205, so that a significant percentage of the voltage V total The current is applied over the ferroelectric material 205 to enable the switching of the electrical polarization direction of the ferroelectric material 205. For similar reasons, in some embodiments the dielectric constant of the channel material 207 is also chosen to be higher than the dielectric constant K. fer of the ferroelectric material 205. In some embodiments, the dielectric constant K cap the covering layer 209 is chosen such that it is twice, five times, ten times or more the dielectric constant K fer of the ferroelectric material 205. Materials with a high dielectric constant, such as AlO x(with a k-value between approximately 9 and approximately 11), HfO (with a k-value between approximately 25 and approximately 27) and TaO2 (with a k-value between approximately 40 and 80) can therefore advantageously be used as the material for the cover layer 209, especially in applications where the stress V total is low. In other embodiments, the dielectric constant K can be cap the dielectric constant K of the covering layer 209 is essentially equal to that of the covering layer. fer of the ferroelectric material or be smaller than it, e.g. in applications where the voltage V total is sufficiently high so that the voltage applied across the ferroelectric material 205 is higher than the switching voltage for the ferroelectric material 205.

[0027] With further reference to Fig. 4. The oxide liner 211 comprises an oxide, such as silicon oxide, and in some embodiments is formed using a suitable formation process, such as an ALD or the like. In some embodiments, the oxide liner 211 protects, for example, sidewall sections of the ferroelectric material 205, the channel material 207, and the cover layer 209 in a subsequent etching process (see Figure 4). Fig. 5).

[0028] Next, in Fig. 5. A suitable etching process, such as an anisotropic etching process, is carried out to remove first sections of the oxide liner 211, first sections of the cover layer 209, first sections of the channel material 207, and first sections of the ferroelectric material 205 from the undersides of the first trenches 206, and consequently the upper surface of the substrate 50 at the underside of the first trenches 206 is exposed. In the illustrated embodiment, due to the anisotropy of the etching process, second sections of the oxide liner 211, second sections of the cover layer 209, second sections of the channel material 207, and second sections of the ferroelectric material 205, which are arranged between the layer stack 202 and side walls 211S of the oxide liner 211 facing the first trench 206, remain after the anisotropic etching process.It should be noted that the second sections of the cover layer 209, the second sections of the channel material 207, and the second sections of the ferroelectric material 205 have L-shaped cross-sections and lower sections located between the second sections of the oxide liner 211 and the substrate 500. As shown in . Fig. As shown in Figure 5, each of the side walls 211S of the oxide liner 211 is vertical (e.g., in the same vertical plane in Fig. 5) aligned with the respective side walls of the second sections of the cover layer 209, the second sections of the channel material 207 and the second sections of the ferroelectric material 205.

[0029] Next, in Fig. 6. A dielectric material 213 is formed in the first trenches 206 to fill the remaining space in the first trenches 206. In some embodiments, the dielectric material 213 is formed by depositing a suitable dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable deposition method, such as ALD or the like. The dielectric material 213 can overfill the first trenches 206 and can form above the top surface of the layer stack 202. Next, a planarization process, such as chemical-mechanical planarization (CMP), is carried out to remove excess sections of the ferroelectric material 205, the channel material 207, the cover layer 209, the oxide liner 211, and the dielectric material 213 from the top surface of the layer stack 202. As shown in Fig. As shown in Figure 6, the remaining sections of the ferroelectric material 205, the channel material 207 and the cover layer 209 after the planarization process have L-shaped cross-sections.

[0030] Next, in Fig. Seven second trenches 212 were formed in the layer stack 202. The second trenches 212 are similar to the first trenches 206 and can be formed using the same or a similar procedure. For the sake of simplicity, it is shown Fig. 7 only a second trench 212. Fig. Figure 9B shows several second trenches 212 in the layer stack 202, which are nested with the first trenches 206. As in Fig. As shown in Figure 9B, the first trenches 206 and the second trenches 212 are formed alternately in the layer stack 202.

[0031] Next, in Fig. 8. The ferroelectric material 205, the channel material 207, the cover layer 209, and the oxide liner 211 are successively formed in the second trenches (e.g., conformally). The materials and formation methods of the ferroelectric material 205, the channel material 207, the cover layer 209, and the oxide liner 211 can be compared to those described above with reference to Fig. The points discussed in section 4 are the same or similar, therefore details will not be repeated.

[0032] Next, in Fig. 9A A suitable etching process, such as an anisotropic etching process, is carried out to remove sections of the dielectric material 213, sections of the oxide liner 211, sections of the cover layer 209, sections of the channel material 207, and sections of the ferroelectric material 205 from the undersides of the second trenches 212. Details of the etching process can be found in those above with reference to Fig. The points discussed in point 5 are the same or similar, which is why the details will not be repeated.

[0033] Next, the dielectric material 213 is formed in the second trenches 212 and completely fills them. A planarization process, such as a CMP, is then carried out to remove excess sections of the oxide liner 211, the cover layer 209, the channel material 207, and the ferroelectric material 205 from the top surface of the layer stack 202.

[0034] Fig. Figure 9B shows a cross-sectional view of the 3D storage device 200. Fig. 9A along cross-section AA. It should be noted that Fig. 9B shows a larger section of the 3D storage device than Fig. 9A and therefore shows several first trenches 206, which are nested with several second trenches 212. The first trenches 206 and the second trenches 212 in Fig. Trenches 9B are filled with various layers of materials (e.g., 205, 207, 209, 211, and 213) to form storage cells in a subsequent processing step. The first trenches 206 and the second trenches 212 can be collectively referred to as trenches 206 / 212.

[0035] The disclosed method forms the structure of Fig. 9A and Fig. 9B, by forming first trenches 206 (e.g., using lithographic and etching techniques), filling the trenches 206 (e.g., by depositing layers of materials 205 / 207 / 209 / 211 / 213), forming the second trenches 212 (e.g., using lithographic and etching techniques), and filling the second trenches 212 (e.g., by depositing layers of materials 205 / 207 / 209 / 211 / 213). Therefore, the disclosed method can also be referred to as an LEDLED (Litho-Etch-Dep-Litho-Etch-Dep) method. In comparison with a reference method in which the first trenches 206 and the second trenches 212 are formed simultaneously (e.g.,(through an identical etching process), the disclosed LEDLED method enables trenches 206 / 212 to be formed closer together without suffering from the problem of “fin collapse” discussed below, thereby enabling storage cells to be formed at a higher density than is otherwise achievable.

[0036] As the semiconductor manufacturing process progresses, the feature size decreases to achieve higher integration density. To increase the memory cell density of the 3D memory device 200, it can be advantageous to form the layer stack 2020 with a large number of layers (e.g., 201, 203) and to form the trenches 206 / 212 with a smaller distance W1 between adjacent trenches 206 / 212. If the trenches 206 / 212 are formed simultaneously, then the sections of the layer stack 202 located between adjacent trenches 206 / 212 (which can be referred to as fin-shaped structures of the layer stack 202) exhibit a high aspect ratio of H / W1, where H represents the height of the layer stack 202. Fin-shaped structures of the layer stack 202 with a high aspect ratio can collapse during subsequent processing, causing defects in the 3D storage device 200.By using the disclosed LEDLED method, the aspect ratio of the fin-shaped structures during the formation of the first trenches 206 is H / W2, which is much smaller than H / W1, since the distance W2 between adjacent first trenches is greater than W1. Similarly, when forming the second trenches 212, the first trenches 206 are already filled, and the aspect ratio of the fin-shaped structure (which has the filled trenches 206) is H / W3, which is much smaller than H / W1. Consequently, the problem of fin collapse associated with a high aspect ratio is avoided by the disclosed LEDLED method, and the device reliability and production yield are improved.

[0037] Next, in Fig. Ten isolation regions 215 are formed in the trenches 206 / 212 and extend vertically through the layer stack 202. The isolation regions 215 can also be referred to as memory cell isolation regions 215 or dielectric plugs 215. In some embodiments, to form the isolation regions 215, a structured mask is formed over the top surface of the layer stack 202, wherein structures (e.g., openings) of the structured mask layer correspond to positions of the isolation regions 215. Next, an anisotropic etching process is carried out using the structured mask layer as an etching mask to form openings in the layer stack 202 that extend vertically through the layer stack 202. Next, the openings in the layer stack 202 are filled with a dielectric material, such as silicon oxide, silicon nitride, or the like, using a suitable forming method, such as…a CVD, a PVD, an ALD, or the like. A planarization process, such as a CMP, can then be carried out to remove excess sections of the dielectric material from the top surface of the layer stack 202, and remaining sections of the dielectric material in the openings form the insulation regions 215.

[0038] In the example of Fig. 10. The width of the insulation regions 215 is substantially equal to the width of a respective trench 206 / 212 in which the insulation is located, such that each insulation region 215 in the respective trench 206 / 212 physically contacts side walls of the layer stack 202 facing the corresponding trench. In other embodiments, the width of the insulation region 215 may be smaller than the width of the trench 206 / 212, and each insulation region 215 in a trench 206 / 212 extends continuously between side walls of the ferroelectric material 205 in the trench. In other words, each insulation region 215 physically contacts opposite side walls of the ferroelectric material 205 in the trench but does not extend through the ferroelectric material 205.

[0039] Next, in Fig. Eleven openings 216 (e.g., by photolithographic and etching techniques) are formed in the oxide liner 211 and the dielectric material 213, the openings 216 extending from the upper surface of the layer stack 202, which faces away from the substrate 50, to the lower surface of the layer stack, which faces the substrate 50. In the example of Fig. 11 Sidewalls of the cover layer 209 are free. The openings 16 are filled with an electrically conductive material (e.g., 217, 219) to form source lines (SLs) 218S and bit lines (BLs) 281B in a subsequent processing step. In other embodiments, the openings 216 are designed to be wider than the openings 216 of Fig. 11, and they lay the side walls of the channel material 207 (see Fig. 15) expose or reveal the side walls of the ferroelectric material 205 (see Fig. 14) free.

[0040] Next, in Fig. 12A A barrier layer 217 is formed in the openings 216 (e.g., conformal) to line the sidewalls and bottom surfaces of the openings 216. The barrier layer 217 may be titanium nitride, although another suitable material, such as tantalum nitride, titanium, tantalum, or the like, may also be used. A suitable forming process, such as CVD, ALD, or the like, may be performed to form the barrier layer 217. Next, an optional anisotropic etching process is performed to remove sections of the barrier layer 217 from the bottom surfaces of the openings 216, exposing the substrate 50 at the bottom surface of the openings 216. Next, an electrically conductive material 219, such as Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt or the like, is formed to fill the openings 216. A planarization process, such asA CMP (Complete Material Processing) can next be performed to remove excess sections of the barrier layer 217 and excess sections of the electrically conductive material 219 from the top surface of the layer stack 202. Remaining sections of the barrier layer 218 and remaining sections of the electrically conductive material 219 in the openings 216 form conductive lines 218. In the illustrated embodiments, the conductive lines 218 are metal columns or pillars extending vertically through the layer stack 202. The conductive lines 218 can also be referred to as the source lines (SLs) 218S or bit lines (BLs) 218B of the 3D storage device.

[0041] Fig. Figure 12B shows a top view of the storage device 200 of Fig. 12A. Fig. 12C, Fig. 12D and Fig. Figure 12E shows cross-sectional views of the storage device 200. Fig. 12B each along cross-sections BB, CC and DD respectively. It should be noted that for clarity... Fig. 12B, Fig. 12C, Fig. 12D and Fig. 12E may represent a section of the 3D storage device 200 that is larger or smaller than the one in Fig. Section 12A of the 3D storage device 200 is shown.

[0042] As seen in the top view of Fig. As shown in Figure 12B, each isolation region 215 extends continuously from a first side wall of the layer stack 202 (e.g., a first side wall of the uppermost dielectric layer 201T of the layer stack 202) to a second side wall of the layer stack 202 (e.g., a second side wall of the uppermost dielectric layer 201T of the layer stack 202), which faces the first side wall of the layer stack 202, wherein the first and second side walls of the layer stack 202 are side walls of the layer stack exposed by the same trench 206 / 212. In other words, the width of the isolation region 215, extending along the horizontal direction of Fig. 12B is measured, equal to a distance between inner sidewalls of the layer stack 202, which are exposed by the same trench and face each other. Furthermore, each of the conductive lines 218 extends continuously from a first sidewall of the cover layer 209 to a second sidewall of the cover layer 209, which faces the first sidewall of the cover layer 209. In other words, a width of the conductive line 218, which extends along the horizontal direction of Fig. 12B is measured, which is equal to a distance between inner side walls of the cover layer 209 in a trench that are facing each other.

[0043] In Fig. In section 12B, some, but not all, of the 225 memory cells of the 3D storage device 200 are highlighted by dashed boxes. Memory cells 225 are also indicated by dashed boxes in... Fig. 12C and Fig. Highlighted in 12E. As in Fig. As shown in figures 12A to 12E, each memory cell 225 is a transistor with an embedded ferroelectric film 205. Within each memory cell 225, the electrically conductive layer 203 acts (see e.g. Fig. 12C) as the gate electrode of the transistor, the conductive lines 218S and 218B (see e.g. Fig. 12B) act as the source / drain regions of the transistor, and the channel material 207 acts as the channel layer between the source / drain regions. The dashed line 226 in Fig. Figure 12B shows the channel region formed in the channel material 207 during operation of the 3D storage device 200, for example, when a voltage is applied to the gate of the transistor, causing the transistor to turn on. The electrical polarization direction of the ferroelectric film 205 in each memory cell 225 indicates the digital information (e.g., a "0" or "1") stored in the memory cell 225 and determines the threshold voltage of the transistor of the memory cell 225, with further details discussed below.

[0044] In the context of storage devices, the electrically conductive layer 203 (e.g. the gate electrode) in each memory cell 225 is referred to as the word line (WL) of the memory cell, and the conductive lines 218S and 218B (e.g. the source / drain regions) can be referred to as the source line (SL) and the bit line (BL) of the memory cell.

[0045] As in Fig. As shown in Figure 12A, each of the electrically conductive layers 203 (e.g., WL) of the storage device 200 electrically connects several storage cells that are formed along the same horizontal plane (e.g., at the same vertical distance from the substrate 50). Furthermore, as shown in Fig. As shown in Figure 12C, each SL or BL 218 electrically connects several vertically stacked stacked memory cells 225. Therefore, the disclosed 3D storage device 200 achieves efficient sharing of the WLs, BLs, and SLs of multiple memory cells 225, and the 3D structure of the memory cells 225 allows multiple layers of the memory cells 225 to be easily stacked together to form high-density memory arrays.

[0046] Fig. 12C and Fig. Figure 12E shows different shapes for the cross-sections of the ferroelectric material 205, the channel material 207, and the cover layer 209 at different positions of the 3D storage device 200. For example, in Fig. 12E, which defines the cross-section along a vertical plane (perpendicular to the upper surface of the substrate 50), which is defined by the dielectric material 213 (e.g. along the cross-section DD in Fig. Figure 12B) shows that the ferroelectric material 205, the channel material 207, and the cover layer 209 have L-shaped cross-sections. Fig. 12C, which defines the cross-section along a vertical plane (perpendicular to the upper surface of the substrate 50), which is defined by the conductive lines 218 (e.g. along the cross-section BB in Fig. 12B) shows that the ferroelectric material 205, the channel material 207 and the cover layer 209 have rectangular cross-sections.

[0047] With reference to Fig. To perform a write operation on a specific memory cell 225, a write voltage is applied across a section of the ferroelectric material 205 within the memory cell 225. The write voltage can be applied, for example, by applying a first voltage to the gate electrode 203 of the memory cell 225 and a second voltage to the source / drain regions 218S / 218B. The voltage difference between the first and second voltages establishes the polarization direction in the ferroelectric material 20. Depending on the polarization direction of the ferroelectric material 205, the threshold voltage VT of the corresponding transistor of the memory cell 225 can be switched from a low threshold voltage VL to a high threshold voltage VH, or vice versa.The threshold voltage value (VL or VH) of the transistor can be used to indicate a bit of "0" or "1" stored in the memory cell.

[0048] To perform a read operation on memory cell 225, a read voltage, which is a voltage between the low threshold voltage VL and the high threshold voltage VH, is applied to the gate electrode 203. Depending on the polarization direction of the ferroelectric material 205 (or the threshold voltage VT of the transistor), the transistor of memory cell 225 may or may not be switched on. Consequently, if a voltage is applied, for example, between the source / drain regions 218S and 218B, an electric current may or may not flow between these regions. The electric current can therefore be detected to determine the digital bit stored in the memory cell.

[0049] Next, in Fig. Thirteen contacts 227 are formed above the layer stack 202 to electrically couple the conductive lines 218. To form the contacts 227, dielectric layers 221 and 223 are formed above the layer stack 202. Openings are formed in the dielectric layers 221 and 223 to expose underlying conductive lines 219. Electrically conductive material(s) are formed in the openings to create the contacts 227.

[0050] In some embodiments, the dielectric layer 221 is formed from silicon nitride, although another suitable dielectric layer, such as silicon oxynitride or silicon carbide, can also be used. The dielectric layer 221 can be formed, for example, by CVD, ALD, or the like. The dielectric layer 223 can be formed from a dielectric material, such as phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like, and can be deposited by any suitable method, such as CVD, PECVD, or FCVD. The openings in the dielectric layers 221 and 223 can be formed by photolithographic and etching techniques. The electrically conductive material(s) filling the opening can be any suitable conductive material, such as...Al, Ti, TiN, TaN, Co, Ag, Au, Cu, Ni, Cr, Hf, Ru, W, Pt or the like.

[0051] Additional processing can be performed to complete the 3D storage device 200, as experienced craftsmen will readily recognize. For example, contacts can be formed to electrically couple the WLs 203, and sections of the layer stack 202 can be removed to form a stepped area to facilitate the formation of the contacts coupled to the WLs. For the sake of simplicity, details will not be discussed here.

[0052] Fig. Figure 14 shows a top view of a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) 200A in another embodiment. The 3D memory device 200A is related to the 3D memory device 200 of Fig. 12B is similar and can be formed using similar processing steps, but the SL 218S and BLs 218B are wider than those in Fig. 12B and extend to side walls of the ferroelectric material 205 in a respective trench 206 / 212 (e.g., physically contacting the side walls).

[0053] Fig. Figure 15 shows a top view of a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) 200B in yet another embodiment. The 3D memory device 200B is related to the 3D memory device 200 of Fig. 12B is similar and can be formed using similar processing steps, but the SL 218S and BLs 218B in Fig. 15 are wider than those in Fig. 12B and narrower than those in Fig. 14 and extend to side walls of the channel material 207 in a respective trench 206 / 212 (e.g., physically contacting the side walls).

[0054] Embodiments can offer advantages. For example, the disclosed LEDLED method avoids or reduces the problem of fin structure collapse by forming the first grooves 206 and the second grooves 212 in different processing steps. Consequently, device reliability and manufacturing yield are improved.

[0055] Fig. Figure 16 shows a flowchart of a method 1000 for forming a three-dimensional (3D) ferroelectric direct-access memory device (FeRAM device) in several embodiments. A person skilled in the art would recognize many variations, alternatives, and modifications. For example, various steps, as shown in Fig. 16 may be shown, added, omitted, replaced, rearranged or repeated.

[0056] With reference to Fig.In Block 1010, a layer stack is formed over a substrate, the layer stack comprising alternating layers of a first dielectric material and a word-line material (WL material). In Block 1020, first trenches are formed such that they extend vertically through the layer stack. In Block 1030, the first trenches are filled, the filling of which includes the formation, within the first trenches, of a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material. In Block 1040, after the first trenches have been filled, second trenches are formed such that they extend vertically through the layer stack, the second trenches being interleaved with the first trenches.At block 1050, the second trenches are filled, the filling of which includes the formation, within the second trenches, of ferroelectric material, channel material above the ferroelectric material, and the second dielectric material above the channel material. At block 1060, after the filling of the second trenches, source lines (SLs) and bit lines (BLs) are formed in the first and second trenches, extending vertically through the layer stack.

[0057] According to one embodiment, a method for forming a ferroelectric random-access memory device (FeRAM device) comprises: forming a layer stack over a substrate, wherein the layer stack comprises alternating layers of a first dielectric material and a word line material (WL material); forming first trenches extending vertically through the layer stack from an upper surface of the layer stack far from the substrate to a lower surface of the layer stack facing the substrate; lining the bottom surfaces and side walls of the first trenches with a ferroelectric material; forming a channel material in the first trenches over the ferroelectric material; filling the first trenches with a second dielectric material; after filling the first trenches, forming second trenches extending vertically through the layer stack.wherein the second trenches are nested with the first trenches; lining the bottoms and sidewalls of the second trenches with the ferroelectric material; forming the channel material in the second trenches over the ferroelectric material; filling the second trenches with the second dielectric material; and after filling the second trenches, forming source lines (SLs) and bit lines (BLs) in the first and second trenches, the SLs and BLs extending vertically through the layer stack. In one embodiment, the WL material is an electrically conductive material, and the channel material is a semiconductor oxide. In another embodiment, the channel material comprises indium gallium zinc oxide, indium zinc oxide, zinc oxide, indium tin oxide, or indium tungsten oxide. In one embodiment, the method further comprises: after forming the channel material in the first trenches and before filling the first trenches,Forming a cover layer in the first trenches over the channel material, wherein the cover layer is a dielectric material having a dielectric constant higher than that of the ferroelectric material; and after forming the channel material in the second trenches and before filling the second trenches, forming the cover layer in the second trenches over the channel material. In one embodiment, the cover layer is formed from a high-k dielectric material. In one embodiment, forming the SLs and BLs comprises: forming openings in the first trenches and the second trenches,wherein the openings extend vertically through the layer stack; forming a barrier layer along the sidewalls of the openings; and filling the openings with an electrically conductive material. In one embodiment, the SLs and BLs extend continuously between opposing sidewalls of the cover layer facing each other and make contact with each other. In one embodiment, the SLs and BLs extend continuously between opposing sidewalls of the channel material facing each other and make contact with each other. In one embodiment, the SLs and BLs extend continuously between opposing sidewalls of the ferroelectric material facing each other and make contact with each other. In one embodiment, the method further comprises: after forming the cover layer in the first trenches and before filling the first trenches,Forming an oxide liner in the first trenches above the cover layer. In one embodiment, the method further comprises: after forming the oxide liner in the first trenches and before filling the first trenches, performing an anisotropic etching process to remove sections of the oxide liner, sections of the cover layer, sections of the channel material, and sections of the ferroelectric material from the bottom surfaces of the first trenches. In one embodiment, the method further comprises forming isolation regions in the first trenches and in the second trenches between the BLs and the SLs, wherein the isolation regions extend vertically through the layer stack, and wherein, in a top view, each of the isolation regions extends through the ferroelectric material in a corresponding trench of the first and second trenches.

[0058] According to one embodiment, a method for forming a ferroelectric random-access memory device (FeRAM device) comprises: forming a layer stack over a substrate, wherein the layer stack has alternating layers of a first dielectric material and a word line material (WL material); forming first trenches extending vertically through the layer stack; filling the first trenches, wherein filling the first trenches comprises forming, in the first trenches, a ferroelectric material, a channel material over the ferroelectric material, and a second dielectric material over the channel material; after filling the first trenches, forming second trenches extending vertically through the layer stack, wherein the second trenches are interleaved with the first trenches;and filling the second trenches, wherein filling the second trenches comprises forming, in the second trenches, the ferroelectric material, the channel material over the ferroelectric material, and the second dielectric material over the channel material. In one embodiment, filling the first trenches further comprises forming a cover layer in the first trenches between the channel material and the second dielectric material, wherein the cover layer is formed from a third dielectric material having a dielectric constant higher than that of the ferroelectric material. In one embodiment, filling the first trenches further comprises forming an oxide liner in the first trenches between the cover layer and the second dielectric material;and prior to forming the second dielectric material in the first trenches, removing sections of the oxide liner, sections of the cover layer, sections of the channel material, and sections of the ferroelectric material from the bottom surfaces of the first trenches by performing an anisotropic etching process. In one embodiment, the method further comprises, after filling the second trenches, forming source lines (SLs) and bit lines (BLs) in the first and second trenches, wherein the SLs and BLs extend vertically through the layer stack, the formation of the SLs and BLs comprising: forming openings in the first and second trenches, the openings extending vertically through the layer stack; and lining the sidewalls and bottom surfaces of the openings with a barrier layer.and filling the openings with an electrically conductive material. In one embodiment, the method further comprises forming insulating regions between the SLs and BLs, wherein the formation of the insulating regions comprises: forming openings in the second dielectric material; and filling the openings with a third dielectric material, wherein the third dielectric material in the openings forms the insulating regions, each of the insulating regions extending continuously from a first side wall of a corresponding trench to a second opposite side wall of the respective trench.

[0059] According to one embodiment, a ferroelectric random access memory device comprises: a layer stack over a substrate, wherein the layer stack has alternating layers of a first dielectric material and a word line material (WL material); a dielectric layer embedded in the layer stack and extending from an upper surface of the layer stack, which is located far from the substrate, to a lower surface of the layer stack, which faces the substrate; a ferroelectric film between the dielectric layer and the layer stack, wherein the ferroelectric film is arranged on opposite sides of the dielectric layer; a channel layer between the ferroelectric film and the dielectric layer;a cover layer between the channel layer and the dielectric layer, wherein the cover layer is a dielectric material having a first dielectric constant that is higher than a second dielectric constant of the ferroelectric film;and source lines (SLs) and bit lines (BLs) that are at least partially embedded in the dielectric layer and extend through the layer stack. In one embodiment, the WL material is an electrically conductive material, and the channel layer is a semiconductor oxide. In another embodiment, the ferroelectric random access memory device further comprises an oxide liner between the cover layer and the dielectric layer, wherein a first section of the ferroelectric film, a second section of the channel layer, and a third section of the cover layer are arranged between the oxide liner and the substrate, wherein a side wall of the oxide liner facing the dielectric layer is in the same plane as a first side wall of the first section of the ferroelectric film, a second side wall of the second section of the channel layer, and a third side wall of the third section of the cover layer.

Claims

[1] Method for forming a ferroelectric direct access memory device, FeRAM device, wherein the method comprises: Forming a layer stack (202) over a substrate (50), wherein the layer stack (202) comprises alternating layers of a first dielectric material (201) and a word line material, WL material (203); Forming first trenches (206) extending vertically through the layer stack (202) from an upper surface of the layer stack (202) away from the substrate (50) to a lower surface of the layer stack (202) facing the substrate (50), Lining the undersides and side walls of the first trenches (206) with a ferroelectric material (205), Formation of a channel material (207) in the first trenches (206) over the ferroelectric material (205), Filling the first trenches (206) with a second dielectric material (213), after filling the first trenches (206), forming second trenches (212) extending vertically through the layer stack (202), with the second trenches (212) being nested with the first trenches (206), Lining the undersides and side walls of the second trenches (212) with the ferroelectric material (205), Formation of the channel material (207) in the second trenches (212) above the ferroelectric material (205), Filling the second trenches (212) with the second dielectric material (213), and after filling the second trenches (212), forming source lines, SLs (218S), and bit lines, BLs (218B), in the first trenches (206) and the second trenches (212), the SLs (218S) and BLs (218B) extending vertically through the layer stack (202), wherein the WL material (203) is an electrically conductive material and the channel material (207) is a semiconductor oxide, wherein the channel material (207) comprises indium tungsten oxide. [2] Method according to claim 1, further comprising: After the formation of the channel material (207) in the first trenches (206) and before the filling of the first trenches (206), a cover layer (209) forms in the first trenches (206) over the channel material (207), wherein the cover layer (209) is a dielectric material, wherein a dielectric constant of the cover layer (209) is higher than a dielectric constant of the ferroelectric material (205), and After forming the channel material (207) in the second trenches (212) and before filling the second trenches (212), forming the cover layer (209) in the second trenches (212) over the channel material (207). [3] Method according to claim 2, wherein the cover layer (209) is formed from a high-k dielectric material. [4] Method according to claim 2 or 3, wherein forming the SLs (218S) and BLs (218B) comprises: Forming openings (216) in the first trenches (206) and the second trenches (212), wherein the openings (216) extend vertically through the layer stack (202), forming a barrier layer along side walls of the openings (216), and Filling the openings (216) with an electrically conductive material. [5] Method according to claim 4, wherein the SLs (218S) and the BLs (218B) extend continuously between opposing side walls of the cover layer (209) which are facing each other and contact each other. [6] Method according to claim 4, wherein the SLs (218S) and the BLs (218B) extend continuously between opposing side walls of the channel material (207) which face each other and contact each other. [7] Method according to claim 4, wherein the SLs (218S) and the BLs (218B) extend continuously between opposing side walls of the ferroelectric material (205) which are facing each other and contact each other. [8] Method according to any one of the preceding claims 2 to 7, further comprising: after forming the cover layer (209) in the first trenches (206) and before filling the first trenches (206), forming an oxide liner (211) in the first trenches (206) above the cover layer (209). [9] Method according to claim 8, further comprising: After forming the oxide liner (211) in the first trenches (206) and before filling the first trenches (206), an anisotropic etching process is carried out to remove sections of the oxide liner (211), sections of the cover layer (209), sections of the channel material (207), and sections of the ferroelectric material (205) from the undersides of the first trenches (206). [10] Method according to one of the preceding claims, further comprising forming isolation regions (215) in the first trenches (206) and in the second trenches (212) between the BLs (218B) and the SLs (218S), wherein the isolation regions (215) extend vertically through the layer stack (202), and wherein, in a top view, each of the isolation regions (215) extends through the ferroelectric material (205) in a corresponding trench of the first trenches (206) and the second trenches (212). [11] Method for forming a ferroelectric direct access memory device, FeRAM device, wherein the method comprises: Forming a layer stack (202) over a substrate (50), wherein the layer stack (202) comprises alternating layers of a first dielectric material (201) and a word line material, WL material (203), Forming first trenches (206) extending vertically through the layer stack (202), Filling the first trenches (206), wherein the filling of the first trenches (206) comprises the formation, in the first trenches (206), of a ferroelectric material (205), a channel material (207) above the ferroelectric material (205) and a second dielectric material (213) above the channel material (207), after filling the first trenches (206), forming second trenches (212) extending vertically through the layer stack (202), with the second trenches (212) being nested with the first trenches (206), and filling the second trenches (212), wherein the filling of the second trenches (212) comprises the formation, in the second trenches (212), of the ferroelectric material (205), of the channel material (207) above the ferroelectric material (205) and of the second dielectric material (213) above the channel material (207), wherein the WL material (203) is an electrically conductive material and the channel material (207) is a semiconductor oxide, wherein the channel material (207) comprises indium tungsten oxide. [12] Method according to claim 11, wherein the filling of the first trenches (206) further comprises forming a cover layer (209) in the first trenches (206) between the channel material (207) and the second dielectric material (213), wherein the cover layer (209) is formed from a third dielectric material having a dielectric constant that is higher than that of the ferroelectric material (205). [13] Method according to claim 12, wherein the filling of the first trenches (206) further comprises: Formation of an oxide liner (211) in the first trenches (206) between the cover layer (209) and the second dielectric material (213), and prior to forming the second dielectric material (213) in the first trenches, sections of the oxide liner (211), sections of the cover layer (209), sections of the channel material (207) and sections of the ferroelectric material (205) are removed from the undersides of the first trenches (206) by performing an anisotropic etching process. [14] A method according to any one of the preceding claims 11 to 13, further comprising, after filling the second trenches (212), forming source lines, SLs (218S), and bit lines, BLs (218B), in the first trenches (206) and the second trenches (212), wherein the SLs (218S) and BLs (218B) extend vertically through the layer stack (202), wherein the formation of the SLs (218S) and BLs (218B) comprises: Forming openings (216) in the first trenches (206) and the second trenches (212), the openings (216) extending vertically through the layer stack (202), Lining the side walls and undersides of the openings (216) with a barrier layer, and Filling the openings (216) with an electrically conductive material. [15] Method according to claim 14, further comprising forming isolation regions (215) between the SLs (218S) and BLs (218B), wherein the formation of the isolation regions (215) comprises: Formation of openings in the second dielectric material (213), and Filling the openings with a third dielectric material, wherein the third dielectric material in the openings forms the insulation regions (215), each of the insulation regions (215) extending continuously from a first side wall of a respective trench to a second opposite side wall of the respective trench. [16] Ferroelectric direct access storage device comprising: a layer stack (202) over a substrate (50), wherein the layer stack (202) comprises alternating layers of a first dielectric material (201) and a word line material, WL material (203), a dielectric layer (213) embedded in the layer stack (202) and extending from an upper surface of the layer stack (202), which is located far from the substrate (50), to a lower surface of the layer stack (202), which faces the substrate (50), a ferroelectric film (205) between the dielectric layer (213) and the layer stack (202), wherein the ferroelectric film (205) is arranged on opposite sides of the dielectric layer (213), a channel layer (207) between the ferroelectric film (205) and the dielectric layer (213), a cover layer (209) between the channel layer (207) and the dielectric layer (213), wherein the cover layer (209) is a dielectric material having a first dielectric constant that is higher than a second dielectric constant of the ferroelectric film (205), and Source lines, SLs (218S), and bit lines, BLs (218B), which are at least partially embedded in the dielectric layer (213) and extend through the layer stack (202), wherein the WL material (203) is an electrically conductive material and the channel layer (207) comprises a semiconductor oxide, wherein the channel layer (207) contains indium tungsten oxide. [17] Ferroelectric direct access memory device according to claim 16, further comprising an oxide liner (211) between the cover layer (209) and the dielectric layer (213), wherein a first section of the ferroelectric film (205), a second section of the channel layer (207), and a third section of the cover layer (209) are arranged between the oxide liner (211) and the substrate (50), wherein a side wall of the oxide liner (211) facing the dielectric layer (213) is in the same plane as a first side wall of the first section of the ferroelectric film (205), a second side wall of the second section of the channel layer (207), and a third side wall of the third section of the cover layer (209).

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