Semiconductor structure with a conductive structure and method for producing the same

Abstract

Method for producing a semiconductor structure (100) comprising the following: Forming a gate structure (142) over a substrate (102); Forming a mask layer (152) that covers the gate structure (142); Forming a source / drain structure (136) adjacent to the gate structure (142) above the substrate (102); Forming a contact (156) over the source / drain structure (136); Formation of a dielectric layer (164) over the contact (156) and the mask layer (152); Forming a first trench (166) through the dielectric layer (164) and the mask layer (152) over the gate structure (142); Formation of a first conductive structure (171) in the first trench (166); Removal of an upper section of the first conductive structure (171); and Formation of a second conductive structure (178) by the dielectric layer (164) to cover both the contact (156) and the first conductive structure (171).

Description

BACKGROUND

[0001] The electronics industry is experiencing ever-increasing demand for smaller and faster electronic components capable of performing a greater number of increasingly complex and demanding functions. Accordingly, the semiconductor industry is seeing a continuing trend toward the production of cost-effective, high-performance, low-power integrated circuits (ICs). To date, these goals have been largely achieved by miniaturizing semiconductor IC dimensions (e.g., minimum feature size), thereby improving production efficiency and reducing associated costs. However, such miniaturization has led to increased complexity in the semiconductor manufacturing process. Therefore, realizing further advances in semiconductor ICs and components requires similar advances in semiconductor manufacturing processes and technology.

[0002] Recently, multi-gate devices have been introduced to improve gate control by increasing gate-channel coupling, reducing reverse current, and minimizing short-channel effects (SCEs). However, integrating the manufacturing of these multi-gate devices can be challenging.

[0003] US 2018 / 0 053 721 A1 discloses a semiconductor structure comprising a contact structure having a grooved upper surface embedded in at least one medium-length (MOL) dielectric material, wherein the contact structure contacts an underlying doped semiconductor material structure. US 9 847 390 B1 discloses a method for fabricating a wrap-around contact on a nanosheet transistor. Further prior art is known from US 2019 / 0 287 851 A1, US 2020 / 0 091288 A1, DE 10 2019 117 925 A1, US 2018 / 0 096 935 A1, US 2020 / 0 321 244 A1, and US 2019 / 0 385 946 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various elements are not shown to scale. In fact, the dimensions of the various elements may have been arbitrarily enlarged or reduced for the sake of clarity. Fig. Figures 1A to 1E illustrate perspective views of intermediate stages in the fabrication of a semiconductor structure in accordance with some embodiments. Fig. Figures 2A-1 to 2P-1 illustrate cross-sectional views of different stages of the fabrication of the semiconductor structure along line AA' in Fig. 1E in accordance with some embodiments. Fig. Figures 2A-2 to 2P-2 illustrate cross-sectional views of different stages of the fabrication of the semiconductor structure along line BB' in Fig. 1E in accordance with some embodiments. Fig. Figure 3 illustrates a cross-sectional view of a further intermediate stage in the fabrication of the semiconductor structure in accordance with some embodiments. Fig. Figure 4 illustrates a cross-sectional view of a further intermediate stage in the fabrication of the semiconductor structure in accordance with some embodiments. Fig. Figure 5 illustrates a cross-sectional view of a semiconductor structure in accordance with some embodiments. Fig. Figures 6A-1, 6A-2, 6B-1 and 6B-2 illustrate cross-sectional views of the fabrication of a semiconductor structure in accordance with some embodiments. Fig. Figure 7 illustrates a cross-sectional view of a semiconductor structure in accordance with some embodiments. Fig. Figure 8 illustrates a cross-sectional view of a semiconductor structure in accordance with some embodiments. Fig. Figure 9 illustrates a cross-sectional view of a semiconductor structure in accordance with some embodiments. Fig. Figure 10 illustrates a cross-sectional view of a semiconductor structure 100e in accordance with some embodiments. Fig. 11A and Fig. Figure 11B illustrates cross-sectional views of the fabrication of a semiconductor structure in accordance with some embodiments. Fig. 12A and Fig. Figure 12B illustrates cross-sectional views of the fabrication of a semiconductor structure in accordance with some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments, or examples, for implementing various features of the intended subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, the formation of a first element above or on top of a second element in the following description may include embodiments in which the first and second elements are in direct contact, and it may also include embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition serves for simplicity and clarity and does not in itself dictate a relationship between the various discussed embodiments and / or configurations.

[0006] Several variations of the embodiments are described. Throughout all the different views and illustrative embodiments, the same reference numbers are used to denote the same elements. It should be understood that additional operations may be provided before, during, or after the method, and some of the described operations may be substituted or eliminated for other embodiments of the method.

[0007] The gate-all-around transistor (GAA) structures described below can be structured by any suitable method. For example, the structures can be structured using one or more photolithography processes, including dual-structuring or multi-structuring processes. In general, dual-structuring or multi-structuring processes combine photolithography and self-alignment processes, allowing the creation of structures with, for example, smaller spacing than can otherwise be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the GAA structure.

[0008] The fins described below can be structured by any suitable method. For example, the fins can be structured using one or more photolithography processes, including dual-structuring or multi-structuring processes. In general, dual-structuring or multi-structuring processes combine photolithography and self-aligning processes, allowing the creation of structures with, for example, smaller spacing than can otherwise be obtained using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed along the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used to structure the fins.

[0009] Embodiments of semiconductor structures and methods for forming them are provided. The semiconductor structures can have a gate structure formed over a substrate and a source / drain structure formed adjacent to the gate structure. A contact can be formed over the source / drain structure, and a conductive structure can be formed to connect the contact and the gate structure. Since the contact and the gate structure can have different heights, the formation of the conductive structure can first involve forming a first section over the gate structure and then forming a second section over the first section and the contact.The first section of the conductive structure formed above the gate structure can have a relatively small height difference to the contact, thus preventing a separation of the connection between the gate structure and the contact due to a large height difference.

[0010] Fig. Figures 1A to 1E illustrate perspective views of intermediate stages in the fabrication of a semiconductor structure 100 in accordance with some embodiments. As in Fig. As shown in Figure 1A, in accordance with some embodiments, first semiconductor material layers 106 and second semiconductor material layers 108 are formed over a substrate 102.

[0011] Substrate 102 can be a semiconductor wafer, such as a silicon wafer. Alternatively or additionally, substrate 102 can contain elemental semiconductor materials, compound semiconductor materials, and / or alloy semiconductor materials. Elemental semiconductor materials may include, but are not limited to, crystalline silicon, polycrystalline silicon, amorphous silicon, germanium, and / or diamond. Compound semiconductor materials may include, but are not limited to, silicon carbide, gallium arsenic, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide. Alloy semiconductor materials may include, but are not limited to, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP.

[0012] In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 are stacked alternately over the substrate 102. In some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108 are made of different semiconductor materials. In some embodiments, the first semiconductor material layers 106 are made of SiGe, and the second semiconductor material layers 108 are made of silicon. It should be noted that, although three first semiconductor material layers 106 and three second semiconductor material layers 108 are formed, the semiconductor structure can also have more or fewer first semiconductor material layers 106 and second semiconductor material layers 108. For example, the semiconductor structure can have two to five first semiconductor material layers 106 and five second semiconductor material layers 108.

[0013] The first semiconductor material layers 106 and the second semiconductor material layers 108 can be formed using low-pressure chemical vapor deposition (LPCVD), an epitaxial growth process, another suitable method, or a combination thereof. In some embodiments, the epitaxial growth process includes molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), or vapor phase epitaxy (VPE).

[0014] After the first semiconductor material layers 106 and the second semiconductor material layers 108 have been formed as a semiconductor material stack over the substrate 102, the semiconductor material stack is structured to form a fin structure 104, as shown in Fig. 1B shown in accordance with some embodiments. In some embodiments, the fin structure 104 has a base fin structure 104B and the semiconductor material stack consisting of the first semiconductor material layers 106 and the second semiconductor material layers 108.

[0015] In some embodiments, the structuring process comprises forming a mask structure 110 over the semiconductor material stack and etching the semiconductor material stack and the underlying substrate 102 through the mask structure 110. In some embodiments, the mask structure 110 is a multilayer structure comprising a pad oxide layer 112 and a nitride layer 114 formed over the pad oxide layer 112. The pad oxide layer 112 can be made of silicon oxide formed by thermal oxidation or CVD, and the nitride layer 114 can be made of silicon nitride formed by CVD, such as LPCVD or plasma-enhanced CVD (PECVD).

[0016] After the fin structure 104 has formed, an isolation structure 116 is formed around the fin structure 104, and the mask structure 110 is removed, as shown in Fig. 1C is shown in accordance with some embodiments. The insulation structure 116 is configured to electrically insulate active regions (e.g., the fin structure 104) of the semiconductor structure 100 and is also referred to as a shallow trench insulation feature (STI feature) in accordance with some embodiments.

[0017] The insulating structure 116 can be formed by depositing an insulating layer over the substrate 102 and leaving the insulating layer recessed so that the fin structure 104 protrudes from the insulating structure 116. In some embodiments, the insulating structure 116 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), another suitable insulating material, or a combination thereof. In some embodiments, a dielectric barrier (not shown) is formed before the insulating structure 116 is formed, and the dielectric barrier is made of silicon nitride, while the insulating structure formed over the dielectric barrier is made of silicon oxide.

[0018] After the isolation structure 116 has been formed, the dummy gate structures 118 are formed over the fin structure 104 and extend over the isolation structure 116, as shown in Fig. Figure 1D shows in accordance with some embodiments. The dummy gate structures 118 can be used to define the source / drain regions and the channel regions of the resulting semiconductor structure 100.

[0019] In some embodiments, the dummy gate structures 118 comprise the dielectric dummy gate layers 120 and the dummy gate electrode layers 122. In some embodiments, the dielectric dummy gate layers 120 are made of one or more dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride (SiON), HfO₂, HfZrO, HfSiO₂, HfTiO₂, HfAlO₂, or a combination thereof. In some embodiments, the dielectric dummy gate layers 120 are formed using thermal oxidation, CVD, ALD, physical vapor deposition (PVD), another suitable method, or a combination thereof.

[0020] In some embodiments, the conductive material comprises polycrystalline silicon (poly-Si), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metals, or a combination thereof. In some embodiments, the dummy gate electrode layers 122 are formed using CVD, PVD, or a combination thereof.

[0021] In some embodiments, hard mask layers 124 are formed over the dummy gate structures 118. In some embodiments, the hard mask layers 124 have multiple layers, such as an oxide layer and a nitride layer. In some embodiments, the oxide layer is silicon oxide and the nitride layer is silicon nitride.

[0022] The formation of the dummy gate structures 118 can include the conformal formation of a dielectric material as the dielectric dummy gate layers 120. Subsequently, a conductive material can be formed over the dielectric material as the dummy gate electrode layers 122, and the hard mask layer 124 can be formed over the conductive material. Next, the dielectric material and the conductive material can be patterned by the hard mask layer 124 to form the dummy gate structures 118.

[0023] After the dummy gate structures 118 have been formed, the gate spacers 126 are formed along and opposite side walls of the dummy gate structure 118, and the fin spacers 128 are formed along and opposite side walls of the source / drain regions of the fin structure 104, as shown in Fig. 1E shown in accordance with some embodiments.

[0024] The gate spacers 126 can be configured to separate the source / drain structures from the dummy gate structure 118 and to support the dummy gate structure 118, and the fin spacers 128 can be configured to restrict lateral growth of a subsequently formed source / drain structure and to support the fin structure 104.

[0025] In some embodiments, the gate spacers 126 and the fin spacers 128 are made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN) and / or a combination thereof. The formation of the gate spacers 126 and the fin spacers 128 can include the conformal deposition of a dielectric material covering the dummy gate structure 118, the fin structure 104 and the insulation structure 116 over the substrate 102, and the performance of an anisotropic etching process, such as dry plasma etching, to remove the dielectric layer covering the upper surfaces of the dummy gate structure 118, the fin structure 104 and sections of the insulation structure 116.

[0026] Fig. Figures 2A-1 to 2P-1 illustrate cross-sectional views of different stages in the fabrication of semiconductor structure 100 along line AA' in Fig. 1E in accordance with some embodiments. Fig. Figures 2A-2 to 2P-2 illustrate cross-sectional views of different stages in the fabrication of semiconductor structure 100 along line BB' in Fig. 1E in accordance with some embodiments. More specifically illustrated. Fig. 2A-1 the cross-sectional view along line AA' in Fig. 1E and Fig. 2A-2 illustrates the cross-sectional view along line BB' in Fig. 1E in accordance with some embodiments.

[0027] After the gate spacers 126 and the fin spacers 128 have been formed, the source / drain regions of the fin structure 104 are recessed to form the source / drain recesses 130, as shown in Fig. 2B-1 and 2B-2 are shown in accordance with some embodiments. More specifically, in accordance with some embodiments, the first semiconductor material layers 106 and the second semiconductor material layers 108, which are not covered by the dummy gate structures 118 and the gate spacers 126, are removed. In addition, some sections of the base fin structure 104B are also omitted to form curved upper surfaces, as shown in Fig. 2B-1 shown in accordance with some embodiments.

[0028] In some embodiments, the fin structure 104 is recessed by performing an etching process. The etching process can be an anisotropic etching process, such as dry plasma etching, and the dummy gate structure 118 and the gate spacers 126 are used as etching masks during the etching process. In some embodiments, the fin spacers 128 are also recessed to form recessed fin spacers 128'.

[0029] After the source / drain recesses 130 have been formed, the first semiconductor material layers 106, which are exposed through the source / drain recesses 130, are recessed laterally to form the notches 132, as shown in Fig. 2C-1 and 2C-2 shown in accordance with some embodiments.

[0030] In some embodiments, an etching process is performed on the semiconductor structure 100 to laterally recess the first semiconductor material layers 106 of the fin structure 104 from the source / drain recesses 130. In some embodiments, the first semiconductor material layers 106 have a higher etch rate (or amount of etch) during the etching process than the second semiconductor material layers 108, thereby forming the notches 132 between adjacent second semiconductor material layers 108. In some embodiments, the etching process is an isotropic etching, such as dry chemical etching, remote plasma etching, wet chemical etching, another suitable technique, and / or a combination thereof.

[0031] Next, the inner spacers 134 are formed in the notches 132 between the second semiconductor material layers 108, as shown in Fig. 2D-1 and 2D-2 are shown in accordance with some embodiments. The inner spacers 134 are configured to separate the source / drain structures and the gate structures, which are formed in subsequent fabrication processes in accordance with some embodiments. In some embodiments, the inner spacers 134 are made of a dielectric material such as silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), silicon oxynitride (SiON), silicon carbon nitride (SiCN), silicon oxide carbonitride (SiOCN), or a combination thereof.

[0032] After the inner spacers 134 have been formed, the source / drain structures 136 are formed in the source / drain recesses 130, as shown in Fig. 2E-1 and 2E-2 are shown in accordance with some embodiments. In some embodiments, the source / drain structures 136 are formed using an epitaxial growth process, such as MBE, MOCVD, VPE, another suitable epitaxial growth process, or a combination thereof. In some embodiments, the source / drain structures 136 are made from any suitable material, such as Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, SiC, SiCP, or a combination thereof.

[0033] In some embodiments, the source / drain structures 136 are doped in situ during the epitaxial growth process. For example, the source / drain structures 136 can be epitaxially grown SiGe doped with boron (B). For example, the source / drain structures 136 can be epitaxially grown Si doped with carbon to form silicon:carbon source / drain features (Si:C source / drain features), with phosphorus to form silicon:phosphorus source / drain features (Si:P source / drain features), or with both carbon and phosphorus to form silicon-carbon-phosphorus source / drain features (SiCP source / drain features). In some embodiments, the source / drain structures 136 are doped in one or more implantation processes after the epitaxial growth process.

[0034] After the source / drain structures 136 have been formed, a contact etch stop layer (CESL) 138 is conformally formed to cover the source / drain structures 136, and an interlayer dielectric layer (ILD) 140 is formed over the contact etch stop layers 138, as shown in Fig. 2F-1 and 2F-2 shown in accordance with some embodiments.

[0035] In some embodiments, the contact etch stop layer 138 is made from a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layers 138 can be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

[0036] The dielectric interlayer 140 can comprise multilayers made from several dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), and / or other suitable dielectric materials with a low k-value. The dielectric interlayer 140 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0037] After the contact etch stop layer 138 and the dielectric intermediate layer 140 have been deposited, a planarization process, such as CMP, or a back-etching process can be carried out until the gate electrode layers 120 of the dummy gate structures 118 are exposed, as shown in Fig. 2F-1 shown in accordance with some embodiments.

[0038] Next, the dummy gate structures 118 are replaced by the gate structure 142, as shown in Fig. 2G-1 and 2G-2 are shown in accordance with some embodiments. More specifically, the dummy gate structures 118 and the first semiconductor material layers 106 are removed to form the nanostructures 108' with the second semiconductor material layers 108 in accordance with some embodiments. The removal process may include one or more etching processes. For example, if the dummy gate electrode layers 122 are polysilicon, a wet etchant, such as a tetramethylammonium hydroxide (TMAH) solution, may be used to selectively remove the dummy gate electrode layers 122. Subsequently, the dielectric dummy gate layers 120 may be removed using plasma dry etching, dry chemical etching, and / or wet etching. The first semiconductor material layers 106 may be removed by performing a selective wet etching process, such as an APM etching process (e.g.,with an ammonium hydroxide-hydrogen peroxide-water mixture). For example, the wet etching process uses etchants such as ammonium hydroxide (NH4OH), TMAH, ethylenediaminepyrocatechol (EDP) and / or potassium hydroxide (KOH) solutions. In some embodiments, the upper sections of the gate spacers 126 are also removed.

[0039] After the nanostructures 108' have formed, the gate structures 142 are formed, which enclose the nanostructures 108', as shown in Fig. 2G-1 and 2G-2 are shown in accordance with some embodiments. The gate structures 142 enclose the nanostructures 108' to form gate-all-around transistor structures in accordance with some embodiments. In some embodiments, the gate structure 142 comprises an interface layer 144, a dielectric gate layer 146, and a gate electrode layer 148.

[0040] In some embodiments, the interface layers 144 are oxide layers formed around the nanostructures 108' and on top of the base fin structure 104B. In some embodiments, the interface layers 144 are formed by carrying out a thermal process.

[0041] In some embodiments, the dielectric gate layers 146 are formed over the interface layers 144, such that the nanostructures 108' are surrounded (e.g., encased) by the dielectric gate layers 146. Furthermore, in some embodiments, the dielectric gate layers 146 also cover the side walls of the gate spacers 126 and the inner spacers 134. In some embodiments, the dielectric gate layers 146 are made from one or more layers of dielectric materials, such as HfO₂, HfSiO₂, HfSiON₄, HfTaO₂, HfTiO₂, HfZrO₂, zirconium oxide, aluminum oxide, titanium oxide, a hafnium dioxide-aluminum oxide alloy (HfO₂-Al₂O₃), another suitable dielectric material with a high k-value, or a combination thereof. In some embodiments, the dielectric gate layers 146 are formed using CVD, ALD, another suitable method or a combination thereof.

[0042] In some embodiments, the gate electrode layers 148 are formed on the dielectric gate layer 146. In some embodiments, the gate electrode layers 148 are made from one or more layers of conductive material, such as aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, another suitable material, or a combination thereof. In some embodiments, the gate electrode layers 148 are formed using CVD, ALD, electroplating, another suitable process, or a combination thereof. Other conductive layers, such as exit work metal layers, can also be formed in the gate structures 142, although they are not shown in the figures.After the interface layers 144, the dielectric gate layers 146 and the gate electrode layers 148 have been formed, a planarization process, such as CMP, or a back-etching process can be carried out until the dielectric intermediate layer 140 is exposed.

[0043] A back-etching process is then carried out to remove the upper section of the gate structures 142, and cover layers 150 and mask layers 152 are formed over the gate structures 142, as shown in Fig. 2G-1 and 2G-2 are shown in accordance with some embodiments. More specifically, the upper section of the gate structures 142 is removed to form a recess in the dielectric intermediate layer 140, and the cover layers 150 and the mask layers 152 are formed in the recess in accordance with some embodiments.

[0044] In some embodiments, the cover layers 150 are made of W, Ti, Co, Ru, Ni, or the like. The cover layers 150 can be formed using CVD, ALD, electroplating, another suitable process, or a combination thereof. In some embodiments, the cover layers 150 are selectively formed over the gate structures 142. In some embodiments, the mask layers 152 are made of SiO2, Si3N4, SiON, SiOCN, SiOCH, or the like. The mask layers 152 can be formed using CVD, ALD, electroplating, another suitable process, or a combination thereof.

[0045] After the mask layers 152 have formed, contact openings are formed by the contact etch stop layer 138 and the dielectric intermediate layer 140, and silicide layers 154 and contacts 156 are formed over the source / drain structures 136, as shown in Fig. 2H-1 and 2H-2 are shown in accordance with some embodiments. In some embodiments, separating layers 158 and barrier layers 160 are formed around the contacts 156.

[0046] More specifically, the contact openings can be formed by the contact etch stop layer 138 and the dielectric intermediate layer 140 to expose the upper surfaces of the source / drain structures 136, and the silicide layers 154 and the contacts 156 can be formed in the contact openings. The contact openings can be formed using a photolithography process and an etching process. Furthermore, some sections of the source / drain structures 136 exposed by the contact openings can also be etched during the etching process.

[0047] After the contact openings have been formed, the silicide layers 154 can be formed by depositing a metal layer over the upper surface of the source / drain structures 136 and annealing the metal layer so that it reacts with the source / drain structures 136 to form the silicide layers 160. The unreacted metal layer can be removed after the silicide layers 154 have been formed.

[0048] Subsequently, the separating layers 158, the barrier layers 160 and the contacts 156 are formed over the silicide layers 154 in the contact openings, and a polishing process is carried out as described in Fig. 2H-1 and 2H-2 are shown in accordance with some embodiments. As in Fig. As shown in Figure 2H-1, the upper surface of contact 156 is, in accordance with some embodiments, essentially at the same level as the upper surface of the mask layer 152.

[0049] In some embodiments, the contacts 156 are made of a conductive material, including aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), titanium nitride (TiN), cobalt, tantalum nitride (TaN), nickel silicide (NiS), cobalt silicide (CoSi), copper silicide, tantalum carbide (TaC), tantalum silicide nitride (TaSiN), tantalum carbide nitride (TaCN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), other suitable conductive materials, or a combination thereof. In some embodiments, the separating layer 158 is made of silicon nitride, although any other suitable dielectric may also be used as an alternative. In some embodiments, the barrier layer 160 is made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, may also be used. The separating layers 158, the barrier layers 160 and the contacts 156 can be produced using a process such as e.g.chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD - Plasma Enhanced Physical Vapor Deposition), atomic layer deposition (ALD) or any other suitable deposition process.

[0050] In some embodiments, the upper surface of the contact 156 is higher than the upper surface of the gate structure 142 and is essentially at the same level as the mask layer 152. In some embodiments, the height difference between the contact 156 and the gate structure 142 is essentially at the same level as the height of the mask layer 152.

[0051] After the contacts 156 have been formed, an etch stop layer 162 is formed over the contacts 156 and the mask layers 152, and a dielectric layer 164 is formed over the etch stop layer 162, as shown in Fig. 2I-1 and 2I-2 shown in accordance with some embodiments.

[0052] In some embodiments, the etch stop layer 162 is made from a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, another suitable dielectric material, or a combination thereof. The dielectric material for the contact etch stop layers 162 can be conformally deposited over the semiconductor structure by performing CVD, ALD, other application methods, or a combination thereof.

[0053] The dielectric layer 164 can have multilayer structures made of several dielectric materials, such as silicon oxide, silicon nitride, silicon oxynitride, phosphosilicate glass (PSG), boron phosphosilicate glass (BPSG), and / or other suitable materials with a low k-value. The dielectric layer 164 can be formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0054] After the dielectric layer 164 has been formed, a first trench 166 is formed through the mask layer 152, the etch stop layer 162 and the dielectric layer 164, as shown in Fig. 2J-1 and 2J-2 are shown in accordance with some embodiments. In some embodiments, the upper portion of the cover layer 150 is also etched when the first trench 166 is formed. The first trench 166 can be formed by performing one or more etching processes, including dry etching processes and / or wet etching processes.

[0055] Next, a conductive material 168 is formed in the first trench 166, as shown in Fig. 2K-1 and 2K-2 are shown in accordance with some embodiments. In some embodiments, the conductive material 168 is W, Ru, Mo, or the like. In some embodiments, the conductive material 168 is formed by performing chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes.

[0056] In some embodiments, the conductive material 168 is formed by performing a bottom-up deposition process. The bottom-up deposition process generally refers to a deposition process that fills an opening from the bottom up. By using the bottom-up deposition process, the first trench 166 can be filled without creating an air gap. In some embodiments, the bottom-up deposition process is a selective CVD process in which the conductive material 168 is selectively deposited over the top layer 150.

[0057] In some embodiments, the conductive material is 168 Ru, and precursor gases used in the bottom-up deposition process include Ru(CO)5 and Ru3(CO). 12, RuCl3, Ru(od)3, Bis(cyclopentadienyl)ruthenium(II), Ru(CO)3C6H8, Ru(CO)2(tmhd)2, Ru(EtCp)2, Ru(CO)2(acac)2, Ru(C6H6)(C6H8), Ru(DMBD)(CO)3, a combination thereof, or the like. In some embodiments, the conductive material is 168 W, and a precursor gas used in the bottom-up deposition process includes W(CO)6, W(F)6, or the like. In some embodiments, the conductive material is 168 Mo, and a precursor gas used in the bottom-up deposition process includes MoF6, Mo(CO)6, MoCl s , MoO x Cl y or the like.

[0058] A polishing process is then carried out to form a conductive structure 170 in the first trench 166 above the gate structure 142, as shown in Fig. 2L-1 and 2L-2 are shown in accordance with some embodiments. In some embodiments, a CMP process is carried out to polish the conductive material 168 such that the upper surface of the conductive structure 170 is essentially at the same level as the upper surface of the dielectric layer 164.

[0059] Next, the conductive structure 170 is truncated to form a truncated conductive structure 171, as shown in Fig. 2M-1 and 2M-2 are shown in accordance with some embodiments. More specifically, the upper section of the conductive structure 170 is back-etched such that the upper surface of the truncated conductive structure 171 is, in accordance with some embodiments, essentially at the same level as the upper surface of the etch stop layer 162.

[0060] In some embodiments, the height H1 of the truncated conductive structure 171 is in a range of approximately 10 nm to approximately 50 nm. In some embodiments, the depth D1 of the trench 167 (e.g., the height of the removed upper section of the conductive structure 170) is in a range of approximately 30 nm to approximately 70 nm. In some embodiments, the ratio of height H1 to depth D1 is in a range of approximately 0.6 to approximately 7.

[0061] After the conductive structure 170 has been shortened, a second trench 172 is formed through the dielectric layer 164 and the etch stop layer 162 to expose both the upper surface of the contact 156 and the upper surface of the shortened conductive structure 171, as shown in Fig. 2N-1 and 2N-2 are shown in accordance with some embodiments. The second groove 172 can be formed by performing an etching process. During the etching process, both the corner of the contact 156 and the corner of the truncated conductive structure 171 are etched such that, in accordance with some embodiments, the contact 156 and the truncated conductive structure 171 have rounded corners facing each other.

[0062] In some embodiments, a section of the mask layer 152 is also removed, such that the second groove 172 has a recessed section 173 extending into the mask layer 152. In some embodiments, the lowermost section of the recessed section 173 of the second groove 172 is lower than the upper surface of the contact 156. Furthermore, in some embodiments, an upper section of the side wall of the truncated conductive structure 171 is exposed by the recessed section 173 of the second groove 172.

[0063] Next, a conductive material 174 is formed in the second trench 172, as shown in Fig. 20-1 and 20-2 are shown in accordance with some embodiments. Since the corner of the truncated conductive structure 171 is etched, the truncated conductive structure 171 and the conductive material 174 have a curved interface in accordance with some embodiments.

[0064] In some embodiments, the conductive material 174 is W, Ru, Mo, Cu, or the like. In some embodiments, the conductive material 174 and the conductive material 168 are the same metal. In some embodiments, the conductive material 174 and the conductive material 168 are different metals.

[0065] In some embodiments, the conductive material 174 is formed by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable processes. In some embodiments, the conductive material 174 is formed by a bottom-up deposition process. The bottom-up deposition process used to form the conductive material 174 may be the same as, or similar to, that used to form the conductive material 168 and is not repeated here. In some embodiments, the deposition processes (e.g., precursor gas) for the conductive material 174 and the conductive material 168 are the same.

[0066] Since the truncated conductive structure 171 is formed first, the height difference between different regions of the second trench 172 (e.g., the region above contact 156 and the region above gate structure 142) can be relatively small. Accordingly, the conductive material 174 can be formed by performing a bottom-up deposition process with an improved connection between contact 156 and gate structure 142.

[0067] In some embodiments, a cavity 176 is formed in the conductive material 174 in the recessed section 173 of the second groove 172. In some embodiments, the cavity 176 is arranged between the contact 156 and the truncated conductive structure 171 and is located directly above the mask layer 152.

[0068] Subsequently, a polishing process is carried out to form a conductive structure 176 in the semiconductor structure 100, as shown in Fig. 2P-1 and 2P-2 are shown in accordance with some embodiments. In some embodiments, a CMP process is carried out to polish the conductive material 174 such that the upper surface of the conductive structure 176 is essentially at the same level as the upper surface of the dielectric layer 164.

[0069] In some embodiments, the height difference H2 between the truncated conductive structure 171 and the contact 156 is less than 10 nm. Since the height difference H2 between the truncated conductive structure 171 and the contact 156 is relatively small, the conductive structure 178 can be formed more effectively. This means that the risk of the connection between the gate structure 142 and the contact 156 breaking due to the height difference between the gate structure 142 and the contact 156 can be reduced. In some embodiments, the ratio of the height difference H2 between the truncated conductive structure 171 and the contact 156 to the height difference H3 between the contact 156 and the gate structure 142 is in the range of approximately 0.2 to approximately 0.5.

[0070] As in Fig. As shown in Figure 2P-1, the conductive structure 178 can have different thicknesses in different sections. In some embodiments, the conductive structure 178 has a first section above the contact 156, and the thickness T1 of the first section is in the range of about 35 nm to about 90 nm. In some embodiments, the conductive structure 178 has a second section above the truncated conductive structure 171, and the thickness T2 of the second section is in the range of about 30 nm to about 70 nm. In some embodiments, the ratio of thickness T2 to thickness T1 is in the range of about 0.5 to about 3.

[0071] In some embodiments, the conductive structure 178 has a third section between the first and second sections, and the thickness T3 of the third section is in the range of about 38 nm to about 100 nm. More specifically, the conductive structure 178 has an extended section inserted between the truncated conductive structure 171 and the contact 156, and the thickness T4 of the extended section is in the range of about 3 nm to about 10 nm.

[0072] In some embodiments, the lowest section of the conductive structure 178 (e.g., the lowest section of the extended section of the conductive structure 178) is located lower than the uppermost sections (e.g., upper surfaces) of the truncated conductive structure 171, the contact 156, the mask layer 152, and the etch stop layer 162. Furthermore, the lowest section of the conductive structure 178 is located higher than the lowermost surfaces of the truncated conductive structure 171, the contact 156, and the mask layer 152.

[0073] It will be understood that, although the in Fig. The cross-sectional views shown in 2P-1 and 2P-2 are described with reference to a procedure, but the structures are not limited to the procedure; rather, they can stand separately from the procedure on their own.

[0074] Fig. Figure 3 illustrates a cross-sectional view of a further intermediate stage in the fabrication of the semiconductor structure 100 in accordance with some embodiments. The process for fabricating the semiconductor structure 100 described above can be carried out, except that a conductive material 168-1 formed in the first trench is, in accordance with some embodiments, thinner than that shown in Figure 3. Fig. The conductive material shown in 2K-1 may be 168.

[0075] The details become more specific in Fig. The processes shown in Figures 1A to 1E, 2A-1 to 2J-1, and 1A-2 to 2J-2 are carried out to form a first trench (e.g., the first trench 166) through the mask layer 152, the etch stop layer 162, and the dielectric layer 164, in accordance with some embodiments. A conductive material 168-1 is then formed in the first trench, as shown in Figures 1A to 1E, 2A-1 to 2J-1, and 1A-2 to 2J-2. Fig. Figure 3 shows in accordance with some embodiments. The conductive material 168-1 may be similar to the conductive material 168, except that the conductive material 168-1 does not cover the upper surface of the dielectric layer 164. The processes and materials for forming the conductive material 168-1 may be similar to or the same as those for forming the conductive material 168 and are not repeated herein.

[0076] In some embodiments, the upper surface of the conductive material 168-1 is lower than the upper surface of the dielectric layer 164, such that the first trench is not completely filled with the conductive material 168-1. After the conductive material 168-1 has formed, a polishing process is carried out, in accordance with some embodiments, to form the conductive structure over the gate structure 142. During the polishing process, the upper portion of the conductive material 168-1 and the upper portion of the dielectric layer 164 are removed, so that the resulting conductive structure and the dielectric layer 164 may still have substantially flat upper surfaces, in accordance with some embodiments (similar to those described in Fig. 2L-1 and 2L-2 are shown). After that, the following can be seen in Fig. The processes shown for forming the semiconductor structure 100 are carried out using 2M-1 to 2P-1 and 2M-2 to 2P-2.

[0077] Fig. Figure 4 illustrates a cross-sectional view of a further intermediate stage in the fabrication of the semiconductor structure 100 in accordance with some embodiments. The processes described above for fabricating the semiconductor structure 100 can be carried out, except that, in accordance with some embodiments, a conductive material 168-2 and an additional conductive material 169 are formed.

[0078] The details become more specific in Fig. The processes shown in Figures 1A to 1E, 2A-1 to 2J-1, and 1A-2 to 2J-2 are carried out to form a first trench (e.g., the first trench 166) through the mask layer 152, the etch stop layer 162, and the dielectric layer 164, in accordance with some embodiments. Then, the conductive material 168-2 is formed in the first trench, and the conductive material 169 is formed over the conductive material 168-2, as shown in Figures 1A to 1E, 2A-1 to 2J-1, and 1A-2 to 2J-2. Fig. 4 shown in accordance with some embodiments. The processes and materials for forming the conductive material 168-2 may be similar to or the same as those for forming the conductive material 168 and are not repeated herein.

[0079] Similar to the conductive material 168-1, the upper surface of the conductive material 168-2 is lower than the upper surface of the dielectric layer 164, such that, in some embodiments, the first trench is not completely filled with the conductive material 168-2. Furthermore, in some embodiments, the upper portion of the first trench is filled with the conductive material 169, and the upper surface of the dielectric layer 164 is covered by the conductive material 169.

[0080] In some embodiments, the conductive material 168-2 and the conductive material 169 are produced from the same material but are formed by different processes. In some embodiments, the conductive material 169 is formed by performing a CVD process.

[0081] After the conductive material 169 has formed, a polishing process is carried out, in accordance with some embodiments, to form the conductive structure over the gate structure 142. In some embodiments, the conductive material 169 is completely removed during the polishing process, so that the resulting conductive structure is made entirely of the conductive material 168-2. In some embodiments, the upper portion of the conductive material 168-2 and the upper portion of the dielectric layer 164 are also removed during the polishing process. Since the upper portion of the first trench is filled with the conductive material 169 and the upper surface of the dielectric layer 164 is covered by the conductive material 169, the uniformity of the polishing process can be improved. Afterward, the... Fig. The processes shown for forming the semiconductor structure 100 are carried out using 2M-1 to 2P-1 and 2M-2 to 2P-2.

[0082] Fig. Figure 5 illustrates a cross-sectional view of a semiconductor structure 200 in accordance with some embodiments. The semiconductor structure 200 can be similar to that shown in Fig. Semiconductor structure 100 shown in Figures 2P-1 and 2P-2 is different, except that semiconductor structure 200 is a FinFET structure in accordance with some embodiments. The materials and processes for fabricating semiconductor structure 200 may be similar to or the same as those for fabricating semiconductor structure 100 described above and are not repeated herein.

[0083] More specifically, a fin structure 204 is formed that protrudes from the substrate 102, and a gate structure 242 is formed over the fin structure 204, as shown in Fig. 5 shown in accordance with some embodiments. The gate structure 242, in accordance with some embodiments, comprises an interface layer 244, a dielectric gate layer 246, and a gate electrode layer 248. The processes and materials for forming the interface layer 244, the dielectric gate layer 246, and the gate electrode layer 248 are the same as those for forming the interface layer 144, the dielectric gate layer 146, and the gate electrode layer 148 and are not repeated herein. Similar to those in Fig. As shown in 2P-1 and 2P-2, the truncated conductive structure 171 is formed over the gate structure 242, and the conductive structure 178 covers both the contact 156 and the truncated conductive structure 171 over the gate structure 242, as shown in Fig. 5 shown in accordance with some embodiments.

[0084] Fig. Figures 6A-1, 6A-2, 6B-1, and 6B-2 illustrate cross-sectional views of the fabrication of a semiconductor structure 100a according to some embodiments. The semiconductor structure 100a may be the same as the semiconductor structure 100, except that, according to some embodiments, the shapes of the contact and the truncated conductive structure are different. The materials and processes for fabricating the semiconductor structure 100a may be similar to or the same as those for fabricating the semiconductor structure 100 described above and are not repeated herein.

[0085] More specific are Fig. 6A-1 and 6B-1 cross-sectional views shown along the fin direction, and Fig. Figures 6A-2 and 6B-2 are cross-sectional views shown along the gate direction. Similar to those used to form the semiconductor structure 100, the ones in Fig. The processes shown in Figures 1A to 1E, 2A-1 to 2M-1, and 1A-2 to 2M-2 are carried out in accordance with some embodiments to form a truncated conductive structure 171a. Thereafter, the etching process to form a second trench 172a through the dielectric layer 164 and the etch stop layer 162 is carried out as shown in Figures 1A to 1E, 2A-1 to 2M-1, and 1A-2 to 2M-2. Fig. 6A-1 and 6B-1 are shown in accordance with some embodiments. During the etching process, the etchant can be selected to exhibit good etch selectivity between the conductive materials and the dielectric materials, so that the shapes of the contact 156a and the truncated conductive structure 171a can be substantially retained.

[0086] Next, the in Fig. The processes shown and previously described in Figures 20-1, 20-2, 2P-1 and 2P-2 for forming a conductive structure 178a in the semiconductor structure 100a were carried out as shown in Figures 20-1, 20-2, 2P-1 and 2P-2. Fig. 6B-1 and 6B-2 are shown in accordance with some embodiments. Furthermore, in accordance with some embodiments, a cavity 176a is formed in the conductive structure 178a and is also arranged between the truncated conductive structure 171a and the contact 156a. The processes and materials for forming the contact 156a, the truncated conductive structure 171a, and the conductive structure 178a may be the same as those for forming the contact 156, the truncated conductive structure 171, and the conductive structure 178 described above and are not repeated herein.

[0087] Fig. Figure 7 illustrates a cross-sectional view of a semiconductor structure 100b in accordance with some embodiments. The semiconductor structure 100b can be the same as that shown in Fig. The semiconductor structure 100 shown in 2P-1 and 2P-2 is identical, except that its cover layer 150b extends over the gate spacers 126 in accordance with some embodiments. The materials and processes for fabricating the semiconductor structure 100b may be similar to or the same as those for fabricating the semiconductor structure 100 described above and are not repeated herein.

[0088] More specifically, in some embodiments, the cover layer 150b is arranged between the truncated conductive structure 171b and the gate structure 142, and is also arranged between the mask layer 152 and the gate spacer 126. In some embodiments, the cover layer 150b is in direct contact with the separating layer 158 around the contacts 156. In some embodiments, the cover layer 150b vertically overlaps the cavity 176b in the conductive structure 178b.

[0089] In some embodiments, the cover layers 150b are made of W, Ti, Co, Ru, Ni, or the like. The cover layers 150b can be formed using CVD, ALD, electroplating, another suitable process, or a combination thereof. The processes and materials for forming the truncated conductive structure 171b and the conductive structure 178b can be the same as those for forming the truncated conductive structure 171 and the conductive structure 178 described above and are not repeated herein.

[0090] Fig. Figure 8 illustrates a cross-sectional view of a semiconductor structure 100c in accordance with some embodiments. The semiconductor structure 100c can be the same as that shown in Fig. The semiconductor structure 100 shown in Figures 2P-1 and 2P-2 may be different, except that, in accordance with some embodiments, a barrier layer 179 is formed around a conductive structure 178c. The materials and processes for fabricating the semiconductor structure 100c may be similar to or the same as those for fabricating the semiconductor structure 100 described above and are not repeated herein.

[0091] It becomes more specific after the second trench has been constructed (e.g., the second trench 172 as in Fig. 2N-1 and 2N-2 are shown), the barrier layer 179 is formed, which lines the second trench, and the conductive structure 178c is formed above the barrier layer 179, as shown in Fig. Figure 8 shows in accordance with some embodiments. In some embodiments, the barrier layer 179 is made of tantalum nitride, although other materials, such as tantalum, titanium, titanium nitride, or the like, can also be used. The barrier layer 179 can be formed by using a process such as chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced CVD (PECVD), plasma-enhanced physical vapor deposition (PEPVD), atomic layer deposition (ALD), or any other suitable deposition process.

[0092] In some embodiments, a portion of the barrier layer 179 is arranged between the truncated conductive structure 171c and the contact 156. In some embodiments, the barrier layer 179 is in direct contact with the contact 156, the mask layer 152, and the truncated conductive structure 171c. In some embodiments, the lowest portion of the barrier layer 179 is located lower than an uppermost portion of the mask layer 152, the uppermost portion of the contact 156, and the uppermost portion of the truncated conductive structure 171c. The processes and materials for forming the truncated conductive structure 171c and the conductive structure 178c can be the same as those for forming the truncated conductive structure 171 and the conductive structure 178 described above and are not repeated here.

[0093] Fig. Figure 9 illustrates a cross-sectional view of a semiconductor structure 100d in accordance with some embodiments. The semiconductor structure 100d can be the same as that shown in Fig. The semiconductor structure 100 shown in Figures 2P-1 and 2P-2 is to be considered, except that, in accordance with some embodiments, no cavity is formed in a conductive structure 178d. The materials and processes for fabricating the semiconductor structure 100d may be similar to or the same as those for fabricating the semiconductor structure 100 described above and are not repeated herein.

[0094] It becomes more specific after the second trench has been formed (e.g., the one in Fig. 2N-1 and 2N-2, second trench 171), the second trench completely filled with the conductive structure 178d, as shown in Fig. 9 in accordance with some embodiments. The processes and materials for forming the truncated conductive structure 171d and the conductive structure 178d may be the same as those for forming the truncated conductive structure 171 and the conductive structure 178 described above and are not repeated here.

[0095] Fig. Figure 10 illustrates a cross-sectional view of a semiconductor structure 100e in accordance with some embodiments. The semiconductor structure 100e can be the same as that shown in Fig. The semiconductor structure 100 shown in Figures 2P-1 and 2P-2 is described, except that, in accordance with some embodiments, a cavity 176e is formed between a conductive structure 178e and a mask layer 152. The materials and processes for fabricating the semiconductor structure 100e may be similar to or the same as those for fabricating the semiconductor structure 100 described above and are not repeated herein.

[0096] More specifically, after the second trench has been formed, the lower section of the dredged section (e.g., of the one in) becomes Fig. The deepened section 173 of the second trench shown in 2N-1 is not filled with the conductive structure 178e, such that the cavity 176e is formed, as shown in Fig. Figure 10 shows in accordance with some embodiments. In some embodiments, a side wall of the truncated conductive structure 171e and the upper surface of the mask layer 152 are exposed through the cavity 176e. In some embodiments, the lowest region of the cavity 176e is deeper than the lowest section of the conductive structure 178e. The processes and materials for forming the truncated conductive structure 171e and the conductive structure 178e can be the same as those for forming the truncated conductive structure 171 and the conductive structure 178 described above and are not repeated here.

[0097] Fig. 11A and Fig. Figure 11B illustrates cross-sectional views of the fabrication of a semiconductor structure 100f in accordance with some embodiments. The semiconductor structure 100f may be the same as the semiconductor structure 100, except that, in accordance with some embodiments, its truncated conductive structure 171f is taller than the truncated conductive structure 171. The materials and processes for fabricating the semiconductor structure 100f may be similar to or the same as those for fabricating the semiconductor structure 100 described above and are not repeated herein.

[0098] More specifically, the following can be found in Fig. The processes shown in 1A to 1E, 2A-1 to 2L-1 and 1A-2 to 2L-2 for forming a conductive structure (e.g., the one in Fig. 2L-1 shown conductive structure 170). Next, the conductive structure is truncated to form a truncated conductive structure 171f, and the top surface of the truncated conductive structure 171f is higher than the top surface of the etch stop layer 162, as shown in Fig. 11A shown in accordance with some embodiments.

[0099] Next, the in Fig. The processes shown and previously described for 2N-1 to 2P-1 and 2N-2 to 2P-2 were carried out to form a conductive structure 178f in the semiconductor structure 100f, as shown in Fig. 11B in accordance with some embodiments. Furthermore, in accordance with some embodiments, a cavity 176f is formed in the conductive structure 178f and arranged between the truncated conductive structure 171f and the contact 156. Since the side wall of the etch stop layer 162 is completely covered by the truncated conductive structure 171f, the etch stop layer 162 can be protected during the etching process for the formation of the second trench, and therefore the risk of a short circuit between the conductive structure 178f and the adjacent contact 156 (e.g., the one in Figure 11B) can be reduced. Fig. 11B (contact shown on the right) will be reduced.

[0100] The processes and materials for forming the truncated conductive structure 171f and the conductive structure 178f may be the same as those for forming the truncated conductive structure 171 and the conductive structure 178 described above and are not repeated here.

[0101] Fig. 12A and Fig. Figure 12B illustrates cross-sectional views of the fabrication of a semiconductor structure 100g in accordance with some embodiments. The semiconductor structure 100g may be the same as the semiconductor structure 100, except that, in accordance with some embodiments, its truncated conductive structure 171g is located deeper than the truncated conductive structure 171. The materials and processes for fabricating the semiconductor structure 100g may be similar to or the same as those for fabricating the semiconductor structure 100 described above and are not repeated herein.

[0102] More specifically, the following can be found in Fig. The processes shown in 1A to 1E, 2A-1 to 2L-1 and 1A-2 to 2L-2 for forming a conductive structure (e.g., the one in Fig. 2L-1 shown conductive structure 170). Next, the conductive structure is truncated to form a truncated conductive structure 171g, and the top surface of the truncated conductive structure 171g is lower than the top surface of the etch stop layer 162, as shown in Fig. 12A shown in accordance with some embodiments.

[0103] Next, the in Fig. The processes shown and previously described for 2N-1 to 2P-1 and 2N-2 to 2P-2 were carried out to form a conductive structure 178g in the semiconductor structure 100g, as shown in Fig. 12B is shown in accordance with some embodiments. Furthermore, in accordance with some embodiments, a cavity 176g is formed in the conductive structure 178g and is also arranged between the truncated conductive structure 171g and the contact 156. Since the side wall of the etch stop layer 162 is partially covered by the truncated conductive structure 171g, the etch stop layer 162 can still be protected during the etching process and the lateral etching of the etch stop layer 162 can be reduced.

[0104] The processes and materials for forming the truncated conductive structure 171g and the conductive structure 178g may be the same as those for forming the truncated conductive structure 171 and the conductive structure 178 described above and are not repeated herein.

[0105] It should be understood that the semiconductor structures 100a to 100g, which feature the above-described abbreviated conductive structure 171a to 171g and the above-described conductive structure 178a to 178g, can also be applied to FinFET structures, similar to those in Fig. The 5 shown can be applied, although this is not shown in the figures.

[0106] In general, a conductive structure can be formed such that a gate structure and a contact are connected via a S / D structure. However, due to the reduction in device size, the conductive structure may need to be formed in a relatively small trench. In some cases, bottom-up deposition can be used to fill the small trench with conductive material, thus reducing air gaps. However, because the contact may be much higher than the gate structure, when forming the conductive material in the trench, the conductive material formed above the contact may initially block the trench opening, such that the conductive material above the gate structure (i.e., in a deeper section of the trench) may not yet be completely filled. This means that the contact and the gate structure may not be properly connected.

[0107] Accordingly, a first conductive structure (e.g., conductive structure 170) is initially formed above the gate structure 142, and an upper portion of the conductive structure is removed to form a truncated conductive structure (e.g., truncated conductive structures 171 and 171a to 171g) in accordance with some embodiments. Forming the truncated conductive structure allows the subsequently formed second conductive structure (e.g., conductive structures 178 and 178a to 178g) to be formed by bottom-up deposition without concerns regarding the blocking problems described above due to the relatively large height difference. Furthermore, since both the truncated conductive structure and the subsequently formed second conductive structure can be formed by bottom-up deposition, trench filling can be improved, and the performance of the resulting semiconductor structure (e.g.,the semiconductor structure 100, 100a to 100g and 200) can therefore also be improved.

[0108] It should be noted that identical elements in Fig. 1A to 12B may be designated by the same numbers and may contain similar or identical materials and be formed by similar or identical processes; therefore, such redundant details have been omitted for the sake of brevity. Furthermore, it will be understood that, although Fig. 1A to 12B were described in relation to the procedure, which is in Fig. The structures disclosed in sections 1A to 12B are not limited to the procedure, but can exist independently of the procedure as structures on their own. Similarly, although the structures disclosed in sections 1A to 12B are not limited to the procedure, they can exist independently of the procedure. Fig.The methods shown in Figures 1A to 12B are not limited to the disclosed structures; they can also exist independently of the structures alone. Furthermore, in accordance with some embodiments, the nanostructures described above can also include nanowires, nanosheets, or other applicable nanostructures.

[0109] Furthermore, while the disclosed methods are illustrated and described below as a series of actions or events, it is understood that the illustrated sequence of such actions or events may be modified in some other embodiments. For example, some actions may occur in a different order and / or simultaneously with other actions or events besides those illustrated and / or described above. Moreover, it may not be necessary to implement one or more aspects or embodiments of the above description all of the illustrated actions. Finally, one or more of the actions illustrated above may be performed in one or more separate actions and / or phases.

[0110] Furthermore, the terms "circa", "essentially", "substantial", and "about" used above take into account minor variations and can be varied in different technologies and can lie within the range of deviation understood by a person skilled in the art. For example, when used in connection with an event or circumstance, the terms can refer to instances in which the event or circumstance occurs precisely, as well as to instances in which the event or circumstance occurs in close approximation.

[0111] Various embodiments for forming semiconductor structures can be provided. The semiconductor structure can include a gate structure, a source / drain structure adjacent to the gate structure, and a contact above the source / drain structure. A first conductive structure can be formed above the gate structure, and the upper portion of this first conductive structure can then be removed. A second conductive structure can be formed above the contact and the first conductive structure. Since the height difference between the truncated first conductive structure and the contact is relatively small, the second conductive structure can be formed more effectively, and the performance of the semiconductor structure can be improved.

[0112] In some embodiments, a method for fabricating a semiconductor structure is provided. The method for fabricating the semiconductor structure comprises forming a gate structure over a substrate and forming a mask layer covering the gate structure. The method for fabricating the semiconductor structure also comprises forming a source / drain structure adjacent to the gate structure over the substrate and forming a contact over the source / drain structure. The method for fabricating the semiconductor structure also comprises forming a dielectric layer over the contact and the mask layer and forming a first trench through the dielectric layer and the mask layer over the gate structure. The method for fabricating the semiconductor structure also comprises forming a first conductive structure in the first trench and removing the upper portion of the first conductive structure.The process for manufacturing the semiconductor structure also includes forming a second conductive structure through the dielectric layer to cover both the contact and the first conductive structure.

[0113] In some embodiments, a method for fabricating a semiconductor structure is provided. This method comprises forming nanostructures over a substrate and forming a gate structure that encloses the nanostructures. The method also includes forming a source / drain structure attached to the nanostructures adjacent to the gate structure and forming a contact extending to the source / drain structure. Furthermore, the method includes forming a dielectric layer over the contact and the gate structure, forming a first conductive structure through the dielectric layer, and covering the gate structure.The process for producing the semiconductor structure also includes etching an upper section of the first conductive structure so that an upper surface of the first conductive structure is lower than an upper surface of the dielectric layer, and forming a second conductive structure through the dielectric layer to cover both the contact and the first conductive structure.

[0114] In some embodiments, a semiconductor structure is provided. The semiconductor structure comprises a substrate and a gate structure formed over the substrate. The semiconductor structure also comprises a mask layer formed over the gate structure and a source / drain structure adjacent to the gate structure formed over the substrate. The semiconductor structure also comprises a contact formed over the source / drain structure and a first conductive structure formed through the mask layer and extending to the gate structure. The semiconductor structure also comprises a second conductive structure that covers the first conductive structure and the contact. Furthermore, the second conductive structure has an extended section arranged between an upper section of the first conductive structure and an upper section of the contact.

Claims

[1] Method for producing a semiconductor structure (100) comprising the following: Forming a gate structure (142) over a substrate (102); Forming a mask layer (152) that covers the gate structure (142); Forming a source / drain structure (136) adjacent to the gate structure (142) above the substrate (102); Forming a contact (156) over the source / drain structure (136); Formation of a dielectric layer (164) over the contact (156) and the mask layer (152); Forming a first trench (166) through the dielectric layer (164) and the mask layer (152) over the gate structure (142); Formation of a first conductive structure (171) in the first trench (166); Removal of an upper section of the first conductive structure (171); and Formation of a second conductive structure (178) by the dielectric layer (164) to cover both the contact (156) and the first conductive structure (171). [2] Method for producing the semiconductor structure (100) according to claim 1, wherein an upper surface of the first conductive structure (171) is located below an upper surface of the dielectric layer (164) after removal of the upper section of the first conductive structure (171). [3] Method for producing the semiconductor structure (100) according to claim 1 or 2, which further comprises: Forming a second trench (172) through the dielectric layer (164), exposing the contact (156) and the first conductive structure (171) through the second trench (172). [4] Method for producing the semiconductor structure (100) according to claim 3, which further comprises: partial removal of the mask layer (152) so that the second trench (172) extends into the mask layer (152). [5] Method for producing the semiconductor structure (100) according to claim 4, wherein the second conductive structure (178) is formed in the second trench (172). [6] A method for producing the semiconductor structure (100) according to any one of the preceding claims, further comprising: Forming a third conductive structure (169) in an upper section of the first trench (166) above the first conductive structure (168-2); and Removing the third conductive structure (169) before forming the second conductive structure (178). [7] Method for producing the semiconductor structure (100) according to one of the preceding claims, wherein the lowest section of the second conductive structure (178) is located below an upper surface of the mask layer. [8] Method for producing a semiconductor structure (100) comprising the following: Formation of nanostructures (108') over a substrate (102); Forming a gate structure (142) which encloses the nanostructures (108'); Forming a source / drain structure (136) attached to the nanostructures (108') adjacent to the gate structure (142); Forming a contact (156) up to the source / drain structure (136); Formation of a dielectric layer (164) over the contact (156) and the gate structure (142); Forming a first conductive structure (170) by covering the dielectric layer (164) and the gate structure (142); Etching an upper section of the first conductive structure (171) such that an upper surface of the first conductive structure (171) is lower than an upper surface of the dielectric layer (164); and Formation of a second conductive structure (178) by the dielectric layer (164) to cover both the contact (156) and the first conductive structure (171). [9] Method for producing the semiconductor structure (100) according to claim 8, wherein a cavity (176) is formed in the second conductive structure (178). [10] Method for producing the semiconductor structure (100) according to claim 8 or 9, which further comprises: Forming a mask layer (152) over the gate structure (142), wherein an upper surface of the mask layer (152) is essentially at the same level as an upper surface of the contact (156). [11] Method for producing the semiconductor structure (100) according to claim 10, which further comprises: Forming an etch stop layer (162) covering the upper surface of the contact (156) and the upper surface of the mask layer (152); and Forming a first trench (166) through the dielectric layer (164), the etch stop layer (162) and the mask layer (152), the first conductive structure (171) is formed in the first trench (166). [12] Method for producing the semiconductor structure (100) according to claim 11, which further comprises: Etching of the dielectric layer (164) and the etch stop layer (162) to form a second trench (172) which exposes the contact (156) after etching the upper section of the first conductive structure (171); Forming a conductive material (178) in the second trench (172); and Polishing the conductive material to form the second conductive structure (178) in the second trench (172). [13] Method for producing the semiconductor structure (100) according to claim 12, which further comprises: Removing a corner section of the first conductive structure (171) prior to forming the conductive material in the second trench (172). [14] Method for producing the semiconductor structure (100) according to one of claims 11 to 13, wherein the upper surface of the first conductive structure (171) is lower than an upper surface of the etch stop layer (162) after etching the upper section of the first conductive structure (171). [15] Semiconductor structure (100) which has the following features: a substrate (102); a gate structure (142) formed over the substrate (102); a mask layer (152) formed over the gate structure (142); a source / drain structure (136) formed adjacent to the gate structure (142) above the substrate (102); a contact (156) formed above the source / drain structure (136); a first conductive structure (171) formed by the mask layer (152) and extending to the gate structure (142); and a second conductive structure (178) covering the first conductive structure (171) and the contact (156), wherein the second conductive structure (178) has an extended section arranged between an upper section of the first conductive structure (171) and an upper section of the contact (156). [16] Semiconductor structure (100) according to claim 15, wherein a lowermost section of the second conductive structure (178) is located below an upper surface of the first conductive structure (171). [17] Semiconductor structure (100) according to claim 15 or 16, wherein a cavity (176) is embedded in the second conductive structure (178). [18] Semiconductor structure (100) according to claim 17, wherein the cavity (176) is arranged between the upper section of the first conductive structure (171) and the upper section of the contact (156). [19] Semiconductor structure (100) according to any one of claims 15 to 18, which further comprises: a dielectric layer (164) formed over the mask layer (152) and the contact (156), wherein the second conductive structure (178) penetrates the dielectric layer (164) and the elongated section of the second conductive structure (178) extends into the mask layer (152). [20] Semiconductor structure (100) according to any one of claims 15 to 19, which further comprises: a barrier layer (179) which surrounds the extended section of the second conductive structure (178), wherein the barrier layer (179) is in direct contact with the first conductive structure (171), the contact (156) and the mask layer (152).

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