III-V compound semiconductor layer stack with electrical insulation provided by an adhesion-rich layer

Abstract

Structure comprehensive: a semiconductor substrate (10) made of a single-crystal semiconductor material, the semiconductor substrate (10) having an upper surface (12); a layer stack (25) positioned on the upper surface (12) of the semiconductor substrate (10), the layer stack (25) comprising a first layer (28) consisting of a first III-V compound semiconductor material; and a polycrystalline layer (18) in the semiconductor substrate (10), the polycrystalline layer (18) extending laterally beneath the layer stack (25), the polycrystalline layer (18) comprising a first section (18b) having a first thickness and a second section (18a) having a second thickness greater than the first thickness, and the second section (18a) of the polycrystalline layer (18) having a boundary substantially coincident with the top surface (12) of the semiconductor substrate (10).

Description

BACKGROUNDThe present invention relates to semiconductor device fabrication and integrated circuits, and more particularly to semiconductor structures including electrical isolation and methods of forming a semiconductor structure including electrical isolation.Device structures, such as high voltage power electronic devices, are prone to high capacitance and body-to-body leakage when formed using a bulk semiconductor wafer. One measure that may be taken to reduce the susceptibility is to provide the bulk semiconductor wafer with triple-well isolation surrounding the active device region containing the device structure. Another measure that may be taken to reduce susceptibility is to replace the bulk wafer with a silicon-on-insulator wafer in which an upper silicon layer provides an active device report and a buried oxide (BOX) layer is disposed between the active device region and the substrate below the buried insulator layer.The document U.S. Pat. No. 10,192,779 B1 discloses a bulk semiconductor substrate with a buried polycrystalline layer.High voltage power electronic devices, such as high electron mobility transistors, may be fabricated using III-V compound semiconductors to take advantage of their material properties, such as carrier mobility greater than the carrier mobility of silicon. III-V compound semiconductors are obtained by combining Group III elements (aluminum, gallium, indium) with Group V elements (nitrogen, phosphorus, arsenic, antimony). A high electron mobility transistor may include a heterojunction between III-V compound semiconductor materials having different band gaps, such as a heterojunction between binary gallium nitride and trinar aluminum gallium nitride. During operation, a two-dimensional electron gas is formed near an interface at the heterojunction of the high electron mobility transistor. The two-dimensional electron gas defines the channel of the high electron mobility transistor.US 2019 / 0 371 886 A1 discloses a structure comprising a silicon substrate and a III-N substrate (for example gallium nitride substrate) over the silicon substrate. A first III-N transistor structure and a second III-N transistor structure are formed on the III-N substrate with an insulator structure interposed between the two transistors. The insulator structure can be, for example, a shallow trench filled with an oxide or nitride.Although such measures have been found suitable for their intended purpose, semiconductor structures with improved electrical isolation and methods of forming a semiconductor structure including improved electrical isolation are needed.SHORT TEAR-OFFIn an embodiment of the invention, a structure comprises a semiconductor substrate made of a single crystalline semiconductor material, the semiconductor substrate having a top surface; a layer stack positioned on the top surface of the semiconductor substrate, the layer stack comprising a first layer made of a first III-V compound semiconductor material; and a polycrystalline layer in the semiconductor substrate, the polycrystalline layer extending laterally below the layer stack, the polycrystalline layer comprising a first section having a first thickness and a second section having a second thickness greater than the first thickness, and the second section of the polycrystalline layer having a boundary substantially coincident with the top surface of the semiconductor substrateIn an embodiment of the invention, a structure comprises a semiconductor substrate made of a single crystalline semiconductor material; a layer stack on the semiconductor substrate, the layer stack comprising a first layer made of a first III-V compound semiconductor material; and a polycrystalline layer in the semiconductor substrate, the polycrystalline layer extending laterally below the layer stack, the polycrystalline layer comprising a first section having a first thickness and a second section having a second thickness greater than the first thickness, the first III-V compound semiconductor material of the first layer being substantially a single crystal over the first section of the polycrystalline layer, and the first III-V compound semiconductor material of the first layer being disordered over the second section of the polycrystalline layerIn an embodiment of the invention, a method comprises forming a polycrystalline layer in a semiconductor substrate, the semiconductor substrate being made of a single crystalline semiconductor material, and forming a layer stack positioned on an upper surface of the semiconductor substrate, the layer stack comprising a layer made of a III-V compound semiconductor material, the polycrystalline layer extending laterally below the layer stack, the polycrystalline layer comprising a first section having a first thickness and a second section having a second thickness that is greater than the first thickness, and the second section of the polycrystalline layer having a first boundary that substantially coincides with the upper surface of the semiconductor substrate.BRIEF DESCRIPTION OF THE DRAWINGSThe accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate various embodiments of the invention and, together with a general description of the invention given above and the detailed description of the embodiments given below, serve to explain the embodiments of the invention. In the drawings, like reference numerals refer to like features throughout the several views. FIGS. 1-4 are cross-sectional views of a structure at successive stages of processing in accordance with embodiments of the invention. FIGS. 5-7 are cross-sectional views of a structure at successive stages of processing in accordance with alternative embodiments of the invention.DETAILED DESCRIPTIONReferring to FIG. 1 and in accordance with embodiments of the invention, a semiconductor substrate 10 is provided that includes a single-crystal semiconductor material, such as single-crystal silicon. The semiconductor substrate 10 may be a bulk substrate including single crystal semiconductor material (e.g., single crystal silicon). In an alternative embodiment, the semiconductor substrate 10 may be a silicon-on-insulator substrate or an "engineered substrate.". In an embodiment, the semiconductor substrate 10 may be a high resistivity bulk substrate including single crystal silicon having an electrical resistivity greater than or equal to 10 Ωm. In an embodiment, the semiconductor substrate 10 may be a high resistivity bulk substrate including single crystal silicon having an electrical resistivity in a range of 10 Ωm to 500 Ωm. In an alternative embodiment, the semiconductor substrate 10 may be a low resistivity bulk substrate containing single crystal silicon having an electrical resistivity of less than 10 Ωm. In an embodiment, the single crystal semiconductor material of the semiconductor substrate 10 may be aligned with a <111> surface normal. The choice of substrate resistivity is determined by the need to minimize radio frequency losses in the semiconductor substrate 10 for active devices such as field effect transistors and passive devices such as inductors or transmission lines. Increasing the resistivity of the semiconductor substrate 10 may reduce radio frequency losses for active and passive devices.An implanted layer 14 containing damaged or amorphous semiconductor material is formed in the semiconductor substrate 10. The implanted layer 14 may be formed by an ion implantation process that introduces energetic ions, as indicated by the single-peak arrows in the drawing, with ion paths moving on paths through the semiconductor substrate 10. The energetic ions lose energy along their paths via stochastic scattering processes with atomic nuclei and electrons in the semiconductor material being traversed. Energy lost during core collisions shifts target atoms of the semiconductor substrate 10 from their original lattice sites, damaging the crystal lattice structure of the semiconductor substrate 10 and producing point defects. The crystal lattice structure of the semiconductor substrate 10 is damaged or amorphized within the implanted layer 14 compared to an undamaged region 16 of the single crystalline semiconductor material of the semiconductor substrate 10 positioned below a lower boundary of the implanted layer 14. Due to the use of a high dose of the implanted species, the implanted layer 14 of the semiconductor substrate 10 may be changed from crystalline semiconductor material (e.g., single crystal silicon) to damaged or amorphous semiconductor material (e.g., amorphous silicon).The ions may be generated from a suitable source gas and implanted into the semiconductor substrate 10 using an ion implantation tool with one or more implantation conditions. The implantation conditions (e.g., ion species, dose, energy) for the ion implantation process may be selected to tune the characteristics of the implanted layer 14. In one embodiment, the ions may be generated from a noble gas such as He, Ne, Ar, Kr, Xe, Rn, or Og. In an alternative embodiment, the ions may be O ions, N ions, Ge ions, Si ions or other elements that either do not or minimally dope the semiconductor wafer. In an embodiment in which the semiconductor substrate 10 is to remain crystalline at the top surface 12, the ion dose is then selected to be less than a threshold ion dose beyond which recrystallization of the damaged semiconductor material in the implanted layer 14 by subsequent annealing is not possible. In one embodiment, the Ar ion dose may be greater than 1×10 14- ions / cm 2. In an embodiment, the Ar ion dose may be within a range of 1×10 14- ions / cm 2 to 5×10 15- ions / cm 2. In an embodiment, the Ar ion energy may be in a range from about 30 keV to about 1000 keV. The energy and dose for other implanted noble gas species could be similar. The energy and dose for the non-noble gas elements could be similar or lower. For example, if O is used, then a much lower dose, i.e., 10 times to 1000 times lower, could be used. The ion implantation conditions may include a single implantation, multiple implantations performed at different energies, segmented implantations, etc. A thin silicon dioxide layer (not shown) may be deposited on the top surface 12 of the semiconductor substrate 10 before performing the ion implantation process and removed after the ion implantation process.Referring to FIG. 2, in which like reference numerals refer to like features in FIG. 1, and at a subsequent fabrication stage of the processing method, the semiconductor substrate 10 is subjected to a thermal treatment (i.e., an annealing process) that subjects the implanted layer 14 (FIG. 1 ) of the semiconductor substrate 10 to the thermal treatment. In an embodiment, the thermal treatment used to thermally treat the implanted layer 14 of the semiconductor substrate 10 may be a rapid thermal anneal. In one embodiment, the rapid thermal annealing may be performed using, for example, a series of flash lamps that heat the semiconductor substrate 10 to a peak temperature in a range from 900° C. to 1125° C. with a dwell time at the peak temperature of 30 milliseconds to 5 seconds, and in a particular embodiment, the peak temperature may be 1000° C. maintained for a dwell time of less than or equal to 1 second.The thermal treatment recrystallizes a portion of the damaged semiconductor material of the implanted layer 14 into a polycrystalline layer 18 in the semiconductor substrate 10. the polycrystalline layer 18 contains grains of polycrystalline semiconductor material (e.g., polysilicon) and defects as remaining damage in addition to the polycrystalline grains. The defects may contain trapped atoms of the implanted species (e.g., Ar). The thermal treatment also recrystallizes the damaged semiconductor material of the implanted layer 14 between the polycrystalline layer 18 and the top surface 12 into a layer 24 of the semiconductor substrate 10 comprising single crystal semiconductor material (e.g., single crystal silicon). The recrystallized single crystal semiconductor material in layer 24 does not have polycrystalline grains and defects, unlike polycrystalline layer 18.In the representative embodiment, the polycrystalline layer 18 may comprise a single layer of polycrystalline semiconductor material. In an alternative embodiment, multiple layers of polycrystalline semiconductor material may result from the implantation and thermal treatment if multiple implant energy (i.e., implant grooves) are used to form the implanted layer 14. The recrystallized single crystal layer 24 is located between an upper boundary 20 of the polycrystalline layer 18 and the top surface 12, and the semiconductor substrate 10 includes single crystal semiconductor material below a lower boundary 22 of the polycrystalline layer 18. In an alternative embodiment, in which the implanted layer 14 is recrystallized by oven annealing as the thermal treatment, the polycrystalline layer 18 may extend entirely to the top surface 12 of the semiconductor substrate 10. The furnace annealing may be performed within a temperature range of 900° C. to 1100° C.The polycrystalline layer 18 may be characterized as a trap-rich (trap-rich) material having an electrical resistivity that is greater than or equal to the electrical resistivity of the single crystalline semiconductor material of the semiconductor substrate 10. In an embodiment, the polycrystalline layer 18 may have an electrical resistivity that is greater than or equal to 10 Ωm. In an embodiment, the electrical resistivity of the polycrystalline layer 18 may be within a range of 100 Ωm to 10,000 Ωm. In an embodiment, the single-crystal semiconductor material of the substrate may have an electrical resistivity of 10 to 100 Ωm, and the polycrystalline layer 18 may have an electrical resistivity 10 times to 100 times larger (i.e., within a range of 100 to 10,000 Ωm).Referring to FIG. 3, wherein like reference numerals refer to like features in FIG. 2, and at a subsequent fabrication stage of the processing method, a layer stack 25 including one or more non-IV group semiconductor layers is formed on the top surface 12 of the semiconductor substrate 10. In an embodiment, the layer stack 25 may comprise one or more layers consisting of Group III-V compound semiconductor materials. In an embodiment, the layer stack 25 may comprise multiple layers consisting of different Group III-V compound semiconductor materials.In an embodiment, the layer stack 25 may include a buffer layer 26, a channel layer 28, a spacer layer 30, and a barrier layer 32. The layers 26, 28, 30, 32 may be serially formed using an epitaxial growth process, such as metal organic chemical vapor deposition. The layers 26, 28, 30, 32 may each have a crystal structure that is a single crystal or, alternatively, substantially a single crystal, with varying levels of crystalline defectivity present. The layers 26, 28, 30, 32 may further comprise a plurality of sub-layers of varying composition or doping. The buffer layer 26 may include multiple sub-layers tailored in material composition, doping, and / or layer thickness to accommodate lattice mismatch between the material of the semiconductor substrate 10 and the material of the channel layer 28. The buffer layer 26 may include a seed layer containing a material, such as aluminum nitride, adjacent to the semiconductor substrate 10. The channel layer 28 disposed over the buffer layer 26 may include a III-V compound semiconductor material such as gallium nitride. The spacer layer 30 and the barrier layer 32 are disposed over the channel layer 28, with the spacer layer 30 between the channel layer 28 and the barrier layer 32. The spacer layer 30 may be thin and may include a material such as aluminum nitride. The barrier layer 32 may include a material, such as aluminum gallium nitride, aluminum nitride, or indium aluminum nitride, that provides an interface with the channel layer 28 of a different composition. Spacer layer 30 and barrier layer 32 contribute, besides the material properties of channel layer 28, to provide a two-dimensional electron gas, during device operation, at the interface filled with highly mobile and abundant electrons.Referring to FIG. 4, in which like reference numerals refer to like features in FIG. 3, and at a subsequent fabrication stage of the processing method, an active device structure 31 may be formed using the layer stack 25 of a III-V compound semiconductor material. For example, the active device structure 31 may be a high electron mobility transistor (HEMT) including a gate electrode 34, a source region 36 and a drain region 38. The gate electrode 34 may be made of a metal, such as a metal nitride, and may be patterned with lithography and etching processes to define a given shape. The source region 36 and the drain region 38 may be formed by patterning openings in the spacer layer 30 and the barrier layer 32 with lithography and etching processes, and then depositing a metal, such as a metal nitride, that may be patterned with lithography and etching processes. The source region 36 and the drain region 38 may directly contact the channel layer 28, and metal atoms from the source and drain regions 36, 38 may diffuse into the channel layer 28. Although not shown, the layer stack 25 may be patterned with lithography and etching processes in connection with the formation of the active device structure 31 to define a raised mesa encapsulated by subsequently deposited dielectric material.There follows middle-of-line processing and back-end-of-line processing, which includes forming contacts, vias, and wiring for an interconnect structure 40 coupled to the active device structure 31. In an embodiment, a passive device 42 such as an inductor, a capacitor, a resistor, or a transmission line may be formed by back-end-of-line processing in the interconnect structure 40. In an embodiment, the active device structure 31 may not be present and only the passive device 42 may be present.The polycrystalline layer 18, which is characterized by a high electrical resistance, may improve the linearity of the active device structure 31 during operation.Referring to FIG. 5, wherein like reference numerals refer to like features in FIG. 2, and at a subsequent fabrication stage of a processing method according to alternative embodiments, a dielectric layer 46 may be deposited on the top surface 12 of the semiconductor substrate 10 after the implanted layer 14 is formed but prior to the thermal treatment converting the implanted layer 14 into the polycrystalline layer 18. The dielectric layer 46 may be patterned with lithography and etching processes such that a portion 48 of the semiconductor substrate 10 is covered and a portion 50 of the semiconductor substrate 10 is uncovered (i.e., exposed). The dielectric layer 46 may be made of silicon nitride and / or silicon dioxide. In one embodiment, the dielectric layer 46 may include a sub-layer of silicon dioxide formed by thermal oxidation and a thicker sub-layer of silicon nitride formed by liquid phase chemical vapor deposition on the silicon dioxide sub-layer.Referring to FIG. 6, wherein like reference numerals refer to like features in FIG. 5, and at a subsequent fabrication stage of the processing method, the thermal treatment is performed as described in connection with FIG. 2 to transform the implanted layer 14 into the polycrystalline layer 18. The layer 24 of single crystal semiconductor material is formed from the implanted layer 14 during the thermal treatment and is formed between the polycrystalline layer 18 and the top surface 12 in the region 50 where the dielectric layer 46 is not present on the top surface 12. A section 18 aof the polycrystalline layer 18 is thicker under the dielectric layer 46 in the region 48 than a section 18 bof the polycrystalline layer 18 in the region 50. in particular, the polycrystalline layer 18 in the region 50 has a thickness, t 1, and the section 18 aof the polycrystalline layer 18 in the region 48 has a thickness, t 2, which is greater than the thickness, t 1. In an embodiment, the section 18 aof the polycrystalline layer 18 has an upper boundary that coincides or substantially coincides with the upper surface 12 of the semiconductor substrate 10. In an embodiment, the sections 18 a, 18 bof the polycrystalline layer 18 and the single crystal layer 24 may have thicknesses in a range from about one hundred (100) nanometers (nm) to about one (1) micrometers (μm).Referring to FIG. 7, wherein like reference numerals refer to like features in FIG. 6, and at a subsequent fabrication stage of the processing method, the dielectric layer 46 is removed and the layer stack 25 is formed on the top surface 12 of the semiconductor substrate 10, as described in connection with FIG. 3. In an embodiment, the active device structure 31 (FIG. 4 ) may subsequently be formed using the layer stack 25 in the region 50.The section of the layer stack 25 in the region 48 formed over the thicker section 18 aof the polycrystalline layer 18 has a different crystallinity state than the section of the layer stack 25 in the region 50 formed over the layer 24 of single crystal semiconductor material. In particular, the section of the layer stack 25 in the region 48 is disordered due to crystallization that is delayed due to the existence of the polycrystalline layer 18 in the region 48 as a non-single crystal template at the top surface 12 for the epitaxial growth process, and the layer stack 25 in the region 50 has a crystal structure that is single crystal or substantially single crystal. In an embodiment, the section of the layer stack 25 formed over the thicker section 18 aof the polycrystalline layer 18 may include amorphous III-V semiconductor material in the portions of the layers 26, 28, 30, 32 associated with that section of the layer stack 25. The section of the layer stack 25 formed in the region 48 may reduce a mechanical stress, which may allow the use of a thinner semiconductor substrate 10, and the section of the layer stack 25 formed in the region 50 may provide an electrical insulation for the subsequently formed active device structure 31.The above-described methods are used in the manufacture of integrated circuit chips. The resulting integrated circuit chips may be sold by the paver in raw wafer form (e.g., as a single wafer having multiple unpackaged chips), as a bare chip (bare die), or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier having conductors attached to a motherboard or other higher level carrier) or in a multichip package (e.g., a ceramic carrier having one or both surface interconnections or buried interconnections). In either case, the chip may then be integrated with other chips, discrete switching elements, and / or other signal processing devices as part of either an intermediate product or an end product.References herein to terms modified by an approximation language, such as "about," "about," and "substantially," are not intended to be limited to the precise value specified. The approximation language may correspond to the precision of an instrument used to measure the value, and may be + / - 10% of the value(s) specified, unless otherwise dependent on the precision of the instrument.References herein to terms such as "vertical," "horizontal," etc., are exemplary and not limiting to provide a reference frame. The term "horizontal" as used herein is defined as a plane parallel to a conventional plane of a semiconductor substrate regardless of its actual three-dimensional spatial orientation. The terms "vertical" and "normal" refer to a direction that is perpendicular to the horizontal as just defined. The term "lateral" refers to a direction within the horizontal plane.A feature "connected" or "coupled" to another feature or to another feature may be directly connected or coupled to or to the other feature, or instead, one or more intervening features may be present. A feature may be "directly connected" or "directly coupled" to another or another feature if intervening features are not present. A feature may be "indirectly connected" or "indirectly coupled" to another or another feature if at least one intervening feature is present. A feature "on" or "contacting" may be directly on or in direct contact with the other feature, or instead, one or more intervening features may be present. A feature may be "directly on" or "in direct contact" with another feature if intervening features are not present. A feature may be "indirectly on" or in "indirect contact" with another feature if at least one intervening feature is present.

Claims

A structure comprising: a semiconductor substrate (10) made of a single crystalline semiconductor material, the semiconductor substrate (10) having a top surface (12); a layer stack (25) positioned on the top surface (12) of the semiconductor substrate (10), the layer stack (25) comprising a first layer (28) made of a first III-V compound semiconductor material; and a polycrystalline layer (18) in the semiconductor substrate (10), the polycrystalline layer (18) extending laterally below the layer stack (25), the polycrystalline layer (18) comprising a first section (18b) having a first thickness and a second section (18a) having a second thickness greater than the first thickness, and the second section (18a) of the polycrystalline layer (18) having a boundary substantially coincident with the upper surface (12) of the semiconductor substrate (10).The structure of claim 1, wherein the single crystal semiconductor material of the semiconductor substrate (10) is aligned with a <111> surface normal.The structure of claim 2, wherein the polycrystalline layer (18) has an electrical resistivity that is within a range of 100 Ωm to 10,000 Ωm.The structure of any of claims 1 to 3, wherein the polycrystalline layer (18) comprises an upper boundary (20) and a lower boundary (22), and the semiconductor substrate (10) comprises a layer (24) of the single crystalline semiconductor material between the upper surface (12) and the upper boundary (20) of the polycrystalline layer (18).The structure of any one of claims 1 to 4, wherein the first III-V compound semiconductor material of the first layer (28) has a crystal structure that is substantially a single crystal.The structure of any of claims 1 to 5, wherein the first III-V compound semiconductor material of the first layer (28) over the first section (18b) of the polycrystalline layer (18) is substantially a single crystal, and the first III-V compound semiconductor material of the first layer (28) over the second section (18a) of the polycrystalline layer (18) is disordered.A structure comprising: a semiconductor substrate (10) made of a single crystalline semiconductor material; a layer stack (25) on the semiconductor substrate (10), the layer stack (25) comprising a first layer (28) made of a first III-V compound semiconductor material; and a polycrystalline layer (18) in the semiconductor substrate (10), the polycrystalline layer (18) extending laterally below the layer stack (25), the polycrystalline layer (18) comprising a first section (18b) having a first thickness and a second section (18a) having a second thickness greater than the first thickness, wherein the first III-V compound semiconductor material of the first layer (28) over the first section (18b) of the polycrystalline layer (18) is substantially a single crystal, and the first III-V compound semiconductor material of the first layer (28) over the second section (18a) of the polycrystalline layer (18) is disordered.The structure of claim 7, wherein the semiconductor substrate (10) has a top surface (12), the layer stack (25) is positioned on the top surface (12), and the second section (18a) of the polycrystalline layer (18) has a boundary substantially coincident with the top surface (12) of the semiconductor substrate (10).The structure of any of claims 1 to 8, further comprising: an active device comprising a gate electrode (34) on the layer stack (25).The structure of claim 9, wherein the active device is a high electron mobility transistor.The structure of any of claims 1 to 10, further comprising: an interconnect structure (40) over the layer stack (25) and the polycrystalline layer (18); and a passive device (42) in the interconnect structure (40).The structure according to any one of claims 1 to 11, wherein the layer stack (25) comprises a second layer (30, 32) made of a second III-V compound semiconductor material, and the second III-V compound semiconductor material has a different composition from the first III-V compound semiconductor material.The structure of any one of claims 1 to 12, wherein the first III-V compound semiconductor material is gallium nitride.A method comprising: forming a polycrystalline layer (18) in a semiconductor substrate (10), the semiconductor substrate (10) being made of a single crystalline semiconductor material; and forming a layer stack (25) positioned on a top surface (12) of the semiconductor substrate (10), the layer stack (25) comprising a layer (28) made of a III-V compound semiconductor material, the polycrystalline layer (18) extending laterally below the layer stack (25), the polycrystalline layer (18) comprising a first section (18b) having a first thickness and a second section (18a) having a second thickness greater than the first thickness, and the second section (18a) of the polycrystalline layer (18) having a boundary substantially coincident with the top surface (12) of the semiconductor substrate (10).The method of claim 14, wherein forming the polycrystalline layer (18) in the semiconductor substrate (10) comprising the single-crystal semiconductor material comprises: implanting ions into the semiconductor substrate (10) to create crystalline damage to the single-crystal semiconductor material of the semiconductor substrate (10) in an implanted layer (14) below the top surface (12) of the semiconductor substrate (10); and recrystalizing the implanted layer (14) of the semiconductor substrate (10) with an annealing process to create the polycrystalline layer (18).The method of any of claims 14 or 15, wherein the polycrystalline layer (18) has an electrical resistivity that is within a range of 100 Ωm to 10,000 Ωm.The method of claim 15 or claim 16, further comprising: depositing a patterned dielectric layer (46) over the top surface (12) of the semiconductor substrate (10) that exposes a first region (50) of the semiconductor substrate (10) and that covers a second region (48) of the semiconductor substrate (10).The method of claim 17, wherein the patterned dielectric layer (46) is deposited before the implanted layer (14) of the semiconductor substrate (10) is recrystallized.The method of any of claims 14 to 18, further comprising: forming an active device gate electrode (34) on the layer stack (25).The method according to any one of claims 14 to 19, wherein the single-crystal semiconductor material of the semiconductor substrate (10) is aligned with a <111> surface normal.

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