DEVICES WITH IMPROVED MRAM CROSS-POINT MEMORY WITH VERTICAL ALIGNMENT OF INVERTED MRAM ELEMENTS AND METHOD FOR OPERATURE THE SAME

Abstract

Facility, showing: having a non-volatile memory: a substrate; one or more memory arrays (502, 602) formed on the substrate, each of the arrays including the following: a first set of conductive lines (WL1,1-WL1,4) that run in a first direction parallel to a surface of the substrate; a second set of conductive lines (BL1-BL5) formed above the first set of conductive lines and running in a second direction parallel to the surface of the substrate; a third set of leading lines (WL2,1-WL2,4) formed above the second set of leading lines and extending in the first direction; a first plurality of memory cells (701) each connected between a corresponding (2300) of the first set of conductive lines and a corresponding (2310) of the second set of conductive lines, each of the first plurality of memory cells including a threshold switching selector (2309) connected in series with a magnetoresistive direct access memory device (2302), wherein the magnetoresistive direct access storage device of each of the first plurality of memory cells includes the following: a reference layer (2301) with a fixed magnetic field polarity; and a free layer (2305) connected in series with the reference layer and having a programmable magnetic field polarity, wherein the free layer is formed below the reference layer; and a second plurality of memory cells (701), each of which is connected between a corresponding (2310) of the second set of conductive lines and a corresponding (2320) of the third set of conductive lines, wherein each of the second plurality of memory cells includes a threshold switching selector (2319) connected in series with a magnetoresistive random access memory device (2312), wherein the magnetoresistive random access memory device of each of the plurality of memory cells includes the following: a reference layer (2315) with a fixed magnetic field polarity; and a free layer (2311) which is connected in series with the reference layer and has a programmable magnetic field polarity, wherein the free layer is formed above the reference layer; wherein the device further comprises one or more control circuits (610, 620) which are connected to the first, second and third set of conductive lines, wherein the one or more control circuits are configured to: simultaneous reading of a selected first plurality of memory cells (701) connected to a first of the second set of conductive lines, and a selected second plurality of memory cells (701) connected to the first of the second set of conductive lines.

Description

BACKGROUND

[0001] Memory is used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, non-mobile computing devices, and data servers. Memory can comprise non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when the non-volatile memory is not connected to a power source (e.g., a battery).

[0002] An example of non-volatile memory is magnetoresistive random access memory (MRAM), which uses magnetization to represent stored data, unlike some other memory technologies that use electronic charges for data storage. In general, MRAM includes a large number of magnetic memory cells formed on a semiconductor substrate, with each memory cell representing (at least) one bit of data. A bit of data is written to a memory cell by changing the direction of magnetization of a magnetic element within the memory cell, and a bit is read by measuring the resistance of the memory cell (a low resistance usually represents a "0" bit, and a high resistance usually represents a "1" bit). As used herein, the magnetization direction is the direction in which the magnetic moment is oriented.

[0003] Although MRAM is a promising technology, it is challenging to achieve high bit density and long endurance for fast write operations with current MRAM memory cell designs.

[0004] US 2019 / 0 027 201 A1 discloses an MRAM memory in which MRAM memory cells are arranged in a cross-point pattern in two layers. US 2016 / 0 372 518 A1 relates to a complementary bit cell with a first and a second magnetic tunnel contact element. US 2010 / 0 283 053 A1 relates to a non-volatile memory array with silicon-based diodes. US 2019 / 0 198 106 A1 relates to devices and techniques for programming phase-change memory cells. US 2019 / 0 259809 A1 relates to MRAM memory with a lower and an upper tunnel contact stack. US 2020 / 0 303 454 A1 discloses an MRAM memory with MRAM memory cells arranged in a cross-point pattern. The object is to create improved memories. SHORT DESCRIPTION OF THE DRAWING

[0005] Like-numbered elements refer to common components in the different figures. Fig. 1 is a block diagram of one embodiment of a storage system coupled to the host. Fig. Figure 2 is a block diagram of one embodiment of a front-end processor circuit. In some embodiments, the front-end processor circuit is part of a controller. Fig. Figure 3 is a block diagram of one embodiment of a back-end processor circuit. In some embodiments, the back-end processor circuit is part of a controller. Fig. 4 is a block diagram of one embodiment of a memory package. Fig. 5 is a block diagram of one embodiment of a memory chip. Fig. 6A and Fig. 6B illustrate an example of control circuits coupled to a memory structure by wafer-to-wafer bonding. Fig. 7A illustrates one embodiment of a portion of a memory array forming a cross-point architecture in an oblique view. Fig. 7B and Fig. 7C show side views and top views of the cross point structure in Fig. 7A. Fig. 7D illustrates an embodiment of a portion of a two-tier memory array forming a cross-point architecture in an oblique view. Fig. 8A and Fig. 8B illustrates one embodiment of the structure of an MRAM memory cell. Fig. 9 illustrates in more detail one embodiment of an MRAM memory cell design as it would be implemented in a cross-point array. Fig. 10A and Fig. 10B illustrates the writing of an MRAM memory cell using a spin torque transfer (STT) mechanism. Fig. 11A and Fig. 11B illustrate embodiments for integrating threshold switch selectors into an MRAM memory array having a cross-point architecture. Fig. 12 illustrates an embodiment of a memory array having a cross-point architecture in which multiple memory cells are accessed simultaneously. Fig. 13 illustrates an embodiment of a memory array with a cross-point architecture showing the positions of contacts from drivers to bit lines and word lines. Fig. 14 is a flow diagram of one embodiment of a process of concurrently accessing multiple memory cells in a crosspoint array. Fig. 15 is a flowchart illustrating one embodiment of a process of concurrently accessing multiple memory cells in a crosspoint array including performing an SSR. Fig. 16A represents the current versus time for the access current driven through the selected word lines during an SRR. Fig. Figure 16B illustrates the voltage versus time for the voltage across a selected MRAM cell during SRR and corresponds to Fig. 16A. Fig. Figure 17 illustrates a flowchart of a process for writing back data to MRAM cells after a destructive SRR. Fig. 18 illustrates a flowchart of a second stage process of writing data to MRAM cells. Fig. 19A illustrates the write current versus time for a write current provided to a selected word line. Fig. Figure 19B shows the voltage across the MRAM cell as a function of time and corresponds to Fig. 19A. Fig. 20 is a flowchart of a process of simultaneously writing MRAM cells in which all selected MRAM cells are first written to the AP state or the P state. Fig. 21A and Fig. 21B are an embodiment of a set of waveforms for the current and voltage, respectively, for the Layer 1 cell of the Fig. 11A and Fig. 11B in one read operation. Fig. 22 shows an example of the voltage of the MRAM device while the threshold switch selector switches from an off state to an on state. Fig. Figure 23 illustrates a two-tier embodiment of a cross-point memory architecture in which the MRAM devices in the lower layer are inverted relative to the upper layer to minimize capacitance during a read operation. Fig. 24 is a flow diagram of an embodiment for performing a self-referencing read operation using the structure of Fig. 23. Fig. 25 is a flow diagram of an embodiment for forming the structure of Fig. 23. DETAILED DESCRIPTION

[0006] The object is achieved by the devices according to patent claims 1 and 11 and the method according to patent claim 9. Further embodiments emerge from the dependent patent claims.

[0007] In a memory array with a cross-point architecture, a first set of conductive lines extends across the surface of a substrate, and a second set of conductive lines is formed over the first set of conductive lines, the second set extending across the substrate in a direction perpendicular to the first set of conductive lines. The memory cells are located at the cross-point contacts of the two sets of conductive lines. Embodiments for the memory cells may include a programmable resistive element, such as an MRAM memory device, connected in series with a selector switch. One type of selector switch is a threshold switch selector, such as an ovonic threshold switch (OTS), which can be implemented in a space-saving manner and without the need for an additional control line compared to other switching elements, such as a transistor.When a voltage or current applied across or through a threshold switch selector is above a certain level, the threshold voltage (V. th ) or the threshold current (I th ), it switches into a conductive state, a V hold in series with a resistor. When the threshold switch selector first turns on, a transient voltage spike is applied across the series-connected MRAM device because the V hold less than V th can be, especially since a higher V th (by thickening the selector) leads to less leakage. And a lower V hold results in more available write current for a given voltage supply, such as 3.3 V. This transient current can be briefly larger than I read or I write, which can change the state of the memory cell before it can be detected, resulting in a disturbance. The risk of such a disturbance can be reduced and a read operation can be performed sooner by dissipating the transient voltage spike more quickly, such as by reducing the cell, line, and transistor selection and the driver capacitance associated with the selected memory bit.

[0008] In a cross-point architecture with two or more memory cell layers, the MRAM devices of each layer would typically be formed with the same vertical alignment of the MRAM device layers. MRAM devices have directionality, whereby, when spin-transfer torque is used to write the memory cell, current applied in one direction is used to write the MRAM device from a high-resistance anti-parallel state (HRS or AP) to a low-resistance parallel state (LRS or P), and current applied in the opposite direction is used to write the MRAM device from the low-resistance state to the high-resistance state. Due to this directionality, there is often also a preferred direction for applying a read current when reading a memory cell, since more current may be required for a longer time to write the bit from P to AP.Because the memory cells of the different layers have the same orientation, one of these layers can discharge the transient voltage spike more quickly when the threshold switch selector turns on for a read operation, as its drive capacity may be lower. By inverting the MRAM structure for one layer relative to the other, both layers can be given the orientation that allows this spike to be dissipated more quickly, reducing the likelihood that a stored data state will be altered before it is captured. This can also lead to improved read latency access time.

[0009] Fig. 1 is a block diagram of one embodiment of a storage system 100 connected to a host 120. The storage system 100 may implement the technology presented herein for operating a cross-point memory array that is excessively drifted. Many different types of storage systems may be used with the technology proposed herein. Example storage systems include solid-state drives ("SSDs"), memory cards including dual in-line memory (DIMM) for DRAM replacement, and embedded memory devices; however, other types of storage systems may also be used.

[0010] The storage system 100 from Fig. 1 includes a controller 102, a non-volatile memory 104 for storing data, and local memory (e.g., DRAM / ReRAM) 106. The controller 102 includes a front-end processor (FEP) circuit 110 and one or more back-end processor (BEP) circuits 112. In one embodiment, the FEP circuit 110 is implemented on an ASIC. In one embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, a unified ASIC controller may combine both the front-end and back-end functions. The ASICs for each of the BEP circuits 112 and the FEP circuit 110 are implemented on the same semiconductor such that the controller 102 is manufactured as a system on a chip ("SoC"). The FEP circuit 110 and the BEP circuit 112 both include their own processors.In one embodiment, FEP circuitry 110 and BEP circuitry 112 operate in a master-slave configuration, with FEP circuitry 110 being the master and each BEP circuitry 112 being a slave. For example, FEP circuitry 110 implements a flash translation layer (FTL) or a media management layer (MML) that performs memory management (e.g., garbage collection, wear leveling, etc.), logical-to-physical address translation, host communication, DRAM (local volatile memory) management, and overall SSD (or other non-volatile memory) operation. BEP circuitry 112 manages storage operations within the memory packages / chip at the request of FEP circuitry 110. For example, BEP circuitry 112 may perform read, erase, and program operations.Additionally, the BEP circuit 112 may perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), control the toggle mode interfaces to the memory packs, etc. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packs.

[0011] In one embodiment, non-volatile memory 104 includes a plurality of memory packages. Each memory package includes one or more memory chips. Therefore, controller 102 is connected to one or more non-volatile memory chips. In one embodiment, each memory chip in memory packages 104 uses NAND flash memory (including two-dimensional NAND flash memory and / or three-dimensional NAND flash memory). In other embodiments, the memory package may include other memory types, such as storage class memory (SCM) based on resistive random access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase change memory (PCM). In other embodiments, the BEP or FEP may be included on the memory chip.

[0012] The controller 102 communicates with the host 120 via an interface 130 implementing a protocol such as NVM Express (NVMe) over PCI Express (PCIe) or using a JEDEC standard Double Data Rate (DDR) or Low-Power Double Data Rate (LPDDR) interface such as DDR5 or LPDDR5. To interoperate with the storage system 100, the host 120 includes a host processor 122, a host memory 124, and a PCIe interface 126 connected along bus 128. The host memory 124 is the physical memory of the host and may be DRAM, SRAM, non-volatile memory, or another memory type. The host 120 is external and separate from the storage system 100. In one embodiment, the storage system 100 is embedded within the host 120.

[0013] Fig. 2 is a block diagram of one embodiment of the FEP circuit 110. Fig. Figure 2 shows a PCIe interface 150 for communicating with host 120 and a host processor 152 in communication with this PCIe interface. Host processor 152 may be any processor type known in the art that is suitable for implementation. Host processor 152 communicates with a Network-On-Chip (NOC) 154. A NOC is a communications subsystem on an integrated circuit, typically between cores in a SoC. NOCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies network theory and techniques to on-chip communications, providing significant improvements over traditional bus and crossbar interconnects. NOC improves the scalability of SoCs and the power efficiency of complex SoCs compared to other designs. The NOC's wires and interconnects are shared by many signals.High parallelism is achieved because all connections in the NOC can work on different data packets simultaneously. Therefore, as the complexity of integrated subsystems grows, a NOC provides improved performance (such as throughput) and scalability compared to previous communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Connected to and in communication with NOC 154 are storage processor 156, SRAM 160, and a DRAM controller 162. DRAM controller 162 is used to work with and communicate with DRAM (e.g., DRAM 106). SRAM 160 is local RAM used by storage processor 156. Storage processor 156 is used to operate the FEP circuitry and perform the various memory operations. Two PCIe interfaces 164 and 166 are also in communication with the NOC. In the embodiment of . Fig. 2, the SSD controller includes two BEP circuits 112; therefore, there are two PCIe interfaces 164 / 166. Each PCIe interface communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two PCIe interfaces.

[0014] The FEP circuitry 110 may also include a Flash Translation Layer (FTL) or, more generally, a Media Management Layer (MML) 158, which performs memory management (e.g., garbage collection, wear leveling, load balancing, etc.), logical-to-physical address conversion, communication with the host, DRAM (local volatile memory) management, and management of the overall operation of the SSD or other non-volatile storage system. The Media Management Layer (MML) 158 may be integrated as part of the memory management, which may handle memory errors and interact with the host. In particular, MML may be a module in the FEP circuitry 110 and be responsible for the internals of memory management. In particular, the MML 158 may include an algorithm in the memory device firmware that translates writes from the host into writes to the memory structure (e.g., 502 / 602 of the following Fig. 5 and Fig. 6) of a chip. MML 158 may be required because: 1) the memory may have a limited duration; 2) the memory structure can only be written to in multiples of pages; and / or 3) the memory structure cannot be written to unless erased as a block. MML 158 understands these potential limitations of the memory structure, which may not be visible to the host. Accordingly, MML 158 attempts to translate writes from the host into writes to the memory structure.

[0015] Fig. 3 is a block diagram of one embodiment of a BEP circuit 112. Fig. Figure 3 shows a PCIe interface 200 for communicating with the FEP circuit 110 (e.g., in conjunction with one of the PCIe interfaces 164 and 166 of Fig. 2). The PCIe interface 200 is for communicating with the two NOCs, 202 and 204. In one embodiment, the two NOCs can be combined into one large NOC. Each NOC (202 / 204) is connected to the SRAM (230 / 260), a buffer (232 / 262), a processor (220 / 250), and a data path controller (222 / 252) via an XOR engine (224 / 254) and an ECC engine (226 / 256). The ECC engines 226 / 256 are used to perform error correction, as is known in the art. The XOR engines 224 / 254 are used to XOR the data so that data can be combined and stored in a manner that can be recovered in the event of a programming error. The data path controller 222 is connected to an interface module to communicate with memory packets over four channels.Thus, the upper NOC 202 is associated with an interface 228 for four channels for communicating with memory packets, and the lower NOC 204 is associated with an interface 258 for four additional channels for communicating with memory packets. Each interface 228 / 258 includes four toggle mode (TM) interfaces, four buffers, and four schedulers. For each channel, there is one scheduler, one buffer, and one TM interface. The processor may be any standard processor known in the art. The datapath controllers 222 / 252 may be a processor, an FPGA, a microprocessor, or another type of controller. The XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuits known as hardware accelerators. In other embodiments, the XOR engines 224 / 254 and ECC engines 226 / 256 may be implemented in software. The schedulers, buffers and TM interfaces are hardware circuits.

[0016] Fig. Figure 4 is a block diagram of one embodiment of a memory package 104 including a plurality of memory chips 292 connected to a memory bus 294 (data lines and chip enable lines). The memory bus 294 is connected to a toggle mode interface 296 for communication with the TM interface of a BEP circuit 112 (see, e.g., Fig. 3). In some embodiments, the memory package may include a small controller connected to the memory bus and the TM interface. The memory package may include one or more memory chips. In one embodiment, each memory package includes eight or 16 memory chips; however, other numbers of memory chips may also be implemented. In another embodiment, the toggle interface is instead the JEDEC standard DDR or LPDDR, with or without variations such as relaxed timing or smaller page sizes. The technology described herein is not limited to any specific number of memory chips.

[0017] Fig. 5 is a block diagram illustrating an example of a memory system 500 that may implement the technology described herein. The memory chip 500, which corresponds to one of the memory chips 292 of Fig. 4, includes a memory array 502 that may include any of the memory cells described below. The array connection lines of the memory array 502 include the various layers of word lines organized as rows and the various layers of bit lines organized as columns. However, other orientations may also be implemented. The memory chip 500 includes a row control circuit 520, the outputs 508 of which are connected to respective word lines of the memory array 502. The row control circuit 520 receives a group of M row address signals and one or more various control signals from the system control logic circuit 560 and may typically include circuits such as row decoders 522, array connection drivers 524, and block select circuits 526 for both read and write operations.Row control circuitry 520 may also include read / write circuitry. In one embodiment, row control circuitry 520 includes sense amplifiers 528, each including circuitry for sensing a state (e.g., voltage) of a word line of memory array 502. In one embodiment, sensing a word line voltage determines a state of a memory cell in a cross-point array. Memory chip 500 also includes column control circuitry 510, whose inputs / outputs 506 are connected to respective bit lines of memory array 502. Although only a single block is shown for array 502, a memory chip may include multiple arrays or "tiles" that can be accessed individually.Column control circuitry 510 receives a group of N column address signals and one or more different control signals from system control logic 560 and may typically include circuitry such as column decoders 512, array port receivers or drivers 514, block select circuits 516, as well as read / write circuits and I / O multiplexers.

[0018] System control logic 560 receives data and commands from a host and provides output data and status to the host. In other embodiments, system control logic 560 receives data and commands from separate control circuitry and provides output data to that control circuitry, where the control circuitry communicates with the host. In some embodiments, system control logic 560 may include a state machine 562 that provides chip-level control of memory operations. In one embodiment, state machine 562 is programmable by software. In other embodiments, state machine 562 uses no software and is implemented entirely in hardware (e.g., electrical circuitry). In another embodiment, state machine 562 is replaced by a microcontroller or microprocessor, either on or off the memory chip.System control logic 560 may also include a power control module 564 that controls the power and voltages supplied to the rows and columns of memory 502 during storage operations, and may include charge pumps and regulation circuitry for generating regulation voltages. System control logic 560 includes a memory 566 in which parameters for the operation of memory array 502 may be stored.

[0019] Commands and data are transferred between controller 102 and memory chip 500 via memory control interface 568 (also referred to as the "communications interface"). Memory control interface 568 is an electrical interface for communicating with memory controller 102. Examples of memory control interface 568 include a toggle mode interface and an Open NAND Flash (ONFI) interface. Other I / O interfaces may also be used. For example, memory control interface 568 may implement a toggle mode interface that connects to the toggle mode interfaces of memory interfaces 228 / 258 for memory controller 102. In one embodiment, memory control interface 568 includes a set of input and / or output pins (I / O pins) connected to lines 102.

[0020] In some embodiments, all elements of memory system 500, including system control logic 560, may be implemented as part of a single chip. In other embodiments, some or all of system control logic 560 may be implemented on a different chip.

[0021] For the purposes of this document, the term “one or more control circuits” may include a controller, a state machine, a microcontroller, and / or other control circuits, such as represented by system control logic 560, or other analog circuits used to control non-volatile memory.

[0022] In one embodiment, memory structure 502 comprises a three-dimensional array of non-volatile memory cells on which multiple memory levels are formed over a single substrate, such as a wafer. The memory structure may comprise any type of non-volatile memory formed monolithically in one or more physical levels of memory cells having an active area disposed over a silicon (or other type of) substrate. In one example, the non-volatile memory cells comprise vertical NAND strings with charge-trapping material.

[0023] In another embodiment, memory structure 502 includes a two-dimensional memory array of non-volatile memory cells. In one example, the non-volatile memory cells are NAND flash memory cells with floating gates. Other types of memory cells (e.g., NOR-type flash memory) may also be used.

[0024] The exact type of memory array architecture or memory cell included in memory structure 502 is not limited to the above examples. Many different types of memory array architectures or memory technologies can be used to form memory structure 326. No specific non-volatile memory technology is required for the purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of memory structure 502 include ReRAM (resistive random access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), and the like.Examples of suitable technologies for the memory cell architectures of memory structure 502 include two-dimensional arrays, three-dimensional arrays, cross-point arrays, stacked two-dimensional arrays, vertical bitline arrays, and the like.

[0025] An example of a ReRAM cross-point memory includes reversible resistive switching elements arranged in cross-point arrays accessed via X-lines and Y-lines (e.g., wordlines and bitlines). In another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element may be used as a state-change element based on the physical relocation of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., silver or copper), with a thin film of the solid electrolyte between the two electrodes.As temperature increases, ion mobility also increases, causing the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element can exhibit a wide range of programming thresholds as a function of temperature.

[0026] Another example is magnetoresistive random access memory (MRAM), which stores data using magnetic storage elements. The elements are formed from two ferromagnetic layers separated by a thin insulating layer, each of which can hold a magnetization. One of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match that of an external field for storing memories. A memory device is constructed from a grid of such memory cells. In one embodiment for programming, each memory cell lies between a pair of write lines arranged at right angles to each other, parallel to the cell, one above and one below the cell. When current flows through them, an induced magnetic field is generated. MRAM-based memory embodiments are discussed in more detail below.

[0027] Phase-change memories (PCMs) exploit the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb2Te3 superlattice to achieve non-thermal phase changes simply by changing the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). Therefore, the programming doses are laser pulses. The memory cells can be locked by preventing the memory cells from receiving the light. In other PCM embodiments, the memory cells are programmed by current pulses. Note that the use of "pulse" in this document does not require a rectangular pulse, but includes a (continuous or discontinuous) oscillation or burst of sound, current, voltage, light, or other wave.These storage elements within each selectable memory cell or bit may include another series element that is a selector, such as an ovonic threshold switch or a metal-insulator substrate.

[0028] The elements of Fig. 5 can be grouped into two parts: the memory cell memory structure 502 and the peripheral circuitry, including all other elements. An important characteristic of a memory circuit is its capacity, which can be increased by increasing the area of ​​the memory chip of the memory system 500 allocated to the memory structure 502; however, this reduces the area available on the memory chip for peripheral circuitry. This can place quite significant limitations on these peripheral elements. For example, the need to fit sense amplifier circuits into the available area can place a significant constraint on sense amplifier design architectures. With respect to the system control logic 560, a reduced availability of area can limit the available functionalities that can be implemented on the chip.Consequently, a fundamental trade-off in designing a memory chip for memory system 500 is the amount of area allocated to memory structure 502 and the amount of area allocated to peripheral circuitry.

[0029] Another area where memory structure 502 and peripheral circuitry often conflict is the processing involved in forming these regions, as these regions often involve different processing technologies and the trade-off of having different technologies on a single chip. For example, if memory structure 502 is NAND flash, it is an NMOS structure, while the peripheral circuitry is often CMOS-based. For example, elements such as sense amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in system control logic 560 often use PMOS devices. Processing operations for fabricating a CMOS chip will differ in many aspects from the processing operations optimized for NMOS flash NAND memory or other memory cell technologies.

[0030] To improve these limitations, the embodiments described below may incorporate the elements of Fig. 5 into separately formed chips, which are then interconnected. In particular, the memory structure 502 may be formed on one chip, and some or all elements of the peripheral circuitry, including one or more control circuits, may be formed on a separate chip. For example, a memory chip may be formed only from the memory elements, such as the array of memory cells of a Flash NAND memory, an MRAM memory, a PCM memory, a ReRAM memory, or another memory type. Some or all of the peripheral circuitry, even including elements such as decoders and sense amplifiers, may then be moved to a separate chip. This allows each of the memory chips to be individually optimized according to its technology.For example, a NAND memory chip can be optimized for an NMOS-based memory array structure without concern for the CMOS elements, which have now been moved to a separate peripheral circuit chip that can be optimized for CMOS processing. This allows more space for the peripheral elements, which can now accommodate additional capabilities that could not be easily accommodated if they were confined to the edges of the same chip containing the memory cell array. The two chips can then be interconnected in a bonded multi-chip memory circuit, with the array on one chip connected to the peripheral elements on the other memory circuit. Although the focus below is on a bonded memory circuit consisting of one memory chip and one peripheral circuit chip, other embodiments may use more chips, such as two memory chips and one peripheral circuit chip.

[0031] Fig. 6A and Fig. 6B show an alternative arrangement to that of Fig. 5, which may be implemented using wafer-to-wafer bonding to provide a bonded die pair for the memory system 600. Fig. 6A shows an example of the peripheral circuitry, including control circuitry, formed in a peripheral circuit or control chip 611 that is coupled to the memory structure 602 formed in the memory chip 601. As at 502 of Fig. 5, the memory chip 601 may include multiple independently accessible arrays or “tiles.” Common components are similar to those in Fig. 5 (e.g., 502 is now 602, 510 is now 610, etc.). It can be seen that the system control circuitry 660, the row control circuitry 620, and the column control circuitry 610 are located in the control chip 611. In some embodiments, all or a portion of the column control circuitry 610 and all or a portion of the row control circuitry 620 are located on the memory structure chip 601. In some embodiments, a portion of the circuitry in the system control logic 660 is located on the memory structure chip 601.

[0032] System control logic 660, row control circuitry 620, and column control circuitry 610 may be formed by a common process (e.g., CMOS process), so adding elements and functionality, such as ECC, that are more typically found on a memory controller 102 may require few or no additional process steps (i.e., the same process steps used to fabricate controller 102 may also be used to fabricate system control logic 660, row control circuitry 620, and column control circuitry 610). While moving such circuitry from a chip, such as memory chip 292, may reduce the number of steps required to fabricate such a chip, adding such control circuitry to a chip, such as control chip 611, does not require any additional process steps.

[0033] Fig. 6A shows column control circuitry 610 on control chip 611 coupled to memory structure 602 on memory chip 601 via electrical paths 606. For example, electrical paths 606 may provide electrical connection between column decoder 612, driver circuitry 614, and block select 616, and the bit lines of memory structure 602. The electrical paths may extend from column control circuitry 610 in control chip 611 through pads on control chip 611 that are connected to corresponding pads of memory structure chip 601, which in turn are connected to bit lines of memory structure 602. Each bit line of memory structure 602 may have a corresponding electrical path in electrical paths 606, including a pair of bonded pads connected to column control circuitry 610.Similarly, row control circuitry 620, including row decoder 622, array driver 624, block select 626, and sense amplifier 628, is coupled to memory structure 602 via electrical paths 608. Each of electrical paths 608 may correspond to a word line, a dummy word line, or a select gate line. Additional electrical paths may also be provided between control chip 611 and array chip 601.

[0034] For the purposes of this document, the term "control circuit" may include one or more of controller 102, system control circuit 660, column control circuit 610, row control circuit 620, a microcontroller, a state machine, and / or other control circuits or other analog circuits used to control non-volatile memory. The control circuit may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FGA, ASIC, an integrated circuit, or another type of circuit.

[0035] In the following discussion, the memory array 502 / 602 of the Fig. 5 and Fig. 6A in the context of a cross-point architecture. In a cross-point architecture, a first set of conductive lines or wires, such as word lines, run in a first direction relative to the underlying substrate, and a second set of conductive lines or wires, such as bit lines, run in a second direction relative to the underlying substrate. The memory cells are located at the intersection of the word lines and bit lines. The memory cells at these cross-points can be formed according to any of a number of technologies, including those described above. The following discussion focuses primarily on embodiments based on a cross-point architecture using MRAM memory cells.

[0036] Fig. 6B is a block diagram showing further details of the arrangement of one embodiment of the integrated memory assembly of the pair of bonded chips 600. The memory chip 601 includes a level or array 602 of memory cells. The memory chip 601 may include additional levels or arrays. A representative bit line (BL) and representative word line (WL) 666 is shown for each level or array 602. There may be thousands or tens of thousands of such bit lines per level or array 602. In one embodiment, an array or level represents a group of connected memory cells that share a common set of uninterrupted word lines and uninterrupted bit lines.

[0037] The control chip 611 includes a series of bitline drivers 614. Each bitline driver 614 is connected to a bitline or, in some embodiments, may be connected to multiple bitlines. The control chip 611 includes a series of wordline drivers 624(1)-624(n). The wordline drivers 660 are configured to provide voltages to the wordlines. In this example, there are "n" wordlines per array or level of memory cells. If the store operation is a program or a read operation, in one embodiment, a wordline within the selected block is selected for the store operation. If the store operation is an erase operation, in one embodiment, all wordlines within the selected block are selected for erasure. The wordline drivers 660 provide voltages to the wordlines in the memory chip 601. As described above with respect to Fig. 6A, the control chip 611 may also include charge pumps, voltage generators, and the like that are not included in Fig. 6B, and which may be used to provide voltages to the word line drivers 660 and / or the bit line drivers 614.

[0038] The memory chip 601 includes a series of bond pads 670a, 670b on a first main surface 682 of the memory chip 601. There may be "n" bond pads 670a to receive voltages from corresponding "n" word line drivers 624(1) through 624(n). One bond pad 670b may be present for each bit line associated with the array 602. The reference number 670 is used to generally refer to the bond pads on the main surface 682.

[0039] In some embodiments, each data bit and each parity bit of a codeword are transmitted through a different pair of bond pads 670b, 674b. The bits of the codeword may be transmitted in parallel across the bond pad pairs 670b, 674b. This provides for very efficient data transmission compared to, for example, the transmission of data between the memory controller 102 and the integrated memory array 600. For example, the data bus between the memory controller 102 and the integrated memory array 600 may provide for, for example, eight, sixteen, or perhaps 32 bits to be transmitted in parallel. However, the data bus between the memory controller 102 and the integrated memory array 600 is not limited to these examples.

[0040] The control chip 611 includes a series of bond pads 674a, 674b on a first main surface 684 of the control chip 611. There may be "n" bond pads 674a to supply voltages from corresponding "n" word line drivers 624(1)-624(n) to the memory chip 601. One bond pad 674b may be present for each bit line associated with the array 602. The reference number 674 is used to generally refer to the bond pads on the main surface 682. Note that there may be bond pad pairs 670a / 674a and bond pad pairs 670b / 674b. In some embodiments, the bond pads 670 and 674, respectively, are flip-chip bond pads.

[0041] In one embodiment, the pattern of bond pads 670 corresponds to the pattern of bond pads 674. Bond pads 670 are bonded to bond pads 674 (e.g., flip-chip bonded). Thus, bond pads 670, 674 electrically and physically couple memory chip 601 to control chip 611. In addition, bond pads 670, 674 enable internal signal transmission between memory chip 601 and control chip 611. Thus, memory chip 601 and control chip 611 are bonded together with bond pads. Although Fig. 6A illustrates a control chip 611 bonded to a memory chip 601, in another embodiment, a control chip 611 is bonded to multiple memory chips 601.

[0042] "Internal signaling" herein refers to the signaling between the control chip 611 and the memory chip 601. Internal signaling enables the circuitry on the control chip 611 to control the storage operations in the memory chip 601. Therefore, the bond pads 670, 674 can be used for storage operation signaling. Herein, "storage operation signaling" refers to all signals related to a storage operation in a memory chip 601. Storage operation signaling could include, but is not limited to, providing a voltage, providing a current, receiving a voltage, receiving a current, sensing a voltage, and / or sensing a current.

[0043] The bond pads 670, 674 may be formed, for example, from copper, aluminum, and alloys thereof. A liner may be located between the bond pads 670, 674 and the main surfaces (682, 684). The liner may be formed, for example, from a titanium / titanium nitride stack. The bond pads 670, 674 and the liner may be applied by vapor deposition and / or plating. The bond pads and the liners together may have a thickness of 720 nm, although this thickness may be greater or lesser in other embodiments.

[0044] Metal interconnects and / or vias may be used to electrically connect various elements in the chips to bond pads 670, 674. Several conductive paths are shown, which may be implemented with metal interconnects and / or vias. For example, a sense amplifier may be electrically connected to bond pad 674b through path 664. With respect to Fig. 6A, electrical paths 606 may correspond to path 664, bond pads 674b, and bond pads 670b. There may be thousands of such sense amplifiers, paths, and bond pads. Note that the BL does not necessarily connect directly to bond pad 670b. Wordline drivers 660 may be electrically connected to bond pads 674a through paths 662. With respect to Fig. 6A, electrical paths 608 may correspond to path 662, bond pads 674a, and bond pads 670a. Note that paths 662 may include a separate conductive path for each wordline driver 624(1)-624(n). Likewise, there may be a separate bond pad 674a for each wordline driver 624(1)-624(n). The wordlines in block 2 of memory chip 601 may be electrically connected to bond pads 670a via paths 664. In Fig. 6B, there are "n" paths 664 for corresponding "n" word lines in a block. A separate pair of bond pads 670a, 674a may be present for each path 664.

[0045] In relation to Fig. 5, the on-chip control circuits of Fig. 6A may also include additional functionality within its logic elements, both more general capabilities typically found in the memory controller 102 and some CPU functions, as well as application-specific features.

[0046] In the following, the system control logic 560 / 660, the column control circuits 510 / 610, the row control circuits 520 / 620 and / or the controller 102 (or equivalent functioning circuits), in combination with all or a subset of the other circuits described in Fig. 5 or on the control chip 611 in Fig. 6A and similar elements in Fig. 5, may be considered part of the one or more control circuits that perform the functions described herein. The control circuits may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FGA, ASIC, integrated circuit, or other type of circuit.

[0047] In the following discussion, the memory array 502 / 602 of Fig. 5 and Fig. 6A is discussed primarily in the context of a cross-point architecture, although much of the discussion can be applied more generally. In a cross-point architecture, a first set of conductive lines or wires, such as word lines, run in a first direction relative to the underlying substrate, and a second set of conductive lines or wires, such as bit lines, run in a second direction relative to the underlying substrate. The memory cells are located at the intersection of the word lines and bit lines. The memory cells at these cross-points can be formed according to any of a number of technologies, including those described above. The following discussion focuses primarily on embodiments based on a cross-point architecture using MRAM memory cells.

[0048] Fig. 7A illustrates an embodiment of a portion of a memory array forming a cross-point architecture in an oblique view. The memory array 502 / 602 of Fig. 7A is an example of an implementation for the memory array 502 in Fig. 5 or Fig. 602 in Fig. 6A, wherein a memory chip may include multiple such array structures. Bit lines BL1-BL5 are arranged in a first direction relative to an underlying substrate (not shown) (shown as extending into the page), and word lines WL1-WL5 are arranged in a second direction perpendicular to the first direction. Fig. Figure 7A is an example of a horizontal cross-point structure in which the word lines WL1-WL5 and BL1-BL5 both run in a horizontal direction relative to the substrate, while the memory cells, two of which are labeled 701, are aligned so that the current flows through a memory cell in a vertical direction (as indicated by I cell shown). In a memory array with additional layers of memory cells as shown below with respect to Fig. 7D, there would be corresponding additional layers of bit lines and word lines.

[0049] As in Fig. 7A, the memory array 502 / 602 includes a plurality of memory cells 701. The memory cells 701 may include rewritable memory cells, such as those implemented using ReRAM, MRAM, PCM, or other material with a programmable resistor. The following discussion focuses on MRAM memory cells, although much of the discussion can be applied more generally. The current in the memory cells of the first memory level is shown as flowing upward, as indicated by arrow I. cell However, current can flow in both directions, as explained in more detail below.

[0050] Fig. 7B and Fig. 7C show side views and top views of the cross point structure in Fig. 7A. The side view of Fig. 7B shows a lower wire or word line WL1 and the upper wires or bit lines BL1-BL nAt the intersection point between each upper and lower wire is a 1201 MRAM memory cell, although PCM, ReRAM, or other technologies may also be used. Fig. 7C is a plan view showing the cross-point structure for M lower wires WL1-WL M and N upper wires BL1-BL N In a binary embodiment, the MRAM cell can be programmed at each crossover point to one of at least two resistance states: high and low. More detailed embodiments of an MRAM memory cell design and techniques for programming them are provided below.

[0051] The crosspoint array of Fig. Figure 7A illustrates an embodiment with a single layer of word lines and bit lines, with the MRAM or other memory cells arranged at the intersection of the two sets of conductive lines. To increase the storage density of a memory chip, multiple layers of such memory cells and conductive lines can be formed. A two-layer example is shown in Fig. 7D illustrates.

[0052] Fig. Figure 7D illustrates an embodiment of a portion of a two-tier memory array forming a cross-point architecture in an oblique view. As shown in Fig. 7A shows Fig. 7D a first layer 718 of memory cells 701 of an array 502 / 602, which are arranged at the intersection points of the first layer of word lines WL 1,1 -WL 1,4 and bit lines BL1-BL5. Above the bit lines BL1-BL5 and between these bit lines and a second set of word lines WL 2,1 -WL 2,4a second layer of memory cells 720 is formed. Although Fig. 7D shows two layers 718 and 720 of memory cells, the structure can be extended upwards by additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array can be Fig. 7D can be biased for read or program operations, so that current flows in each layer from the wordline layer to the bitline layer, or vice versa. The two layers can be structured so that the current flows in the same direction in each layer for a particular operation, or so that the current flows in opposite directions.

[0053] The use of a cross-point architecture enables arrays with a small footprint, and multiple such arrays can be formed on a single chip. The memory cells formed at each cross-point can be resistive-type memory cells, with data values ​​encoded as different resistance levels. Depending on the embodiment, the memory cells can be binary, with either a low-resistance state or a high-resistance state, or multilevel cells (MLCs), which can have an additional resistance between the low-resistance state and the high-resistance state. The cross-point arrays described here can be implemented as memory chip 292 from Fig. 4 can be used to replace the local memory 106, or both. Resistive-type memory cells can be formed according to many of the technologies mentioned above, such as ReRAM, FeRAM, PCM, or MRAM. The following discussion is presented primarily in the context of memory arrays using a cross-point architecture with binary-valued MRAM memory cells, although much of the discussion is more generally applicable.

[0054] Fig. 8A and Fig. 8B illustrate an embodiment of the structure of an MRAM memory cell. In Fig. 8A is a voltage applied across the memory cell between the corresponding word line and bit line of the memory cell, as voltage source V app813. The memory cell includes a bottom electrode 801, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separation or tunneling layer of, in this example, magnesium oxide (MgO) 805, and then a top electrode 811 separated from the free layer 807 by a spacer 809. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 803 and the free layer 807: when the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low resistance state (LRS); and when they have the opposite orientation, the memory cell is in an antiparallel (AP) high resistance state (HRS). An MLC embodiment would include additional intermediate states. The orientation of the reference layer 803 is fixed and, in the example of Fig. 15 is oriented upwards. The reference layer 803 is also known as the fixed layer or pinned layer.

[0055] Data is written to an MRAM memory cell by programming the free layer 807 to have either the same orientation or the opposite orientation. The reference layer 803 is configured to maintain its orientation while programming the free layer 807. The reference layer 803 may have a more complicated structure, including synthetic antiferromagnetic layers and additional reference layers. For simplicity, the figures and discussion omit these additional layers and focus only on the fixed magnetic layer, which is primarily responsible for the tunneling magnetoresistance in the cell.

[0056] In the embodiment of Fig. 8B, a forced current approach is used to access the MRAM cell. The forced current approach can be used to read or write the MRAM cell. In the forced current approach, an access current (e.g., I read I write ) is driven by the lower electrode 801. The current source 823 is part of the driver circuit for the lower electrode 801. A voltage (e.g., V select ) is applied to the upper electrode 811. The terms “read current” (I read ) and “write current” (I write) in conjunction with access currents driven by MRAM cells. A write current is a current driven by a first conductive line (e.g., word line) which, in combination with a voltage applied to a second conductive line (e.g., bit line), will change the state of the MRAM cell. A write current flowing in one direction through the MRAM cell changes an AP-state MRAM cell from the AP state to the P-state. A write current flowing in the other direction through the MRAM cell changes a P-state MRAM cell from the P-state to the AP state. In general, a read current will not change the state of an MRAM cell from the P-state to the AP state or from the AP state to the P-state if it is applied for a limited time, such as less than 30 ns.

[0057] As defined herein, the access current may have a positive magnitude or a negative magnitude. An access current of positive magnitude driven by a first conductive line (e.g., word line) at a given point flows in the opposite direction as an access current of negative magnitude driven by the first conductive line at that given point. Thus, the access current may flow in either direction through the MRAM cell, depending on whether the access current is defined as having a positive or negative magnitude. In one embodiment, the MRAM cell is read by, for example, applying 0 V to the top electrode 811 while driving a current of, for example, 15 microamperes (µA) through the bottom electrode 801. This read current flows from the bottom electrode 801 to the top electrode 811.In one embodiment, the MRAM cell is written from the AP state to the P state by, for example, applying 3 V to the top electrode 811 while driving a write current of, for example, -30 µA through the bottom electrode 801. This write current flows from the top electrode 811 to the bottom electrode 801. In one embodiment, the MRAM cell is written from the P state to the AP state by, for example, applying 0 V to the top electrode 811 while driving a current of, for example, 30 µA through the bottom electrode 801. This write current flows from the bottom electrode 801 to the top electrode 811.

[0058] Fig. Figure 9 illustrates in more detail one embodiment of an MRAM memory cell design as it would be implemented in a cross-point array. When arranged in a cross-point array, the top and bottom electrodes of the MRAM memory cells are two of the adjacent layers of wires of the array, for example, the top and bottom wires of the bi-level or bi-deck array. In the embodiment shown here, the bottom electrode is the word line (WL) 901 and the top electrode is the bit line (BL) 911 of the memory cell, but these can be reversed in some embodiments by reversing the orientation of the memory element. Between the word line 901 and the bit line 911 are the reference layer 903 and the free layer 907, which in turn are separated by the MgO barrier 905. In the embodiment shown in Fig. In the embodiment shown in Figure 9, an MgO cap 908 is also formed on the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. On each side of the memory cell structure, there is a liner 921 and 923, which may be part of the same structure, but in cross-section from Fig. 9 appear separate. On both sides of the lining 921, 923 shows a portion of the filling material 925, 927 used to fill the otherwise empty areas of the cross-point structure.

[0059] Regarding the free layer design 907, embodiments include CoFe or CoFeB alloy with a thickness on the order of ~1-2 nm, where an Ir layer may be interspersed in the free layer near the MgO barrier 905, and the free layer 907 may be doped with Ta, W, or Mo. Embodiments for the reference layer 903 may include a bilayer of CoFeB and a CoPt multilayer coupled with an Ir or Ru spacer 902. The MgO cap 908 is optional but may be used to increase the anisotropy of the free layer 907. The conductive spacers may be conductive metals such as Ta, W, Ru, CN, TiN, and TaN, among others.

[0060] To capture a data state stored in an MRAM, a voltage is applied across the memory cell as represented by V appto determine its resistance state. To read an MRAM memory cell, the voltage difference V app in any direction; however, MRAM memory cells exhibit directionality, and therefore, in some circumstances, reading in one direction may be preferred over the other. For example, the optimal current amplitude for writing a bit in AP (high resistance state, HRS) may be approximately 20% greater than that for writing in P (low resistance state), so that the bit error rate (read disturbance) is less likely when reading in AP (2AP). Some of these circumstances and the resulting directionality of a read operation are discussed below. Bias directionality is particularly addressed in some embodiments for programming MRAM memory cells, as further discussed with respect to Fig. 10A and Fig. 10B is discussed.

[0061] The following discussion is mainly discussed with respect to a perpendicular spin transfer torque MRAM memory cell, where the free layer 807 / 907 of Fig. 8 and Fig. 9 has a switchable magnetization direction perpendicular to the plane of the free layer. Spin-transfer torque ("STT") is an effect in which the orientation of a magnetic layer in a magnetic tunnel junction can be modified using a spin-polarized current. Charge carriers (such as electrons) have a property known as spin, which is a small amount of angular momentum intrinsic to the carrier. An electric current is generally unpolarized (e.g., it consists of 50% spin-up and 50% spin-down electrons). A spin-polarized current is one with more electrons with one of the spins (e.g., a majority of spin-up electrons or a majority of spin-down electrons). By passing a current through a thick magnetic layer (the reference layer), a spin-polarized current can be created.When this spin-polarized current is directed into a second magnetic layer (the free layer), angular momentum can be transferred to this second magnetic layer, changing the magnetization direction of the second magnetic layer. This is called spin-transfer torque. Fig. 10A and Fig. 10B illustrates the use of spin-transfer torque for programming or writing to MRAM. Spin-transfer torque random access memory (STT-MRAM) has the advantages of lower power consumption and better scalability over other MRAM variants. Compared to other MRAM implementations, the STT switching technique requires relatively low power, virtually eliminates the problem of adjacent bit perturbations, and exhibits more favorable scaling for higher memory cell densities (reduced MRAM cell size). The latter also favors STT-MRAM, in which the magnetizations of the free and reference layers are oriented perpendicular to the film plane rather than in-plane.

[0062] Since the STT phenomenon is easier to describe in terms of electron behavior, the Fig. 10A and Fig. 10B and its discussion as electron current, where the direction of the write current is defined as the direction of electron flow. Therefore, the term “write current” with respect to the Fig. 10A and Fig. 10B refers to an electron current. Since electrons are negatively charged, the electron current will be opposite to the conventionally defined current, so that an electron current flows from a lower voltage level to a higher voltage level, rather than the conventional current flow from a higher voltage level to a lower voltage level.

[0063] Fig. 10A and Fig. 10B illustrates writing an MRAM memory cell using the STT mechanism, showing a simplified schematic representation of an example of an STT-switching MRAM memory cell 1000 in which both the reference and free-layer magnetization are in the perpendicular direction. The memory cell 1000 includes a magnetic tunnel junction (MTJ) 1002 comprising an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014 as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is the free layer FL, and the direction of its magnetization can be reversed. The lower ferromagnetic layer 1012 is the reference (or fixed) layer PL, and the direction of its magnetization cannot be reversed.When the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively low. When the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across the memory cell 1000 is relatively high. The data ("0" or "1") in the memory cell 1000 is read by measuring the resistance of the memory cell 1000. In this context, the electrical conductors 1006 / 1008 connected to the memory cell 1000 are used to read the MRAM data. Due to the process and circuit design, both the parallel and antiparallel configurations remain stable in the idle state and / or during a read operation (with a sufficiently low read current).

[0064] For both the reference layer RL 1012 and the free layer FL 1010, the direction of magnetization is the perpendicular direction (i.e., perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). For example, Fig. 10A and Fig. 10B that the magnetization direction of the reference layer RL 1012 is upwards and the magnetization direction of the free layer FL 1010 is switchable between upwards and downwards, which in turn is perpendicular to the plane.

[0065] In one embodiment, the tunnel barrier 1014 is made of magnesium oxide (MgO); however, other materials may also be used. The free layer 1010 is a ferromagnetic metal that has the ability to change / reverse its magnetization direction. Multilayers based on transition metals such as Co, Fe, and their alloys may be used to form the free layer 1010. In one embodiment, the free layer 1010 comprises an alloy of cobalt, iron, and boron. The reference layer 1012 can be many different types of materials, including (but not limited to) multilayers of cobalt and platinum or an alloy of cobalt and iron.

[0066] To “set” the bit value of the MRAM cell (i.e., to select the direction of magnetization of the free layer), an electrical write current 1050 is applied from the conductor 1008 to the conductor 1006, as shown in Fig. 10A. To generate the electron write current 1050, the upper conductor 1006 is set to a higher voltage level than the lower conductor 1008 due to the electron's negative charge. The electrons in the write current 1050 become spin-polarized as they pass through the reference layer 1012 because the reference layer 1012 is a ferromagnetic metal. As the spin-polarized electrons move through the tunnel barrier 1014, conservation of angular momentum can impart a torque to both the free layer 1010 and the reference layer 1012, but this torque is (intentionally) insufficient to affect the magnetization direction of the reference layer 1012.In contrast, if the initial magnetization orientation of free layer 1010 was antiparallel (AP) to reference layer 1012, this spin-transfer torque is (intentionally) sufficient to change the magnetization orientation in free layer 1010 to become parallel (P) to that of reference layer 1012, which is referred to as an antiparallel-to-parallel (AP2P) write operation. The parallel magnetizations then remain stable before and after the write current is turned off.

[0067] In contrast, if the magnetizations of free layer 1010 and reference layer 1012 are initially parallel, the magnetization of free layer 1010 can be switched to become antiparallel to reference layer 1012 by applying an electron write current in the opposite direction to the above case. For example, an electron write current 1052 is applied from conductor 1006 to conductor 1008, as shown in Fig. 10B, by applying the higher voltage level to the lower conductor 1008. This writes a free layer 1010 in a P-state to an AP state, referred to as parallel-to-antiparallel (P2AP) writing. Thus, using the same STT physics, the direction of magnetization of the free layer 1010 can be deterministically tuned to one of two stable orientations by deliberately choosing the electron write current direction (polarity).

[0068] The data ("0" or "1") in memory cell 1000 can be read by measuring the resistance of memory cell 1000. A low resistance typically represents a "0" bit, and a high resistance typically represents a "1" bit, although occasionally the other convention occurs. A read current can be applied across the memory cell (e.g., across magnetic tunnel junction 1002) by applying an electron read current from conductor 1008 to conductor 1006, as described for 1050 in Fig. 10A (the “AP2P direction”); alternatively, the electron read current can be applied from conductor 1006 to conductor 1008, which flows as shown for 1052 in Fig. 10B (the “P2AP direction”). During a read operation, if the electron write current is too high, this can disturb data stored in a memory cell and change its state. For example, if the electron read current exceeds the P2AP direction of Fig. 10B, too high a current or voltage level can switch any memory cells in the low-resistance P-state to the high-resistance AP state. Consequently, although the MRAM memory cell can be read in either direction, the directionality of the write operation may, in various embodiments, favor one read direction over the other, such as when the required write current is higher; e.g., P2AP, so reading in that direction may result in a lower BER (read disturbance).

[0069] Although the discussion of Fig. 10A and Fig. 10B was made in the context of electron current for the read and write currents, the following discussion will be made in the context of conventional current unless otherwise stated.

[0070] Regardless of whether selected memory cells in the array structures of the Fig. 7A-7D are to be read or written, the bit line and the word line corresponding to a selected memory cell (bit) are biased to apply a voltage across the selected memory cell and induce the flow of electrons, as described with respect to the Fig. 10A or Fig. 10B. This will also apply a voltage across unselected memory cells of the array, which can induce currents in unselected memory cells. Although this power dissipation can be mitigated to some extent by designing the memory cells to have relatively high resistance levels for both high and low resistance states, it still results in increased current and power consumption, as well as additional design constraints on the memory cell and array layout.

[0071] One approach to addressing this undesirable leakage current is to place a select element in series with each MRAM or other resistive (e.g., ReRAM, PCM, and FeRAM) memory cell. For example, a select transistor can be placed with each resistive memory cell element in the Fig. 7A-7D can be connected in series, so that elements 701 are now a combination of a selector and a programmable resistor. However, the use of a transistor requires the introduction of additional control lines to turn on the corresponding transistor of a selected memory cell. Furthermore, transistors often do not scale in the same way as the resistive memory element, so as memory arrays move to smaller sizes, the use of transistor-based selectors can be a limiting factor.

[0072] An alternative approach to select elements is to use a threshold switch selector in series with the programmable resistance element to form a single memory cell or bit. A threshold switch selector has a high resistance (in an off or non-conducting state) when set to a voltage less than its threshold voltage (V th ) and a current less than its threshold current (I th) and a low resistance (in an on or conducting state) when biased to a current greater than its threshold current and holding current. The threshold switch selector remains on until its current is reduced below a holding current or the voltage is reduced below a holding voltage. When this occurs, the threshold switch selector returns to the off state. Accordingly, to program a memory cell, a voltage or current sufficient to turn on the associated threshold switch selector and set or reset the memory cell with the resulting state determined by the current direction is applied at a crosspoint if the magnitude is sufficient for writing, for example, when the current is greater than 35 µa for an MRAM with a critical dimension of 20 nm with a resistive area (RA) of 10 Ω-µm 2and to read a memory cell, the threshold switch selector must also be activated by switching on before the resistance state of the memory cell can be determined. One set of examples of a threshold switch selector is an ovonic threshold switch material of an ovonic threshold switch (OTS). Examples, as in Fig. 14 shown below include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si and Ge-Se-As-Te.

[0073] Fig. 11A and Fig. 11B illustrate embodiments for integrating threshold switch selectors into an MRAM memory array with a cross-point architecture. The examples of Fig. 11A and Fig. 11B show two MRAM cells in a two-layer cross-point array, as in Fig. 7D, but in a side view. Fig. 11A and Fig. 11B show a lower first conductive line of word line 1 1100, an upper first conductive line of word line 2 1120 and an intermediate second conductive line of bit line 1110. In these figures, all these lines are shown running from left to right across the page for ease of illustration; in a cross-point array, they would, as shown in the oblique view of Fig. 7D, where the word lines or first conductive lines or wires run in one direction parallel to the surface of the underlying substrate and the bit lines or second conductive lines or wires run in a second direction parallel to the surface of the substrate that is substantially orthogonal to the first direction. The MRAM memory cells are also shown in a simplified form showing only the reference layer, the free layer, and the intermediate tunnel barrier, but in an actual implementation would typically include the additional structure described above with respect to Fig. 9 is described.

[0074] An MRAM cell 1102, which includes the free layer 1101, the tunnel barrier 1103, and the reference layer 1105, is formed above the threshold switch selector 1109, wherein this series connection of the MRAM device 1102 and the threshold switch selector 1109 together forms the layer 1 cell between the bit line 1110 and the word line 1 1100. The series connection of the MRAM device 1102 and the threshold switch selector 1109 functions largely as described above with respect to the Fig. 10A and Fig. 10B when the threshold switch selector 1109 is turned on, except for a small voltage drop across the threshold switch selector 1109. However, first, the threshold switch selector 1109 must be turned on by applying a voltage or current above the threshold value of the threshold switch selector 1109, and then the bias current or voltage must be maintained high enough above the holding current or voltage of the threshold switch selector 1109 to keep it turned on during the subsequent read or write operation.

[0075] On the second layer, an MRAM cell 1112 encloses the free layer 1111, the tunnel barrier 1113, and the reference layer 1115, and is formed above the threshold switch selector 1119. The series connection of the MRAM device 1112 and the threshold switch selector 1119 together forms the Layer 2 cell between the bit line 1110 and the word line 2 1120. The Layer 2 cell operates like the Layer 1 cell, although the lower conductor now corresponds to a bit line 1110 and the upper conductor is now a word line, Word Line 2 1120.

[0076] In the embodiment of Fig. 11A, the threshold switch selector 1109 / 1119 is formed below the MRAM device 1102 / 1112, but in alternative embodiments, the threshold switch selector for one or both layers may be formed above the MRAM device. As described with respect to Fig. 10A and Fig. 10B, the MRAM memory cell is directional. In Fig. 11A, MRAM devices 1102 and 1112 have the same orientation, with free layer 1101 / 1111 overlying (relative to the substrate, not shown) reference layer 1105 / 1115. Forming the layers between the conductive lines with the same structure can have several advantages, particularly with regard to processing, since each of the two layers, as well as subsequent layers in multi-layer embodiments, can be formed following the same processing sequence.

[0077] Fig. Figure 11B illustrates an alternative embodiment similar to that of Fig. 11A, except that in the layer 2 cell, the positions of the reference layer and the free layer are reversed. More specifically, layer cell 1 connects between the word line 1 1150 and the bit line 1160, as shown in Fig. 11A, an MRAM structure 1152 with a free layer 1151 formed over the tunnel barrier 1153, which in turn is formed over the reference layer 1155, wherein the MRAM structure 1152 is formed over the threshold switching selector 1159. The second layer of the embodiment of Fig. 11B again includes an MRAM device 1162 formed over a threshold switch selector 1169 between the bit line 1160 and the word line 2 1170, but with respect to Fig. 11A, the MRAM device 1162 is inverted, with the reference layer 1161 now formed above the tunnel barrier 1163 and the free layer 1165 now formed below the tunnel barrier 1163.

[0078] Although the embodiment of Fig. 11B requires a different processing sequence for forming layers, it may have advantages in some embodiments. In particular, the directionality of the MRAM structure may affect the embodiment of Fig. 11B attractive because when writing or reading in the same direction (with respect to the reference and free layers), the bit line for both the lower layer and the upper layer is biased equally, and both word lines are biased equally. For example, when both layer 1 and layer 2 memory cells are read in the P2AP direction (with respect to the reference and free layers), the bit line layer 1160 is biased, such as in the P2AP direction, the bit line 1160 is biased low (e.g., 0 V) ​​for both the upper and lower cells, with word line 1 1150 and word line 2 1170 both biased to a higher voltage level. Similarly, for writing to the high-impedance AP state, the bit line 1160 is biased low (e.g.,0 V), with word line 1 1150 and word line 2 1170 both biased to a higher voltage level; and for writing to the low resistance P state, bit line 1160 is biased to the high voltage level, with word line 1 1150 and word line 2 1170 both biased to the low voltage level. In contrast, for the embodiment of . Fig. 11A, the bit lines and word lines have reversed their bias levels to perform one of these operations at the upper level relative to the lower level.

[0079] To read or write data from or to an MRAM memory cell, a current is passed through the memory cell. In embodiments where a threshold switch selector is connected in series with the MRAM element, the threshold switch selector must be turned on by applying a sufficient voltage across the series connection of the threshold switch selector and the MRAM element before the current can flow through the MRAM element.

[0080] It can be quite difficult to access more than one bit in a cross-point memory array simultaneously. Techniques for simultaneously accessing multiple memory cells in a cross-point array are disclosed herein. In one embodiment, multiple memory cells in a cross-point array are read simultaneously. In one embodiment, multiple memory cells in a cross-point array are written simultaneously.

[0081] Fig. 12 illustrates one embodiment of a memory array 1202 having a cross-point architecture in which multiple memory cells are accessed simultaneously. The array 1202 includes a set of first conductive lines 1206a-1206h and a set of second conductive lines 1208a-1208d. In one embodiment, the set of first conductive lines 1206a-1206h are wordlines, and the set of second conductive lines 1208a-1208d are bitlines. For convenience, the set of first conductive lines 1206a-1206h may be referred to as wordlines, and the set of second conductive lines 1208a-1208d may be referred to as bitlines. However, the set of first conductive lines 1206a-1206h could be bit lines and the set of second conductive lines 1208a-1208d could be word lines.

[0082] The array 1202 includes a series of memory cells 701. Each memory cell 701 is connected between one of the first conductive lines 1206 and a corresponding one of the second conductive lines 1208. Each memory cell 701 includes a magnetoresistive random access memory (MRAM) element 1202 in series with a threshold switch selector 1204. Therefore, each memory cell 701 may be referred to as an MRAM cell. The threshold switch selector 1204 is configured to become conductive in response to the application of a voltage or current level that exceeds the threshold value of the threshold switch selector 1204.

[0083] Each first conductive line 1206 is driven by one of the current drivers 1210a-1210h. For example, the first conductive line 1206a is driven by the current driver 1210a, the first conductive line 1206b is driven by the current driver 1210b, etc. Each second conductive line 1208 is driven by one of the voltage drivers 1212a-1212d. For example, the second conductive line 1208a is driven by the voltage driver 1212a, the second conductive line 1208b is driven by the voltage driver 1212b, etc. The current driver 1210b drives an access current (I access ) through the selected word line 1206b. Likewise, the current driver 1210g drives I access through the selected word line 1206b. The current drivers 1210 are configured to either source a current or sink a current. Thus, I accessflow in both directions through the selected wordline. Whether a current driver 1210 sources or sinks current, this is referred to herein as driving the current through the wordline. In one embodiment, a relatively low current is driven through unselected wordlines (e.g., 1206a, 1206c, 1206d, 1206e, 1206f, and 1206h). Note that herein, a "selected wordline" means that the wordline is connected to a selected memory cell. An "unselected wordline" means that the wordline is not connected to a selected memory cell. In other words, all memory cells connected to an unselected wordline are unselected memory cells. Note that herein, a "selected bitline" means that the bitline is connected to at least one selected memory cell.An "unselected bit line" means that the bit line is not connected to a selected memory cell. In other words, all memory cells connected to an unselected bit line or an unselected word line are unselected memory cells.

[0084] Two of the memory cells 701b, 701e are selected for simultaneous access. The selected memory cell 701b is located at the intersection of the selected word line 1206b and the selected bit line 1208b. The other memory cells are not selected for access (i.e., unselected memory cells). For example, the memory cells 701a, 701c, 701d, as well as memory cells that are not specifically labeled with a reference number, are not selected for access. The selected memory cell 701e is located at the intersection of the selected word line 1206g and the selected bit line 1208. All other word lines and all other bit lines are not selected. To select a memory cell 701, a selection voltage (V select) is applied to the selected bit line (e.g., bit line 1208b) and an access current is driven through a selected word line (e.g., word lines 1206b, 1206g). A non-selection voltage (V unsel ) is applied to the unselected bit lines (e.g., bit lines 1208a, 1208c, 1208d). In one embodiment, V select a quantity by which the threshold switch selector 1204 is switched on in a selected memory cell. In contrast, V unsel a size that does not turn on the threshold switch selector 1204 in a non-selected memory cell.

[0085] One of the sense amplifiers (SA) 1228a-1228h is connected to each word line. For example, SA 1228a is connected to word line 1206a, SA 1228b is connected to word line 1206b, and so on. Each sense amplifier is configured to sense a voltage on the word line 1206 to which the SA is connected.

[0086] In the example of Fig. 12, there are more word lines than bit lines in the crosspoint array. In one embodiment, there are more bit lines than word lines in the crosspoint array. In one embodiment, the number of bit lines corresponds to the number of word lines in the crosspoint array. In the example of Fig. 12, there are twice as many word lines as bit lines in the crosspoint array; however, a different ratio could also be used.

[0087] In some embodiments, the voltage drivers 1212 are connected at strategic locations to the respective bit lines 1208. In some embodiments, the current drivers 1210 are connected at strategic locations to the respective word lines 1206. Fig. Figure 13 illustrates an embodiment of a memory array 1202 having a cross-point architecture showing the positions of contacts from drivers to bit lines and word lines. The memory array 1202 of Fig. 13, which corresponds to the array 502 / 602 of the Fig. 5 or Fig. 6A, represents the same word lines 1206a-1206h and bit lines 1208a-1208d as the array of Fig. 12. However, the memory cells 701 are in Fig. 13 not shown.

[0088] Each current driver 1210a-1210h is connected to one of the wordlines 1206 via a corresponding one of the wordline contacts 1302a-1302h. In one embodiment, a current driver is connected to its corresponding wordline via a via. Thus, the current driver could be located at a different level of the crosspoint array than the wordline it drives. The current drivers 1210 could be located outside the crosspoint array, such as on the control chip 611. Each wordline contact 1302 is connected to a wordline 1206 at a location that divides the respective wordline 1206 into a first portion and a second portion. For example, the wordline contact 1302c connects to the wordline 1206c at a location that divides the wordline 1206c into a first portion 1312a and a second portion 1312b.In some embodiments, half of the bitlines 1208 are arranged to cross the wordlines 1206 somewhere in the respective first portions, and the other half of the bitlines are arranged to cross the wordlines somewhere in the respective second portions. For example, bitlines 1208a and 1208b cross the first portion 1312a of the wordline 1206c, whereas bitlines 1208c and 1208d cross the second portion 1312b of the wordline 1206c. In some embodiments, the wordline contacts 1302 are located at a midpoint of the respective wordlines 1206. Thus, in some embodiments, the first and second portions of the respective wordlines are approximately the same length.

[0089] Each voltage driver 1212a-1212d is connected to one of the bitlines 1208 via a corresponding one of the bitline contacts 1304a-1304d. In one embodiment, a voltage driver is connected to its corresponding bitline via a via. Thus, the voltage driver could be located at a different level of the crosspoint array than the bitline it drives. The voltage driver 1212 could be located outside the crosspoint array, such as on the control chip 611. Each bitline contact 1304 is connected to a bitline 1208 at a location that divides the respective bitline 1208 into a first portion and a second portion. For example, the bitline contact 1304a connects to the bitline 1208a at a location that divides the bitline 1208a into a first portion 1314a and a second portion 1314b.In some embodiments, half of the wordlines 1206 are arranged to cross the bitlines somewhere in the respective first portions, and the other half of the wordlines 1206 are arranged to cross the bitlines somewhere in the respective second portions. For example, wordlines 1206a-1206d cross the first portion 1314a of bitline 1208a, whereas wordlines 1206e-1206h cross the second portion 1314b of bitline 1208a. In some embodiments, bitline contacts 1304 are located at a midpoint of the respective bitlines 1208. Thus, in some embodiments, the first and second portions of the respective bitlines 1208 are approximately the same length.

[0090] Fig. 14 is a flowchart of one embodiment of a process 1400 of simultaneously accessing multiple memory cells in a cross-point array. In one embodiment, the memory cells are MRAM cells. In one embodiment, the process 1400 is performed to simultaneously read one or more memory cells in a cross-point array. In one embodiment, the process 1400 is performed to simultaneously write multiple memory cells in a cross-point array. In one embodiment, the process 1400 is performed by a control circuit in the memory chip 500. In one embodiment, the process 1400 is performed by a control circuit in the control chip 611. For an explanation of the process 1400, reference is made to the Fig. 13; however, the process 1400 is not limited to the crosspoint array shown in Fig. 13 shown array.

[0091] Step 1402 includes applying a selection voltage to a selected second conductive line 1208. Referring to Fig. 13 becomes V select applied to the second conductive line 1208b by the voltage driver 1212b. Step 1402 may also include applying a non-selection voltage to unselected second conductive lines 1208. Referring to Fig. 13 becomes V unsel by voltage driver 1212a to second conductive line 1208a, by voltage driver 1212c to second conductive line 1208c, and by voltage driver 1212d to second conductive line 1208d. In some embodiments, the second conductive lines are bit lines.

[0092] Step 1404 includes separately driving an access current through each selected first conductive line 1206 to separately drive the access current through each selected memory cell at the same time. Note that the access current can flow in either direction through the first conductive line 1206, depending on whether the access current is defined as having a positive or negative magnitude. The access current is driven through the memory cells while the selection voltage is applied to the selected second conductive line. Referring to Fig. 13 becomes I access driven by the current driver 1210b through the selected first conductive line 1206b to I access through the memory cell 701b. At about the same time, I access driven by the current driver 1210g through the selected first conductive line 1206g to I access through the memory cell 701e. Thus, Iaccess currently driven separately by several selected memory cells in the crosspoint array.

[0093] In one embodiment, the access current used in step 1404 to read the memory cells simultaneously is a current sufficient to read I hold to exceed, for example 15 µa if the MRAM has a CD of 20 nm with an RA of 10 Ω-µm 2 Therefore, the access current may be referred to as a read current. In this case, process 1500 may further include sensing a voltage on each respective selected first conductive line 1206 to read each memory cell simultaneously.

[0094] In one embodiment, the access current in step 1404 is used to simultaneously write the memory cells. Therefore, the access current may be referred to as a write current. In one embodiment, the access current shifts an MRAM cell from the P state to the AP state. Thus, multiple MRAM cells in the crosspoint array can be simultaneously programmed from the P state to the AP state. In one embodiment, the access current shifts an MRAM cell from the AP state to the P state. Thus, multiple MRAM cells in the crosspoint array can be simultaneously programmed from the AP state to the P state. In some embodiments, the write operation is a two-stage operation. In one embodiment of a two-stage MRAM write operation, a first stage shifts all selected memory cells to the AP state. The second stage writes the corresponding or selected MRAM cells from the AP state to the P state.Alternatively, the first stage could program to the P-state and the second stage to the AP-state. In another embodiment, the cell is first read in the P2AP direction with a read current, such as 15 µA, generating a resulting voltage at the global decoded node into the sense amplifier (above the bitline drive to approximately 0 V, bitline decoder, bitline, memory cell, wordline, wordline decoder), with the global node driven by a read current sufficiently high to turn on the bit selector and maintain it in a conducting state. The resulting voltage can be buffered on a capacitor and boosted by coupling the charge of another capacitor into the storage capacitor whose other terminal switches from low to high voltage, e.g., by shifting the stored voltage by 150 mV.Next, the P2AP current is increased to a write current, such as 35 µA, for approximately 50 ns. Next, the reading is performed again, but the resulting voltage is compared by a comparator with the previously stored and set voltage. If the voltage has changed sufficiently (e.g., by more than 150 mV), the bit is in the LRS state. If the change was less than 150 mV, the bit is in the HRS state. Next, the bit can be written back to the LRS state by reversing the direction of the write current, or it can be left in the HRS state.

[0095] A number of different strategies can be used to select which memory cells in the crosspoint array are accessed simultaneously. Referring again to Fig. 13, in some embodiments, the selected memory cells are selected with respect to their positions relative to the bitline contact 1304. In one embodiment of concurrent access, there is a selected bitline and one or more pairs of selected wordlines. For illustrative purposes, some examples are discussed in which there is a selected bitline and a pair of selected wordlines. In one embodiment, the pair of selected wordlines is selected based on the distance from the bitline contact 1304 of the selected bitline to the point where the selected wordline crosses the selected bitline. In one embodiment, the distance from the bitline contact 1304 of the selected bitline to the aforementioned crossing point is approximately the same for both elements of the pair of selected wordlines.In other words, the two elements of the pair of selected wordlines are equidistant from the connection point of the bitline contact to the respective points where each element crosses the selected bitline. Where "equidistant" herein means "approximately the same distance apart." In one embodiment, the difference in distances is less than five percent. Referring to . Fig. 14, for example, the pair could include wordlines 1206b and 1206g. Alternatively, the pair could include wordlines 1206d and 1206e. This strategy results in the IR drop being approximately equal between the location where bitline contact 1304 connects to the selected bitline and the location where the selected bitline connects to the respective selected memory cell. This strategy helps improve read margin, thus ensuring accurate detection of each selected memory cell.

[0096] A similar strategy to the distance-based example above is based on the number of wordlines between the selected wordline and the location where bitline contact 1304 connects to the selected bitline. In one embodiment, each member of the wordline pair is "n" wordlines away from the connection point where bitline contact 1304 connects to the selected bitline. For example, wordlines 1206b and 1206g are each three wordlines away from the location where bitline contacts 1304 connect to bitlines 1208 (in this example, wordlines 1206b and 1206g are counted as one of the three wordlines).Note that in some embodiments, the wordlines may be symmetrically spaced with respect to the position of the bitline contacts, so this strategy also results in approximately the same IR drop between the location where bitline contact 1304 connects to the selected bitline and the location where the selected bitline connects to each respective selected memory cell. Therefore, this strategy helps improve read margin, ensuring accurate detection of each selected memory cell.

[0097] In another distance-based embodiment, the positions of the selected word lines are chosen such that the total distance between the location at which the bit line contact 1304 is connected to the selected bit line and the location at which the respective selected word lines cross the selected bit line remains approximately the same. This will be explained using an example. With reference to Fig. 13, the wordline pairs may be wordlines 1206a and 1206e; wordlines 1206b and 1206f; wordlines 1206c and 1206f; and wordlines 1206d and 1206h. This strategy may be advantageous for error correction. In some cases, the position of the selected memory cell (and thus the position of the selected wordline) affects the reliability of the data stored in the memory cell. As an example, data stored in memory cells along wordline 1206a may be less reliable than data stored in memory cells along wordline 1206d. Likewise, data stored in memory cells along wordline 1206h may be less reliable than data stored in memory cells along wordline 1206e. This strategy therefore reads data with lower reliability at the same time as data with higher reliability.In some embodiments, these two data bits are part of the same ECC codeword. If, instead, a memory cell along wordline 1206a and a memory cell along wordline 1206b were read simultaneously, two lower-reliability bits would be read together, increasing the probability that the codeword would fail to decode. However, by mixing lower-reliability bits with higher-reliability bits, the probability that the codeword would fail to decode is lower. Thus, this strategy improves the decoding of codewords stored in the memory cells.

[0098] A similar strategy to the above-mentioned total pitch-based example is based on the total number of wordlines between the respective elements of a pair of selected wordlines and where the bitline contact 1304 is connected to the selected bitline. In one embodiment, the total number of wordlines is the same for each pair of selected wordlines. Referring to Fig. 13, when the wordline pairs are wordlines 1206a and 1206e, wordlines 1206b and 1206f, wordlines 1206c and 1206f, and wordlines 1206d and 1206h, there are in each case a total of three wordlines between the respective elements of the pair of selected wordlines and where bitline contact 1304 is connected to the selected bitline (in this example, the selected wordlines are not counted as one of the wordlines that are “between” the respective elements of a pair of selected wordlines and where bitline contact 1304 is connected to the selected bitline).

[0099] In some embodiments, concurrently accessing multiple memory cells in a cross-point array includes performing a self-referencing read (SRR) operation. In one embodiment, an SRR read operation is used during concurrent reading of multiple memory cells in a cross-point array. In one embodiment, an SRR read operation is used during concurrent writing of multiple memory cells in a cross-point array. In one embodiment, the SRR read is used to simultaneously place multiple MRAM cells into an AP state.

[0100] Fig. 15 is a flowchart illustrating one embodiment of a process 1500 of simultaneously accessing multiple memory cells in a cross-point array, including performing an SSR. The SRR may be referred to as a destructive SRR, meaning that the original state of the memory cell may be changed during the SRR. In one embodiment, the process 1500 is performed to simultaneously read multiple memory cells in a cross-point array. In one embodiment, the process 1500 is performed during a simultaneous write to multiple memory cells in a cross-point array. In one embodiment, the process 1500 is performed by control circuitry in memory chip 500. In one embodiment, the process 1500 is performed by control circuitry in control chip 611.

[0101] To explain the process 1500, reference is made to Fig. 13; however, the process 1500 is not limited to the crosspoint array shown in Fig. 13. In process 1500, the memory cells are referred to as MRAM cells. However, process 1500 may also be used with other types of memory cells in cross-point arrays. Process 1500 will be described with reference to Fig. 16A and Fig. 16B explained. Fig. 16A represents the current versus time for the access current driven through the selected word lines. Fig. Figure 16B illustrates the voltage versus time for the voltage across a selected MRAM cell.

[0102] Step 1502 includes driving a first read current through each selected word line while applying a select voltage to a selected bit line to drive the first access current through each selected MRAM cell. Referring to Fig. 13 becomes Iaccess driven by the current driver 1210b through the selected first conductive line 1206b to I access through the memory cell 701b. At about the same time, I access driven by the current driver 1210g through the selected first conductive line 1206g to I access through the memory cell 701e. With reference to Fig. 13 becomes V select applied by the voltage driver 1212b to the second conductive line 1208b. In one embodiment, I access 15 µA and V select is 0 V.

[0103] The Fig. 16A and Fig. 16B will now be discussed with respect to an MRAM cell 701 to further execute step 1502. Referring to Fig. 16A, the access current at time t1 is I read increased and up to t3 to I read With reference to Fig. 16B, the voltage across memory cell 701 increases from t1 to t2. Threshold selector 1204 is off between t1 and t2. Between t1 and t2, the access current causes the wordline voltage to increase. The access current also supports any leakage currents in the path. Once the voltage across threshold selector 1204 exceeds the threshold voltage V th When the threshold switch selector 1204 reaches its maximum value, it turns on and enters a low-resistance state (at t2). Therefore, the voltage across the series circuit consisting of the threshold switch selector 1204 and the resistive MRAM element 1202 increases when the threshold switch selector is in the off state.

[0104] As soon as the threshold switch selector 1204 is in the on state (at t2), the I read -current through the selected memory cell 701. Since the access current is limited to I readis maintained, the voltage across the memory cell drops to a level that depends on the series resistance of MRAM element 1202 and the on-resistance of threshold switch selector 1204. For a binary embodiment, the memory cell has a high-resistance AP state and a low-resistance P state. The voltage across the series-connected MRAM element 1202 and threshold switch selector 1204 in response to the I read The voltage resulting from the high resistance state (HRS) and low resistance state (LRS) currents, respectively, is shown as lines 1610 and 1612. Although the discussion here is in the context of an MRAM-based memory cell connected in series with the threshold switch selector, this sensing technique can be similarly applied to other programmable resistance memory cells, such as PCM or ReRAM devices.

[0105] To get back to Fig. 15, step 1504 includes driving a write current through each selected word line while applying a select voltage to the selected bit line to simultaneously drive the write current through each selected MRAM cell. Referring to Fig. 13 becomes l access driven by the current driver 1210b through the selected first conductive line 1206b to l access through the memory cell 701b. At about the same time, I access driven by the current driver 1210g through the selected first conductive line 1206g to I access through the memory cell 701e. With reference to Fig. 13 becomes V select applied by the voltage driver 1212b to the second conductive line 1208b. In one embodiment, I access 30 µA and V select is 0 V.

[0106] The Fig. 16A and Fig. 16B will now be discussed with respect to an MRAM cell 701 to further execute step 1504. Referring to Fig. 16A, the access current at time t3 is I write increased and up to t5 to I write With reference to Fig. 16B, at t3, the voltage across MRAM cell 701 rises. If MRAM cell 701 was in the HRS (line 1610), then the voltage across the MRAM cell rises to the level indicated by line 1620 at t3 and remains there until t5. Recall that the HRS is the AP state. Thus, this MRAM cell remains in the AP state.

[0107] If MRAM cell 701 was in the LRS (line 1612), the voltage across the MRAM cell rises to the level indicated by line 1622 at t3. Recall that the LRS is the P state. If MRAM cell 701 was in the P state, it transitions to the AP state. Fig. Figure 16B shows that line 1622 rises at t4 and intersects with line 1620. This means that the MRAM cell has transitioned from the P-state (LRS) to the AP-state (HRS). A reasonably skilled person will understand that the actual measured voltage is behind the cell and the decoders, at a so-called global decoded node, which goes to the sense amplifier. Current is applied to this global node to drive the memory cell to the memory bit through the wordline decoder, and the other side of the memory bit is held near ground by the bitline decoder driver's N-channel transistor with its source connected to ground.

[0108] To get back to Fig. Returning to Figure 15, step 1506 includes driving a second read current through each selected word line while applying a select voltage to the selected bit line to drive the second access current through each selected MRAM cell. In one embodiment, the second access current has the same direction and substantially the same magnitude as the first access current. Referring to Fig. 13 becomes I access driven by the current driver 1210b through the selected first conductive line 1206b to I access through the memory cell 701b. At about the same time, I access driven by the current driver 1210g through the selected first conductive line 1206g to I access through the memory cell 701e. With reference to Fig. 13 becomes V select applied by the voltage driver 1212b to the second conductive line 1208b. In one embodiment, I access 15 µA and Vselect is 0 V.

[0109] The Fig. 16A and Fig. 16B will now be discussed with respect to an MRAM cell 701 to further execute step 1506. Referring to Fig. 16A, the access current at time t5 is I write on I read reduced and up to t6 to I read With reference to Fig. 16B, the voltage across memory cell 701 drops to the level indicated by 1630 at t5 and remains at that level until t6. Note that line 1630 is at the HRS level. Recall that regardless of the initial state of the MRAM cell, the MRAM cell was placed in the HRS state (AP state) in step 1504.

[0110] Returning again to Fig. 15, step 1508 includes determining a state of each selected MRAM cell prior to reading based on a comparison of a first voltage on each selected wordline from driving the first read current through the selected wordline with a second voltage on each selected wordline from driving the second read current through the selected wordline.

[0111] The Fig. 16A and Fig. 16B will now be discussed with respect to an MRAM cell 701 to further execute step 1508. The first voltage on the selected wordline from applying the first read current is the voltage between t2 and t3. Thus, the first voltage is either the HRS level 1610 or the LRS level 1612. Note that this first voltage may be stored in step 1504, for example, by charging a read capacitor using the wordline voltage. The second voltage on the selected wordline from applying the second read current is the voltage between t5 and t6. This second voltage is typically at about the HRS level 1610. However, the second voltage may differ slightly from the HRS level 1610. By comparing the first voltage with the second voltage, it can be determined whether the MRAM cell was at the HRS level 1610 or at the LRS level 1612 between t2 and t3.

[0112] To get back to Fig. To return to Figure 15, process 1500 has two options after step 1508. Step 1510a is a read option. Step 1510a involves driving a write current through selected word lines 1206 to write back to the memory cell's original state, if necessary. Recall that step 1504 placed all MRAM cells in the AP state. Thus, in step 1510a, all MRAM cells that were originally in the P state are written back to the P state. All MRAM cells that were originally in the AP state are left in the AP state in step 1510a.

[0113] Step 1510b is a write option. Step 1510b includes driving a write current through selected word lines 1206 to write the new state of the memory cell, if necessary. As mentioned, all MRAM cells were set to the AP state in step 1504. Thus, all MRAM cells that are to be written to the P state, regardless of their original state, are written to the P state in step 1510b. All MRAM cells that are to be written to the AP state are left in the AP state in step 1510b.

[0114] Fig. 17 illustrates a flowchart of a process 1700 for writing data back to MRAM cells after a destructive SRR. Process 1700 provides further details of an embodiment of step 1510a. Step 1702 includes performing ECC on data read from the MRAM cells. Process 1500 may simultaneously read multiple bits of a codeword from a single crosspoint array. In some cases, other bits of the codeword are stored in other crosspoint arrays. In one embodiment, system control logic 560 / 660 on either memory chip 500 or control chip 611 reads multiple crosspoint arrays to obtain all bits of the codeword. In one embodiment, system control logic 560 / 660 sends the bits of the codeword to memory controller 102, which decodes the codeword. In some embodiments, the control chip 611 decodes the codeword.Regardless of where the decoding is performed, any errors in the data are corrected.

[0115] Step 1704 includes identifying a set of MRAM cells that were in the P state prior to the destructive SRR. In one embodiment, step 1704 is performed by system control logic 560 / 660 on either memory chip 500 or control chip 611. This identification may be performed based on the results of step 1508 of process 1500.

[0116] Step 1706 includes applying a selection voltage to the selected bit line. Step 1708 includes driving a write current through word lines connected to the identified set of MRAM cells. In one embodiment, I access -30 µA and V selectis 0 V. In step 1708, the current flows through the MRAM cells in the opposite direction compared to the current that flowed in step 1504 of process 1500. Thus, while step 1504 was used to place MRAM cells in the AP state, step 1708 is used to place MRAM cells in the P state.

[0117] Fig. 18 illustrates a flowchart of a second-stage process 1800 of writing data to MRAM cells. Process 1800 provides further details of an embodiment of step 1510b. Step 1802 includes identifying a set of the MRAM cells to be programmed to the P state after the destructive SRR. In one embodiment, step 1802 is performed by system control logic 560 / 660 on either memory chip 500 or control chip 611. This identification may be based on data sent from memory controller 102 to system control logic 560 / 660. For example, system control logic 560 / 660 may determine that MRAM cells are to be programmed to the AP state to store a "0" and that memory cells are to be programmed to the P state to store a "1."

[0118] Step 1804 includes applying a selection voltage to the selected bit line. Step 1806 includes driving a write current through word lines connected to the identified set of MRAM cells. In one embodiment, I access -30 µA and V select is 0 V. In step 1806, the current flows through the MRAM cells in the opposite direction compared to the current that flowed in step 1504 of process 1500. Thus, while step 1504 was used to place MRAM cells in the AP state, step 1806 is used to place MRAM cells in the P state.

[0119] In the Fig. 19A and Fig. Figure 19B shows timing diagrams applied during an MRAM cell write operation. The timing diagrams can be applied to either process 1700 or 1800. Fig. 19A represents the current versus time for the current driven through the selected word lines. Fig. Figure 19B shows the voltage across the MRAM cell versus time. The timing diagrams are similar to those of Fig. 16A and Fig. 16B and 16C illustrate, in some embodiments, the timing following the timing diagrams of the SRR. Thus, for the Fig. 19A and Fig. 19B assume that the MRAM cell is in the AP state at time t1. At time t1, the current supplied to the selected word line drops from 0 A to level I write off. In Fig. 19A is I write shown as a negative value. While I write in Fig. 16A can be 30 µA, for example, I write in Fig. 19A -30 µA. The access current is set to I from t1 to t5 writeIt should be noted that, as defined herein, this access current may flow with negative magnitude from the selected word line 1206 to the current driver 1210. In other words, the current driver 1210 lowers the access current in the example of Fig. 19A. As defined herein, this is an example of driving a negative current through the word line.

[0120] With reference to Fig. 19B the voltage on the MRAM drops from 0 V to V between t1 and t3 ss . The threshold switch selector 1204 is switched off between t1 and t2. As soon as the voltage across the threshold switch selector 1204 exceeds the threshold voltage V thof the threshold switch selector 1204 is reached, it turns on and switches (at t2) to a low-resistance state. After the threshold switch selector 1204 is turned on, the voltage across the MRAM cell can continue to decrease. At time t3, the voltage across the MRAM cell is at a steady-state value (V ss ). In addition, after time t2 the entire I write through the MRAM cell. At time t4, the MRAM cell was switched from the AP state to the P state. Since the P state is a lower-resistance state than the AP state, the absolute magnitude of the voltage across the MRAM cell decreases at t4. In other words, the voltage across the MRAM cell approaches 0 V at t4.

[0121] In one embodiment, MRAM cells in a crosspoint array are written simultaneously by first writing all selected MRAM cells in the crosspoint array to the AP state simultaneously. Then, a set of the selected MRAM cells is simultaneously written from the AP state to the P state. This technique can be modified to first write all selected MRAM cells in the crosspoint array to the P state simultaneously. Then, a set of the selected MRAM cells is simultaneously written from the P state to the AP state.

[0122] Fig. 20 is a flowchart of a process 2000 of concurrently writing MRAM cells, in which all selected MRAM cells are first written to the AP state or the P state. In one embodiment, the process 2000 is performed by a control circuit in memory chip 500. In one embodiment, the process 2000 is performed by a control circuit in control chip 611.

[0123] Step 2002 includes receiving data to be stored in the non-volatile memory device on a communication interface 568 / 668. In one embodiment, memory chip 500 receives the data from memory controller 102. In one embodiment, control chip 611 receives the data from memory controller 102.

[0124] Step 2004 includes identifying a first set of MRAM cells 701 in the crosspoint array for storing a first bit value and a second set of MRAM cells 701 in the crosspoint array for storing a second bit value to store the data. The first set of MRAM cells 701 and the second set of MRAM cells 701 represent all selected MRAM cells 701 in the crosspoint array. In one embodiment, the first bit value is a "1" and the second bit value is a "0." In one embodiment, the first bit value is represented by the AP state and the second bit value is represented by the P state. Thus, a "1" may be represented by the AP state and a "0" may be represented by the P state; however, this mapping may also be reversed.

[0125] Step 2006 includes setting all MRAM cells 701 in the first and second sets to the AP state or the P state. Thus, all selected MRAM cells 701 in the crosspoint array are set to either the AP state or the P state. By this, it is meant that all selected MRAM cells 701 in the crosspoint array are set to either the AP state or, alternatively, all selected MRAM cells 701 in the crosspoint array are set to the P state. In one embodiment, step 2006 includes performing at least a portion of an SRR. For example, step 2006 may include performing at least steps 1502-1504 of process 1500. In one embodiment, steps 1502-1506 are performed. In one embodiment, steps 1502-1508 are performed.

[0126] Step 2008 includes simultaneously placing the first set of MRAM cells in the other of the two states AP or P, while leaving the second set of MRAM cells in one of the two states AP or P. In one embodiment, the first set of MRAM cells has two or more cells and the second set of MRAM cells has zero or more cells. In one embodiment, the first set of MRAM cells has zero or more cells and the second set of MRAM cells has two or more cells. In one embodiment, the first set of MRAM cells has one or more cells and the second set of MRAM cells has one or more cells.

[0127] The following two examples will explain steps 2006 to 2008 in more detail. As one example, in step 2006, both the first and second sets of MRAM cells 701 in the crosspoint array are set to the AP state. In step 2008 of the first example, the first set of MRAM cells is written from the AP state to the P state, while the second set of MRAM cells is left in the AP state. As a second example, in step 2006, both the first and second sets of MRAM cells 701 in the crosspoint array are set to the P state. In step 2008 of the second example, the first set of MRAM cells is written from the P state to the AP state, while the second set of MRAM cells is left in the P state.

[0128] As explained above, when reading data from or writing data to an MRAM memory cell, a current is conducted through the memory cell. In embodiments in which a threshold switch selector is arranged in series with the MRAM device, the threshold switch selector must be turned on before the current can flow through the MRAM device by applying a sufficient voltage across the series connection of the threshold switch selector and the MRAM device. Fig. 21A, Fig. 21B and Fig. 22 this activation of the threshold switch selector is examined in more detail in connection with a read operation.

[0129] The Fig. 21A and Fig. 21B are an embodiment of a set of waveforms for the current and voltage, respectively, for the Layer 1 cell of the Fig. 11A and Fig. 11B in a read operation, where the time axes of the Fig. 21A and Fig. 21B and have the same scaling. Compared to the Fig. 16A and Fig. 16B consider the Fig. 21A and Fig. 21B shows the period up to time t3. In this embodiment, for a read operation, the reading is performed in the P2AP direction, in which the word line 1 1100 / 1150 is biased high and the bit line 1110 / 1160 is set low (e.g., 0 V), so that the (conventional) current flows upwards and flows through the reference layer 1105 / 1155 before flowing through the free layer 1101 / 1151. (Regarding the electron current, the electron flow is in contrast to the conventional current as in Fig. 10B.)

[0130] In the embodiment of the Fig. 21A and Fig. 21B, a forced current approach is used, where the memory is supplied from the reference layer side with a read current I readfrom a current source in the driver circuit for the line. How Fig. 21A through the solid line 2101, the current is set to the value I read and held there for the duration of the current read operation. This current moves the lines that supply the current to the selected memory cell, such as word line 1 1100 / 1150 for the layer 1 memory cell in Fig. 11A / B, and also supports any leakage in the path. As in Fig. As shown in Figure 21B at 2151, the current through the parallel circuit of the threshold selector and the resistive MRAM element increases when the threshold selector is in an off state. Once the voltage across the threshold selector exceeds the threshold voltage V th of the threshold switch selector at 2153 is reached, it switches on and switches to a low-impedance state.

[0131] As soon as the threshold switch selector is in the on state, the I read -Current through the selected memory cell. This is Fig. 21A by the dashed line 2103, which represents the current through the memory cell changing from zero to I read jumps when the threshold switch selector at 2153 turns on. Since the current level is on I read is maintained, the voltage across the memory cell drops to a level that depends on the series resistance of the MRAM device and the on-resistance of the threshold switch selector. For a binary embodiment, the memory cell has a high-resistance anti-parallel state and a low-resistance parallel state. The voltage across the series-connected MRAM device and the threshold switch selector in response to the I readThe resulting voltage for the high resistance state (HRS) and low resistance state (LRS) currents, respectively, is shown as lines 2155 and 2153. The resulting voltage difference can then be measured by a sense amplifier to determine the data state stored in the memory cell. Although the discussion here is in the context of an MRAM-based memory cell connected in series with the threshold switch selector, this sensing technique can be similarly applied to other memory cells with programmable resistance, such as PCM or ReRAM devices.

[0132] Fig. Figure 21B shows the voltage applied during the increase at 2151 until it reaches 2153 V thand then drops to either the high impedance state level at 2155 or the low impedance state at 2153. In an actual device, there is some delay due to resistance and capacitance when the voltage peak at 2153 drops to either 2155 or 2153. This is caused by Fig. 22 for the example of a low-resistance state.

[0133] Fig. Figure 22 shows an example of the voltage across the MRAM device while the threshold switch selector switches from an off state to an on state. Compared to Fig. 21B shows Fig. 22 the voltage V MRAM only above the MRAM device, while Fig. Figure 21B illustrates the voltage across the series circuit consisting of the threshold selector and the resistive MRAM element. Initially, before the threshold selector turns on, the voltage across the MRAM device is zero, while the applied voltage increases up to Vth voltage rises. Once the threshold switch selector turns on, current begins to flow through the MRAM device, and the voltage across the MRAM device is increased to V th -level rise, minus the voltage V hold , which has fallen above the threshold switching selector. Consequently, V MRAM from 0 V to ΔV= (V th - V hold ) jump, after which they react to the applied I read until the voltage drop across the MRAM device in the resistive state; e.g., I read × R MRAM . With an LRS of 25 KΩ and a read current of 15 µA, the voltage across the MRAM device is one V MRAM of 375 mV. Whereas with an HRS of 50 KΩ V mram750 mV (unless the compliance voltage, which limits the voltage at a terminal voltage, is reached). The 375 mV difference can be captured, for example, by adjusting the stored level by a threshold amount, such as 150 mV.

[0134] The speed at which the V MRAM -Voltage close to the asymptotic V MRAM -level depends on the size of the peak of the “snapback voltage” ΔV, which is the difference between (V th - V hold ) and V MRAM and the rate at which charge can flow out of the device, which depends on the RC properties of the memory cell and the lines between which it is connected. This behavior has some practical consequences for the operation of the memory cell.

[0135] A first consequence is that both the low-impedance state and the high-impedance state decay, as in Fig. 22, where Fig. 22 shows the low-impedance state. The high-impedance state exhibits similar behavior, but with a higher asymptotic state. To distinguish these two states, they must be separated by a sufficient distance so that a readout operation can only be performed after sufficient time has elapsed for the two states to have well-defined and differentiable voltage levels.

[0136] Another consequence is that the overcurrent spikes can disrupt the data stored in the memory cell. As with regard to Fig. 10A and Fig. 10B, the state of an MRAM memory can be changed by passing a current through the memory cell, so that if the voltage across or the current through a memory cell is long enough, it can change from a parallel state to an antiparallel state (a P2AP write operation), depending on the direction of the current, as in Fig. 10B, or changes an antiparallel state to a parallel state (an AP2P write operation), as shown in Fig. 10A. For example, the reading process of the Fig. 21A and Fig. 21B as being carried out in the P2AP direction, so that interference from the waveform of Fig. 22 could switch a memory cell with a low-resistance state to the high-resistance state before the data state can be stored.

[0137] As mentioned above, the threshold switch selector controls access to the memory cells. In particular, to apply a voltage or current to a memory cell in order to read or change its resistance state, the corresponding selector must first be activated by applying a sufficiently high voltage, e.g., a voltage that is higher in magnitude than the operating threshold voltage V th, into a conducting state. When the selector is in a non-conducting state, e.g., when a voltage across the selector is less than the operating threshold voltage, the memory cell is isolated and maintains its existing resistive state, since the MRAM voltage has a ratio of [R MRAM / (R MRAM + R selector )] × V applied = V MRAM If the non-conductive R selector (e.g. > 1 MΩ) much larger than the R MRAM (e.g. < 100 Ω), the V MRAM sufficiently low until the selector switches on and its resistance is reduced to, for example, 1 KΩ.

[0138] Consequently, when selecting an MRAM memory cell for reading its data content, the corresponding threshold switch selector is switched on, which provides a snapback of ΔV from V th on V holdThis transient is induced quickly, since an OTS turn-on is, for example, less than 1 ns and the V selector difference is impressed across the MRAM device and decays in a time determined by the threshold switch selector and the internal resistance of the MRAM, the capacitance across the array node (e.g., wire-to-wire capacitance and the capacitance of the transistor and other elements in the drivers), and the series resistance to these capacitive elements. Since this transient can cause a disturbance to the data state stored in the memory cell, and the memory cell cannot be read until the transient has sufficiently decayed, the faster this overvoltage can be dissipated, the less read disturbance will be and the faster a read operation can be completed.

[0139] If in a multi-layer cross-point array structure, as in Fig. 7D, the orientation of the MRAM device in the upper layer 720 is the same as in the lower layer 718 (as in the embodiment of Fig. 11A), during a read in the P2AP direction, as described above for the self-referencing read (SRR), the current in the two layers will flow in different directions. More specifically, during a read in the P2AP direction, the current flows with the direction as shown in Fig. 11A, the current for both the layer 1 cell and the layer 2 cell is in the upward direction. Consequently, when performing a read operation in the P2AP direction for the layer 1 memory cell, word line 1 1100 is set to a high voltage level and bit line 1110 is set to a low voltage level, while when performing a read operation in the P2AP direction for the layer 2 memory cell, bit line 1110 is set to a high voltage level and word line 2 1120 is set to a low voltage level. Note that this requires that bit line 1110 of Fig. 11A is biased low to serve as a current sink when layer 1 is read in the SRR process; but when reading layer 2 in an SRR process, bit line 1110 is instead biased high to serve as a current source. This prevents simultaneous reading of the layer 1 memory cell and the layer 2 memory cell.

[0140] When forming a multi-layer storage structure, as in Fig. 7D or Fig. 11A, it is preferable from a processing point of view that each of the layers is formed in the same way, so that only one module is required. For example, considering Fig. 11A, after forming the first set of conductive lines (word line 1 1100) over a substrate (not shown), a processing module may sequentially form the threshold switch selector, the reference layer, the tunnel barrier, and the free layer (1109, 1105, 1103, and 1101, respectively). After subsequently forming a second set of conductive lines (bit line 1110), the memory cell processing module may then be repeated to form the threshold switch selector, the reference layer, the tunnel barrier, and the free layer (1119, 1115, 1113, and 1111, respectively). Repeating the same set of steps for each subsequent layer simplifies processing, especially since MRAM structures 1102 and 1112 are shown in simplified form and an actual processing module for these elements is more complex.

[0141] Although it is generally advantageous to form all MRAM layers with the same orientation, reversing the orientation of the MRAM device from alternative layers can provide several advantages. Fig. Figure 11B illustrates an embodiment in which the layer 2 memory cell is compared to Fig. 11A has been inverted, so that during an SRR operation, current is forced from word line 1 1150 to bit line 1160 when reading layer 1 memory cells, and from word line 2 1170 to bit line 1160 when reading layer 2 memory cells. This allows the same bias level on bit line 1160 to be used when reading from either level, and also allows simultaneous reading of the memory cells of both levels in the manner of simultaneous access to multiple memory cells described above with respect to the Fig. 14, Fig. 15 and in subsequent figures. Alternatively, the layer 1 memory cells of Fig. 11A may have an inverted orientation, forcing current from bit line 1110 to word line 1 1100 and / or word line 2 1120 during an SRR read operation. Although reversing the orientation of either layer may allow the same bias voltage of bit line 1110 when reading the memory cell of either level, the decision as to which of the two layers is inverted may affect how quickly the Fig. 22 can be derived from the type of transient voltage shown.

[0142] As described above, how quickly the transient spike is generated across the MRAM element when the threshold switch selector is turned on depends on the resistance and capacitance along the path through which this voltage spike discharges. Fig. 11A, where the alignment is the same in both layer 1 and layer 2, for example, word line 1 1100 is pulled high for an SRR read operation in layer 1, while word line 2 is pulled low for an SRR read operation in layer 2. Referring to the word line drivers 1210a-1210h in Fig. 12 or Fig. 13, the pull-up of a word line for the lower level can be implemented using a P-channel device, while the pull-down of a word line for the upper level can be implemented using an N-channel device. Regardless of whether it is based on a PMOS pull-up transistor or an NMOS pull-down transistor, the capacitance of such a driver is largely proportional to its size. NMOS devices can be formed in a smaller size than a PMOS device, given the need for a driver resistor. Consequently, in a device as shown in Fig. 12 or Fig. 13, where the word lines are shorter than the bit lines, the transient is transmitted via the Fig. 22 can be discharged most quickly via a word line selected using an N-channel device that pulls to ground, and the bit line for selecting either the lower or upper layer is pulled close to the positive power supply, for example, 3.3 V for reading P2AP. In order for both layers to have a word line as in the upper layer of Fig. 11A, the orientation of the lower level MRAM device as shown in Fig. 23. Such an arrangement can significantly reduce the bit error rate when reading data by reducing read noise and also enables improved read latency performance.

[0143] Fig. Figure 23 illustrates a two-tier embodiment of a cross-point memory architecture in which the MRAM devices in the lower layer are inverted relative to the upper layer to minimize capacitance during a read operation. Fig. 23 the elements from Fig. 11A is repeated and similarly numbered (e.g., word line 1 1100 is now 2300), but the MRAM component of the layer 1 cell is inverted.

[0144] More precisely, in Fig. 23, the layer-1 memory cell is formed between the lower conductive line of word line 1 2300 and the middle conductive line of bit line 2310. For MRAM device 2302, reference layer 2301 is now formed above tunnel barrier 2303, which in turn is formed above free layer 2305. This is in comparison to layer-1 MRAM device 1101 of Fig. 11A, such that the layer 1 memory cell is detected by forcing current from bit line 2310 through MRAM device 2302. This is represented by the bold arrow leading from bit line 2310 to word line 1 2300. In the embodiment of Fig. 23, the threshold switch selector 2309 is still located below the MRAM device 2302, allowing the processing sequence related to forming this element to be the same in both layers, but alternative embodiments reverse the order of the MRAM device 2302 and the threshold switch selector 2309.

[0145] In layer 2, the memory cell is between the word line 2 2320 and the bit line 2310 as in Fig. 11A, with the free layer 2311 formed over the tunnel barrier 2313, which in turn is formed over the reference layer 2315 with the underlying threshold switch selector 2319. As with the layer 1 memory cell, the layer 2 memory cell is sensed by forcing current from the bit line 2310 through the MRAM device 2312. This is represented by the bold arrow leading from the bit line 2310 to the word line 2320.

[0146] Fig. 23 also schematically illustrates the selection and driver circuitry for word line 1 2300, bit line 2310 and word line 1 2320. Referring to the Fig. 12 and Fig. 13, these elements can be considered part of one of the wordline drivers 1210a-1210h or the bitline drivers 1212a-1212d. As illustrated by the bold arrows, during a read operation in the P2AP direction, the read current is driven from bitline 2310 to one or both of wordline 1 2300 and wordline 2 2320. The current I read (P2AP) can be provided by a current source 2345, which can be based, for example, on a current mirror connected to a supply plane. The current source 2345 supplies the read current I read(P2AP) to bit line 2310 through PMOS device 2343, which receives a decode control signal BL Sel for selecting bit line 2310. The read current is discharged from word line 1 2300 and word line 2 2320 through respective NMOS devices 2341 and 2347, which receive the decode control signal WL1 Sel for selecting word line 1 2300 and the decode control signal WL2 Sel for selecting word line 2 2320, respectively.

[0147] Leakage currents in the threshold switching devices are reduced by increasing the threshold voltage (V th ) and the largest permissible V th -range is achieved when a P-channel pullup device is used on one of the word lines or the bit line for the memory cell and an N-channel pulldown on the other of the word lines and the bit line to V th-crashes. In the dual-layer embodiments primarily described herein, bit lines tend to be intermittent due to their placement between the two separate word lines and also because in the Fig. 12 and Fig. 13 illustrate embodiments. Bitlines tend to have a longer length, the larger the capacitance. Consequently, the rate at which the transient voltage spike can be dissipated when a threshold selection is toggled is primarily determined by the RC characteristic of the wordline. One way to reduce dissipation time and read latency is to reduce capacitance by shortening the lengths of the conductive wires and increasing the wire-to-wire spacing of the array, but both techniques reduce storage density. Another way to reduce dissipation time and read latency without compromising storage density is to reduce the size of the transistors used to drive the conductive wires.By using the smaller sized NMOS devices 2341 and 2347 for the word lines 2300 and 2320 and using the larger sized PMOS device 2343 on the bit line 2310, the capacitance of the primary path for dissipating the transient voltage can be reduced without reducing the density of the array.

[0148] With reference to the Fig. 16A and Fig. 16B, in both readouts between t1-t3 and t5-t6, the current flow is as in Fig. 23, and in both I read used. For the write operation at t3-t5, in which all memory cells are put into the high-resistance AP state, the current is also in the P2AP direction, as in Fig. 23, but using a current source with I write for the forced current. Consequently, in the embodiment of Fig. 23 the array can be operated such that the bit line 2310 is constantly pulled high by the PMOS device 2343, with the current source 2345 being set to I during the time interval t3-t5 write and word lines 2300 and 2320 are constantly pulled low by NMOS devices 2341 and 2347. Only when selected memory cells are written back to the parallel low resistance state (AP2P), as shown in the Fig. 19A and Fig. 19B, these bias voltages are reversed, setting a selected bit line 2310 low and a selected word line of one or both of the word lines 2300 and 2320 high to provide I writein the AP2P direction through a selected memory cell. Note that since both the layer 1 and layer 2 memory cells are biased in the same direction for each of the sub-operations of the SRR process, this enables embodiments in which these operations are performed in parallel for both layers.

[0149] Fig. 24 is a flow diagram of an embodiment for performing a self-referencing read operation using the structure of Fig. 23. The flow describes an SRR process for both the layer 1 memory cell and the layer 2 memory cell, with steps alternating between the two layers. The two layers can be operated independently, so that only the layer 1 or layer 2 operations are performed, or they can be operated simultaneously, so that a particular layer 2 operation is performed concurrently with the corresponding layer 1 operation to read the data contents of both layers simultaneously, as described above for simultaneous reading along multiple word lines.

[0150] In step 2401, the data content of the layer 1 MRAM device 2302 is acquired by I readfrom bit line 2310 to word line 1 2300 by applying the BL-Sel signal to PMOS 2343 and the WL1-Sel signal to NMOS 2341. The resistance state of MRAM device 2302 can then be determined by the corresponding sense amplifier (i.e., one of SAs 1228a-1228h). Similarly, in step 2403, the data content of layer 2 MRAM device 2312 is acquired by applying I read from bit line 2310 to word line 2 2320 by applying the BL-Sel signal to PMOS 2343 and the WL2-Sel signal to NMOS 2347, with the resistance state of MRAM device 2312 determined by the corresponding sense amplifier (i.e., one of SAs 1228a-1228h). Since both the layer 1 and layer 2 memory cells can be biased simultaneously, as in steps 2401 and 2403, these read operations can be performed simultaneously in some embodiments.

[0151] In step 2405, the layer 1 MRAM device 2302 is written to the AP state by I write from the bit line 2310 to the word line 1 2300 by applying the BL-Sel signal to PMOS 2343 and the WL1-Sel signal to NMOS 2341, but with the current source 2345 now I write In step 2407, the layer 2 MRAM device 2312 is written to the AP state by I write from the bit line 2310 to the word line 2 2320 by applying the BL-Sel signal to PMOS 2343 and the WL1-Sel signal to NMOS 2347, with the current source 2345 now being I writeSince both the layer 1 and layer 2 memory cells can be biased simultaneously, as in steps 2405 and 2407, these read operations can be performed simultaneously in some embodiments. The second read of the SRR process can then occur in steps 2409 and 2411, which can be performed as described above for steps 2401 and 2403, respectively.

[0152] When the MRAM element 2302 of the layer 1 memory cell is selected to be written to the low resistance parallel state, an AP2P operation is performed in step 2413 by increasing the write current I writefrom word line 1 2300 to bit line 2310 (i.e., in the opposite direction as in the previous steps). Similarly, when MRAM element 2312 of the layer 2 memory cell is selected to be written to the low-resistance parallel state, an AP2P operation is performed in step 2415 by driving the write current I write from word line 2 2320 to bit line 2310. Since both steps 2413 and 2415 drive current from the corresponding word line into the same bit, these operations can be performed simultaneously.

[0153] As in the previous discussion of Fig. As noted in Figure 24, these steps can be performed in parallel, since each pair of steps biases the bit line and the corresponding word line in the same way. Conversely, if only one of the layers is to be read, only the steps relevant to that layer can be performed.

[0154] Fig. 25 is a flow diagram of an embodiment for forming the structure of Fig. 23. Within each step, the processing may be similar to the processing required to form the structure of Fig. 11A would be carried out, but Fig. Figure 25 highlights the change in the order of processing steps between Layer 1 and Layer 2. As mentioned above, Fig. 23 simplified, showing only the free layer, the tunnel barrier and the reference layer of the MRAM, while a more detailed description would include this additional structure described above, for example, with respect to Fig. 9 is described.

[0155] In step 2501, a first set of conductive wires extending in a first direction is formed over a substrate that is in Fig. 23 is not shown. In the view of Fig. 23, the first conductive lines include word line 1 2300 and would correspond to the lower set of word lines of Fig. 7D. In the embodiment of Fig. 23, the threshold switching devices are formed below the MRAM device of each layer, and the threshold switching selector 2309 is formed in step 2503. In other embodiments, the threshold switching devices could be formed above the MRAM device in one or both of the layers. In step 2504, the layer 1 MRAM device 2302 is formed. In the embodiment of Fig. 23, in which the layer 1 MRAM device is inverted, step 2504 includes a sequence of substeps, wherein at step 2505 the free layer 2305 is formed over the threshold switching selector 2309, at step 2507 the tunnel barrier 2303 is formed over the free layer 2305, and then at step 2509 the reference layer 2301 is formed over the tunnel barrier 2303.

[0156] At step 2511, the second set of conductive lines is formed over the layer 1 MRAM device 2302. The second layer of conductive lines includes bit line 2310 and corresponds to the bit lines of Fig. 7D. With the completion of step 2511, the layer 1 memory structure is complete. In a cross-point architecture, this second set of conductive lines extends across the substrate in a second direction that is perpendicular to the first layer of conductive lines (the lower set of word lines). Although in Fig. 23 (and in the preceding Fig. 11A and Fig. 11B) both the word lines and the bits are shown as running from left to right for illustrative purposes, when viewed within the larger structure, one of these elements (either the bit lines or the two layers of word lines) would be more accurately shown running into the page, as in the Fig. 7B-7D.

[0157] The second layer is formed starting at step 2513, which forms the layer 2 threshold switch selector 2319 over the second set of conductive lines (bit line 2310). In the processing sequence for the embodiment of Fig. 23, the layer 2 threshold switch selector is again formed beneath the MRAM device of the layer's memory cell, but as with layer 1, other embodiments could reverse this. The layer 2 MRAM device 2312 is then formed in step 2514. The substeps of step 2514 reverse the order compared to layer 1: step 2515 forms the reference layer 2315 over the threshold switch selector 2319, step 2517 forms the tunnel barrier 2313 over the reference layer 2315, and step 2519 forms the free layer 2311 over the tunnel barrier 2313. The upper layer of conductive lines, including word line 2 2320, is formed in step 2521, extending in the same direction over the underlying structure as the lower layer of conductive lines, which includes word line 1 2300. 2521 completes the two-layer structure of Fig.23 is completed. If further layers are to be formed, the process can be continued in the same way, alternating the processing module of layer 1 with that of module 2.

[0158] According to a first set of aspects, a device includes a non-volatile memory having a substrate and one or more memory arrays formed on the substrate. Each of the arrays includes: a first set of conductive lines running in a first direction parallel to a surface of the substrate; a second set of conductive lines formed over the first set of conductive lines and running in a second direction parallel to the surface of the substrate; a third set of conductive lines formed over the second set of conductive lines and running in the first direction; and first and second sets of memory cells.Each of the first plurality of memory cells is connected between a corresponding one of the first set of conductive lines and a corresponding one of the second set of conductive lines, wherein each of the first plurality of memory cells includes a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device, the MRAM device of each of the first plurality of memory cells including: a reference layer having a fixed magnetic field polarity; and a free layer connected in series with the reference layer and having a programmable magnetic field polarity, the free layer formed beneath the reference layer.The second plurality of memory cells are each connected between a corresponding one of the second set of conductive lines and a corresponding one of the third set of conductive lines, wherein each of the second plurality of memory cells includes a threshold switch selector connected in series with an MRAM device, the MRAM device of each of the plurality of memory cells including: a reference layer having a fixed magnetic field polarity; and a free layer connected in series with the reference layer and having a programmable magnetic field polarity, the free layer formed over the reference layer.

[0159] In additional aspects, a method includes detecting a data state of a selected one of a first plurality of memory cells by forcing a read current from a second conductive line to a corresponding first conductive line, wherein the selected one of the first plurality of memory cells is part of an array including the first plurality of memory cells and a second plurality of memory cells, each of the first and second plurality of memory cells having a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device. The method also includes detecting a data state of a selected one of the second plurality of memory cells,by forcing the read current from the corresponding second conductive line to a corresponding third conductive line. Furthermore, the method may include writing a selected one of the first plurality of memory cells from a first state to a second state by forcing a write current from the corresponding second conductive line to the corresponding first conductive line, and writing a selected one of the first plurality of memory cells from the second state to the first state by forcing the write current from the corresponding first conductive line to the corresponding second conductive line; and may also include writing a selected one of the second plurality of memory cells from a first state to a second state by forcing the write current from the corresponding second conductive line to the corresponding third conductive line,and writing a selected one of the second plurality of memory cells from the second state to the first state by forcing the write current from the corresponding third conductive line to the corresponding second conductive line.

[0160] In another set of aspects, a device includes a control circuit configured to connect to an array of memory cells, each having a threshold switch selector connected in series with a magnetoresistive random access memory (MRAM) device, the array including a first plurality of memory cells each connected between a corresponding one of a first set of conductive wires and a corresponding one of a second set of conductive wires, and a second plurality of memory cells each connected between a corresponding one of a third set of conductive wires and a corresponding one of the second set of conductive wires, the control circuit configured to: read the selected one of the first plurality of memory cells by biasing the corresponding one of the first set of conductive lines to a lowerVoltage than the corresponding one of the second set of conductive lines; Reading selected ones of the second plurality of memory cells by biasing the corresponding one of the third set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Writing selected ones of the first plurality of memory cells from a first state to a second state by biasing the corresponding one of the first set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Writing selected ones of the first plurality of memory cells from the second state to the first state by biasing the corresponding one of the first set of conductive lines to a higher voltage than the corresponding one of the second set of conductive lines; Writing a selected one of the second plurality of memory cells from the first state to the second state byBiasing the corresponding one of the third set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; and writing a selected one of the second plurality of memory cells from the second state to the first state by biasing the corresponding one of the third set of conductive lines to a higher voltage than the corresponding one of the second set of conductive lines.

[0161] For the purposes of this document, reference in the specification to "one embodiment," "some embodiments," or "another embodiment" may be used to describe different embodiments or the same embodiment.

[0162] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when one element is referred to as being connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element through intervening elements. When an element is referred to as being directly connected to another element, there are no intervening elements between the element and the other element. Two devices are "in communication" when they are connected, directly or indirectly, so that they can pass electronic signals between each other.

[0163] For the purposes of this document, the term “based on” can be read as “at least partly based on”.

[0164] For the purposes of this document, without additional context, the use of numeric expressions such as a "first" object, a "second" object, and a "third" object may not imply ordering of objects, but may instead be used for identification purposes to identify different objects.

[0165] For the purposes of this document, the term “set” of objects may refer to a “set” of one or more of the objects.

Claims

[1] Facility comprising: a non-volatile memory comprising: a substrate; one or more memory arrays (502, 602) formed on the substrate, each of the arrays including: a first set of conductive lines (WL1,1-WL1,4) extending in a first direction parallel to a surface of the substrate; a second set of conductive lines (BL1-BL5) formed over the first set of conductive lines and extending in a second direction parallel to the surface of the substrate; a third set of conductive lines (WL2,1-WL2,4) formed over the second set of conductive lines and extending in the first direction; a first plurality of memory cells (701) each connected between a corresponding one (2300) of the first set of conductive lines and a corresponding one (2310) of the second set of conductive lines, each of the first plurality of memory cells including a threshold switch selector (2309) connected in series with a magnetoresistive random access memory device (2302), wherein the magnetoresistive random access memory device includes each of the first plurality of memory cells: a reference layer (2301) having a fixed magnetic field polarity; and a free layer (2305) connected in series with the reference layer and having a programmable magnetic field polarity, the free layer being formed beneath the reference layer; and a second plurality of memory cells (701) each connected between a corresponding one (2310) of the second set of conductive lines and a corresponding one (2320) of the third set of conductive lines, wherein each of the second plurality of memory cells includes a threshold switch selector (2319) connected in series with a magnetoresistive random access memory device (2312), the magnetoresistive random access memory device of each of the plurality of memory cells including: a reference layer (2315) having a fixed magnetic field polarity; and a free layer (2311) connected in series with the reference layer and having a programmable magnetic field polarity, the free layer being formed over the reference layer; wherein the device further comprises one or more control circuits (610, 620) connected to the first, second and third sets of conductive lines, the one or more control circuits being arranged to: simultaneously reading a selected one of the first plurality of memory cells (701) connected to a first one of the second set of conductive lines and a selected one of the second plurality of memory cells (701) connected to the first one of the second set of conductive lines. [2] The device according to claim 1, wherein the non-volatile memory is formed on a memory chip, the device further comprising: a control chip (611) connected to the memory chip (601) and configured to write data to and read data from the one or more memory arrays (502, 602), the control chip being formed separately from and bonded to the memory chip. [3] Device according to claim 1, wherein the one or more control circuits are further configured to: Reading selected ones of the first plurality of memory cells by biasing the corresponding one of the first set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Reading selected ones of the second plurality of memory cells by biasing the corresponding one of the third set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Writing selected ones of the first plurality of memory cells from a first state to a second state by biasing the corresponding one of the first set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Writing selected ones of the first plurality of memory cells from the second state to the first state by biasing the corresponding one of the first set of conductive lines to a higher voltage than the corresponding one of the second set of conductive lines; Writing a selected one of the second plurality of memory cells from the first state to the second state by biasing the corresponding one of the third set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; and Writing a selected one of the second plurality of memory cells from the second state to the first state by biasing the corresponding one of the third set of conductive lines to a higher voltage than the corresponding one of the second set of conductive lines. [4] Device according to claim 3, wherein the first state is a high impedance state and the second state is a low impedance state. [5] The device of claim 3, wherein the one or more control circuits include: a first set of drivers each connected to a corresponding one of the first set of conductive lines; a second set of drivers each connected to a corresponding one of the second set of conductive lines; and a third set of drivers, each connected to a corresponding one of the third set of conductive lines, wherein, when reading a selected one of the first plurality of memory cells, a corresponding one of the first set of drivers connects the corresponding one (2300) first conductive line through an N-channel device (2341) to a low voltage level and a corresponding one of the second set of drivers connects the corresponding one (2310) second conductive line through a P-channel device (2343) to a high voltage level, and wherein, upon reading a selected one of the second plurality of memory cells, a corresponding one of the third set of drivers connects the corresponding one (2320) third conductive line to the low voltage level through an N-channel device (2347) and a corresponding one of the second set of drivers connects the corresponding one (2310) second conductive line to the high voltage level through a P-channel device (2343). [6] Device according to claim 5, wherein: when reading the selected one of the first plurality of memory cells, the corresponding one of the second set of drivers is arranged to drive a read current through the selected one of the first plurality of memory cells, and when reading the selected one of the second plurality of memory cells, the corresponding one of the second set of drivers is configured to drive the read current through the selected one of the second plurality of memory cells. [7] The device according to claim 3, wherein the second set of conductive lines (BL1-BL5) is longer than both the first set of conductive lines (WL1,1-WL1,4) and the third set of conductive lines (WL2,1-WL2,4). [8] The device according to claim 1, wherein in each of the first plurality of memory cells (701), the threshold switching selector (2309) is formed below the series-connected magnetoresistive random access memory device (2302), and in each of the second plurality of memory cells, the threshold switching selector (2310) is formed below the series-connected magnetoresistive random access memory device (2312). [9] Method comprising: Detecting a data state of a selected one of a first plurality of memory cells (701) by forcing a read current from a second conductive line (BL1-BL5) to a corresponding first conductive line (WL1,1-WL1,4), wherein the selected one of the first plurality of memory cells is part of an array (502, 602) including the first plurality of memory cells and a second plurality of memory cells, wherein each of the first and second plurality of memory cells comprises a threshold switch selector (1159, 11169) connected in series with a magnetoresistive random access memory device; detecting a data state of a selected one of the second plurality of memory cells (701) by forcing the read current from the corresponding second conductive line to a corresponding third conductive line (WL2,1-WL2,4); Writing (2405) a selected one of the first plurality of memory cells from a first state to a second state by forcing a write current from the corresponding second conductive line to the corresponding first conductive line; Writing (2413) a selected one of the first plurality of memory cells from the second state to the first state by forcing the write current from the corresponding first conductive line to the corresponding second conductive line; Writing (2407) a selected one of the second plurality of memory cells from a first state to a second state by forcing the write current from the corresponding second conductive line to the corresponding third conductive line; and Writing (2415) a selected one of the second plurality of memory cells from the second state to the first state by forcing the write current from the corresponding third conductive line to the corresponding second conductive line; wherein detecting the data state of the selected one of the first plurality of memory cells and detecting the data state of the selected one of the second plurality of memory cells are performed simultaneously. [10] A method according to claim 9, wherein: detecting (2401, 2403) the data state of the selected one of the first plurality of memory cells (701) by forcing the read current from the second conductive line to the corresponding first conductive line includes connecting the corresponding (2300) first conductive line to a low voltage level through an N-channel device (2341); and sensing (2403, 2411)) the data state of the selected one of the second plurality of memory cells (701) by forcing the read current from the corresponding second conductive line to the corresponding third conductive line includes connecting the corresponding (2320) third conductive line to the low voltage level through an N-channel device (2347). [11] Facility comprising: a control circuit configured to connect to an array (502, 602) of memory cells (701), each having a threshold switch selector (1159, 1169) connected in series with a magnetoresistive random access memory device, the array comprising a first plurality of memory cells each connected between a corresponding one of a first set of conductive lines (WL1,1-WL1,4) and a corresponding one of a second set of conductive lines (BL1-BL5), and a second plurality of memory cells each connected between a corresponding one of a third set of conductive lines (WL2,1-WL2,4) and a corresponding one of the second set of conductive lines, wherein the control circuit is arranged to: Reading selected ones of the first plurality of memory cells by biasing the corresponding one of the first set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Reading selected ones of the second plurality of memory cells by biasing the corresponding one of the third set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Writing selected ones of the first plurality of memory cells from a first state to a second state by biasing the corresponding one of the first set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; Writing selected ones of the first plurality of memory cells from the second state to the first state by biasing the corresponding one of the first set of conductive lines to a higher voltage than the corresponding one of the second set of conductive lines; Writing a selected one of the second plurality of memory cells from the first state to the second state by biasing the corresponding one of the third set of conductive lines to a lower voltage than the corresponding one of the second set of conductive lines; and Writing a selected one of the second plurality of memory cells from the second state to the first state by biasing the corresponding one of the third set of conductive lines to a higher voltage than the corresponding one of the second set of conductive lines; wherein the control circuit is further configured to simultaneously read a selected one of the first plurality of memory cells connected to a first one of the second set of conductive lines and a selected one of the second plurality of memory cells connected to the first one of the second set of conductive lines. [12] Device according to claim 11, wherein the control circuit comprises: a first set of drivers each configured to be connected to a corresponding one of the first set of conductive lines; a second set of drivers each configured to be connected to a corresponding one of the second set of conductive lines; and a third set of drivers, each arranged to be connected to a corresponding one of the third set of conductive lines, wherein, when reading a selected one of the first plurality of memory cells, a corresponding one of the first set of drivers connects the corresponding one (2300) first conductive line through an N-channel device (2341) to a low voltage level and a corresponding one of the second set of drivers connects the corresponding one (2310) second conductive line through a P-channel device (2343) to a high voltage level, and wherein, upon reading a selected one of the second plurality of memory cells, a corresponding one of the third set of drivers connects the corresponding one (2320) third conductive line to the low voltage level through an N-channel device (2347) and a corresponding one of the second set of drivers connects the corresponding one (2310) second conductive line to the high voltage level through a P-channel device (2343). [13] Device according to claim 12, wherein: when reading the selected one of the first plurality of memory cells, the corresponding one of the second set of drivers is arranged to drive a read current through the selected one of the first plurality of memory cells, and when reading the selected one of the second plurality of memory cells, the corresponding one of the second set of drivers is configured to drive the read current through the selected one of the second plurality of memory cells. [14] Device according to claim 11, wherein the control circuit is formed on a control chip (611), the device further comprising: a memory chip (601) enclosing the memory array (502, 602) of memory cells, the memory chip being formed separately from and bonded to the control chip (611). [15] The device of claim 11, further comprising the array (502, 602) of memory cells, the array of memory cells comprising: a substrate; the first set of conductive lines (WL1,1-WL1,4) extending in a first direction parallel to a surface of the substrate; the second set of conductive lines (BL1-BL5) formed over the first set of conductive lines and extending in a second direction parallel to the surface of the substrate; the third set of conductive lines (WL2,1-WL2,4) formed over the second set of conductive lines and extending in the first direction; the first plurality of memory cells each connected between a corresponding one of the first set of conductive lines and a corresponding one of the second set of conductive lines, wherein the magnetoresistive random access memory device (2302) of each of the first plurality of memory cells includes: a reference layer (2301) having a fixed magnetic field polarity; and a free layer (2305) connected in series with the reference layer and having a programmable magnetic field polarity, the free layer being formed beneath the reference layer; and the second plurality of memory cells each connected between a corresponding one of the second set of conductive lines and a corresponding one of the third set of conductive lines, wherein the magnetoresistive random access memory device (2312) of each of the plurality of memory cells includes: a reference layer (2315) having a fixed magnetic field polarity; and a free layer (2311) connected in series with the reference layer and having a programmable magnetic field polarity, the free layer being formed over the reference layer. [16] The device of claim 15, wherein the second set of conductive lines (BL1-BL5) is longer than both the first set of conductive lines (WL1,1-WL1,4) and the third set of conductive lines (WL2,1-WL2,4). [17] The device of claim 11, wherein the first state is a high impedance state and the second state is a low impedance state.

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