TRANSISTOR GATE STRUCTURES AND METHOD FOR FORMING THESE

Abstract

Building element, comprehensive: an isolation area (72); Nanostructures (64, 66) that protrude above an upper surface of the insulation area (72); a gate structure (130) surrounding the nanostructures (64, 66), wherein the gate structure (130) has a lower surface that contacts the insulation area (72), the lower surface of the gate structure (130) extending away from the nanostructures (64, 66) at a first distance (D1), and the gate structure (130) having a side wall that is arranged at a second distance (D2) from the nanostructures (64, 66), the first distance (D1) being smaller than the second distance (D2); and a mixing fin (82) on the side wall of the gate structure (130).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as PCs, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by successively depositing layers of insulating or dielectric material, layers of conductive material, and semiconductor layers onto a semiconductor substrate, and structuring the various layers using lithography to create circuit components and elements.

[0002] The semiconductor industry continuously improves the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, thus enabling more components to be integrated into a given area. However, reducing the minimum feature sizes introduces additional problems that need to be addressed.

[0003] Publication US 2020 / 0006154A1 describes separate GAA-FET devices with respective non-complementary stacks of nanowires arranged on respective mesa structures and wrapped by respective gate structures. Publications US 2020 / 0098878A1 and US 10510620B1 each describe separate GAA-FET devices with respective stacks of nanowires and respective gate structures. Publication US 2020 / 0243522A1 describes a fabrication method for GAA-FET devices with respective stacks of nanowires and respective gate structures. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of this disclosure are best understood by referring to the following detailed description, when read in conjunction with the accompanying figures. It should be noted that, in accordance with standard industry practice, several features are not drawn to scale. In fact, the dimensions of the various features may have been enlarged or reduced as desired for clarity of discussion. Fig. Figure 1 illustrates an example of nanostructured transistors / FETs according to some embodiments. The Fig. Figures 2-22C show views of intermediate stages in the fabrication of nanostructured transistors / FETs according to some embodiments. The Fig. 23A - 23C are views of nanostructured transistors / FETs according to different embodiments. The Fig. 24A - 24C are views of nanostructured transistors / FETs according to different embodiments. The Fig. 25A - 25C are views of nanostructured transistors / FETs according to different embodiments. The Fig. Figures 26A - 26C are detailed views of nanostructured transistors / FETs. The Fig. Figures 27A - 27D are views of intermediate stages in the fabrication of nanostructured transistors / FETs according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or exemplary embodiments for implementing various features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on top of a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and also embodiments in which additional features can be formed between the first and second features such that the first and second features may not be in direct contact. Furthermore, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself imply any relationship between the various designs and / or configurations discussed.

[0006] Furthermore, spatially relative terms such as "under," "below," "lower," "above," "upper," and the like can be used here to simplify the description and describe the relationship of one element or feature to another element(s) or feature(s), as illustrated in the figures. In addition to the orientation shown in the figures, these spatially relative terms are intended to encompass different orientations of the component in use or operation. The object may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptions used here can be interpreted accordingly.

[0007] In various embodiments, dummy gates with a small foot profile are formed around semiconductor fins and nanostructures surrounded by a mixing fin. The dummy gates are removed in a replacement gate process. Forming the dummy gates with a small foot profile can increase the process window for subsequent operations, such as a replacement gate process and / or an epitaxial growth process for the source / drain regions.

[0008] Embodiments are described in a specific context, where one die includes nanostructured transistors / FETs. However, different embodiments can be applied to dies that include other types of transistors / FETs (e.g., fin field-effect transistors (FinFETs), planar transistors, or the like) instead of, or in combination with, the nanostructured transistors / FETs.

[0009] Fig. Figure 1 illustrates an example of nanostructured transistors / FETs (e.g., nanowire FETs, nanosheet FETs, or the like) according to some embodiments. Fig. Figure 1 is a three-dimensional view in which some features of the nanostructured transistors / FETs have been omitted for clarity of illustration. The nanostructured transistors / FETs can be nanosheet field-effect transistors (NSFETs), nanowire field-effect transistors (NWFETs), gate-all-around field-effect transistors (GAAFETs), or the like.

[0010] The nanostructured transistors / FETs enclose nanostructures 66 (e.g., nanosheets, nanowires, or the like) via semiconductor fins 62 on a substrate 50 (e.g., a semiconductor substrate), the nanostructures 66 serving as channel regions for the nanostructured transistors / FETs. The nanostructures 66 can include p-nanostructures, n-nanostructures, or a combination thereof. Insulation regions 72, such as shallow trench isolation (STI) regions, are arranged between adjacent semiconductor fins 62 and may protrude above and between adjacent insulation regions 72. Although the insulation regions 72 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein may refer to the semiconductor substrate alone or to a combination of the semiconductor substrate and the insulation regions.Furthermore, although the bottom sections of the semiconductor fins 62 are illustrated as separate from the substrate 50, the bottom sections of the semiconductor fins 62 can consist of single continuous materials with the substrate 50. In this context, the semiconductor fins 62 refer to the section that extends above and between the adjacent insulating regions 72.

[0011] Gate structures 130 are located above the upper surfaces of the semiconductor fins 62 and along the upper surfaces, side walls, and lower surfaces of the nanostructures 66. The epitaxial source / drain regions 108 are arranged on the semiconductor fins 62 on opposite sides of the gate structures 130. The epitaxial source / drain regions 108 can be shared among the different semiconductor fins 62. For example, adjacent epitaxial source / drain regions 108 can be electrically connected, such as by coupling the epitaxial source / drain regions 108 to the same source / drain contact.

[0012] Mixing cysts 82 are arranged over the isolation areas 72 and between adjacent epitaxial source / drain areas 108. The mixing cysts 82 block epitaxial growth to prevent coalescence of some of the epitaxial source / drain areas 108 during epitaxial growth. For example, the mixing cysts 82 can be formed at cell margins to separate the epitaxial source / drain areas 108 from neighboring cells.

[0013] Fig. Figure 1 further illustrates reference cross-sections used in subsequent figures. Cross-section AA' runs along a longitudinal axis of a semiconductor fin 62 and in a direction, for example, of current flow between the epitaxial source / drain regions 108 of the nanostructured transistor / FET. Cross-section BB' runs along a longitudinal axis of a gate structure 130 and in a direction, for example, perpendicular to a direction of current flow between the epitaxial source / drain regions 108 of a nanostructured transistor / FET. Cross-section CC' is parallel to cross-section BB' and extends through the epitaxial source / drain regions 108 of the nanostructured transistors / FETs. For clarity, subsequent figures refer to these reference cross-sections.

[0014] The Fig. Figures 2-22C show views of intermediate stages in the fabrication of nanostructured transistors / FETs according to some embodiments. Fig. 2, Fig. 3 and Fig. Four are three-dimensional views. Fig. 5A, Fig. 6A, Fig. 10A, Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 21A and Fig. 22A are cross-sectional views taken along a similar cross-section to the reference cross-section AA' in Fig. 1 are illustrated. Fig. 5B, 6B, 7A - 9C, 10B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B and 22B are cross-sectional views that follow a cross-section similar to the reference cross-section BB' in Fig. 1 are illustrated. Fig. 10C, Fig. 11C, Fig. 12C, Fig. 13C, Fig. 14C, Fig. 15C, Fig. 16C, Fig. 17C, Fig. 18C, Fig. 19C, Fig. 20C, Fig. 21C and Fig. 22C are cross-sectional views taken along a similar cross-section to the reference cross-section CC' in Fig. 1 are illustrated.

[0015] In Fig. 2. A substrate 50 is provided to form nanostructured transistors / FETs. The substrate 50 can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p- or n-type impurity) or undoped. The substrate 50 can be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used.In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide and / or indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and / or gallium indium arsenide phosphide; combinations thereof or the like.

[0016] Substrate 50 features an n-region 50N and a p-region 50P. The n-region 50N can be used to form n-type devices such as NMOS transistors, e.g., n-nanostructured transistors / FETs, and the p-region 50P can be used to form p-type devices such as PMOS transistors, e.g., p-nanostructured transistors / FETs. The n-region 50N can be physically separated from the p-region 50P (not illustrated separately), and any number of device features (e.g., other active components, doped regions, insulated structures, etc.) can be placed between the n-region 50N and the p-region 50P. Although one n-region 50N and one p-region 50P are illustrated, any number of n-regions 50N and p-regions 50P can be provided.

[0017] The substrate 50 can be weakly doped with a p- or n-type foreign material. An implantation against punch-through-out (APT) process can be performed on an upper portion of the substrate 50 to form an APT region. During APT implantation, foreign materials can be implanted into the substrate 50. These foreign materials can have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-type region 50N and the p-type region 50P. The APT region can extend below the source / drain regions in the nanostructured transistors / FETs. The APT region can be used to reduce leakage from the source / drain regions into the substrate 50. In some embodiments, the doping concentration in the APT region can be in the range of 10 18 cm -3 up to 10 19 cm -3 lay.

[0018] A multilayer stack 52 is formed on top of the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed from a first semiconductor material, and the second semiconductor layers 56 are formed from a second semiconductor material. The semiconductor materials can each be selected from the candidates of the semiconductor materials of the substrate 50. In the illustrated embodiment, the multilayer stack 52 includes three layers of each of the first semiconductor layers 54 and the second semiconductor layers 56. It is understood that the multilayer stack 52 can include any number of first semiconductor layers 54 and second semiconductor layers 56. For example, the multilayer stack 52 can include one to ten layers of each of the first semiconductor layers 54 and the second semiconductor layers 56.

[0019] In the illustrated embodiment, and as described in greater detail below, the first semiconductor layers 54 are removed and the second semiconductor layers 56 are structured to form channel regions for the nanostructured transistors / FETs in the n-region 50N and the p-region 50P. The first semiconductor layers 54 are sacrificial (or dummy) layers that are removed in a subsequent processing step to expose the top and bottom faces of the second semiconductor layers 56. The first semiconductor material of the first semiconductor layers 54 is a material with high etch selectivity for the second semiconductor layers 56, such as silicon-germanium. The second semiconductor material of the second semiconductor layers 56 is a material suitable for both n- and p-type devices, such as silicon.

[0020] In another embodiment (not shown separately), the first semiconductor layers 54 are structured to form channel regions for nanostructured transistors / FETs in one region (e.g., the p-region 50P), and the second semiconductor layers 56 are structured to form channel regions for nanostructured transistors / FETs in another region (e.g., the n-region 50N). The first semiconductor material of the first semiconductor layers 54 can be a material suitable for p-type devices, such as silicon-germanium (e.g., Si3). x Ge 1-x, where x can be in the range of 0 to 1), pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The second semiconductor material of the second semiconductor layers 56 can be a material suitable for n devices, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. The first semiconductor material and the second semiconductor material can exhibit high etch selectivity with respect to each other, such that the first semiconductor layers 54 can be removed without removing the second semiconductor layers 56 in the n region 50N, and the second semiconductor layers 56 can be removed without removing the first semiconductor layers 54 in the p region 50P.

[0021] Each layer of the multilayer stack 52 can be grown by a process such as vapor deposition (VDE) or molecular beam epitaxy (MBE) and deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Each layer can have a small thickness, such as a thickness in the range of 5 nm to 30 nm. In some embodiments, some layers (e.g., the second semiconductor layers 56) are formed thinner than other layers (e.g., the first semiconductor layers 54).For example, in embodiments where the first semiconductor layers 54 are sacrificial (or dummy) layers and the second semiconductor layers 56 are structured to form channel regions for the nanostructured transistors / FETs in both the n-region 50N and the p-region 50P, the first semiconductor layers 54 can have a first thickness and the second semiconductor layers 56 can have a second thickness that is 30% to 60% less than the first thickness. Forming the second semiconductor layers 56 with a smaller thickness allows for the formation of channel regions with a higher density.

[0022] In Fig. 3. Trenches are structured in the substrate 50 and the multilayer stack 52 to form semiconductor fins 62, nanostructures 64, and nanostructures 66. The semiconductor fins 62 are structured semiconductor strips in the substrate 50. The nanostructures 64 and 66 each comprise the remaining portions of the first semiconductor layers 54 and the second semiconductor layers 56, respectively. The trenches can be structured by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), or a combination thereof. The etching can be anisotropic.

[0023] The semiconductor fins 62 and the nanostructures 64, 66 can be structured by any suitable method. For example, the semiconductor fins 62 and the nanostructures 64, 66 can be structured using one or more photolithography processes, including dual or multiple structuring processes. In general, dual or multiple structuring processes combine photolithography and self-aligning processes, which enables the fabrication of structures with smaller dimensions than, for example, achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacers are formed adjacent to the structured sacrificial layer using a self-aligning process.The sacrificial layer is then removed, and the remaining spacers can then be used as a mask 58 for structuring the semiconductor fins 62 and the nanostructures 64, 66. In some embodiments, the mask 58 (or another layer) can remain on the nanostructures 64, 66.

[0024] The semiconductor fins 62 and the nanostructures 64, 66 can each have widths in a range from 8 nm to 40 nm. In the illustrated embodiment, the semiconductor fins 62 and the nanostructures 64, 66 have essentially the same widths in the n-region 50N and the p-region 50P. In another embodiment, the semiconductor fins 62 and the nanostructures 64, 66 are wider or narrower in one region (e.g., the n-region 50N) than in another region (e.g., the p-region 50P).

[0025] In Fig. 4. STI regions 72 are formed above the substrate 50 and between adjacent semiconductor fins 62. The STI regions 72 are arranged around at least one section of the semiconductor fins 62 such that at least one section of the nanostructures 64, 66 protrudes between adjacent STI regions 72. In the illustrated embodiment, the upper surfaces of the STI regions 72 are located below the upper surfaces of the semiconductor fins 62. In some embodiments, the upper surfaces of the STI regions 72 are located above the upper surfaces of the semiconductor fins 62 or are coplanar (within process variations) with the upper surface of the semiconductor fins.

[0026] The STI regions 72 can be formed by any suitable method. For example, an insulating material can be formed over the substrate 50 and the nanostructures 64, 66, as well as between adjacent semiconductor fins 62. The insulating material can be an oxide, such as silicon oxide, a nitride, such as silicon nitride, the like, or a combination thereof, which can be formed by a chemical vapor deposition (CVD) process, such as high-density plasma (HDP)-CVD, flowable chemical vapor deposition (FCVD), the like, or a combination thereof. Other insulating materials formed by any acceptable process can be used. In some embodiments, the insulating material is silicon oxide formed by FCVD. Once the insulating material is formed, an annealing process can be performed.In one embodiment, the insulating material is formed such that the excess insulating material covers the nanostructures 64, 66. Although the STI regions 72 are each illustrated as a single layer, in some embodiments multiple layers can be used. For example, in some embodiments, a lining (not shown separately) can first be formed along surfaces of the substrate 50, the semiconductor fins 62, and the nanostructures 64, 66. Then, an insulating material, such as those described above, can be formed over the lining. A removal process is then applied to the insulating material to remove excess insulating material over the nanostructures 64, 66. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, can be used.In embodiments where a mask 58 remains on the nanostructures 64, 66, the planarization process can either expose or remove the mask 58. After the planarization process, the upper surfaces of the insulating material and the mask 58 (if present) or the nanostructures 64, 66 are coplanar (within process variations). Accordingly, the upper surfaces of the mask 58 (if present) or the nanostructures 64, 66 are exposed through the insulating material. In the illustrated embodiment, the mask 58 remains on the nanostructures 64, 66. The insulating material is then recessed to form the STI regions 72. The insulating material is recessed such that at least one section of the nanostructures 64, 66 protrudes between adjacent sections of the insulating material.Furthermore, the upper surfaces of the STI regions 72 can have a flat surface as illustrated, a convex surface, a concave surface (as by trough formation), or a combination thereof. In the illustrated embodiment, the upper surfaces of the STI regions 72 are concave surfaces, such that sections of the STI regions 72 extend upwards to the sidewalls of the semiconductor fins 62. The upper surfaces of the STI regions 72 can be formed flat, convex, and / or concave by appropriate etching. The insulating material can be indented using any acceptable etching process, such as one that is selective with respect to the insulating material (e.g., one that selectively etches the insulating material of the STI regions 72 at a faster rate than the materials of the semiconductor fins 62 and the nanostructures 64, 66).For example, oxide removal can be carried out using dilute hydrofluoric acid (dHF).

[0027] The process described above is only one example of how the semiconductor fins 62 and the nanostructures 64, 66 can be formed. In some embodiments, the semiconductor fins 62 and / or the nanostructures 64, 66 can be formed using a mask and an epitaxial growth process. For example, a dielectric layer can be formed over a top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures can be grown epitaxially in the trenches, and the dielectric layer can be deepened such that the epitaxial structures protrude from the dielectric layer to form the semiconductor fins 62 and / or the nanostructures 64, 66.The epitaxial structures can include the previously described alternating semiconductor materials, such as the first semiconductor material and the second semiconductor material. In some embodiments where epitaxial structures are grown epitaxially, the epitaxially grown materials can be doped in situ during growth, thereby avoiding prior and / or subsequent implantations; however, in-situ and implantation doping can also be used together.

[0028] Furthermore, suitable wells (not illustrated separately) can be formed in the nanostructures 64, 66, the semiconductor fins 62, and / or the substrate 50. The wells can have a conductivity type opposite to that of the source / drain regions subsequently formed in each of the n-region 50N and the p-region 50P. In some embodiments, a p-well is formed in the n-region 50N and an n-well is formed in the p-region 50P. In some embodiments, either a p-well or an n-well is formed in both the n-region 50N and the p-region 50P.

[0029] In embodiments with different well types, different implantation steps for the n-region 50N and the p-region 50P can be implemented using a mask (not shown separately), such as a photoresist. For example, a photoresist can be formed over the semiconductor fins 62, the nanostructures 64, 66, and the STI regions 72 in the n-region 50N. The photoresist is patterned to expose the p-region 50P. The photoresist can be formed using a spin-deposition technique and patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-foreign material implantation is performed in the p-region 50P, and the photoresist can serve as a mask that essentially prevents n-foreign materials from being implanted into the n-region 50N. The n-excess substances can be phosphorus, arsenic, antimony, or the like, occurring in the range with a concentration in the range of 1013 cm -3 up to 10 14 cm -3 are implanted. After implantation, the photoresist can be removed by any acceptable ashing process.

[0030] Before or after the implantation of the p-region 50P, a mask (not shown separately), such as a photoresist, is formed over the semiconductor fins 62, the nanostructures 64 and 66, and the STI regions 72 in the p-region 50P. The photoresist is patterned to expose the n-region 50N. The photoresist can be formed using a spin-coating technique and patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-foreign material implantation can be performed in the n-region 50N, and the photoresist can serve as a mask that essentially prevents p-foreign materials from being implanted into the p-region 50P. The p-foreign materials can be boron, boron fluoride, indium, or the like, present in the region at a concentration in the range of 10 13 cm -3 up to 10 14 cm -3are implanted. After implantation, the photoresist can be removed by any acceptable ashing process.

[0031] Following the implantation of the n-region 50N and the p-region 50P, an annealing step can be performed to repair implantation damage and activate the implanted p- and / or n-type foreign materials. In some embodiments where epitaxial structures are grown for the semiconductor fins 62 and / or the nanostructures 64, 66, the grown materials can be doped in situ during growth, thus avoiding the need for implantation, although in-situ and implantation doping can be used together.

[0032] The Fig. Sections 5A-22C illustrate various additional steps in the manufacture of components according to embodiments. Fig. Figures 5A-22C illustrate features in either the n-region 50N or the p-region 50P. For example, the illustrated structures can be applied to both the n-region 50N and the p-region 50P. Differences between the structures of the n-region 50N and those of the p-region 50P are described (where applicable) in the text accompanying each figure. As described in greater detail below, mixed fins 82 are formed between the semiconductor fins 62. Fig. Figures 5A - 22C illustrate two semiconductor fins 62 as well as sections of the mixed fins 82 and the STI areas 72, which are arranged between the two semiconductor fins 62, in their respective cross-sections.

[0033] In the Fig. 5A - 5B, a dummy gate layer 74 is conformally formed over the mask 58 (if present), the semiconductor fins 62, the nanostructures 64, 66, and the STI regions 72. The dummy gate layer 74 can be formed from a semiconductor material (such as one selected from the candidate semiconductor materials of the substrate 50), which can be grown by a process such as vapor deposition (VDE) or molecular beam epitaxy (MBE) and deposited by a process such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. The dummy gate layer 74 can, for example, be formed from silicon or silicon-germanium. The dummy gate layer 74 can be formed over the STI regions 72 with a thickness T1 in the range of 1 nm to 100 nm. The thickness of the dummy gate layer 74 determines the dimensions of the substitute gate structures for the nanostructure transistors / FETs.

[0034] In the Fig. In steps 6A-6B, the dummy gate layer 74 is patterned to form dummy gates 76 around the mask 58 (if present), the semiconductor fins 62, and the nanostructures 64, 66. The dummy gates 76 are positioned over the STI regions 72. The dummy gate layer 74 has sections that, when patterned, remain on the sidewalls of the mask 58 (if present), the semiconductor fins 62, and the nanostructures 64, 66 (thus forming the dummy gates 76). The dummy gates 76 cover the sidewalls of the nanostructures 64, 66, which are exposed in subsequent processing to form channel regions. The dummy gates 76 are used as temporary spacers during processing and are subsequently removed to expose sidewalls of the sections of the nanostructures 66 that will serve as channel areas for the nanostructure transistors / FETs.In the illustrated embodiment, the dummy gates 76 and the nanostructures 64 are subsequently removed and replaced by gate structures surrounding the nanostructures 66. The dummy gates 76 are formed from a material exhibiting high etch selectivity with respect to the etching of the nanostructure material 66. The dummy gates 76 can be formed from the same semiconductor material as the nanostructures 64 or from a different material.

[0035] As described in greater detail below, the dummy gates 76 are formed such that they have a small foot profile. The foot profile of the dummy gates 76 refers to the shape and dimensions of the sections of the dummy gates 76 that extend along the upper surfaces of the STI areas 72. Forming the dummy gates 76 with a small foot profile means that the sections of the dummy gates 76 on the upper surfaces of the STI areas 72 do not open outwards along the concave surfaces of the STI areas 72. The lower surfaces of the dummy gates 76 extend away from the nanostructures 64, 66 at a first distance D1, and the outer side walls of the dummy gates 76 are arranged at a second distance D2 from the nanostructures 64, 66, wherein the first distance D1 is less than or equal to (e.g. not greater than) the second distance D2.The first distance D1 is measured below the upper surface of the semiconductor fins 62, and the second distance D2 is measured between the upper surface of the semiconductor fins 62 and the lower surface of the lower nanostructure 66. The first distance D1 and the second distance D2 are subsequently described in greater detail. Forming the dummy gates 76 with a small foot profile can increase the process window for subsequent operations, such as a replacement gate process and / or an epitaxial growth process for the source / drain regions.

[0036] The Fig. Figures 7A-9C show intermediate stages in the structuring of dummy gates 76 with a small foot profile according to some embodiments. The dummy gates 76 with a small foot profile are formed by structuring the dummy gate layer 74 using multiple etching processes. In particular, a first etching process is carried out to initially structure the dummy gate layer 74 as dummy gates 76 (see Figure 7A-9C). Fig. 7A - 7B). The protective layers 80 are formed along the upper sections 76U of the dummy gates 76 (see Fig. 7A - 7B), and the lower sections 76L of the dummy gates 76 remain exposed through the protective layers 80. A second etching process is then carried out to trim the lower sections 76L of the dummy gates 76, while the upper sections 76U of the dummy gates 76 are covered by the protective layers 80 (see Fig. 8A - 8C). Trimming the lower sections 76L of the dummy gates 76 reduces the foot profile of the dummy gates 76 by decreasing the widths of the lower sections 76L of the dummy gates 76. The protective layers 80 can be removed optionally (see Fig. 9A - 9C).

[0037] In the Fig. 7A - 7B a first etching process is carried out to create the dummy gate layer 74 (see Fig. 5A - 5B) are initially structured as dummy gates 76. The first etching process can be dry etching, wet etching, the like, or a combination thereof. The first etching process can be anisotropic. The sections of the dummy gate layer 74 above the mask 58 (if present) or the nanostructures 64, 66 are removed by the first etching process.

[0038] The areal density of the nanostructures 64, 66 determines the result of the first etching process, for example by influencing a load during the first etching process. The dummy gates 76 along the nanostructures 64, 66 in the sparse regions can be structured such that the STI regions 72 between the nanostructures 64, 66, as in Fig. Figure 7A illustrates that the dummy gates 76 along the nanostructures 64, 66 in the dense regions can be structured such that the STI regions 72 between the nanostructures 64, 66, as shown in Figure 7A, are exposed. Fig. Figure 7B illustrates that the nanostructures 64 and 66 are covered. In some embodiments, the critical size (CD) between the nanostructures 64 and 66 lies in a range from 2 nm to 2000 nm, where a sparse region refers to an area where the CD is near the lower limit of the region, and a dense region refers to an area where the CD is near the upper limit of the region. The same substrate 50 can have sparse and dense regions, so the first etching process covers the structures of the Fig. 7A and Fig. 7B forms 50 on the same substrate.

[0039] The first etching process forms the dummy gates 76 with a large foot profile. Forming the dummy gates 76 with a large foot profile refers to forming the dummy gates 76 such that the sections of the dummy gates 76 on the upper surfaces of the STI areas 72 open outwards along the concave surfaces of the STI areas 72. In other words, the side walls of the dummy gates 76 are spaced apart with a gap that increases in a direction extending from the top of the dummy gates 76 to the bottom of the dummy gates 76. Referring to Fig. 7A is when the dummy gates 76 are structured such that the STI regions 72 between the nanostructures 64, 66 are exposed, and the first distance D1 is greater than the second distance D2. In this embodiment, the sections of the dummy gate layer 74 above the STI regions 72 are removed. Referring to Fig. In embodiment 7B, the dummy gates 76 extend over the concave surfaces of the STI regions 72 when the dummy gates 76 are structured such that the STI regions 72 between the nanostructures 64, 66 are covered. In this embodiment, the sections of the dummy gate layer 74 over the STI regions 72 are made thinner. Consequently, after the first etching process, the thickness T1 of the dummy gates 76 over the STI regions 72 is reduced. After the first etching process, the dummy gate layer 74 can have a thickness T2 in the range of 0.3 nm to 20 nm over the STI regions 72, where thickness T2 is less than thickness T1.

[0040] Furthermore, protective layers 80 are formed along the upper sections 76U of the dummy gates 76 and over the mask 58 (if present) or the nanostructures 64, 66. In this embodiment, the protective layers 80 are not formed along the lower sections 76L of the dummy gates 76, so that the lower sections 76L of the dummy gates 76 are exposed and can subsequently be trimmed. The protective layers 80 are also not formed along the sections of the dummy gates 76 that cover the upper surfaces of the STI areas 72 (see Fig. 7B), so that these sections of the dummy gates 76 are exposed and can subsequently be removed during trimming. In this context, the upper sections 76U of the dummy gates 76 refer to the sections with straight side walls and a rounded upper surface, spaced at a constant distance from one another, and the lower sections 76L of the dummy gates 76 refer to the sections that open outwards along the STI regions 72. In some embodiments, the lower section 76L of each dummy gate 76 is located below the lower surface 64B of the nanostructure(s) 64 / 66 that is adjacent to the dummy gate 76 and is / are located closest to (and above) the STI regions 72. In some embodiments, the upper section 76U of each dummy gate 76 is arranged above the lower surface 64B of the nanostructure(s) 64 / 66.

[0041] In this embodiment, the protective layers 80 are by-product layers 80B, which are generated by the first etching process used to structure the dummy gate layer 74. The by-product layers 80B are formed by enclosing a passivating gas with the etchants used during the first etching process. The passivating gas controls the selectivity of the first etching process and promotes the generation of etching by-products, leaving the by-product layers 80B behind after the first etching process. The by-product layers 80B can have a thickness ranging from 2 Å to 150 Å. The by-product layers 80B can have a top thickness greater than a bottom thickness along the sidewall of the dummy gates 76, giving the by-product layers 80B an inverted trapezoidal outline.Forming the by-product layers 80B with such thickness and shape protects the upper sections 76U of the dummy gates 76 if the lower sections 76L of the dummy gates 76 are subsequently trimmed. Forming the by-product layers 80B with such thickness or shape may not protect the upper sections 76U of the dummy gates 76 if the lower sections 76L of the dummy gates 76 are subsequently trimmed.

[0042] In some embodiments, the first etching process is a dry etching performed with a gas source that includes a primary etching gas and a passivation gas. The primary etching gas can be Cl₂, HBr, CF₄, CHF₃, CH₂F₂, CH₃F, C₄F₆, BCl₃, SF₆, H₂, or the like. The passivation gas can be N₂, O₂, CO₂, SO₂, CO, CH₄, SiCl₄, or the like. In some embodiments, the gas source also includes a diluent gas, such as Ar, He, Ne, or the like. A plasma is generated during the first etching process. In some embodiments, the first etching process is implemented cyclically. For example, the first etching process can include a cyclical operation between the distribution of the primary etching gas and the distribution of the passivation gas. The etching cycle can be repeated up to 50 times.In some embodiments, the process conditions of the first etching process include: a pressure in the range of 1 mTorr to 800 mTorr; a plasma source power (configured to control the ion-to-radical ratio) in the range of 10 W to 3000 W; a plasma bias power (configured to control the etching direction (e.g., isotropic or anisotropic etching)) in the range of 0 W to 3000 W; and a gas source flow rate in the range of 1 sccm to 5000 sccm. Performing the first etching process with parameters in these ranges enables the formation of the by-product layers 80B with a desired thickness and shape (described above).

[0043] The composition of the by-product layers 80B depends on the passivation gas used in the first etching process. Continuing with the example where the dummy gate layer 74 is formed from silicon or silicon germanium, the by-product layers 80B can be SiO or SiGeO by-products formed when an oxygen-based passivation gas (e.g., O2, CO2, SO2, CO, or the like) is used; the by-product layers 80B can be SiN or SiGeN by-products formed when a nitrogen-based passivation gas (e.g., N2 or the like) is used; and the by-product layers 80B can be SiS or SiGeS by-products formed when a sulfur-based passivation gas (e.g., SO2 or the like) is used. In some embodiments, a variety of passivation gases can be used in the first etching process.For example, a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas, a sulfur-based passivation gas (e.g. SO2 and N2) can be used in the first etching process, and the by-product layers 80B can be SiGeS. x O y N z -By-products.

[0044] In the Fig. In processes 8A to 8C, a second etching process is performed to trim the lower sections 76L of the dummy gates 76, while the upper sections 76U of the dummy gates 76 are covered by the protective layers 80. The second etching process can be a wet cleaning process and reduces the foot profile of the dummy gates 76 by decreasing the widths of the lower sections 76L. Specifically, the second etching process etches the lower sections 76L of the dummy gates 76 laterally until the dummy gates 76 have a small foot profile. The second etching process can have a higher lateral etch rate than the first etching process and a lower vertical etch rate than the first etching process, thus enabling the second etching process to function as a trimming process. In embodiments in which the dummy gates 76 cover the STI regions 72 between the nanostructures 64, 66 (see Fig. 7B), the second etching process also exposes the upper surfaces of the STI areas 72. The protective layers 80 act as etch-stop layers during the second etching process to protect the upper sections 76U of the dummy gates 76, preventing them from being trimmed during the second etching process. In other words, the lower sections 76L of the dummy gates 76 are etched during the second etching process, and the upper sections 76U of the dummy gates 76 are not etched during the second etching process (or at least less etched than the lower sections 76L of the dummy gates 76). In some embodiments, after the second etching process, the first gap D1 is equal to the second gap D2, as shown by Fig. Figure 8A illustrates this. In some embodiments, after the second etching process, the first distance D1 is smaller than the second distance D2, as shown by the Fig. 8B and Fig. 8C is illustrated.

[0045] In some embodiments, the second etching process is a wet etching carried out with a primary etching chemical and an auxiliary etching chemical in a solvent. The primary etching chemical may be HF, F2, or the like. The auxiliary etching chemical may be O3, H2SO4, HCl, HBr, or the like. The solvent may be deionized (DI) water, alcohol, acetone, or the like.

[0046] The structure of Fig. 8A can be achieved by performing the second etching process on the structure of Fig. 7A can be obtained, for example, by structuring the dummy gates 76 such that the STI regions 72 between the nanostructures 64, 66 are exposed, and then by trimming the lower sections 76L of the dummy gates 76. For example, the second etching process (e.g., by adjusting the plasma bias power) can be controlled to etch in a lateral direction that is substantially parallel to the main surface of the substrate 50. In this embodiment, the side walls of the lower sections 76L of the dummy gates 76 are spaced apart at a distance that is constant in a direction extending from the top of the dummy gates 76 to the bottom of the dummy gates 76. Thus, the side walls of the lower sections 76L of the dummy gates 76 are substantially perpendicular to the main surface of the substrate 50.

[0047] The structure of Fig. 8B can be modified by performing the second etching process on the structure of Fig. 7A can be obtained, for example, by structuring the dummy gates 76 so that the STI regions 72 between the nanostructures 64, 66 are exposed, and then by trimming the lower sections 76L of the dummy gates 76. For example, the second etching process (e.g., by adjusting the plasma bias power) can be controlled to etch in a lateral direction that is essentially parallel to the main surface of the substrate 50. The dummy gates 76 in the embodiment of Fig. 8B can be etched more deeply than in the embodiment of Fig. 8A, so that they are open inwards along the STI areas 72. In this embodiment, the side walls of the lower sections 76L of the dummy gates 76 are spaced apart by a distance that decreases linearly in a direction extending from the top of the dummy gates 76 to the bottom of the dummy gates 76. The side walls of the lower sections 76L of the dummy gates 76 therefore form acute angles with a plane parallel to the main surface of the substrate 50.

[0048] The structure of Fig. 8C can be obtained by performing the second etching process on the structure of Fig. 7B can be obtained, for example, by structuring the dummy gates 76 such that the STI regions 72 between the nanostructures 64, 66 are covered, and then by trimming the lower sections 76L of the dummy gates 76 so that the STI regions 72 are exposed. For example, the second etching process (e.g., by adjusting the plasma bias power) can be controlled to etch in a diagonal direction forming an acute angle with a plane parallel to the main surface of the substrate 50. In this embodiment, the sidewalls of the lower sections 76L of the dummy gates 76 are spaced apart by a distance that decreases non-linearly in a direction extending from the top of the dummy gates 76 to the bottom of the dummy gates 76, and then also increases non-linearly in this direction. If the dummy gates have 76 sections that cover the STI areas 72 (see Fig. 7B), etching these sections can reduce the lateral etching of the second etching process. The sidewalls of the lower sections 76L of the dummy gates 76 can therefore enclose sidewall recesses 76R. The undersides of the sidewall recesses 76R are arranged at a third distance D3 from the nanostructures 64, 66, where the third distance D3 is smaller than the second distance D2 and the first distance D1. The third distance D3 is measured between the points where the second distance D2 and the first distance D1 are measured.

[0049] In the Fig. In 9A - 9C, the protective layers 80 are optionally removed. In some embodiments, the protective layers 80 are removed by wet cleaning, which is carried out after trimming the lower sections 76L of the dummy gates 76. In some embodiments, the protective layers 80 are removed by the second etching process for trimming the lower sections 76L of the dummy gates 76. In other embodiments (which are described subsequently), the protective layers 80 are not removed but remain in the finished components.

[0050] The Fig. Figures 10A - 22C show the embodiment of Fig. 9A. Furthermore, in the illustrated embodiment, the protective layers 80 are removed. It is understood that a similar process using the embodiments of the Fig. 8A - 8C or 9B - 9C can be carried out.

[0051] In the Fig. 10A - 10C is a conformal mixed fin layer 78 formed over the mask 58 (if present), the semiconductor fins 62, the nanostructures 64, 66, and the dummy gates 76. The mixed fin layer 78 is formed from one or more dielectric materials exhibiting high etch selectivity for etching the semiconductor fins 62, the nanostructures 64, 66, and the dummy gates 76. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, silicon carbonitride, a metal-based dielectric material, combinations thereof, or the like, which may be formed by a conformal deposition process such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), flowable chemical vapor deposition (FCVD), or the like.Other insulating materials formed by any acceptable process may be used. In some embodiments, the mixed fin layer 78 is formed from a dielectric material with a low k-value (e.g., a dielectric material with a k-value of less than about 3.5), such as fluorosilicate glass (FSG). The mixed fin layer 78 fills the remaining area between the semiconductor fins 62 and the nanostructures 64, 66 that is not filled with the dummy gates 76 and may be formed over the top surfaces of the mask 58 (if present) or the nanostructures 64, 66. In some embodiments, the mixed fin layer 78 includes several sublayers, e.g., a lining layer 78A and a filler layer 78B, which may be formed from different materials.

[0052] In the Fig. In 11A-11C, a removal process is performed to remove the excess sections of material(s) from the mixed fin layer 78, wherein the excess sections are located above the top surfaces of the mask 58 (if present) or the nanostructures 64, 66, thereby forming the mixed fins 82. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The mixed fin layer 78 has sections which, when planarized, remain in the region between the semiconductor fins 62 and the nanostructures 64, 66 (thus forming the mixed fins 82). After the planarization process, the top surfaces of the mixed fins 82, the dummy gates 76, and the mask 58 (if present) or the nanostructures 64, 66 are coplanar (within process variations).

[0053] In embodiments where a mask 58 remains on the nanostructures 64, 66, the removal process can either expose or remove the mask 58. Furthermore, in some embodiments, the mask 58 is removed by a separate process performed after the removal process. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, can be used to remove the mask 58. The etching can be anisotropic. In some embodiments where the mask 58 is removed, the removal process can also (or not) deepen the dummy gates 76.

[0054] In the Fig. 12A - 12C is a dummy gate layer 84 formed on the mixing fins 82, the dummy gates 76 and the mask 58 (if present) or the nanostructures 64, 66. The dummy gate layer 84 can be deposited and then planarized, for example by a CMP. The dummy gate layer 84 can be formed from a conductive or non-conductive material, such as amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), a metal, a metal nitride, a metal silicide, a metal oxide, or the like, which can be deposited by physical vapor deposition (PVD), CVD, or the like.The dummy gate layer 84 can also be formed from a semiconductor material (such as a selected one from the candidate semiconductor materials of the substrate 50), which can be deposited by a process such as vapor deposition (VDE) or molecular beam epitaxy (MBE), deposition by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), or the like. The dummy gate layer 84 can be formed from a material that exhibits high etch selectivity with respect to insulating materials, e.g., the mixed fins 82. A mask layer 86 can be deposited over the dummy gate layer 84. The mask layer 86 can be formed from a dielectric material, such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 84 and a single mask layer 86 are formed across the n-region 50N and the p-region 50P.

[0055] In the Fig. In steps 13A-13C, the mask layer 86 is patterned using acceptable photolithography and etching techniques to form masks 96. The patterning of the masks 96 is then transferred to the dummy gate layer 84 by any acceptable etching technique to form dummy gates 94. The dummy gates 94 cover the top surface of the nanostructures 64, 66, which are exposed in subsequent processing to form channel regions. The patterning of the masks 96 can be used to physically separate adjacent dummy gates 94. The dummy gates 94 can also have longitudinal directions that are substantially perpendicular (within process variations) to the longitudinal directions of the semiconductor fins 62. After patterning, the masks 96 can optionally be removed by any acceptable etching technique.

[0056] The dummy gates 76 and 94 extend together along the sections of the nanostructures 66 that are to be structured to form the channel regions 68. The subsequently formed gate structures will replace the dummy gates 76 and 94. Forming the dummy gates 94 over the dummy gates 76 allows the subsequently formed gate structures to have a greater height.

[0057] As noted above, the dummy gates 94 can be formed from a semiconductor material. In such embodiments, the nanostructures 64, the dummy gates 76, and the dummy gates 94 are each formed from semiconductor materials. In some embodiments, the nanostructures 64 and the dummy gates 76 are formed from a first semiconductor material (e.g., silicon germanium), and the dummy gates 94 are formed from a second semiconductor material (e.g., silicon), so that during the replacement gate process, the dummy gates 94 can be removed in a first etching step, and the nanostructures 64 and the dummy gates 76 can be removed together in a second etching step.If the nanostructures 64 and the dummy gates 76 are formed from silicon-germanium, the nanostructures 64 and the dummy gates 76 can have similar germanium concentrations, the nanostructures 64 can have a higher germanium concentration than the dummy gates 76, or the dummy gates 76 can have a higher germanium concentration than the nanostructures 64. In some embodiments, the nanostructures 64 are formed from a first semiconductor material (e.g., silicon-germanium), and the dummy gates 76 and the dummy gates 94 are formed from a second semiconductor material (e.g., silicon), so that during a replacement gate process, the dummy gates 76 and the dummy gates 94 can be removed together in a first etching step, and the nanostructures 64 can be removed in a second etching step.

[0058] Furthermore, gate spacers 98 are formed above the mask 58 (if present) or the nanostructures 64, 66, and on exposed sidewalls of the masks 96 (if present) and the dummy gates 94. The gate spacers 98 can be formed by conformal deposition of one or more dielectric materials and subsequent etching of the dielectric material(s). Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, or the like, which can be formed by a conformal deposition process such as chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), or the like. Other insulating materials formed by any acceptable process may be used.Any acceptable etching process, such as dry etching, wet etching, the like, or a combination thereof, can be performed to pattern the dielectric material(s). The etching can be anisotropic. When etched, the dielectric material(s) will have sections that remain on the sidewalls of the dummy gates 94 (forming the gate spacers 98). After etching, the gate spacers 98 can have straight sidewalls (as illustrated) or curved sidewalls (not illustrated separately).

[0059] Furthermore, implantations can be performed to form lightly doped source / drain regions (LDD regions) (not illustrated separately). In embodiments with different device types, a mask (not illustrated separately), such as a photoresist, can be formed over the n-region 50N while exposing the p-region 50P, similar to the implantations for the previously described wells, and foreign materials of a suitable type (e.g., p-type) can be implanted into the semiconductor fins 62 and / or the nanostructures 64, 66 exposed in the p-region 50P. The mask can then be removed. Subsequently, a mask (not illustrated separately), such as a photoresist, can be formed over the p-region 50P while exposing the n-region 50N, and foreign materials of a suitable type (e.g., p-type) can be implanted into the p-region 50P.n-type foreign materials can be implanted into the semiconductor fins 62 and / or the nanostructures 64, 66 exposed in the n-region 50N. The mask can then be removed. The n-type foreign materials can be any of the previously described n-type foreign materials, and the p-type foreign materials can be any of the previously described p-type foreign materials. During implantation, the channel regions 68 remain covered by the dummy gates 94, so that the channel regions 68 remain essentially free of the foreign material implanted to form the LDD regions. The LDD regions can contain a concentration of foreign materials in the range of 10. 15 cm -3 up to 10 19 cm -3 exhibit. A tempering step can be used to repair implantation damage and activate the implanted foreign materials.

[0060] It should be noted that the preceding disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences can be used. For example, fewer or additional spacers can be used, different sequences of steps can be used, additional spacers can be formed and removed, and / or the like. Furthermore, the n-elements and the p-elements can be formed using different structures and steps.

[0061] In the Fig. 14A - 14C are source / drain depressions 104 formed in the mask 58 (if present), the nanostructures 64, 66, and the dummy gates 76. In the illustrated embodiment, the source / drain depressions 104 extend through the nanostructures 64, 66 and into the semiconductor fins 62. The source / drain depressions 104 can also extend into the substrate 50. In various embodiments, the source / drain depressions 104 can extend to an upper surface of the substrate 50 without etching the substrate 50; the semiconductor fins 62 can be etched such that lower surfaces of the source / drain depressions 104 are located below the upper surfaces of the STI areas 72; or the like. The source / drain depressions 104 can be formed by etching the nanostructures 64, 66 and the dummy gates 76 using an anisotropic etching process such as RIE, NBE or the like.The gate spacers 98 and the dummy gates 94 together mask sections of the semiconductor fins 62 and / or the nanostructures 64, 66 during the etching processes used to form the source / drain depressions 104. A single etching process can be used to etch each of the nanostructures 64, 66, or multiple etching processes can be used to etch the nanostructures 64, 66. Time-controlled etching processes can be used to stop the etching of the source / drain depressions 104 after they have reached a desired depth. In some embodiments, sections of the STI regions 72 adjacent to the mixing fins 82 can also be etched during the formation of the source / drain depressions 104.

[0062] Since the dummy gates 76 have a small foot profile, they can be removed more easily without leaving any residue on the upper surface of the STI areas 72. Consequently, more surface area is available for the source / drain areas, and these areas can be formed in such a way that no dummy gate residue remains beneath them. As a result, etching of the subsequently formed source / drain areas during a replacement gate process can be avoided, thereby increasing production yield.

[0063] Optionally, the inner spacers 106 are formed on the sidewalls of the remaining sections of the mask 58 (if present) and the nanostructures 64, e.g., the sidewalls exposed by the source / drain recesses 104. As will be described in more detail below, source / drain regions are subsequently formed in the source / drain recesses 104, and the nanostructures 64 are subsequently replaced by corresponding gate structures. The inner spacers 106 serve as insulating features between the subsequently formed source / drain regions and the subsequently formed gate structures. Furthermore, the inner spacers 106 can be used to essentially prevent damage to the subsequently formed source / drain regions by subsequent etching processes, such as those used to remove the nanostructures 64.

[0064] As an example of forming the internal spacers 106, the source / drain depressions 104 can be laterally extended. In particular, the sections of the sidewalls of the nanostructures 64 exposed by the source / drain depressions 104 can be deepened. Although the sidewalls of the nanostructures 64 are illustrated as straight, they can be concave or convex. The sidewalls can be deepened by any acceptable etching process, such as one that is selective with respect to the nanostructures 64 (e.g., selectively etching the materials of the nanostructures 64 at a faster rate than the material of the nanostructures 66). The etching can be isotropic. For example, if the nanostructures 66 are formed from silicon and the nanostructures 64 are formed from silicon-germanium, the etching process can be a wet etch using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like.In another embodiment, the etching process can be a dry etching using a fluorine-based gas, such as hydrogen fluoride gas (HF gas). In some embodiments, the same etching process can be performed continuously to form the source / drain depressions 104 and to deepen the sidewalls of the nanostructures 64. Then, internal spacers 106 are formed on the deepened sidewalls of the nanostructures 64. The internal spacers 106 can be formed by conformal fabrication of an insulating material and subsequent etching of the insulating material. The insulating material can be silicon nitride or silicon oxynitride, although any suitable material, such as a dielectric material with a low k-value, can be used. The insulating material can be deposited by a conformal deposition process, such as ALD, CVD, or the like. The etching of the insulating material can be anisotropic.For example, the etching process can be a dry etch, such as a RIE, an NBE, or the like. Although the outer sidewalls of the inner spacers 106 are illustrated as flush with the sidewalls of the gate spacers 98, the outer sidewalls of the inner spacers 106 can extend beyond or be recessed into the sidewalls of the gate spacers 98. In other words, the inner spacers 106 can partially fill, completely fill, or overfill the sidewall recesses. Although the sidewalls of the inner spacers 106 are illustrated as straight, the sidewalls of the inner spacers 106 can furthermore be concave or convex. Sections of the sidewalls of the mask 58 (if any) can also be recessed, and the inner spacers 106 can also be formed on the recessed sidewalls of the mask 58.

[0065] In the Fig. In 15A - 15C, epitaxial source / drain regions 108 are formed in the source / drain recesses 104. The epitaxial source / drain regions 108 are formed in the source / drain recesses 104 such that each dummy gate 94 (and the corresponding channel region 68) is arranged between respective adjacent pairs of epitaxial source / drain regions 108. In some embodiments, the gate spacers 98 and the inner spacers 106 are used to separate the epitaxial source / drain regions 108 from the dummy gates 94 and the nanostructures 64 by an appropriate lateral distance, so that the epitaxial source / drain regions 108 are not short-circuited with the subsequently formed gates of the resulting nanostructure transistors / FETs. A material of the epitaxial source / drain regions 108 can be chosen such that a voltage is exerted in the respective channel regions 68 to improve performance.

[0066] The epitaxial source / drain regions 108 in the n-region 50N can be formed by masking the p-region 50P. Then, the epitaxial source / drain regions 108 in the n-region 50N are epitaxially grown in the source / drain depressions 104 in the n-region 50N. The epitaxial source / drain regions 108 can enclose any acceptable material suitable for n-type devices. For example, if the nanostructures 66 are made of silicon, the epitaxial source / drain regions 108 in the n-region 50N can include materials that exert tensile stress in the channel regions 68, such as silicon, silicon carbide, phosphor-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 108 in the n-region 50N can be referred to as “n-source / drain regions”.The epitaxial source / drain regions 108 in the n-region 50N can have surfaces that are raised from the respective surfaces of the semiconductor fins 62 and the nanostructures 64, 66, and can have facets.

[0067] The epitaxial source / drain regions 108 in the p-region 50P can be formed by masking the n-region 50N. Then, the epitaxial source / drain regions 108 in the p-region 50P are epitaxially grown in the source / drain depressions 104 in the p-region 50P. The epitaxial source / drain regions 108 can contain any acceptable material suitable for p-type devices. For example, if the nanostructures 66 are made of silicon, the epitaxial source / drain regions 108 in the p-region 50P can contain materials that exert a compressive load in the channel regions 68, such as silicon germanium, boron-doped silicon germanium, germanium, germanium tin, or the like. The epitaxial source / drain regions 108 in the p-region 50P can be referred to as “p-source / drain regions”.The epitaxial source / drain regions 108 in the p-region 50P can have surfaces raised from the respective surfaces of the semiconductor fins 62 and the nanostructures 64, 66, and can have facets.

[0068] The epitaxial source / drain regions 108, the nanostructures 64, 66 and / or the semiconductor fins 62 can be implanted with foreign materials to form source / drain regions, similar to the previously described process for forming the LDD regions, followed by annealing. The source / drain regions can accommodate a foreign material concentration in the range of 10 19 cm -3 up to 10 21 cm -3 exhibit. The n- and / or p-substances for source / drain regions can be any of the previously described substances. In some embodiments, the epitaxial source / drain regions 108 can be doped in situ during growth.

[0069] The epitaxial source / drain regions 108 can enclose one or more semiconductor material layers. For example, the epitaxial source / drain regions 108 can each include a lining layer 108A, a main layer 108B, and a finishing layer 108C (or, more generally, a first, a second, and a third semiconductor material layer). Any number of semiconductor material layers can be used for the epitaxial source / drain regions 108. Each of the lining layer 108A, the main layer 108B, and the finishing layer 108C can be formed from a different semiconductor material and can be doped with a different concentration of impurities.In some embodiments, the lining layer 108A can have a lower concentration of impurities than the main layer 108B, and the finishing layer 108C can have a higher concentration of impurities than the lining layer 108A and a lower concentration of impurities than the main layer 108B. In embodiments in which the epitaxial source / drain regions 108 enclose three semiconductor material layers, the lining layers 108A can be grown in the source / drain depressions 104, and the main layers 108B can be grown on the lining layers 108A, and the finishing layers 108C can be grown on the main layers 108B.

[0070] As a result of the epitaxial processes used to form the epitaxial source / drain regions 108, the upper surfaces of these regions exhibit facets that extend laterally outward beyond the sidewalls of the semiconductor fins 62 and the nanostructures 64, 66. However, the mixing fins 82 block this lateral epitaxial growth. Therefore, the adjacent epitaxial source / drain regions 108 remain separated after the epitaxial process has ceased, as indicated by Fig. Figure 15C illustrates this. The epitaxial source / drain regions 108 contact the side walls of the mixing fins 82. In the illustrated embodiment, the epitaxial source / drain regions 108 are grown such that their upper surfaces are located below the upper surfaces of the mixing fins 82. In various other embodiments, the upper surfaces of the epitaxial source / drain regions 108 are located above the upper surfaces of the mixing fins 82; the upper surfaces of the epitaxial source / drain regions 108 have sections located above and below the upper surfaces of the mixing fins 82; or the like. Furthermore, in the illustrated embodiment, the epitaxial source / drain regions 108 are grown such that their upper surfaces are coplanar with the upper surfaces of the nanostructures 64, 66.In another embodiment, the epitaxial source / drain regions 108 are grown such that the upper surfaces of the epitaxial source / drain regions 108 are arranged above the upper surfaces of the nanostructures 64, 66.

[0071] In the Fig. In 16A - 16C, a first interlayer dielectric (ILD) 114 is deposited over the epitaxial source / drain regions 108, the gate spacers 98, the masks 96 (if present), or the dummy gates 94. The first ILD 114 can be formed from a dielectric material that can be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), FCVD, or the like. Acceptable dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used.

[0072] In some embodiments, a contact etch stop layer (CESL) 112 is formed between the first ILD 114 and the epitaxial source / drain regions 108, the gate spacers 98, and the masks 96 (if present) or the dummy gates 94. The CESL 112 can be formed from a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like, exhibiting high etch selectivity with respect to the etching of the first ILD 114. The CESL 112 can be formed by any suitable method, such as CVD, ALD, or the like.

[0073] In the Fig. In 17A-17C, a removal process is performed to ensure that the upper surfaces of the first ILD 114 are flush with the upper surfaces of the masks 96 (if present) or the dummy gates 94. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. The planarization process may also remove the masks 96 on the dummy gates 94 and sections of the gate spacers 98 along the sidewalls of the masks 96. After the planarization process, the upper surfaces of the gate spacers 98, the first ILD 114, the CESL 112, and the masks 96 (if present) or the dummy gates 94 are coplanar (within process variations). Accordingly, the upper surfaces of the masks 96 (if present) or the dummy gates 94 are exposed by the first ILD 114.In the illustrated embodiment, the masks 96 remain, and the planarization process causes the upper surfaces of the first ILD 114 to be flush with the upper surfaces of the masks 96.

[0074] In the Fig. In 18A-18C, the masks 96 (if present) and the dummy gates 94 are removed in an etching process, forming depressions 116. In some embodiments, the dummy gates 94 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using a reactive gas(es) that selectively etches the dummy gates 94 at a faster rate than the first ILD 114 or the gate spacers 98. Each depression 116 exposes and / or lies over sections of the channel regions 68. Sections of the nanostructures 66 serving as the channel regions 68 are arranged between adjacent pairs of the epitaxial source / drain regions 108.

[0075] The remaining sections of the nanostructures 64 are then removed to enlarge the recesses 116, forming openings 118 in regions between the nanostructures 66. The remaining sections of the dummy gates 76 are also removed to enlarge the recesses 116, forming openings 120 in regions between the semiconductor fins 62 and the mixing fins 82. The remaining sections of the nanostructures 64 and the dummy gates 76 can be removed by any acceptable etching process that selectively etches the material(s) of the nanostructures 64 and the dummy gates 76 at a faster rate than the material of the nanostructures 66. The etching can be isotropic.For example, if the nanostructures 64 and the dummy gates 76 are formed from silicon-germanium and the nanostructures 66 are formed from silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. The masks 58 (if present) can also be removed. In some embodiments, a trimming process (not illustrated separately) is performed to reduce the thickness of the exposed sections of the nanostructures 66.

[0076] Since the dummy gates 76 have a small foot profile, they can be removed more easily without leaving any residue on the upper surface of the STI areas 72. This provides more surface area for the replacement gates and prevents the formation of voids in the replacement gates, thereby increasing device performance. Furthermore, the epitaxial source / drain areas 108 are formed so that no residue of the dummy gates 76 remains below them, as noted above. This prevents etching below the epitaxial source / drain areas 108 during the formation of the depressions 116, thus reducing the risk of damage to the epitaxial source / drain areas 108.

[0077] In the Fig. In 19A - 19C, a dielectric gate layer 124 is formed in the recesses 116. A gate electrode layer 126 is formed on the dielectric gate layer 124. The dielectric gate layer 124 and the gate electrode layer 126 are replacement gate layers and each surround all (e.g., four) sides of the nanostructures 66. Thus, the dielectric gate layer 124 and the gate electrode layer 126 are formed in the openings 118 and 120 (see Fig. 18B).

[0078] The dielectric gate layer 124 is arranged on the side walls and / or the upper surfaces of the semiconductor fins 62; on the upper surfaces, side walls, and lower surfaces of the nanostructures 66; on the side walls of the gate spacers 98 and the inner spacers 106; and on the upper surfaces and side walls of the mixing fins 82. The dielectric gate layer 124 can also be formed on the upper surfaces of the first ILD 114 and the gate spacers 98. The dielectric gate layer 124 can include an oxide, such as a silicon oxide or a metal oxide, a silicate, such as a metal silicate, combinations thereof, multiple layers thereof, or the like. The dielectric gate layer 124 can be a dielectric material with a high k-value (e.g.,a dielectric material with a k-value greater than approximately 7.0), such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Although a single-layer dielectric gate layer 124 in the . Fig. As illustrated in 19A - 19C, the dielectric gate layer 124 can include any number of interface layers and any number of main layers.

[0079] The gate electrode layer 126 can include a metal-containing material such as titanium nitride, titanium oxide, tungsten, cobalt, ruthenium, aluminum, combinations thereof, multiple layers thereof, or the like. Although a single-layer gate electrode layer 126 is used in the Fig. As illustrated in 19A - 19C, the gate electrode layer 126 can include any number of work function-setting layers, any number of barrier layers, any number of adhesive layers and a filler material.

[0080] The formation of the gate dielectric layers 124 in the n-region 50N and the p-region 50P can occur simultaneously, so that the gate dielectric layers 124 in each region are formed from the same materials, and the formation of the gate electrode layers 126 can occur simultaneously, so that the gate electrode layers 126 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 124 in each region can be formed by different processes, so that the gate dielectric layers 124 can be made of different materials and / or have a different number of layers, and / or the gate electrode layers 126 in each region can be formed by different processes, so that the gate electrode layers 126 can be made of different materials and / or have a different number of layers.When different processes are used, different masking steps can be employed to mask or reveal appropriate areas.

[0081] In the Fig. In 20A - 20C, a removal process is performed to remove the excess material from the dielectric gate layer 124 and the gate electrode layer 126, wherein the excess material is located above the top surfaces of the first ILD 114 and the gate spacers 98, forming the gate structures 130. In some embodiments, a planarization process, such as chemical-mechanical polishing (CMP), a back-etching process, combinations thereof, or the like, may be used. When planarized, the dielectric gate layer 124 has sections that remain in the depressions 116 (forming gate dielectrics for the gate structures 130). When planarized, the gate electrode layer 126 has sections that remain in the depressions 116 (forming gate electrodes for the gate structures 130).The upper surfaces of the gate spacers 98, the CESL 112, the first ILD 114, and the gate structures 130 are coplanar (within process variations). The gate structures 130 are substitute gates for the resulting nanostructured transistors / FETs and can be referred to as "metal gates." The gate structures 130 each extend along the upper surfaces, sidewalls, and lower surfaces of a channel region 68 of the nanostructures 66.

[0082] Some gate structures 130 are cover gate structures 130C. The cover gate structures 130C are non-functional structures located at the ends of the semiconductor fins 62 and over the STI areas 72 between the semiconductor fins 62. The cover gate structures 130C are located between the mixing fins 82 and the semiconductor fins 62 in the cross-section of Fig. 20A arranged.

[0083] The gate structures 130 fill the area previously occupied by the nanostructures 64, the dummy gates 76, and the dummy gates 94. After their formation, the gate structures 130 have the same outline shape as the dummy gates 76. The outline shapes of the gate structures 130 are subsequently described in greater detail.

[0084] In some embodiments, isolation regions 132 are formed such that they extend through some of the gate structures 130. An isolation region 132 is formed to divide (or "cut") a gate structure 130 into multiple gate structures 130. The isolation region 132 can be formed from a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, which can be formed by a deposition process such as CVD, ALD, or the like. As an example of forming the isolation regions 132, openings in the desired gate structures 130 can be patterned. Any acceptable etching process, such as dry etching, wet etching, or a combination thereof, can be performed to pattern the openings. The etching can be anisotropic. One or more layers of dielectric material can be deposited in the openings.A removal process can be carried out to remove the excess sections of the dielectric material, the excess sections being located above the upper surfaces of the gate structures 130, thereby forming the isolation regions 132.

[0085] In Fig. In embodiments 21A-21C, a second ILD 136 is deposited over the gate spacers 98, the CESL 112, the first ILD 114, and the gate structures 130. In some embodiments, the second ILD 136 is a flowable film formed by a flowable CVD process. In other embodiments, the second ILD 136 is formed from a dielectric material such as PSG, BSG, BPSG, USG, or the like, which can be deposited by any suitable process, such as CVD, PECVD, or the like.

[0086] In some embodiments, an etch stop layer (ESL) 134 is formed between the second ILD 136 and the gate spacers 98, the CESL 112, the first ILD 114, and the gate structures 130. The ESL 134 can include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, with high etch selectivity for etching the second ILD 136.

[0087] In Fig. Gate contacts 142 and source / drain contacts 144 are formed at 22A - 22C to contact the gate structures 130 and the epitaxial source / drain regions 108, respectively. The gate contacts 142 are physically and electrically coupled to the gate structures 130. The source / drain contacts 144 are physically and electrically coupled to the epitaxial source / drain regions 108.

[0088] As an example of forming the gate contacts 142 and the source / drain contacts 144, openings for the gate contacts 142 are formed by the second ILD 136 and the ESL 134, and openings for the source / drain contacts 144 are formed by the second ILD 136, the ESL 134, the first ILD 114, and the CESL 112. The openings can be formed using acceptable photolithography and etching techniques. A lining (not illustrated separately), such as a diffusion barrier, an adhesive layer, or the like, and a conductive material are formed in the openings. The lining can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as a CMP, can be performed to remove excess material from one surface of the second ILD 136.The remaining lining and the conductive material form the gate contacts 142 and the source / drain contacts 144 in the openings. The gate contacts 142 and the source / drain contacts 144 can be formed in different processes or in the same process. Although they are shown as being formed in the same cross-section, it is understood that each of the gate contacts 142 and the source / drain contacts 144 can be formed in different cross-sections, which can prevent short-circuiting of the contacts.

[0089] Optionally, the metal-semiconductor alloy regions 146 are formed at the interfaces between the epitaxial source / drain regions 108 and the source / drain contacts 144. The metal-semiconductor alloy regions 146 can be silicide regions formed from a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), germanide regions formed from a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), silicon germanide regions formed from both a metal silicide and a metal germanide, or the like. The metal-semiconductor alloy regions 146 can be formed upstream of the source / drain contact material(s) 144 by depositing a metal in the openings for the source / drain contacts 144 and then performing a thermal tempering process. The metal can be any metal that is compatible with the semiconductor materials of the epitaxial source / drain regions 108 (e.g.B. silicon, silicon-germanium, germanium, etc.) can react to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be deposited by a deposition process such as ALD, CVD, PVD, or the like. After the thermal tempering process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the source / drain contact openings 144, as well as from the surfaces of the metal-semiconductor alloy areas 146. Then, the source / drain contact material(s) 144 can be formed on the metal-semiconductor alloy areas 146.

[0090] The Fig. Figures 23A-23C are views of nanostructured transistors / FETs according to different embodiments. Fig. 23A, Fig. 23B and Fig. Figures 23C show the resulting gate structures 130 after performing a replacement gate process in the embodiments of the Fig. 9A, Fig. 9B and Fig. 9C. As noted above, the gate structures 130 have the same outline shape as the dummy gates 76. In particular, the sections of the gate structures 130 on the upper surfaces of the STI areas 72 are not open to the outside along the concave surfaces of the STI areas 72.

[0091] In the embodiment of Fig. In 23A, after the replacement gate process, the lower surfaces of the gate structures 130 extend from the nanostructures 66 at a first distance D1, and the outer sidewalls of the gate structures 130 are arranged at a second distance D2 from the nanostructures 66, where the first distance D1 is equal to the second distance D2. Furthermore, the mixing fins 82 are arranged at the first distance D1 from the semiconductor fins 62 and at the second distance D2 from the nanostructures 66. In this embodiment, the sidewalls of the lower sections of the gate structures 130 are spaced apart by a constant width. The distance D1 and the distance D2 can each be in the range of 0.5 nm to 30 nm.

[0092] In the embodiment of Fig. In 23B, after the replacement gate process, the lower surfaces of the gate structures 130 extend from the nanostructures 66 at a first distance D1, and the outer sidewalls of the gate structures 130 are arranged at a second distance D2 from the nanostructures 66, the first distance D1 being smaller than the second distance D2. Furthermore, the mixing fins 82 are arranged at the first distance D1 from the semiconductor fins 62 and at the second distance D2 from the nanostructures 66. In this embodiment, the sidewalls of the lower sections of the gate structures 130 are spaced apart by a distance that decreases linearly in a direction extending from the top of the gate structures 130 to the bottom of the gate structures 130. The distance D1 and the distance D2 can each be in the range of 0.5 nm to 30 nm.

[0093] In the embodiment of Fig. In 23C, after the replacement gate process, the lower surfaces of the gate structures 130 extend from the nanostructures 66 at a first distance D1, and the outer sidewalls of the gate structures 130 are arranged at a second distance D2 from the nanostructures 66, the first distance D1 being smaller than the second distance D2. Furthermore, the mixing fins 82 are arranged at the first distance D1 from the semiconductor fins 62 and at the second distance D2 from the nanostructures 66. In this embodiment, the sidewalls of the lower sections of the gate structures 130 are spaced apart by a distance that decreases non-linearly in a direction extending from the top of the gate structures 130 to the bottom of the gate structures 130, and then also increases non-linearly in this direction. The sidewalls of these sections of the gate structures 130 include sidewall recesses 130R.The mixing fins 82 extend into the sidewall recesses 130R of the gate structures 130. The undersides of the sidewall recesses 130R are arranged at a third distance D3 from the nanostructures 66, where the third distance D3 is smaller than the second distance D2 and the first distance D1. The distance D1, the distance D2, and the distance D3 can each be in the range of 0.5 nm to 30 nm.

[0094] The Fig. Figures 24A-24C are views of nanostructured transistors / FETs according to different embodiments. These embodiments are similar to the embodiments shown in the Fig. 23A - 23C, except that the protective layers 80 were not removed and remain in the finished devices. The protective layers 80 extend along the sections of the sidewall of the gate structures 130 that are adjacent to the nanostructures 66. In these embodiments, the protective layers 80 have a constant width. The protective layers 80 are in contact with the upper sections of the sidewalls of the gate structures 130. The protective layers 80 can have a height H0 in the range of 1 nm to 300 nm and a width W0 in the range of 0.3 nm to 15 nm. The lower sections of the sidewalls of the gate structures 130 that are not covered by the protective layers 80 can have a height H1 in the range of 0 nm to 300 nm.

[0095] The Fig. Figures 25A-25C are views of nanostructured transistors / FETs according to different embodiments. These embodiments are similar to the embodiments shown in the Fig. 24A - 24C, except that the protective layers 80 have a width that decreases in a direction extending from the top of the protective layers 80 to the bottom of the protective layers 80.

[0096] The Fig. 26A - 26C are detailed views of areas 50R in the Fig. 23A - 23C. Referring to Fig. 26A The side walls of the lower sections of the gate structures 130 are essentially perpendicular to a plane parallel to the main surface of the substrate 50. For example, the angle θ1 between the side walls of the gate structures 130 and the upper surfaces of the STI areas 72 can be in the range of 80 degrees to 100 degrees. Referring to Fig. 26B The side walls of the lower sections of the gate structures 130 form an acute angle with a plane parallel to the main surface of the substrate 50. For example, the angle θ2 between the side walls of the gate structures 130 and the upper surfaces of the STI areas 72 can be in the range of 30 degrees to 85 degrees. Referring to Fig. 26C The surfaces of the gate structures 130, which define the sidewall recesses 130R, form several angles. In particular, the surfaces of the gate structures 130, which define the sidewall recesses 130R, form an angle θ3 with the upper surfaces of the STI regions 72 and an angle θ4 with a plane that is parallel to the main surface of the substrate 50. The angle θ3 and the angle θ4 can each be in the range of 95 degrees to 150 degrees.

[0097] The Fig. Figures 27A-27D show intermediate stages in the structuring of dummy gates 76 with a small foot profile according to some other embodiments. The dummy gates 76 are structured with a small foot profile by structuring the dummy gate layer 74 with several etching processes in a similar manner to that used for the Fig. The protective layers 80 are formed as described in Figures 7A-9C. In this embodiment, a different type of protective layer 80 is used. In particular, the protective layers 80 are passivation layers 80P. The passivation layers 80P can be formed by a separate process before or after the initial structuring of the dummy gate layer 74. Advantageously, the passivation layers 80P can be formed with a more uniform thickness than the by-product layers 80B. Furthermore, the passivation gas from the first etching process for the initial structuring of the dummy gates 76 can be omitted.

[0098] The passivation layers 80P can be formed by a surface modification process or a deposition process. Generally, surface modification processes are easier to control to minimize damage to the dummy gates 76, and deposition processes are easier to control the thickness of the resulting passivation layers 80P. The surface modification process can be a plasma modification process, a chemical modification process, or the like. In some embodiments, the thickness of the passivation layers 80P ranges from 2 Å to 150 Å.

[0099] In embodiments where a plasma modification process is used, the formation of the passivation layers 80P may involve exposing the structure to a passivation gas while a plasma is generated. The passivation gas may be CH4, SiCl4, N2, O2, CO2, SO2, CO, or the like. In some embodiments, a dilution gas, such as Ar, He, Ne, or combinations thereof, may be used. In some embodiments, the process conditions of the plasma modification process include: a pressure in the range of 1 mTorr to 10 Torr; a plasma source power (configured to control the ion-to-radical ratio) in the range of 10 W to 3000 W; a plasma bias power (configured to control the plasma direction) in the range of 0 W to 3000 W; and a gas source flow rate in the range of 1 sccm to 5000 sccm.The composition of the passivation layers 80P formed by the plasma modification process depends on the passivation gas used. Continuing with the example where the dummy gate layer 74 is formed from silicon or silicon germanium, the by-product layers 80P can be SiO₂ or SiGeO₂ when an oxygen-based passivation gas (e.g., O₂, CO₂, SO₂, CO, or the like) is used; the by-product layers 80P can be SiN or SiGeN when a nitrogen-based passivation gas (e.g., N₂, or the like) is used; and the by-product layers 80P can be SiS or SiGeS when a sulfur-based passivation gas (e.g., SO₂, or the like) is used. In some embodiments, a variety of passivation gases can be used in the plasma modification process.For example, a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas and a sulfur-based passivation gas (e.g. SO2 and N2) can be used in the plasma modification process, and the passivation layers 80P can be made of SiGeS. x O y N z be formed.

[0100] In embodiments where a chemical modification process is used, the formation of the passivation layers 80P can involve exposing the structure to a passivation solution without generating a plasma. The passivation solution can include a primary passivation chemical and an auxiliary passivation chemical in a solvent. The primary passivation chemical can be O3, CO2, or the like. The auxiliary passivation chemical can be H2SO4, NH3, or the like. The solvent can be deionized (DI) water, alcohol, acetone, or the like.

[0101] In embodiments where a deposition process is used, the formation of the passivation layers 80P can include PECVD, CVD, ALD, PVD, or a growth process suitable for depositing a dielectric material. The passivation layers 80P can be formed from a dielectric material such as SiN, SiON, SiCON, SiC, SiOC, SiO2, or the like.

[0102] In some embodiments, the passivation layers 80P are formed on the dummy gate layer 74 before the dummy gate layer 74 is structured, as described by the Fig. Figure 27A illustrates this. After the formation of the passivation layers 80P, the dummy gate layer 74 and the passivation layers 80P can be patterned simultaneously to form dummy gates 76 with a small foot profile. For example, an etching process can be performed to etch both the dummy gate layer 74 and the passivation layers 80P. The etching process can be controlled (e.g., by adjusting the plasma bias power) to etch in a lateral direction that is essentially parallel to the main face of the substrate 50. Sections of the passivation layers 80P can be removed by the etching process to expose the lower sections of the dummy gate layer 74, and the lateral direction of the etching process results in the etching of the dummy gate layer 74 to form dummy gates 76 with a small foot profile.In some embodiments, sections of the dummy gates 76 can extend over the mask 58 (if present) and the nanostructures 64, 66. These sections of the dummy gates 76 can be removed in a subsequent process, such as the removal process, to remove the sections of the mixing fin layer 78 over the mask 58 (if present) and the nanostructures 64, 66 (see Figure 1). Fig. 11A - 11C) to be removed.

[0103] In some embodiments, the passivation layers 80P are formed after the initial structuring of the dummy gate layer 74, but before the trimming of the dummy gates 76, so that the STI areas 72 are covered, as shown in the Fig. Figure 27B illustrates this. After forming the passivation layers 80P, the dummy gates 76 can be trimmed while covered by the passivation layers 80P to form dummy gates 76 with a small foot profile, thus improving the structure of Fig. 8C is obtained. For example, an etching process can be performed to etch both the dummy gates 76 and the passivation layers 80P. The etching process can be controlled (e.g., by adjusting the plasma bias power) to etch in a lateral direction that is essentially parallel to the main surface of the substrate 50. Sections of the passivation layers 80P can be removed by the etching process (thereby altering the structure of Fig. 7B is formed), and the lateral direction of the etching process leads to an etching of the lower sections of the dummy gates 76 to form dummy gates 76 with a small foot profile (thereby the structure of Fig. 8C is formed).

[0104] In some embodiments, the passivation layers 80P are formed after the initial structuring of the dummy gate layer 74, but before the trimming of the dummy gates 76, so that the STI areas 72 are exposed, as shown by the Fig. 27C and Fig. 27D is illustrated. In some embodiments where the passivation layers 80P are formed by a surface modification process, the passivation layers 80P can be selectively formed on the mask 58 (if present) and the dummy gates 76 without being formed on the STI areas 72, as shown by the Fig. 27C is illustrated. In some embodiments where the passivation layers 80P are formed by a deposition process, the passivation layers 80P can be conformally formed on the mask 58 (if present), the dummy gates 76 and the STI areas 72, as shown by the Fig. Figure 27D illustrates this. After forming the passivation layers 80P, the dummy gates 76 can be trimmed while covered by the passivation layers 80P to form dummy gates 76 with a small foot profile, thus improving the structure of the Fig. 8A or Fig. 8B is obtained. For example, an etching process can be performed to etch both the dummy gates 76 and the passivation layers 80P. The etching process can be controlled (e.g., by adjusting the plasma bias power) to etch in a diagonal direction that forms an acute angle with a plane parallel to the main surface of the substrate 50. The diagonal direction of the etching process results in etching through the passivation layers 80P at the lower sections of the dummy gates 76 (thereby restoring the structure of Fig. 7A is formed) and then the lower sections of the dummy gates 76 are etched to form dummy gates 76 with a small foot profile (thereby the structures of the Fig. 8A or Fig. 8B are formed).

[0105] As noted above, the same substrate 50 can have sparse and dense regions. In such embodiments, the passivation layers 80P can have different thicknesses in different regions. As a result, dummy gates 76 with different foot profiles can be formed from the same initial structure. For example, the structure of Fig. 27A are formed in a dense region and a sparse region. The passivation layers 80P can be formed over these structures, and then the dummy gates 76 are structured, with the structure of the Fig. 8A or Fig. 8B leads to the dense area and the structure of the Fig. 8C leads to the sparse area.

[0106] Embodiments can offer advantages. Forming the dummy gates 76 with a small foot profile can increase the process window for subsequent operations, such as a replacement gate process and / or an epitaxial growth process for the source / drain regions. In particular, no residue of the dummy gates 76 can remain under the epitaxial source / drain regions 108, thus preventing damage to the epitaxial source / drain regions 108 when the dummy gates 76 are removed in a replacement gate process. Furthermore, dummy gates 76 with a small foot profile can be removed more easily in a replacement gate process, avoiding the formation of cavities in the replacement gates and thereby increasing device performance.

[0107] In one embodiment, a component includes: an insulating region; nanostructures projecting above an upper surface of the insulating region; a gate structure surrounding the nanostructures, the gate structure having a lower surface contacting the insulating region, the lower surface of the gate structure extending from the nanostructures by a first distance, the gate structure having a side wall arranged at a second distance from the nanostructures, the first distance being less than or equal to the second distance; and a mixing fin on the side wall of the gate structure. According to the invention, the first distance is less than the second distance. In some embodiments of the component, the mixing fin extends into a side wall recess of the gate structure. Not according to the invention, the first distance is equal to the second distance.In some embodiments of the component, the first and second distances are each in the range of 0.5 nm to 30 nm. In some embodiments, a component further includes the following: a protective layer arranged between the mixing fin and the gate structure, wherein the protective layer covers an upper section of the side wall of the gate structure, while a lower section of the side wall of the gate structure is not covered by the protective layer.

[0108] In one embodiment, a device includes: an insulating region; a semiconductor fin projecting above an upper surface of the insulating region; nanostructures above the semiconductor fin; a gate structure surrounding the nanostructures; and a mixing fin on a sidewall of the gate structure, wherein the mixing fin is positioned at a first distance from the semiconductor fin and at a second distance from the nanostructures, the second distance being greater than the first distance. In some embodiments, a device further includes: a protective layer between the mixing fin and the gate structure, wherein the protective layer extends along a portion of the sidewall of the gate structure adjacent to the nanostructures. In some embodiments of the device, the protective layer includes SiGeS x O y N zIn some embodiments of the device, the protective layer encloses a dielectric material. In some embodiments of the device, a portion of the mixing fin extends into a sidewall recess of the gate structure, wherein the portion of the mixing fin is arranged at a third distance from the semiconductor fin, the third distance being smaller than the first distance and the second distance.

[0109] In one embodiment, a method includes: depositing a dummy gate layer over an isolation region and alternating first and second nanostructures, wherein the first and second nanostructures protrude above an upper surface of the isolation region; structuring the dummy gate layer to form a dummy gate on sidewalls of the first nanostructures, sidewalls of the second nanostructures, and the upper surface of the isolation region; forming a protective layer on an upper portion of the dummy gate; trimming a lower portion of the dummy gate while the protective layer covers the upper portion of the dummy gate; and replacing the dummy gate and the first nanostructures with a metal gate, wherein the metal gate surrounds the second nanostructures.In some embodiments of the method, the protective layer is a by-product layer formed during the structuring of the dummy-gate layer, and the structuring of the dummy-gate layer includes etching the dummy-gate layer with a gas source that includes a primary etching gas and a passivation gas. In some embodiments of the method, the dummy-gate layer and the initial nanostructures include silicon or silicon-germanium; and the passivation gas is a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas, and a sulfur-based passivation gas. In some embodiments of the method, the protective layer is a passivation layer formed after the structuring of the dummy-gate layer, and the formation of the protective layer includes exposing the dummy-gate to a passivation gas while generating a plasma.In some embodiments of the method, the protective layer is a passivation layer formed after structuring the dummy gate layer, and the formation of the protective layer involves exposing the dummy gate to a passivation solution without generating a plasma. In some embodiments of the method, the protective layer is a passivation layer formed after structuring the dummy gate layer, and the formation of the protective layer involves depositing a dielectric material on the dummy gate.According to the invention, the dummy gate has a side wall and a bottom surface that contacts the insulation area, wherein the side wall of the dummy gate is arranged at a first distance from the second nanostructures, and the trimming of the bottom section of the dummy gate includes: etching the bottom section of the dummy gate until the bottom surface of the dummy gate extends away from the second nanostructures by a second distance that is smaller than the first distance.Not according to the invention, the dummy gate has a side wall and a lower surface that contacts the insulation area, wherein the side wall of the dummy gate is arranged at a first distance from the second nanostructures, and the trimming of the lower section of the dummy gate includes the following: etching the lower section of the dummy gate until the lower surface of the dummy gate extends away from the second nanostructures by a second distance equal to the first distance. In some embodiments of the method, the etching of the lower section of the dummy gate forms a side wall recess in the lower section of the dummy gate.

Claims

[1] Building element, comprising: an isolation area (72); Nanostructures (64, 66) that protrude above an upper surface of the insulation area (72); a gate structure (130) surrounding the nanostructures (64, 66), wherein the gate structure (130) has a lower surface that contacts the insulation area (72), the lower surface of the gate structure (130) extending away from the nanostructures (64, 66) at a first distance (D1), and the gate structure (130) having a side wall that is arranged at a second distance (D2) from the nanostructures (64, 66), the first distance (D1) being smaller than the second distance (D2); and a mixing fin (82) on the side wall of the gate structure (130). [2] Component according to claim 1, wherein the mixing fin (82) extends into a side wall recess (130R) of the gate structure (130). [3] Component according to claim 1, wherein the first distance (D1) and the second distance (D2) are each in a range of 0.5 nm to 30 nm. [4] Component according to any one of claims 1 to 3, further comprising: a protective layer (80) arranged between the mixing fin (82) and the gate structure (130), wherein the protective layer (80) covers an upper section of the side wall of the gate structure (130), and wherein a lower section of the side wall of the gate structure (130) is not covered by the protective layer (80). [5] Building element, comprising: an isolation area (72); a semiconductor fin (62) that protrudes above an upper surface of the insulation area (72); Nanostructures (64, 66) above the semiconductor fin (62); a gate structure (130) surrounding the nanostructures (64, 66); and a mixing fin (82) on a side wall of the gate structure (130), wherein the mixing fin (82) is arranged at a first distance (D1) from the semiconductor fin (62) and the mixing fin (82) is arranged at a second distance (D2) from the nanostructures (64, 66), wherein the second distance (D2) is greater than the first distance (D1). [6] Component according to claim 5, further comprising: a protective layer (80) between the mixing fin (82) and the gate structure (130), wherein the protective layer (80) extends along a section of the side wall of the gate structure (130) adjacent to the nanostructures (64, 66). [7] Component according to claim 6, wherein the protective layer (80) SiGeS x O y N z includes. [8] Component according to claim 6, wherein the protective layer (80) comprises a dielectric material. [9] Component according to one of claims 5 to 8, wherein a section of the mixing fin (82) extends into a side wall recess (130R) of the gate structure (130), wherein the section of the mixing fin (82) is arranged at a third distance (D3) from the semiconductor fin (62), wherein the third distance (D3) is smaller than the first distance (D1) and the second distance (D2). [10] Procedures, including: Deposition of a dummy gate layer (74) over an isolation region (72) and alternating first nanostructures (64) and second nanostructures (66), wherein the first nanostructures (64) and the second nanostructures (66) protrude above an upper surface of the isolation region (72), wherein the dummy gate (76) has a side wall and a lower surface that contacts the isolation region (72), wherein the side wall of the dummy gate (76) is arranged at a first distance (D2) from the second nanostructures (66); Structuring the dummy gate layer (74) to form a dummy gate (76) on side walls of the first nanostructures (64), side walls of the second nanostructures (66) and the upper surface of the insulation area (72); Forming a protective layer (80) on an upper section of the dummy gate (76); Trimming a lower section (76L) of the dummy gate (76) while the protective layer (80) covers the upper section of the dummy gate (76), wherein the trimming of the lower section (76L) of the dummy gate (76) comprises etching the lower section (76L) of the dummy gate (76) until the lower surface of the dummy gate (76) extends away from the second nanostructures (66) by a second distance (D1) that is smaller than the first distance (D2); and Replacing the dummy gate (76) and the first nanostructures (64) with a metal gate (130), wherein the metal gate (130) surrounds the second nanostructures (66). [11] Method according to claim 10, wherein the protective layer (80) is a by-product layer (80B) formed during the structuring of the dummy gate layer (74), and the structuring of the dummy gate layer (74) comprises etching the dummy gate layer (74) with a gas source comprising a principal etching gas and a passivation gas. [12] Method according to claim 11, wherein the dummy gate layer (74) and the first nanostructures (64) comprise silicon or silicon germanium; and the passivation gas is a mixture of an oxygen-based passivation gas, a nitrogen-based passivation gas and a sulfur-based passivation gas. [13] Method according to any one of claims 10 to 12, wherein the protective layer (80) is a passivation layer (80P) formed after structuring the dummy gate layer (74), and the formation of the protective layer (80) comprises exposing the dummy gate (76) to a passivation gas while generating a plasma. [14] Method according to any one of claims 10 to 12, wherein the protective layer (80) is a passivation layer (80P) formed after structuring the dummy gate layer (74), and the formation of the protective layer (80) comprises exposing the dummy gate (76) to a passivation solution without generating a plasma. [15] Method according to any one of claims 10 to 12, wherein the protective layer (80) is a passivation layer (80P) formed after structuring the dummy gate layer (74), and the formation of the protective layer (80) comprises depositing a dielectric material on the dummy gate (76). [16] Method according to any one of claims 10 to 15, wherein the etching of the lower section (76L) of the dummy gate (76) forms a side wall recess (130R) in the lower section (76L) of the dummy gate (76).

Images