Semiconductor device containing bonding pad metal layer structure

Abstract

Semiconductor device (100) comprising: a wiring metal layer structure (102); a dielectric layer structure (104) disposed directly on the wiring metal layer structure (102); a bonding pad metal layer structure (106) which is arranged at least partially directly on the dielectric layer structure (104), wherein a layer thickness (td) of the dielectric layer structure (104) ranges from 1% to 30% of a layer thickness (tw) of the wiring metal layer structure (102), the wiring metal layer structure (102) and the bonding pad metal layer structure (106) are electrically connected by completely filled openings (108) in the dielectric layer structure (104), and the bonding pad metal layer structure (106) or a part thereof is formed from aluminum with at least 50% mole fraction, and wherein the wiring metal layer structure (102) or a part thereof is formed from aluminum with at least 50% mole fraction.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to semiconductor devices, in particular to semiconductor devices including a bonding pad metal layer structure. BACKGROUND

[0002] Semiconductor device technologies aim to achieve improved efficiency and higher reliability requirements for products containing power semiconductor devices such as insulated-gate bipolar transistors (IGBTs) or diode-containing chips. The semiconductor devices, e.g., modules or encapsulated assemblies, are intended to achieve even higher current densities and lower resistance while decreasing in size. For example, reference is made to the disclosures in US 2004 / 0 070 042 A1 and DE 10 2006 052 202 B3. The shrinking or downsizing of semiconductor devices is accompanied by an increase in bond foot density. Wire bonds or wire connections can be limited in current density due to material heating in combination with thermal expansion of the wire bond material used, e.g., aluminum (Al).

[0003] Power cycling and temperature cycling are common thermal acceleration tests used in the reliability assessment of semiconductor devices. Power cycling tests are accelerated tests in which the power in semiconductor devices is switched (on and off) in such a way that the temperature in the device varies (cyclically). Power cycling tests involve conduction and switching and approximate the actual operation of the device.

[0004] The suitability of semiconductor devices for power cycling can be limited by the metal pad / wire bond connection. For example, mechanical parameters of the pad and wire, such as hardness, cannot be freely tuned, and there are limitations on the maximum energy applied to the system to ensure a robust bond. Undesirable cracks can occur at the wire-pad interface and propagate during power cycling.

[0005] It is desirable to improve the reliability of a semiconductor device and to provide a manufacturing method therefor. SUMMARY

[0006] The invention is defined in the independent claims. Further developments are the subject of the dependent claims. One example of the present disclosure relates to a semiconductor device. The semiconductor device includes a wiring metal layer structure. The semiconductor device further includes a dielectric layer structure arranged directly on the wiring metal layer structure. The semiconductor device moreover includes a bonding pad metal layer structure arranged at least partially directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal layer structure are electrically connected through openings in the dielectric layer structure. The bonding pad metal layer structure is formed from aluminum with at least 50% mole fraction.

[0007] Another example of the present disclosure relates to a method for manufacturing a semiconductor device. The method includes forming a wiring metal layer structure. The method further includes forming a dielectric layer structure disposed directly on the wiring metal layer structure. Moreover, the method includes forming a bonding pad metal layer structure disposed at least partially directly on the dielectric layer structure. A layer thickness of the dielectric layer structure ranges from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal layer structure are electrically connected through openings in the dielectric layer structure. The bonding pad metal layer structure or a part thereof comprises Al (aluminum) with at least 50% mole fraction.

[0008] Those skilled in the art will recognize additional features and advantages upon reading the following detailed description and upon viewing the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying drawings are included to provide a further understanding of embodiments and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of semiconductor devices, e.g., vertical power semiconductor devices, and together with the description serve to explain the principles of the embodiments. Further embodiments are described in the following description and claims. Fig. 1 is a schematic cross-sectional view to illustrate an example of a semiconductor device including a dielectric layer structure disposed between a wiring metal layer structure and a bonding pad metal layer structure. Fig. 2A to 2E are schematic plan views to illustrate layouts of the dielectric layer structure. Fig. 3A to 3C are schematic cross-sectional views to illustrate layouts of a wiring region including the wiring metal layer structure, the dielectric layer structure, and the bonding pad metal layer structure of the semiconductor body. DETAILED DESCRIPTION

[0010] In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific embodiments in which the invention may be practiced. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. For example, features illustrated or described for one embodiment may be used on or in connection with other embodiments to arrive at still another embodiment. It is intended that the present invention encompass such modifications and variations. The examples are described using specific language that should not be construed as limiting the scope of the appended claims.The drawings are not to scale and are for illustrative purposes only. For clarity, the same elements are designated by corresponding reference numerals in the various drawings unless otherwise stated.

[0011] The terms "have," "contain," "comprise," "have," and the like are open-ended terms. These terms indicate the presence of the identified structures, elements, or characteristics, but do not preclude the presence of additional elements or characteristics. The indefinite and definite articles are intended to include both the plural and the singular, unless the context clearly indicates otherwise.

[0012] Ranges specified for physical dimensions include the boundary values. For example, a range for a parameter y from a to b is written as a ≤ y ≤ b. A parameter y with a value of at least c is written as c ≤ y, and a parameter with a value of at most d is written as y ≤ d.

[0013] The term "on" should not be construed to mean only "directly on." Rather, if an element is positioned "on" another element (e.g., a layer is "on" another layer or "on" a substrate or semiconductor body), another component (e.g., another layer) may be positioned between the two elements (e.g., another layer may be positioned between a layer and a substrate if the layer is "on" the substrate).

[0014] An example of a semiconductor device may include a wiring metal layer structure. The semiconductor device may further include a dielectric layer structure disposed directly on the wiring metal layer structure. Furthermore, the semiconductor device may include a bonding pad metal layer structure disposed at least partially directly on the dielectric layer structure. A layer thickness of the dielectric layer structure may range from 1% to 30%, or from 3% to 25%, or from 5% to 20%, or from 5% to 15%, or from 10% to 20% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal layer structure may be electrically connected through openings in the dielectric layer structure.

[0015] The bonding pad metal layer structure or a portion of the bonding pad metal layer structure may be formed from aluminum with a mole fraction of at least 50%, at least 70%, at least 85%, or even at least 94%. The mole fraction may refer to the number of atoms in the bonding pad metal layer structure. For example, at least 50%, at least 70%, at least 85%, or even at least 94% of the atoms in the bonding pad metal layer structure or portion thereof may be aluminum atoms.

[0016] The wiring metal layer structure or a portion of the wiring metal layer structure may be formed of aluminum with a mole fraction of at least 50%, at least 70%, at least 85%, or even at least 94%. The mole fraction may refer to the number of atoms in the wiring metal layer structure. For example, at least 50%, at least 70%, at least 85%, or even at least 94% of the atoms in the wiring metal layer structure or portion thereof may be aluminum atoms.

[0017] The semiconductor device may, for example, be an integrated circuit or a discrete semiconductor device or a semiconductor module. The semiconductor device may be or include a power semiconductor device, e.g., a vertical power semiconductor device with a load current flow between a first load terminal on a first side of the device and a second load terminal on a second side opposite the first side, or a lateral power semiconductor device with a load current flow between load terminals on a same side of the device. The semiconductor device may be a power semiconductor IGBT (insulated gate bipolar transistor) or a reverse conducting (RC) power semiconductor IGBT or a power semiconductor transistor such as a power semiconductor IGFET (insulated gate field effect transistor, e.g.,The power semiconductor device may be or contain a metal-oxide-semiconductor field-effect transistor (MSO) or a power semiconductor diode. The power semiconductor device may be configured to conduct currents of more than 1 A, more than 10 A, or even more than 30 A, and may further be configured to block voltages between load terminals, e.g., between the emitter and collector of an IGBT or between the drain and source of a MOSFET, in the range of several hundred to several thousand volts, e.g., 400 V, 650 V, 1.2 kV, 1.7 kV, 3.3 kV, 4.5 kV, 5.5 kV, 6 kV, 6.5 kV. The blocking voltage may, for example, correspond to a voltage class specified in a datasheet of the power semiconductor device.

[0018] The interconnect metal layer structure may be disposed over a semiconductor body that may include or consist of a Group IV elemental semiconductor material, a IV-IV compound semiconductor material, a III-V compound semiconductor material, or a II-VI compound semiconductor material. Examples of Group IV elemental semiconductor materials include, but are not limited to, silicon (Si) and germanium (Ge). Examples of IV-IV compound semiconductor materials include, but are not limited to, silicon carbide (SiC) and silicon germanium (SiGe). Examples of a III-V compound semiconductor material include, but are not limited to, gallium arsenide (GaAs), gallium nitride (GaN), gallium phosphide (GaP), indium phosphide (InP), indium gallium nitride (InGaN), and indium gallium arsenide (InGaAs). Examples of II-VI compound semiconductor materials include cadmium telluride (CdTe), mercury cadmium telluride (CdHgTe), and cadmium magnesium telluride (CdMgTe).The semiconductor body can be, for example, a magnetic Czochralski, MCZ, or a float zone or zone melt (FZ) semiconductor body or a semiconductor body with epitaxially deposited silicon.

[0019] The wiring metal layer structure may, for example, correspond to or be a part of a wiring level of a wiring region above the semiconductor body or semiconductor substrate. In some examples, the one wiring level containing the wiring metal layer may be closest to the semiconductor body in the case of multiple wiring levels. In some other examples, one or more further wiring levels may be arranged between the one wiring level containing the wiring metal layer and the semiconductor body. The wiring region may contain two, three, four, or even more wiring levels. Each wiring level may be formed by a single or a stack of conductive layers, e.g., metal layer(s), and / or highly doped semiconductor materials such as highly doped polycrystalline silicon.For example, some or all of the wiring levels can be lithographically patterned. By patterning wiring levels, any desired wiring lines, bond pads, contact areas, or any combination thereof can be formed. An intermediate dielectric can be arranged between stacked wiring levels. Contact plugs and / or a contact line(s) can be formed in openings in the intermediate dielectric in order to electrically connect parts, e.g., wiring lines or contact areas, of different wiring levels to one another. A dielectric layer can, for example, also be arranged between the semiconductor body and the wiring level closest to the semiconductor body. Contact plugs and / or contact lines can be formed in openings in the dielectric layer in order to electrically connect parts, e.g.,To electrically connect wiring lines or contact regions of the wiring level closest to the semiconductor body and active regions in the semiconductor body, e.g., doped regions in the semiconductor body such as anode or cathode regions of a diode or emitter, base or collector regions of an IGBT or source, body or drain regions of an IGFET.

[0020] Similar to the wiring metal layer structure, the bonding pad metal layer structure may correspond to or be part of another wiring level of the wiring region above the semiconductor body or semiconductor substrate. The wiring level of the bonding pad metal layer structure may, for example, have a greater vertical distance from the semiconductor body than the wiring level of the wiring metal layer structure. For example, the bonding pad metal layer structure may be part of or correspond to the metal wiring level that, among the wiring levels in the wiring region, has, for example, the greatest vertical distance from the semiconductor body. The bonding pad metal layer structure may, for example, be a continuous metal structure.

[0021] The dielectric layer structure may include one layer or a combination of layers, e.g., a layer stack of dielectric layers, for example, oxide layers such as thermal oxide layers or deposited oxide layers, e.g., undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), oxynitride or nitride layers, high-k or low-k dielectric layers, undoped or intrinsic semiconductor materials such as undoped polycrystalline silicon. The dielectric layer structure may form, or be part of, an intermediate dielectric layer arranged vertically between wiring layers.In some examples, the formation processes of the dielectric layer structure include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma enhanced CVD (or PECVD), spin coating, and other applicable processes.

[0022] A layer thickness of any layer of the wiring region, e.g., the dielectric layer structure or the bonding pad metal layer structure or the wiring metal layer structure, may correspond to a vertical extension of the respective layer, e.g., measured along a vertical direction perpendicular to a main surface plane of the semiconductor body.

[0023] The dielectric layer structure can, for example, serve as a stress absorption and structural tuning layer. While typical intermediate dielectric layers focus on electrical insulation between adjacent wiring levels, the dielectric layer structure is thinner and is designed to enable a low-resistance electrical connection between the bonding pad metal layer structure and the wiring metal layer structure.

[0024] In addition, the dielectric layer structure can enable a number of technical advantages, as described below.

[0025] For example, the dielectric layer structure can serve as an etch stop layer when the bonding pad metal layer structure is formed by patterning the respective wiring level. Therefore, this can allow for thicker metallization in required areas, e.g., bond islands or bond pads, and protect underlying metal wiring, e.g., the wiring level containing the wiring metal layer structure, from etching. This allows metal structures in the kerf, e.g., a process control monitor, PCM structures, or in non-bond pad areas, e.g., a metal routing guide or a gate runner, to be formed with only one thickness of the wiring layer containing the metal wiring layer structure, provided that the dielectric layer is thick enough to ensure sidewall coverage of the covered structures.This allows for sawing through the structures and avoids the need for double kerf or block PCMs, which reduce the amount of active area per wafer and increase chip costs. Metal structures without bond pads on the chip, used for routing, for example, can remain only one thickness of the wiring metal layer structures. Consequently, the requirement for modifying critical dimensions can be reduced. The ability to pattern the wiring metal layer structure and the bonding pad metal layer structure separately can also enable the use of thick hard passivation layer(s), since the passivation layer(s) can only cover the topological step up to one thickness of the wiring metal layer structure.This can prevent the formation of thinned passivation areas, cracks and layer interruptions that occur at high topography levels.

[0026] The dielectric layer structure between the wiring metal layer structure and the bonding pad metal layer structure can be customized. For example, the dielectric layer structure can absorb bonding forces if the dielectric layer structure is thick enough to be mechanically relevant or useful. The layer structure can be adapted to the requirements of different bonding processes, for example, wire material and the number of bond pads.

[0027] Since only a portion of the interface between the wiring metal layer structure and the bonding pad metal layer structure is covered with the dielectric layer structure, there is no or negligible reduction in current flow even if the thickness of the dielectric layer structure is too thick to be conductive. The thickness of the dielectric layer structure can be balanced to provide sufficient buffering capacity for bonding forces while still allowing the deposition of the bonding pad metal layer structure without forming voids. Consequently, the thickness of the dielectric layer structure may depend on the layout of an inner part, e.g., a central part, of the dielectric layer structure.

[0028] The provision of the dielectric layer structure can enable a reduction in the grain size of the material of the bonding pad metal layer structure compared to a single thick metallization layer. If an aluminum-based metallization layer is deposited, the average grain size grown during a metal anneal can be in the range of the full layer thickness. A thick metal layer deposited without any intervening layer can have a larger average grain size than, for example, a stack with the dielectric layer structure between the wiring metal layer structure and the bonding pad metal layer structure. Furthermore, edges, corners, and topography of the patterned dielectric layer structure can serve as starting points for metal grain growth. This can result in smaller grains and a higher total number of metal grains.This, in turn, can improve the absorption capacity of bonding forces. With regard to the flexibility of the design of the dielectric layer structure, symmetries can be established to enable, for example, specific adjustment of the grain size and grain orientation of the bonding pad metal layer structure.

[0029] At an overlap area between the bonding pad metal layer structure and a passivation layer structure, an intermediate dielectric, e.g., a protective dielectric frame, can be formed as part of the dielectric layer structure. This intermediate dielectric can serve as additional protection against chemical attack or ionic contamination from the package.

[0030] The layer thickness of the dielectric layer structure can, for example, range from 50 nm to 1 µm. The layer thickness of the dielectric layer structure can, for example, be less than 500 nm.

[0031] For example, a lateral end of the dielectric layer structure may protrude beyond a lateral end of the bonding pad metal structure. This may allow the dielectric layer structure to serve as an etch stop layer when the bonding pad metal layer structure is formed by patterning the respective wiring level.

[0032] For example, the semiconductor device may further include a passivation layer structure arranged in a peripheral part of the dielectric layer structure between the dielectric layer structure and the wiring metal layer structure. The peripheral part may, for example, partially or completely laterally surround the dielectric layer structure. The passivation layer structure may, for example, cover edge regions of the wiring metal layer structure. The passivation layer structure is formed to protect the elements of an integrated circuit or a discrete semiconductor device formed in the semiconductor body and also the edge regions of the wiring metal layer structure. In some examples, the passivation layer structure is a hermetic or airtight layer to prevent moisture from coming into contact with the device elements, e.g., pn junctions or wiring.In some examples, the passivation layer structure is formed from any polymer (such as polyimide or polybenzoxazole), oxide, oxynitride, nitride, or other dielectric materials, or any combination thereof. In some examples, additional passivation layer structures are formed over the wiring region (not shown) and in the same plane as or above the bonding pad metal layer structure. The passivation layer structure, in some examples, has a thickness in a range of about 0.1 µm to about 3 µm. In some examples, the formation methods include physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (or PECVD), spin-on, and other applicable methods.

[0033] For example, at least one of the wiring metal layer structure or the bonding pad metal layer structure (typically the wiring metal layer structure and the bonding pad metal layer structure) may comprise at least one of the following: a pure metal, a metal alloy, or a metal compound. In some examples, the wiring metal layer and / or the bonding pad metal layer structure (excluding impurities) may be made of a pure metal, a metal alloy, or a metal compound. The wiring metal layer structure and / or the bonding pad metal layer structure may comprise or be a metal layer stack. The wiring metal layer structure and / or the bonding pad metal layer structure may comprise at least one of the following: Al, Cu, an aluminum-copper alloy (e.g., AlCu), AlSi, or AlSiCu.Typically, the wiring metal layer structure and / or the bonding pad metal layer structure comprise / comprises aluminum. The wiring metal layer structure and / or the bonding pad metal layer structure may comprise the same metal compound or a different metal compound.

[0034] For example, the wiring metal layer structure or part thereof comprises a first metal compound of at least Cu and Al, or AlSiCu.

[0035] For example, the bonding pad metal layer structure or the part thereof comprises a second metal compound of at least Cu and Al. The first metal compound and the second metal compound may be the same or different.

[0036] For example, the wiring metal layer structure or part thereof comprises AlSiCu, and the bonding pad metal layer structure or part thereof comprises AlCu.

[0037] The first metal compound can be formed from aluminum with at least 50%, at least 70%, at least 85%, or even at least 94% mole fraction. The second metal compound can be formed from aluminum with at least 50%, at least 70%, at least 85%, or even at least 94% mole fraction. The mole fraction can refer to the number of atoms in the respective metal compound. For example, at least 50%, at least 70%, at least 85%, or even at least 94% of the atoms in the first metal compound can be aluminum atoms. For example, at least 50%, at least 70%, at least 85%, or even at least 94% of the atoms in the second metal compound can be aluminum atoms. The remaining percentages of atoms in the respective metal compound can be, for example, Si and / or Cu atoms.

[0038] For example, AlCu can be a metal compound that contains only aluminum and copper. AlSiCu can be a metal compound that contains only aluminum, silicon, and copper. AlSiCu can be softer than AlCu. AlCu can be harder than AlSiCu.

[0039] The dielectric layer structure may, for example, be any one, or any combination, e.g., stacked combination, of an oxide layer, a silicon oxide layer or nitride layer and an undoped (e.g., unintentionally doped or intrinsic) polycrystalline silicon layer.

[0040] For example, the bonding pad metal layer structure may include a central portion and a peripheral portion. Any wire connection on the bonding pad metal layer structure may be located in the central portion.

[0041] A number of wire connections or wire bonds on the bonding pad metal layer structure can be, for example, two or more, e.g., three, four, five or even more.

[0042] The dielectric layer structure may, for example, have a closed peripheral portion. The dielectric layer structure may, for example, be in the form of a closed loop. The dielectric layer structure may further comprise one or more dielectric layer portions within the closed loop and / or at least partially surrounded by it. The one or more dielectric layer portions located within and / or surrounded by the closed loop may, for example, be laterally spaced from the closed loop and / or merge with the closed loop. The closed peripheral portion may, for example, border the peripheral portion of the bonding pad metal layer structure.

[0043] The dielectric layer structure can, for example, have a central portion, e.g., free-floating oxide structures, which is laterally spaced from the closed peripheral portion by a separating opening in the dielectric layer structure. The separating opening can, for example, also be in the form of a closed loop. This can reduce the risk of crack propagation outside the bonding pad region, e.g., the passivation layers. Fracture of the free-floating oxide structures during a bonding process can be permitted without affecting outer regions. The absorption of bonding forces can enable higher ultrasonic power during bonding without endangering the material of the semiconductor body, e.g., silicon, underneath. This can result in an expansion of the window for wire bonding process conditions, enabling greater power cycling capabilities, also through the use of harder bonding materials, e.g., AlMg.

[0044] A maximum lateral extent of the openings in the central part of the dielectric layer structure may, for example, be smaller than a sum of the layer thickness of the wiring metal layer structure and the layer thickness of the bonding pad metal layer structure. The openings in the central part of the dielectric layer may be filled with a conductive material, e.g., a portion of the conductive material of the bonding pad metal layer structure, which, for example, electrically connects the bonding pad metal layer structure and the wiring metal layer structure. In some other examples, a maximum lateral extent of the openings in the central part of the dielectric layer structure may be smaller than a sum of the layer thickness of the dielectric layer structure, the layer thickness of the wiring metal layer structure, and the layer thickness of the bonding pad metal layer structure.

[0045] A minimum lateral extension of the openings in the central part of the dielectric layer structure can, for example, be equal to twice the layer thickness of the dielectric layer structure or greater.

[0046] The dielectric layer structure may, for example, cover 25% to 90% or 35% to 80% or 50% to 70% of a bottom surface of the bonding pad metal layer structure in the central part of the bonding pad metal layer structure.

[0047] An example of a method for manufacturing a semiconductor device may include forming a wiring metal layer structure. The method may further include forming a dielectric layer structure disposed directly on the wiring metal layer structure. The method may further include forming a bonding pad metal layer structure disposed at least partially directly on the dielectric layer structure. A layer thickness of the dielectric layer structure may range from 1% to 30% of a layer thickness of the wiring metal layer structure. The wiring metal layer structure and the bonding pad metal layer structure may be electrically connected through openings in the dielectric layer structure.

[0048] For example, the method may include forming a passivation layer structure on at least a portion of the wiring metal layer structure prior to forming the dielectric layer structure. In some examples, the passivation layer structure may be formed with a thickness in a range of about 0.1 µm to about 3 µm. The passivation layer structure may, in some examples, be formed by one or any combination of physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (or PECVD), spin-on coating, and other applicable methods.

[0049] Forming the dielectric layer structure and forming the bonding pad metal layer structure may, for example, include forming a dielectric layer on the wiring metal layer structure and on the passivation layer structure. The dielectric layer may, for example, be patterned by one or more masked etching processes in a central portion of a bonding pad region. A bonding pad metal layer may then be formed on the dielectric layer.

[0050] The method may further include, for example, forming the bonding pad metal layer structure by patterning the bonding pad metal layer. Patterning the bonding pad metal layer may include an etching process using the dielectric layer as an etch stop layer.

[0051] Furthermore, the method may include, for example, patterning the dielectric layer in a part surrounding the central part of the bonding pad region after forming the bonding pad metal layer.

[0052] The examples and features described above and below can be combined.

[0053] Functional and structural details described with respect to the examples above are intended to apply equally to the exemplary examples illustrated in the figures and described below.

[0054] Further examples of semiconductor devices are explained below in conjunction with the accompanying drawings. Functional and structural details described with respect to the above examples are intended to apply equally to the exemplary examples illustrated in the figures and described below.

[0055] Fig. 1 schematically and exemplarily shows a portion of a cross-sectional view of a semiconductor device 100.

[0056] The semiconductor device 100 includes a wiring metal layer structure 102. A dielectric layer structure is disposed directly on at least a portion of the wiring metal layer structure 102. At least a portion of a passivation layer structure 114 is disposed in a peripheral portion of the dielectric layer structure 104 between the dielectric layer structure 104 and the wiring metal layer structure 102. A bonding pad metal layer structure 106 is disposed at least partially directly on the dielectric layer structure 104. The bonding pad metal layer structure 106 includes a central portion 1181 and a peripheral portion 1182.

[0057] The passivation layer structure 114 may be formed by patterning a dielectric layer of the dielectric layer structure 104 in a part surrounding the central part 1181 of the bonding pad metal layer structure 106 after forming a metal layer of the bonding pad metal layer structure 106.

[0058] A layer thickness td of the dielectric layer structure 104 ranges from 1% to 30% or from 3% to 25% or from 5% to 20% or from 5% to 15% or from 10% to 20% of a layer thickness tw of the wiring metal layer structure 102. The wiring metal layer structure 102 and the bonding pad metal layer structure 106 are electrically connected by openings 108 in the dielectric layer structure 104.

[0059] A lateral end 110 of the dielectric layer structure 104 projects laterally beyond a lateral end 112 of the bonding pad metal layer structure 106.

[0060] Fig. 2A to 2E schematically and exemplarily show a portion of a top view of a semiconductor device for illustrating exemplary layouts of the dielectric layer structure 104.

[0061] Referring to the schematic plan views of the Fig. 2A, Fig. 2B, the dielectric layer structure 104 comprises a central part 1042, which is laterally spaced from the closed peripheral part 1041 by a separating opening 120 in the dielectric layer structure 104. While the central part 1042 of the dielectric layer structure 104 in the Fig. 2A, the central portion 1042 of the dielectric layer structure 104 in the example shown in Fig. 2B illustrates a plurality of dielectric islands 10421.

[0062] A maximum lateral extension 1 of the openings 108 in the central part 1042 of the dielectric layer structure 104 may be smaller than a sum of the layer thickness tw of the wiring metal layer structure 102 and a layer thickness of the bonding pad metal layer structure 106.

[0063] A coverage of a bottom side of the central part 1181 of the bonding pad metal layer structure 106 with the dielectric layer structure 104 may range, for example, from 25% to 90% or from 35% to 80% or from 50% to 70%.

[0064] Referring to the schematic plan views of the Fig. 2C, Fig. 2D, Fig. 2E, the central portion 1042 of the dielectric layer structure 104 is fused to the closed peripheral portion 1041 of the dielectric layer structure 104. In some examples, the openings 108 in the central portion 1042 may be formed as shown in Fig. 2C, Fig. 2D illustrates that the openings 108 may be regularly arranged. In other examples, for example, some openings 108 may differ from other openings in terms of shape and arrangement. A layout of the central part 1041 of the dielectric layer structure 104 may be chosen, for example, with respect to mechanical stability in certain areas of the bonding pad metal layer structure 106 and / or to enable a certain grain size and orientation in the bonding pad metal layer structure 106.

[0065] Fig. 3A to 3C schematically and exemplarily show a portion of a cross-sectional view of a semiconductor device 100 to illustrate example configurations of a wiring region including the wiring metal layer structure 102, the dielectric layer structure 104, and the bonding pad metal layer structure 106. The number of wire bonds 121 on the bonding pad metal layer structure 106 is two or more.

[0066] In the example of Fig. 3A, the wiring metal layer structure 102 directly adjoins a surface 122 of a semiconductor body 124. Device elements of a discrete semiconductor or an integrated circuit, e.g., doped regions, dielectrics, trenches, are formed in the semiconductor body 124.

[0067] In the example of Fig. 3B, an interlayer dielectric 126 is disposed between the interconnect metal layer structure 102 and the surface 122 of the semiconductor body 124. Contact plugs or contact lines 128 extend through the interlayer dielectric 126 to connect the interconnect metal layer structure 102 to the semiconductor body 124.

[0068] In the example of Fig. 3C, one or more interlayer dielectrics and one or more wiring levels may be arranged between the wiring metal layer structure and the surface 122 of the semiconductor body 102.

Claims

[1] Semiconductor device (100) comprising: a wiring metal layer structure (102); a dielectric layer structure (104) disposed directly on the wiring metal layer structure (102); a bonding pad metal layer structure (106) which is arranged at least partially directly on the dielectric layer structure (104), wherein a layer thickness (td) of the dielectric layer structure (104) ranges from 1% to 30% of a layer thickness (tw) of the wiring metal layer structure (102), the wiring metal layer structure (102) and the bonding pad metal layer structure (106) are electrically connected by completely filled openings (108) in the dielectric layer structure (104), and the bonding pad metal layer structure (106) or a part thereof is formed from aluminum with at least 50% mole fraction, and wherein the wiring metal layer structure (102) or a part thereof is formed from aluminum with at least 50% mole fraction. [2] Semiconductor device (100) according to the preceding claim, wherein the wiring metal layer structure (102) or the part thereof comprises a first metal compound of at least Cu and Al, or AlSiCu. [3] Semiconductor device (100) according to one of the preceding claims, wherein the bonding pad metal layer structure (106) or the part thereof comprises a second metal compound of at least Cu and Al. [4] A semiconductor device (100) according to any one of the preceding claims, wherein the wiring metal layer structure (102) or the part thereof comprises AlSiCu, and the bonding pad metal layer structure (106) or the part thereof comprises AlCu. [5] Semiconductor device (100) according to one of the preceding claims, wherein the layer thickness (td) of the dielectric layer structure (104) ranges from 50 nm to 1 µm. [6] Semiconductor device (100) according to one of the preceding claims, wherein a lateral end (110) of the dielectric layer structure (104) protrudes laterally beyond a lateral end (114) of the bonding pad metal layer structure (106). [7] A semiconductor device (100) according to any one of the preceding claims, further comprising a passivation layer structure (114) arranged in a peripheral part (116) of the dielectric layer structure (104) between the dielectric layer structure (104) and the wiring metal layer structure (102). [8] Semiconductor device (100) according to one of the preceding claims, further comprising a semiconductor body, wherein the wiring metal layer structure (102) directly adjoins a surface of the semiconductor body. [9] A semiconductor device (100) according to any one of the preceding claims, wherein the dielectric layer structure (104) comprises any one, or any combination, of an oxide layer, a silicon oxynitride layer or nitride layer, or an undoped polycrystalline silicon layer. [10] A semiconductor device (100) according to any one of the preceding claims, wherein the semiconductor device (100) is a power semiconductor device. [11] The semiconductor device (100) according to any one of the preceding claims, wherein the bonding pad metal layer structure (106) includes a central part (1181) and a peripheral part (1182), and any wire connection on the bonding pad metal layer structure (106) is located in the central part (1181). [12] The semiconductor device (100) according to the preceding claim, wherein a number of wire connections on the bonding pad metal layer structure (106) is two or more. [13] Semiconductor device (100) according to one of the two preceding claims, wherein the dielectric layer structure (104) includes a closed peripheral part (1041). [14] Semiconductor device (100) according to the preceding claim, wherein the dielectric layer structure (104) includes a central part (1042) which is laterally spaced from the closed peripheral part (1041) by a separating opening (120) in the dielectric layer structure (104). [15] Semiconductor device (100) according to one of the two preceding claims, wherein a maximum lateral extent (1) of the openings in the central part (1042) of the dielectric layer structure (104) is less than a sum of the layer thickness (tw) of the wiring metal layer structure (102) and the layer thickness of the bonding pad metal layer structure (106). [16] Semiconductor device (100) according to one of the three preceding claims, wherein a minimum lateral extension of the openings (108) in the central part (1042) of the dielectric layer structure (104) is equal to or greater than twice the layer thickness (td) of the dielectric layer structure (104). [17] The semiconductor device (100) according to any one of the three preceding claims, wherein the dielectric layer structure (104) covers 25% to 90% of a bottom surface of the bonding pad metal layer structure (106) in the central part (1181) of the bonding pad metal layer structure (106). [18] A method of manufacturing a semiconductor device (100), comprising: forming a wiring metal layer structure (102), wherein the wiring metal layer structure (102) or a part thereof is formed from aluminum with at least 50% mole fraction; forming a dielectric layer structure (104) arranged directly on the wiring metal layer structure (102); forming a bonding pad metal layer structure (106) arranged at least partially directly on the dielectric layer structure (104), wherein the bonding pad metal layer structure (106) or a part thereof is formed from aluminum with at least 50% molar fraction, and wherein a layer thickness (td) of the dielectric layer structure (104) ranges from 1% to 30% of a layer thickness (tw) of the wiring metal layer structure (102) and the wiring metal layer structure (102) and the bonding pad metal layer structure (106) are electrically connected by openings (108) in the dielectric layer structure (104). [19] Method according to the preceding claim, further comprising: forming a passivation layer structure (114) on at least a portion of the wiring metal layer structure (102) after forming the dielectric layer structure (104). [20] The method according to the preceding claim, wherein forming the dielectric layer structure (104) and forming the bonding pad metal layer structure (106) comprise: forming a dielectric layer on the wiring metal layer structure and on the passivation layer structure (114); patterning the dielectric layer in a central part of a bonding pad region; and then forming a bonding pad metal layer on the dielectric layer. [21] Method according to the preceding claim, further comprising: forming the bonding pad metal layer structure (106) by patterning the bonding pad metal layer, wherein patterning the bonding pad metal layer includes an etching process using the dielectric layer as an etch stop layer. [22] Method according to one of the two preceding claims, further comprising: structuring the dielectric layer in a part surrounding the central part of the bonding pad region after forming the bonding pad metal layer.

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