Semiconductor structures with crack-stop ring trenches to prevent the propagation of epitaxial cracks and methods for their production

Abstract

Semiconductor structure (700) comprising: a stacked semiconductor substrate (101, 200) comprising a semiconductor material disposed over a base semiconductor substrate (102), wherein the base semiconductor substrate (102) has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion different from the first coefficient of thermal expansion; wherein the stacked semiconductor substrate (101, 200) comprises one or more sidewalls defining a crack-stop annular trench (116) extending continuously in a closed path between a central region (110) of the stacked semiconductor substrate (101, 200) and an edge region (112) of the stacked semiconductor substrate (101, 200) surrounding the central region (110), wherein the central region (110) comprises a plurality of chip regions, each comprising a device region with one or more semiconductor devices and separated from one another by one or more scribe lines (310) configured to be removed during the singulation of the stacked semiconductor substrate (101, 200), wherein the crack stop annular trench (116) is defined by sidewalls of the semiconductor material and sidewalls of the base semiconductor substrate (102); wherein the edge region (112) of the stacked semiconductor substrate (101, 200) has a plurality of cracks and the central region (110) is substantially free of cracks; wherein the semiconductor structure further comprises a plurality of dielectric materials (401-408) disposed within the crack stop annular trench (116), the plurality of dielectric materials (401-408) extending continuously from within the crack stop annular trench (116) to across the stacked semiconductor substrate (101, 200); wherein the semiconductor structure comprises an upper dielectric interlayer (512) overlying the plurality of dielectric materials (401-408); and wherein the chip regions each have a sealing ring structure (312) extending in a second closed path around the device region (314) and comprising a plurality of stacked conductive layers extending through the plurality of dielectric materials (401-408) and the upper dielectric interlayer (512).

Description

BACKGROUNDModern integrated chips consist of millions or billions of semiconductor devices formed on a semiconductor substrate (e.g., silicon). Silicon-based semiconductor devices, such as transistors and photodiodes, have been standard in the semiconductor industry for four decades. However, semiconductor devices based on alternative materials are increasingly attracting attention. For example, Group III-N semiconductor devices, such as gallium nitride (GaN), have found wide use in high power applications, optoelectronic applications, high temperature applications, etc.US 2013 / 0189829 A1 discloses a device comprising a device on a substrate and a crack stopper in the substrate. A similar device is known from US 2015 / 0 371 956 A1. DE 10 2015 116 473 A1 describes a semiconductor component having a substrate, a plurality of columnar drift zones comprising a group III nitride having a first conductivity type and having a plurality of charge compensation structures. Further semiconductor structures are known from U.S. Pat. No. 2018, / 0 012 770 A1 and U.S. Pat. No. 2015 / 0 060 942 A1.BRIEF DESCRIPTION OF THE DRAWINGSThe invention is defined by independent claims 1, 8 and 15. Embodiments of the invention are provided in the dependent claims, the description and the drawings. Aspects of the present disclosure may best be understood from the following detailed description when read in conjunction with the accompanying figures. It should be appreciated that, in accordance with common practice in the industry, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion.FIGS. 1A-1B show some embodiments of a semiconductor structure having a crack stop ring trench configured to control the propagation of cracks in a stacked semiconductor substrate.FIGS. 2A-2B show some additional embodiments of a semiconductor structure having a crack-stop ring trench that suppresses the propagation of cracks in a stacked semiconductor substrate.FIGS. 3A-3B show top views of some additional embodiments of a semiconductor structure having a crack stop ring trench. FIG. 4 shows a cross-sectional view of some further embodiments of a semiconductor structure with a crack stop ring trench FIG. 5 shows a cross-sectional view of some additional embodiments of a semiconductor structure having a crack stop ring trench and a device region having a transistor device. FIG. 6 shows a cross-sectional view of some additional embodiments of a semiconductor structure having a crack stop ring trench and a device region having optoelectronic devices. FIG. 7 shows a cross-sectional view of some further embodiments of a semiconductor structure with a crack stop ring trench and a seal ring structure.FIGS. 8-26 show cross-sectional views of some embodiments of a method of manufacturing a semiconductor structure having a crack stop ring trench configured to control the propagation of cracks in a stacked semiconductor substrate. FIG. 27 shows a flow diagram of some embodiments of a method of manufacturing a semiconductor structure including a crack stop ring trench configured to control the propagation of cracks in a stacked semiconductor substrate. FIG. 28 shows a flow diagram of some additional embodiments of a method of manufacturing a semiconductor structure having a crack stop ring trench configured to mitigate the propagation of cracks in a stacked semiconductor substrate.DETAILED DESCRIPTIONThe following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements will be described below. These are of course only examples, which should not be understood as restrictive. For example, the formation of a first feature over or on a second feature in the following description may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features are not in direct contact. Moreover, in the present disclosure, reference numerals and / or letters may be repeated in the various examples. This repetition is for convenience and clarity and does not in itself establish a relationship between the various embodiments and / or configurations discussed.Further, for convenience of description, spatially relative terms such as "below," "below," "below," "over," "over," and the like may be used herein to describe the relationship of one element or feature to another element or feature as depicted in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative terms used herein may also be interpreted accordingly.Silicon-based semiconductor transistors have been widely used in the semiconductor industry for four decades. However, as the size of the semiconductor components continues to increase (e.g., shrink), it becomes more difficult to fabricate more powerful transistors on silicon substrates. As the scaling of silicon devices becomes more difficult, semiconductor devices made of alternative materials are receiving more and more attention. Gallium nitride (GaN) materials are an alternative to silicon materials. GaN devices have high charge carrier mobility and a wide band gap that enable high voltage and / or high power applications. For example, the higher charge carrier mobility allows a GaN transistor device to have a smaller physical size than a silicon transistor device at a given on-resistance and / or a given breakdown voltage.GaN-on-silicon technology (e.g., the deposition of GaN on a silicon substrate) has become an increasingly attractive option for GaN semiconductor devices. Silicon substrates are inexpensive, available in large diameters, and have well characterized electrical and thermal properties. Therefore, the formation of GaN on a silicon substrate enables the formation of the resulting stacked semiconductor substrate at relatively low cost through the use of a process compatible with the existing CMOS (complementary metal-oxide-semiconductor) silicon process machines and / or processes. However, GaN is typically grown on an underlying silicon substrate at a relatively high temperature (e.g., greater than or equal to about 500° C.). Since GaN has a greater coefficient of thermal expansion (CTE) than silicon (e.g., about 54% greater), the stacked semiconductor substrate deflects when cooled to room temperature after GaN formation. When the bending results in a curvature exceeding the mechanical strength of the stacked semiconductor substrate, cracks are formed along the outer edges of the stacked semiconductor substrate. The cracks may then propagate through the stacked semiconductor substrate during downstream manufacturing processes (e.g., thermal annealing). When the cracks reach device regions within the stacked semiconductor substrate, the cracks may negatively impact the devices within the device regions. For example, the cracks may result in yield losses, reliability issues, device operation instabilities (e.g., high temperature reverse bias (HTRB) burn-out), or the like.The present disclosure relates, in some embodiments, to a semiconductor structure having a crack stop ring trench configured to mitigate the propagation of cracks in a stacked semiconductor substrate. In some embodiments, the semiconductor structure includes a stacked semiconductor substrate having a group III-N semiconductor disposed over a silicon base semiconductor substrate (e.g., a base silicon substrate). The stacked semiconductor substrate includes a central region having a plurality of device regions and a peripheral region surrounding the central region. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench continuously extending in a closed path between the central region and the edge region. The crack stop etch stop ring is configured to prevent a plurality of cracks from propagating into the central region within the edge region, such that the central region is substantially free of cracks. By preventing the plurality of cracks from propagating into the central region, the crack stopping ring trench is capable of preventing the propagation of cracks into the device regions, and thereby improving the yield, reliability, and performance of devices within the device regions.FIGS. 1A-1B show some embodiments of a semiconductor structure 100 that includes a crack stop ring trench configured to control the propagation of cracks in a stacked semiconductor substrate.As shown in the cross-sectional view of FIG. 1A, the semiconductor structure 100 includes a stacked semiconductor substrate 101 having one or more stacked semiconductor materials 104- 108 disposed over a base semiconductor substrate 102. In some embodiments, the base semiconductor substrate 102 may include or be a first semiconductor material having a first coefficient of thermal expansion (CTE), and the one or more stacked semiconductor materials 104- 108 may include a second semiconductor material having a second CTE different from (e.g., greater than) the first CTE. In some embodiments, the first semiconductor material may also have a first lattice constant different from a second lattice constant of the second semiconductor material.In some embodiments, the one or more stacked semiconductor materials 104- 108 may include a buffer layer 104 disposed over the base semiconductor substrate 102. In some additional embodiments, the one or more stacked semiconductor materials 104- 108 may further include a barrier layer 106 disposed over the buffer layer 104 and a doped semiconductor layer 108 disposed over the barrier layer 106. In some embodiments, the base semiconductor substrate 102 may include or be a silicon base semiconductor substrate (e.g., a silicon wafer) and the buffer layer 104 may include or be a group III-nitride (III-N) semiconductor (e.g., gallium nitride (GaN)). In some additional embodiments, the barrier layer 106 may include or consist of aluminum gallium nitride (AlGaN) and the doped semiconductor layer 108 may include or consist of a doped III-N semiconductor (e.g., GaN doped with a p-type dopant (p-GaN)).The stacked semiconductor substrate 101 includes a central region 110 and a peripheral region 112 surrounding the central region 110. The central region 110 includes one or more device regions configured to include one or more semiconductor devices (e.g., transistor devices, optoelectronic devices, or the like). The edge portion 112 includes a plurality of cracks 114 defined by crack sidewalls 114 sof the stacked semiconductor substrate 101. The stacked semiconductor substrate 101 further includes one or more sidewalls 116 sdefining a crack stop ring trench 116 extending into the stacked semiconductor substrate 101 between the central region 110 and the edge region 112. In some embodiments, the crack stop ring trench 116 may extend from a top surface of the doped semiconductor layer 108 to the interior of the base semiconductor substrate 102. In some embodiments, one or more dielectric materials 118 may be disposed within the crack stop ring trench 116.As shown in the top view 120 of FIG. 1B, the crack stop ring trench 116 extends continuously in a first closed path around the central region 110. The edge region 112 extends continuously in a second closed path around the crack stop ring trench 116 and along an outermost edge (e.g., the outermost perimeter) of the stacked semiconductor substrate 101. The crack stop ring trench 116 laterally separates the plurality of cracks 114 within the edge region 112 from the central region 110. In some embodiments, the plurality of cracks 114 continuously extend from the outermost edge of the stacked semiconductor substrate 101 to the ends separated from the central region 110 by the crack stopping ring trench 116. In some embodiments, the plurality of cracks 114 may terminate at and / or within the dielectric material 118.The crack stopping ring trench 116 is configured to prevent the plurality of cracks 114 from propagating from the edge region 112 into the central region 110, such that the central region 110 is substantially free of cracks. By preventing the plurality of cracks 114 from propagating into the central region 110, the crack stop ring trench 116 prevents the plurality of cracks 114 from acting on devices (e.g., transistor devices, photonic devices, or the like) within the central region 110 and causing stray losses, high temperature reverse bias (HTRB), and / or potential reliability issues.FIG. 2A shows a cross-sectional view of some additional embodiments of a stacked semiconductor substrate 200 including a crack stop ring trench configured to control the propagation of cracks in a stacked semiconductor substrate.The stacked semiconductor substrate 101 includes a plurality of semiconductor materials disposed over a base semiconductor substrate 102. In some embodiments, the plurality of semiconductor materials may include a buffer layer 104 over the base semiconductor substrate 102, an active layer 202 (e.g., a channel layer) over the buffer layer 104, a barrier layer 106 over the active layer 202, and a doped semiconductor layer 108 over the barrier layer 106. In some additional embodiments, the plurality of semiconductor materials may include a nucleation layer 204 disposed between the buffer layer 104 and the base semiconductor substrate 102.In some embodiments, the base semiconductor substrate 102 may include or consist of silicon, the nucleation layer 204 may include or consist of aluminum nitride, the buffer layer 104 may include or consist of gallium nitride, the active layer 202 may include or consist of gallium nitride, the barrier layer 106 may include or consist of aluminum gallium nitride, and the doped semiconductor layer 108 may include or consist of p-doped gallium nitride. In some embodiments, buffer layer 104 may include a dopant species configured to improve the performance of the overlying devices (e.g., reduce leakage current within the overlying devices). In various embodiments, the buffer layer 104 may include, for example, a carbon dopant species, an iron dopant species, or the like.In some embodiments, the buffer layer 104 may have a first thickness 206. The first thickness 206 may be in a range between about 5 nm and about 10 micrometers, between about 10 nm and about 5 micrometers, or other similar values. In some embodiments, the barrier layer 106 may have a second thickness 208. The second thickness 208 may be in a range between about 1 nm and about 100 nm, between about 1 nm and about 30 nm, between about 10 nm and about 30 nm, about 20 nm, or other similar values. In some embodiments, the doped semiconductor layer 108 may have a third thickness 210. The third thickness 210 may be in a range between about 1 nm and about 100 nm, between about 50 nm and about 100 nm, between about 80 nm and about 100 nm, about 90 nm, or other similar values.The stacked semiconductor substrate 101 includes sidewalls 116 sdefining a crack stop ring trench 116 disposed between a central region 110 of the stacked semiconductor substrate 101 and a peripheral region 112 of the stacked semiconductor substrate 101. In some embodiments, the sidewalls 116 smay be angled at an acute angle 116 θwith respect to a bottom of the buffer layer 104 as measured by the buffer layer 104, such that a width 212 of the crack-stop ring trench 116 decreases as a depth of the crack-stop ring trench 116 increases. In some embodiments, the width 212 of the crack stop ring trench 116 may be in a range between about 3 microns (μm) and about 5 μm, between about 3 μm and about 4 μm, of about 3.5 μm, or other similar values. In some embodiments, the crack stop ring trench 116 may be defined by sidewalls of one or more base semiconductor substrates 102, the nucleation layer 204, the buffer layer 104, the active layer 202, the barrier layer 106, and / or the doped semiconductor layer 108. In some additional embodiments, the crack stop ring trench 116 may extend into the base semiconductor substrate 102 a non-zero distance 214. In some embodiments, the non-zero distance 214 may be in a range between about 100 nm and about 150 nm, between about 75 nm and about 200 nm, between about 50 nm and about 250 nm, or other similar values.In some embodiments, a plurality of cracks 114 a- 114 bare disposed within the edge region 112. In some embodiments, the plurality of cracks 114 a- 114 bmay include a first plurality of cracks 114 abeing filled with a dielectric material. In some embodiments, the first plurality of cracks 114 amay extend to a top surface of the doped semiconductor layer 108. In some additional embodiments, the plurality of cracks 114 a- 114 bmay further include a second plurality of cracks 114 bnot containing a solid material. In some such embodiments, the second plurality of cracks 114 bmay be filled with a gas and have an upper boundary defined by a lower surface of the stacked semiconductor substrate 101.In some embodiments, the edge region 112 may have a width 216 (e.g., a distance from an outermost edge of the stacked semiconductor substrate 101 to the crack stop ring trench 116) of between about 2 millimeters (mm) and about 5 mm, between about 3 mm and about 5 mm, between about 3 mm and about 4 mm, of about 3.5 mm, of about 3.4 mm, or other similar values. In some embodiments, the distance from a sidewall of the stacked semiconductor substrate 101 to the corresponding outer sidewall of the crack stop ring trench 116 may be adjusted or varied according to the positions of the cracks 114 on a wafer and may not be less than the distance from the sidewall of the stacked semiconductor substrate 101 to the corresponding inner terminal of the corresponding cracks 114. The crack stop ring trench 116 may separate the cracks 114 from the device regions in advance.As shown in the top view 218 of FIG. 2B, in some embodiments, the width 216 of the edge region 112 (e.g., measured along a straight line extending through a center of the stacked semiconductor substrate 101) may be between about 1% and about 3% of a diameter 220 of the stacked semiconductor substrate 101. In other embodiments, the width 216 of the edge region 112 may be between about 2% and about 5% of the diameter 220 of the stacked semiconductor substrate 101.In some embodiments, the crack stop ring trench 116 may consist of a substantially circular trench. In other embodiments, the crack stop ring trench 116 may include a substantially square shaped trench, a substantially polygonal shaped trench, or the like. In some embodiments, the plurality of cracks 114 may extend partially through a dielectric material 118 within the crack-stop ring trench 116. For example, in some embodiments, the plurality of cracks 114 may extend into the dielectric material 118 to a range between about 0% and 90% of the width (e.g., 212 of FIG. 2A ) of the crack-stop ring trench 116.In some embodiments, a first angle θ 1 may separate a first line 222 extending along a diameter of the stacked semiconductor substrate 101 and a sidewall 116 sof the stacked semiconductor substrate 101 forming the crack stop ring trench 116. In some embodiments, a second angle θ 2 may separate the first line 222 extending along the diameter of the stacked semiconductor substrate 101 from a second line 224 extending along a crack of the plurality of cracks 114 closest to the first line 222. In some embodiments, the first angle θ 1 may be greater than the second angle θ 2.FIG. 3A shows a top view of some additional embodiments of a semiconductor structure 300 with a crack stop ring trench.The semiconductor structure 300 comprises a stacked semiconductor substrate 101 having one or more semiconductor materials arranged over a base semiconductor substrate. In some embodiments, the stacked semiconductor substrate 101 may include a notch 302 disposed along an outermost periphery of the stacked semiconductor substrate 101.The stacked semiconductor substrate 101 further includes a crack stop ring trench 116 disposed between a central region 110 of the stacked semiconductor substrate 101 and a peripheral region 112 of the stacked semiconductor substrate 101. In some embodiments, one or more alignment marks 304 may be disposed within the edge region 112 of the stacked semiconductor substrate 101. The one or more alignment marks 304 are configured to align with alignment marks on a photolithography reticle to provide alignment during a lithography process (e.g., when printing an overlying processing plane, alignment marks on a reticle are aligned with the one or more alignment marks 304 to properly align the reticle). In some embodiments, the one or more alignment marks 304 may include recesses disposed within the stacked semiconductor substrate 101.In some embodiments, a plurality of wafer identification marks 306 may also be disposed within the edge region 112 of the stacked semiconductor substrate 101. The plurality of wafer identification marks 306 may include a plurality of alphanumeric characters arranged side by side as a string of characters. In some embodiments, the plurality of wafer identification marks 306 may include recesses disposed within the stacked semiconductor substrate 101.A plurality of chip regions 308 are arranged within the central region 110. The plurality of die regions 308 are separated from each other by scribe lines 310 configured to be removed during dicing of the stacked semiconductor substrate 101 into a plurality of separate dies. In some embodiments, the scribe lines 310 extend along the outer peripheries of the plurality of chip regions 308. In some embodiments, the plurality of chip regions 308 may further include a sealing ring structure 312 extending in a closed loop around a device region 314 having one or more semiconductor devices. In various embodiments, the one or more semiconductor devices may include a transistor device (e.g., a high electron mobility transistor (HEMT)), an optoelectronic or photonic device (e.g., a photodiode, a light emitting diode, etc.), or the like. In some embodiments, the crack stop ring trench 116 may extend into one or more of the plurality of die regions 308 (e.g., into one or more of the peripheral die regions). In some embodiments (not shown), the semiconductor substrate 101 may include one or more cracks 114 extending in or near a peripheral chip region of the plurality of chip regions 308. In some embodiments, the crack stop ring trench 116 may extend over the peripheral chip region to separate the one or more cracks 114 from inner chip regions of the plurality of chip regions and thus protect the inner chip regions from expansion of the one or more cracks 114. In such embodiments, the peripheral die region may include the one or more cracks and the crack stopping ring trench 116. In some embodiments, the peripheral die region may be a dummy die or a test die.FIG. 3B shows a top view of some embodiments of a die 316 that includes a portion of a crack stop ring trench.The chip 316 includes a device region 314 having one or more semiconductor devices. In some embodiments, the seal ring structure 312 surrounds the device region 314. The seal ring structure 312 is configured to mitigate stresses during dicing of the semiconductor substrate and / or ingress of contaminants into the device region 314 during dicing of the semiconductor substrate. A portion of the crack stop ring trench 116 extends to the interior of the chip 316. In some such embodiments, a portion of the crack stop ring trench 116 may extend along one or more sides of the chip 316. In some embodiments, the seal ring structure 312 may be disposed between the portion of the crack stop ring trench 116 and the device region 314.FIG. 4 shows a cross-sectional view of some additional embodiments of a semiconductor structure 400 having a crack stop ring trench separating a central region from a surrounding edge region.The semiconductor structure 400 comprises a stacked semiconductor substrate 101 having a plurality of semiconductor materials stacked on a base semiconductor substrate 102. In some embodiments, the plurality of semiconductor materials may include a buffer layer 104 disposed over the base semiconductor substrate 102, an active layer 202 over the buffer layer 104, a barrier layer 106 over the active layer 202, and a doped semiconductor layer 108 over the barrier layer 106. A crack stop ring trench 116 extends through the barrier layer 106, the active layer 202, the buffer layer 104, and into the base semiconductor substrate 102.A plurality of dielectric materials 401 are disposed over the stacked semiconductor substrate 101, within the crack stop ring trench 116, and / or within one or more of a plurality of cracks 114. In some embodiments, a first plurality of dielectric materials may be disposed within the crack stop ring trench 116 and a second plurality of dielectric materials may be disposed within the plurality of cracks 114. In some embodiments, the first plurality of dielectric materials may include more dielectric materials than the second plurality of dielectric materials (e.g., such that more dielectric materials are in the crack stop ring trench 116 than in the plurality of cracks 114).In some embodiments, the plurality of dielectric materials 401 includes a first dielectric material 402 disposed over the doped semiconductor layer 108, within the crack stopping ring trench 116, and / or within one or more of a plurality of cracks 114. The first dielectric material 402 may have outer sidewalls extending along the sidewalls 116 sof the stacked semiconductor substrate 101 and inner sidewalls defining a first recess within a top surface of the first dielectric material 402. In some embodiments, the first dielectric material 402 may be configured to passivated surface traps within the stacked semiconductor substrate 101 (e.g., along the sidewalls of the base semiconductor substrate 102, the buffer layer 104, the active layer 202, the barrier layer 106, and / or the doped semiconductor layer 108). In some embodiments, the first dielectric material 402 may include an oxide (e.g., silicon oxide).In some additional embodiments, the plurality of dielectric materials 401 may further include a second dielectric material 404 disposed on the first dielectric material 402 and within the crack stop ring trench 116. In some embodiments, the second dielectric material 404 may fill the first recess within a top surface of the first dielectric material 402. In some embodiments, the second dielectric material 404 may include a second recess within a top surface of the second dielectric material 404. The second recess may be disposed directly above the first recess. In some embodiments, the first dielectric material 402 may include an oxide (e.g., silicon dioxide).In some additional embodiments, the plurality of dielectric materials 401 may further include a third dielectric material 406 disposed over the second dielectric material 404 and a fourth dielectric material 408 disposed over the third dielectric material 406. In some embodiments, the third dielectric material 406 may have sidewalls defining a third recess located within an upper surface of the third dielectric material 406 and directly above the second recess. In some embodiments, the fourth dielectric material 408 may have sidewalls defining a fourth recess 410 located within an upper surface of the fourth dielectric material 408 and directly above the third recess. In some embodiments, the third dielectric material 406 and the fourth dielectric material 408 may each include an inter-level dielectric (ILD) layer (inter-level dielectric) layer) configured to surround one or more conductive interconnects (not shown). In some embodiments, the third dielectric material 406 and the fourth dielectric material 408 may each comprise an oxide (e.g., silicon dioxide).FIG. 5 shows a cross-sectional view of some additional embodiments of a semiconductor structure 500 including a crack stop ring trench and a device region including a transistor device.The semiconductor structure 500 includes a stacked semiconductor substrate 101 having a buffer layer 104 over the base semiconductor substrate 102, an active layer 202 over the buffer layer 104, a barrier layer 106 over the active layer 202, and a doped semiconductor layer 108 over the barrier layer 106. A crack stop ring trench 116 extends into the stacked semiconductor substrate 101 between a central region 110 and a peripheral region 112. The central region 110 includes a device region 314 having one or more semiconductor devices. A plurality of dielectric materials 401 are disposed over the stacked semiconductor substrate 101 and / or within the crack stop ring trench 116.In some embodiments, the one or more semiconductor devices may include a high electron mobility transistor (HEMT) device 502 disposed over the stacked semiconductor substrate 101. The HEMT device 502 includes a gate structure 504 laterally disposed between a source contact 506 and a drain contact 508. In some embodiments, the source contact 506 and / or the drain contact 508 may vertically extend through one or more of the plurality of dielectric materials 401 and through the doped semiconductor layer 108 to a bottom surface contacting the barrier layer 106. In some embodiments, the gate structure 504 may vertically extend through one or more of the plurality of dielectric materials 401 to a bottom surface contacting the doped semiconductor layer 108. In some embodiments, the gate structure may include a field plate region 505 extending outward from a sidewall of the gate structure 504 to over a first dielectric material 402 of the plurality of dielectric materials 401.A two-dimensional electron gas (2DEG) is inherently present at the heterojunction between the active layer 202 and the barrier layer 106. Since a 2DEG is inherently present between the active layer 202 and the barrier layer 106, the electrons can freely move along the interface. The gate structure 504 is configured to control the flow of electrons between the source contact 506 and the drain contact 508 during operation of the HEMT device 502 (e.g., to disrupt the underlying 2DEG so that the electrons cannot move freely under the gate structure). In some embodiments, the doped semiconductor layer 108 allows the gate structure 504 to prevent undesired currents from flowing between the source contact and the drain contact (i.e., the HEMT device 502 is formed in a "normally off" mode).In some embodiments, the gate structure 504 may include a first conductive material such as a metal (e.g., aluminum, titanium, copper, tungsten, tantalum, or the like) or doped polysilicon. In some embodiments, the source contact 506 and / or the drain contact 508 may comprise a second conductive material such as a metal (e.g., aluminum, titanium, copper, tungsten, tantalum, or the like).The gate structure 504, the source contact 506, and the drain contact 508 are electrically connected to one or more conductive layers 510. In some embodiments, the one or more conductive layers 510 may be disposed within an upper interlayer dielectric (ILD) 512 disposed over the plurality of dielectric materials 401. In some further embodiments, the one or more conductive layers 510 may be disposed within one or more of the plurality of dielectric materials 401. In some embodiments, the one or more conductive layers 510 may include interconnects, including conductive contacts 514, bond wires 516, and / or bond vias 518. In some additional embodiments (not shown), the one or more conductive layer(s) 510 may also include redistribution layers, conductive layers within an interposer substrate, conductive traces on a circuit board, or the like. In various embodiments, the one or more conductive layers 510 may include copper, tungsten, ruthenium, aluminum, carbon nanotubes, or the like. In some embodiments, the upper ILD layer 512 may include one or more of the following materials: silicon dioxide, silicon nitride, carbon doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), a porous dielectric material, or the like.FIG. 6 shows a cross-sectional view of some additional embodiments of a semiconductor structure 600 having a crack stop ring trench and a photonic device device region.The semiconductor structure 600 includes a stacked semiconductor substrate 101 including a buffer layer 104 over a base semiconductor substrate 102, a first doped semiconductor layer 602 over the buffer layer 104, a multiple quantum well structure (MQW) 604 (e.g., indium gallium nitride InGaN) over the first doped semiconductor layer 602, and a second doped semiconductor layer 606 over the MQW structure 604. The first doped semiconductor layer 602 may have a first doping type (e.g., an n-doping) different from a second doping type (e.g., a p-doping) of the second doped semiconductor layer 606. In some embodiments, the first doped semiconductor layer 602 and the second doped semiconductor layer 606 may comprise the same semiconductor material (e.g., GaN).A crack stop ring trench 116 extends into the stacked semiconductor substrate 101 between a central region 110 and a peripheral region 112. The central region 110 includes a device region 314 having one or more semiconductor devices. A plurality of dielectric materials 401 are disposed over the stacked semiconductor substrate 101 and / or within the crack stop ring trench 116.In some embodiments, the one or more semiconductor devices may include optoelectronic or photonic devices. In some embodiments, the one or more semiconductor devices may include, for example, a photodiode 608. In such embodiments, photodiode 608 may include a stack including first doped semiconductor layer 602, MQW structure 604, and second doped semiconductor layer 606. A first conductive contact 610 is disposed on the second doped semiconductor layer 606 and a second conductive contact 612 is disposed on the first doped semiconductor layer 602. In some embodiments, an ohmic contact layer 614 a(e.g., indium tin oxide (ITO)) may be disposed between the second doped semiconductor layer 606 and the first conductive contact 610. In other embodiments, the first conductive contact 610 may directly contact the second doped semiconductor layer 606.In other embodiments, the one or more semiconductor devices may include a light emitting diode (LED) 616. In such embodiments, the LED 616 may include a stack including the first doped semiconductor layer 602, the MQW structure 604, and the second doped semiconductor layer 606. A third conductive contact 618 is disposed on the second doped semiconductor layer 606 and a fourth conductive contact 620 is disposed on the first doped semiconductor layer 602. In some embodiments, an ohmic contact layer 614 b(e.g., indium tin oxide (ITO)) may be disposed between the second doped semiconductor layer 606 and the third conductive contact 618. In other embodiments, the third conductive contact 618 may directly contact the second doped semiconductor layer 606.FIG. 7 shows a cross-sectional view of some additional embodiments of a semiconductor structure 700 having a crack stop ring trench surrounding a central region with one or more semiconductor devices.The semiconductor structure 700 includes a stacked semiconductor substrate 101 having a buffer layer 104 over the base semiconductor substrate 102, an active layer 202 over the buffer layer 104, a barrier layer 106 over the active layer 202, and a doped semiconductor layer 108 over the barrier layer 106. A crack stop ring trench 116 extends into the stacked semiconductor substrate 101 between a central region 110 and a peripheral region 112 of the stacked semiconductor substrate 101. The central region 110 includes a device region 314 having one or more semiconductor devices and a seal ring structure 312 disposed between the device region 314 and the crack stop ring trench 116. A plurality of dielectric materials 401 are disposed over the stacked semiconductor substrate 101 and / or within the crack stop ring trench 116.The seal ring structure 312 is configured to mitigate dicing stress and / or the ingress of contaminants into the device region 314 of the stacked semiconductor substrate during dicing. In some embodiments, the seal ring structure 312 may include a plurality of stacked conductive layers (e.g., interconnect layers) disposed within the plurality of dielectric materials 401, and an upper ILD layer 512 overlying the plurality of dielectric materials 401. In some embodiments, the seal ring structure 312 may include conductive contacts 704, bond wires 706, and / or bond holes 708 stacked one above the other and arranged in a continuous and uninterrupted conductive structure surrounding the device region 314 (e.g., as shown in the top view of FIG. 3B ).FIGS. 8-26 show cross-sectional views 800-2600 of some embodiments of a method of manufacturing a semiconductor structure including a crack stopping ring trench configured to control the propagation of cracks in a stacked semiconductor substrate. Although FIGS. 8-26 are described with respect to a method, the structures shown in FIGS. 8-26 are not limited to such a method, but may be structures independent of the method alone.As shown in cross-sectional view 800 of FIG. 8, a base semiconductor substrate 102 is present. In various embodiments, the base semiconductor substrate 102 may be a silicon substrate, a silicon wafer, or the like. In some embodiments, the base semiconductor substrate 102 may include or be a first semiconductor material having a first coefficient of thermal expansion (CTE). In some additional embodiments, the first semiconductor material may have a first lattice constant.As shown in cross-sectional view 900 of FIG. 9, a buffer layer 104 is formed on the base semiconductor substrate 102. The buffer layer 104 may be formed on the base semiconductor substrate 102 at a first temperature higher than room temperature. In some embodiments, the first temperature may be greater than about 500° C., greater than about 800° C., greater than about 1000° C., or other similar values. In some embodiments, a nucleation layer may be formed on the base semiconductor substrate 102 prior to forming the buffer layer 104.The buffer layer 104 comprises or is a second semiconductor material. In various embodiments, the second semiconductor material may comprise or be a group III-nitride (III-N) semiconductor, such as a gallium nitride layer. The buffer layer 104 rmay be formed with a thickness in the range between about 5 nanometers and about 10 micrometers. In some embodiments, the second semiconductor material may include a second CTE different (e.g., larger) from the first CTE. In some additional embodiments, the second semiconductor material may have a second lattice constant that is different (e.g., greater) from the first lattice constant. In some embodiments, there may be a lattice mismatch between the first lattice constant and the second lattice constant of greater than about 14%, resulting in loading of the buffer layer 104. In some embodiments, the buffer layer 104 may be formed on the base semiconductor substrate 102 by deposition processes (e.g., chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PE-CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), molecular organic chemical vapor deposition (MOCVD), etc.), molecular beam epitaxy (MOCVD), or vapor deposition.), molecular beam epitaxy (MBE), or the like.As shown in cross-sectional view 1000 of FIG. 10, in some embodiments, an active layer 202 may be formed on buffer layer 104. In various embodiments, the active layer 202 may comprise a III-N semiconductor material, such as a gallium nitride layer. In some embodiments, the active layer 202 may be formed on the buffer layer 104 by deposition methods (e.g., CVD, PE-CVD, ALD, PVD, MOCVD methods, etc.), an MBE method, or the like. In some embodiments, the active layer 202 may be formed at or above room temperature (e.g., at greater than about 500° C., greater than about 800° C., greater than about 1000° C., or other similar values).As shown in cross-sectional view 1100 of FIG. 11, a barrier layer 106 is formed over the active layer 202. The barrier layer 106 may include aluminum gallium nitride. In various embodiments, the barrier layer 106 may be formed by a MOCVD method, an MBE method, or the like. In some embodiments, the barrier layer 106 may be formed at or above room temperature (e.g., at greater than about 500° C., greater than about 800° C., greater than about 1000° C., or other similar values).As shown in cross-sectional view 1200, a doped semiconductor layer 108 may be formed over the barrier layer 106 to form a stacked semiconductor substrate 101. The doped semiconductor layer 108 may include a p-doped gallium nitride (p-GaN) layer. In some embodiments, the doped semiconductor layer 108 may be formed by a MOCVD method, an MBE method, or the like. In some embodiments, the doped semiconductor layer 108 may be formed at or above room temperature (e.g., at greater than about 500° C., greater than about 800° C., greater than about 1000° C., or other similar values).As shown in the cross-sectional view 1300, the stacked semiconductor substrate 101 is cooled to a second temperature lower than the first temperature. In some embodiments, the second temperature may be less than or equal to about 20° C., less than or equal to about 30° C., less than or equal to about 50° C., or other similar values. Since the buffer layer 104 has a different (e.g., greater) coefficient of thermal expansion (CTE) than the base semiconductor substrate 102, the stacked semiconductor substrate 101 will buckle or curve upon cooling to the second temperature. In some embodiments, the warping of the stacked semiconductor substrate 101 may result in an outermost edge of the stacked semiconductor substrate 101 being at a height vertically offset from the center of the stacked semiconductor substrate 101 by a non-zero distance 1302.As shown in cross-sectional view 1400 of FIG. 14, after cooling to the second temperature, the stacked semiconductor substrate 101 again assumes a substantially flat structure. However, when the curvature of the stacked semiconductor substrate 101 exceeds the mechanical strength of the material as shown in the cross-sectional view 1300 of FIG. 13, a plurality of cracks 114 are formed in the stacked semiconductor substrate 101. The plurality of cracks 114 may be formed in an edge region 112 of the stacked semiconductor substrate 101. As shown in the top view 1402 of FIG. 14, the edge portion 112 of the stacked semiconductor substrate 101 surrounds a central portion 110 of the stacked semiconductor substrate 101. In some embodiments, the stress caused by the lattice mismatch between the base semiconductor substrate 102 and the buffer layer 104 in conjunction with the thermal stress caused by the different CTEs may also contribute to the formation of the plurality of cracks 114.As shown in the cross-sectional view 1500 and the plan view 1502 of FIG. 15, a crack stop ring trench 116 is formed in the stacked semiconductor substrate 101. The crack stop ring trench 116 extends in a continuous and closed loop around the stacked semiconductor substrate 101. The crack stop ring trench 116 separates the edge region 112 of the stacked semiconductor substrate 101 from the central region 110 of the stacked semiconductor substrate 101. In some embodiments, the central region 110 of the stacked semiconductor substrate 101 may include a plurality of chip regions 308 configured to subsequently include one or more semiconductor devices.In some embodiments, the crack stop ring trench 116 may extend vertically from a top surface of the doped semiconductor layer 108 to the interior of the base semiconductor substrate 102. In some embodiments, the crack stop ring trench 116 may be formed by an etching process. In such embodiments, the stacked semiconductor substrate 101 may be selectively exposed to one or more etchants corresponding to a masking layer formed over the stacked semiconductor substrate 101. In some embodiments, the one or more etchants may comprise a dry etch (e.g., a reactive ion etchant, an inductively coupled reactive ion etchant). In various embodiments, the masking layer may include a dielectric material (e.g., silicon dioxide, silicon nitride, or the like), a photosensitive material (e.g., photoresist), or the like. In other embodiments, the crack stop ring trench 116 may be formed by a laser drilling process or other similar processes.As shown in cross-sectional view 1600 and top view 1602 of FIG. 16, one or more alignment marks 304 may be formed within the edge region 112 of the stacked semiconductor substrate 101. The one or more alignment marks 304 are configured to align with alignment marks on a photolithographic reticle to enable alignment during a lithographic process. In some embodiments, the one or more alignment marks 304 may be formed by an etching process that forms recesses within a top surface of the stacked semiconductor substrate 101.In some additional embodiments, a plurality of wafer identification marks 306 may also be formed within the edge region 112 of the stacked semiconductor substrate 101. The plurality of wafer identifying characters 306 may include a plurality of alphanumeric characters arranged side by side as a string of characters. In some embodiments, the plurality of wafer identification marks 306 may be formed by an etching process that forms recesses disposed within the stacked semiconductor substrate 101.As shown in cross-sectional view 1700 of FIG. 17, a first dielectric material 402 is formed over the stacked semiconductor substrate 101 and along the sidewalls of the stacked semiconductor substrate 101 defining the crack stop ring trench 116. In some embodiments, the first dielectric material 402 lines the sidewalls of the stacked semiconductor substrate 101 defining the crack stop ring trench 116, and has inner sidewalls defining a first recess within a top surface of the first dielectric material 402. In some additional embodiments, the first dielectric material 402 may fill one or more of the plurality of cracks 114. In some embodiments, the first dielectric material 402 may include an oxide (e.g., silicon dioxide). In some embodiments, the first dielectric material 402 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, PVD, etc.). In some embodiments, the first dielectric material 402 may be configured to passivated surface defects (e.g., surface traps) that result in the formation of the crack stop ring trench 116. Passivation of the surface defects may reduce leakage current within the devices subsequently formed in the stacked semiconductor substrate 101.As shown in cross-sectional view 1800 of FIG. 18, a first patterning process is performed to pattern the first dielectric material 402. In the first patterning process, portions of the first dielectric material 402 are removed to form source / drain openings 1702 exposing a top surface of the barrier layer 106 in a device region 314 in the central region 110 of the stacked semiconductor substrate 101.In some embodiments, the first patterning process may selectively expose the first dielectric material 402 to a first etchant 1802 according to a first masking pattern 1804 formed over the barrier layer 106. In some embodiments, the first masking structure 1804 may include a photosensitive material (e.g., a photoresist). In other embodiments, the first masking structure 1804 may include a dielectric masking layer (e.g., silicon oxide, silicon dioxide, or the like), a hard mask, and / or the like. In some embodiments, the first etchant 1802 may include a dry etchant (e.g., having a fluorochemistry, a chlorochemistry, or the like). In other embodiments, the first etchant 1802 may be a wet etchant (e.g., with hydrofluoric acid, potassium hydroxide, or the like).As shown in cross-sectional view 1900 of FIG. 19, a source contact 506 and a drain contact 508 are formed within the source / drain openings 1702. In some embodiments, the source contact 506 and the drain contact 508 may be formed by forming a conductive material (e.g., aluminum, copper, or the like) within the source / drain openings 1702 and over the first dielectric material 402. The conductive material is then etched to define the source contact 506 and the drain contact 508. In some embodiments, the conductive material may be formed by a deposition process and / or a plating process.As shown in cross-sectional view 2000 of FIG. 20, a second dielectric material 404 is formed over a top surface of the first dielectric material 402 and along the inner sidewalls of the first dielectric material 402. In some embodiments, the second dielectric material 404 has a top surface that is directly above the crack stop ring trench 116 and lies vertically above the top surface of the stacked semiconductor substrate 101. In some additional embodiments, the second dielectric material 404 may include one or more sidewalls defining a second recess 2002 located directly above the crack stop ring trench 116. In some embodiments, the second dielectric material 404 may comprise a nitride (e.g., silicon nitride). In some embodiments, the second dielectric material 404 may be formed by a deposition process (e.g., CVD, PE-CVD, ALD, PVD, etc.),As shown in cross-sectional view 2100 of FIG. 21, a second patterning process is performed to pattern the first dielectric material 402 and the second dielectric material 404 to form a gate opening 2102 exposing a top surface of the doped semiconductor layer 108 within the device region 314. In some embodiments, the second patterning process may selectively expose the first dielectric material 402 and the second dielectric material 404 to a second etchant 2104 corresponding to a second masking pattern 2106 formed over the second dielectric material 404. In various embodiments, the second masking structure 2106 may include a photosensitive material (e.g., a photoresist), a dielectric masking layer (e.g., silicon oxide, silicon dioxide, or the like), a hard mask, and / or the like. In various embodiments, the second etchant 2104 may be a dry etchant or a wet etchant.As shown in cross-sectional view 2200 of FIG. 22, a gate structure 504 is formed within the gate opening 2102. In some embodiments, the gate structure 504 may be formed by forming a conductive material (e.g., aluminum, copper, doped polysilicon, or the like) within the gate opening 2102 and over the second dielectric material 404. The conductive material is then etched to define the gate structure 504. In some embodiments, the conductive material may be formed by a deposition process and / or a plating process.As shown in cross-sectional view 2300 of FIG. 23, a third dielectric material 406 is formed over a top surface of the second dielectric material 404. In some embodiments, the third dielectric material 406 may include one or more sidewalls defining a third recess 2302 that is directly above the crack stop ring trench 116. In some embodiments, the third dielectric material 406 may comprise an oxide (e.g., silicon dioxide).As shown in cross-sectional view 2400 of FIG. 24, a fourth dielectric material 408 is formed over a top surface of the third dielectric material 406. In some embodiments, the fourth dielectric material 408 may include one or more sidewalls defining a fourth recess 2402 that is directly above the crack stop ring trench 116. In some embodiments, the fourth dielectric material 408 may comprise an oxide (e.g., silicon dioxide).As shown in cross-sectional view 2500 of FIG. 25, an upper interlayer dielectric (ILD) 512 is formed over an upper surface of the fourth dielectric material 408. In some embodiments, the upper ILD layer 512 may include one or more of the following materials: silicon dioxide, silicon nitride, carbon doped silicon dioxide, silicon oxynitride, borosilicate glass (BSG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), undoped silicate glass (USG), a porous dielectric material, or the like.As shown in cross-sectional view 2600 of FIG. 26, a plurality of conductive layers 510 are formed within the plurality of dielectric materials 402- 408 and / or the upper ILD layer 512. In some embodiments, the plurality of conductive layers 510 may include interconnects formed by a damascene process and / or a dual damascene process. In some such embodiments, the upper ILD layer 512 is etched to form holes and / or trenches, which are subsequently filled with a conductive material (e.g., tungsten, copper, and / or aluminum). A chemical mechanical planarization (CMP) process is then performed to remove excess conductive material from the upper ILD layer 512.FIG. 27 shows a flow diagram of some embodiments of a method 2700 of manufacturing a semiconductor structure comprising a crack stop ring trench configured to control the propagation of cracks in a stacked semiconductor substrate.Although the disclosed methods (e.g., methods 2700 and 2800) are illustrated and described herein as a series of acts or events, the illustrated order of such acts or events is not to be understood in a limiting sense. For example, some acts may occur in a different order and / or concurrently with other acts or events than those illustrated and / or described herein. Moreover, not all illustrated acts may be required to implement one or more aspects or embodiments of the description contained herein. Further, one or more of the acts depicted herein may be performed in one or more separate acts and / or phases.At operation 2702, a base semiconductor substrate of a first semiconductor material having a first coefficient of thermal expansion (CTE) is provided. In some embodiments, the first semiconductor material may be silicon. FIG. 8 shows a cross-sectional view 800 of some embodiments corresponding to operation 2702.In operation 2704, a second semiconductor material having a second CTE different from the first CTE is formed at a first temperature on the base semiconductor substrate. In some embodiments, the second semiconductor material may be a group III-nitride (III-N) semiconductor material. FIG. 9 shows a cross-sectional view 900 of some embodiments corresponding to operation 2704.At operation 2706, the base semiconductor substrate and the second semiconductor material are cooled to a second temperature that is lower than the first temperature. FIGS. 13-14 show cross-sectional views 1300-1400 of some embodiments corresponding to operation 2706.At operation 2708, the base semiconductor substrate and the second semiconductor material are patterned to form a crack stop ring trench that extends in a closed loop and separates a central portion of the second semiconductor material from a peripheral portion of the second semiconductor material. FIG. 15 shows a cross-sectional view 1500 of some embodiments corresponding to operation 2708.FIG. 28 shows a flow diagram of some additional embodiments of a method 2800 of manufacturing a semiconductor structure having a crack stop ring trench configured to mitigate the propagation of cracks in a stacked semiconductor substrate.In operation 2802, a stacked semiconductor substrate having a central region surrounded by a peripheral region is formed at a first temperature. In some embodiments, the stacked semiconductor substrate may be formed according to steps 2804-2810.At operation 2804, a buffer layer is formed on a base semiconductor substrate. FIG. 9 shows a cross-sectional view 900 of some embodiments corresponding to operation 2804.At operation 2806, an active layer is formed on the buffer layer. FIG. 10 shows a cross-sectional view 1000 of some embodiments corresponding to operation 2806.At operation 2808, a barrier layer is formed on the active layer. FIG. 11 shows a cross-sectional view 1100 of some embodiments corresponding to operation 2808.At operation 2810, a doped semiconductor layer is formed on the barrier layer. FIG. 12 shows a cross-sectional view 1200 of some embodiments corresponding to operation 2810.At operation 2812, the stacked semiconductor substrate is cooled to a second temperature that is lower than the first temperature. FIGS. 13-14 show cross-sectional views 1300-1400 corresponding to operation 2812.At operation 2814, the stacked semiconductor substrate is patterned to form a crack stop ring trench extending in a closed loop around the central region. FIG. 15 shows a cross-sectional view 1500 of some embodiments corresponding to step 2814.In operation 2816, an alignment mark is formed on the stacked semiconductor substrate. FIG. 16 shows a cross-sectional view 1600 of some embodiments corresponding to operation 2816.At operation 2818, one or more dielectric materials are formed on the stacked semiconductor substrate and within the crack stop ring trench. FIGS. 17, 20 and 23-25 show cross-sectional views 1700, 2000, 2300-2500 of some embodiments corresponding to operation 2818.At operation 2820, a semiconductor device is formed on the stacked semiconductor substrate. FIGS. 18-22 show cross-sectional views 1800-2200 of some embodiments corresponding to step 2820.At operation 2822, one or more interconnects are formed over the stacked semiconductor substrate. FIGS. 23-27 show cross-sectional views 2300- 2700 of some embodiments corresponding to operation 2822.At operation 2824, a seal ring structure is formed over the stacked semiconductor substrate. FIGS. 23-27 show cross-sectional views 2300- 2700 of some embodiments corresponding to operation 2824.Accordingly, in some embodiments, the present disclosure relates to a semiconductor structure including a stacked semiconductor substrate having a crack stop ring trench configured to mitigate propagation of cracks within a stacked semiconductor substrate. The crack stop ring trench is configured to prevent a plurality of cracks from propagating from an edge region of the stacked semiconductor substrate to device regions in a central region of the stacked semiconductor substrate, thereby improving the yield, reliability, and / or performance of devices in the device regions.In some embodiments, the present disclosure relates to a semiconductor structure comprising a stacked semiconductor substrate including a semiconductor material disposed over a base semiconductor substrate, the base semiconductor substrate having a first coefficient of thermal expansion and the semiconductor material having a second coefficient of thermal expansion different from the first coefficient of thermal expansion; the stacked semiconductor substrate including one or more sidewalls defining a crack-stop ring trench continuously extending in a closed path between a central region of the stacked semiconductor substrate and an edge region of the stacked semiconductor substrate surrounding the central region; and the edge region of the stacked semiconductor substrate including a plurality of cracks, and the central region being substantially free of cracks. In some embodiments, the central region includes a plurality of device regions each having one or more semiconductor devices. In some embodiments, the plurality of cracks each and continuously extend from an outermost edge of the stacked semiconductor substrate to an end separated from the central region by the crack stopping ring trench. In some embodiments, the crack stop ring trench comprises a substantially circular trench. In some embodiments, the base semiconductor substrate includes a silicon wafer and the semiconductor material includes a gallium nitride buffer layer. In some embodiments, the stacked semiconductor substrate further includes a barrier layer including aluminum gallium nitride disposed over the gallium nitride buffer layer. In some embodiments, the crack stop ring trench is defined by sidewalls of the semiconductor material and sidewalls of the base semiconductor substrate. In some embodiments, the semiconductor structure further comprises one or more dielectric materials disposed within the crack-stop ring trench, wherein the one or more dielectric materials extend continuously from the interior of the crack-stop ring trench to above the stacked semiconductor substrate. In some embodiments, the central region includes a plurality of chip regions separated from each other by one or more scribe lines configured to be removed during dicing of the stacked semiconductor substrate.In other embodiments, the present disclosure relates to a semiconductor structure including a stacked semiconductor substrate including a buffer layer including a first semiconductor material disposed over a base semiconductor substrate including a second semiconductor material, the stacked semiconductor substrate including a central region including a plurality of chip regions and an edge region surrounding the central region; a semiconductor device is disposed over the stacked semiconductor substrate and within a device region of one of the plurality of chip regions; a first plurality of dielectric materials is disposed within a crack stop ring trench defined by sidewalls of the stacked semiconductor substrate, wherein a first angle separates a first line extending along a diameter of the stacked semiconductor substrate and one of the sidewalls of the stacked semiconductor substrate; the stacked semiconductor substrate has crack sidewalls defining a plurality of cracks between an outermost edge of the stacked semiconductor substrate and the crack stopping ring trench, the first line being separated from a second line extending along a closest one of the plurality of cracks by a second angle less than the first angle; and a second plurality of dielectric materials being disposed within the plurality of cracks, the first plurality of dielectric materials comprising more dielectric materials than the second plurality of dielectric materials. In some embodiments, the second plurality of dielectric materials comprises an oxide. In some embodiments, the plurality of die regions each include a sealing ring structure extending around the device region in a second closed path. In some embodiments, the crack stop ring trench has a width ranging from about 3 microns to about 4 microns. In some embodiments, the edge portion extends continuously along a straight line having a width ranging from about 1% to about 3% of the diameter of the stacked semiconductor substrate. In some embodiments, one or more of the first plurality of dielectric materials extends into the base semiconductor substrate. In some embodiments, the base semiconductor substrate is a silicon and the buffer layer is gallium nitride. In some embodiments, the crack stop ring trench extends into one or more of the plurality of chip regions.In still other embodiments, the present disclosure relates to a method of forming a semiconductor structure, comprising forming a group III-nitride (III-N) semiconductor material over a base silicon substrate at a first temperature; cooling the III-N semiconductor material and the base silicon substrate to a second temperature lower than the first temperature; cooling the III-N semiconductor material and the base silicon substrate causing a plurality of cracks to be formed in an edge region of the III-N semiconductor material, wherein the peripheral region of the III-N semiconductor material surrounds a central region of the III-N semiconductor material and etching the III-N semiconductor material and the base silicon substrate to form a crack-stop ring trench extending around the central region of the III-N semiconductor material, wherein the crack-stop ring trench separates the central region of the III-N semiconductor material from the peripheral region of the III-N semiconductor material. In some embodiments, the central region is substantially free of cracks within the III-N semiconductor material. In some embodiments, the plurality of cracks continuously extend from an outermost edge of the III-N semiconductor material to the crack stopping ring trench.

Claims

A semiconductor structure (700) comprising: a stacked semiconductor substrate (101, 200) comprising a semiconductor material disposed over a base semiconductor substrate (102), wherein the base semiconductor substrate (102) has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion different from the first coefficient of thermal expansion; wherein the stacked semiconductor substrate (101, 200) comprises one or more side walls defining a crack stop ring trench (116) extending continuously in a closed path between a central region (110) of the stacked semiconductor substrate (101, 200) and an edge region (112) of the stacked semiconductor substrate (101, 200) surrounding the central region (110), wherein the central region (110) comprises a plurality of chip regions each comprising a device region having one or more semiconductor devices and separated from each other by one or more scribe lines (310) configured to be removed during dicing of the stacked semiconductor substrate (101, 200), wherein the crack stop ring trench (116) is defined by side walls of the semiconductor material and side walls of the base semiconductor substrate (102); wherein the edge portion (112) of the stacked semiconductor substrate (101, 200) has a plurality of cracks and the central portion (110) is substantially free of cracks; wherein the semiconductor structure further comprises a plurality of dielectric materials (401-408) disposed within the crack-stop ring trench (116), wherein the plurality of dielectric materials (401-408) extend continuously from within the crack-stop ring trench (116) to over the stacked semiconductor substrate (101, 200); wherein the semiconductor structure comprises an upper interlayer dielectric layer (512) overlying the plurality of dielectric materials (401-408); and wherein the chip regions each have a sealing ring structure (312) extending in a second closed path around the device region (314) and comprising a plurality of stacked conductive layers extending through the plurality of dielectric materials (401-408) and the upper interlayer dielectric layer (512).The semiconductor structure (700) of claim 1, wherein the stacked semiconductor substrate (101, 200) comprises a plurality of semiconductor materials, the plurality of semiconductor materials comprising a buffer layer (104) disposed over the base semiconductor substrate (102), an active layer (202) over the buffer layer (104), a barrier layer (106) over the active layer (202), and a doped semiconductor layer (108) over the barrier layer (106), wherein the crack stop ring trench (116) extends through the barrier layer (106), the active layer (202), the buffer layer (104), and into the base semiconductor substrate (102).The semiconductor structure (700) of claim 1 or 2, wherein the plurality of cracks each extend continuously from an outermost edge of the stacked semiconductor substrate to an end separated from the central region by the crack stopping ring trench.The semiconductor structure (700) of any of the preceding claims, wherein the crack stop ring trench (116) comprises a substantially circular trench.The semiconductor structure (700) of any of the preceding claims, wherein the base semiconductor substrate comprises a silicon wafer and the semiconductor material comprises a gallium nitride buffer layer.The semiconductor structure (700) of claim 5, wherein the stacked semiconductor substrate (101, 200) further comprises a barrier layer (106) of aluminum gallium nitride disposed over the gallium nitride buffer layer.The semiconductor structure (700) of any of the preceding claims, wherein the plurality of cracks comprises a first plurality of cracks filled with a dielectric material.A semiconductor structure (700) comprising: a stacked semiconductor substrate (101, 200) having a buffer layer (104) comprising a first semiconductor material disposed over a base semiconductor substrate (102) comprising a second semiconductor material, the stacked semiconductor substrate (101, 200) comprising a central region (110) having a plurality of chip regions (308) and an edge region (112) surrounding the central region (110), the chip regions (308) being separated from each other by one or more scribe lines (310) configured to be removed during singulation of the stacked semiconductor substrate (101, 200); a semiconductor device disposed over the stacked semiconductor substrate (101, 200) and within a device region (314) of one of the plurality of chip regions (308); a first plurality of dielectric materials (401-408) arranged within a crack-stop ring trench (116) defined by sidewalls of the stacked semiconductor substrate (101, 200) and extending continuously in a closed path between the central region (110) of the stacked semiconductor substrate (101, 200) and the edge region (112) of the stacked semiconductor substrate (101, 200) surrounding the central region (110), the crack-stop ring trench (116) being defined by sidewalls of the first semiconductor material and sidewalls of the base semiconductor substrate (102); wherein the stacked semiconductor substrate has crack sidewalls (114s) defining a plurality of cracks (114) between an outermost edge of the stacked semiconductor substrate (101, 200) and the crack-stop ring trench (116); wherein a first dielectric material (402) is disposed within the plurality of cracks; wherein the semiconductor structure comprises an upper interlayer dielectric layer (512) overlying the first plurality of dielectric materials (401-408); and wherein the chip regions each have a sealing ring structure (312) extending in a second closed path around the device region (314) and comprising a plurality of stacked conductive layers extending through the first plurality of dielectric materials (401-408) and the upper interlayer dielectric layer (512).The semiconductor structure (700) of claim 8, wherein the first dielectric material (401-408) comprises an oxide.The semiconductor structure (700) of claim 8 or 9, wherein the crack stop ring trench (116) has a width (212, 216) ranging between about 3 microns and about 4 microns.The semiconductor structure (700) of any of claims 8 to 10, wherein the edge portion (112) extends continuously along a straight line over a width (212, 216), which is in a range between about 1% and about 3% of the diameter of the stacked semiconductor substrate (101, 200).The semiconductor structure (700) of any of claims 8 to 11, wherein one or more dielectric materials (401-408) of the first plurality of dielectric materials (401-408) extend into the base semiconductor substrate (102).The semiconductor structure (700) of any of claims 8 to 12, wherein the base semiconductor substrate (102) is a silicon base semiconductor substrate and the buffer layer (104) is gallium nitride.The semiconductor structure (700) of any of claims 8 to 13, wherein the crack stop ring trench (116) extends into one or more chip regions of the plurality of chip regions.A method of manufacturing a semiconductor structure (700), comprising: forming a stacked semiconductor substrate (101, 200) by forming a group III-nitride (III-N) semiconductor material over a silicon-based semiconductor substrate at a first temperature; cooling the III-N semiconductor material and the silicon-based semiconductor substrate to a second temperature that is lower than the first temperature, wherein cooling the III-N semiconductor material and the silicon-based semiconductor substrate causes formation of a plurality of cracks in an edge region (112) of the III-N semiconductor material, wherein the edge region (112) of the III-N semiconductor material surrounds a central region (110) of the III-N semiconductor material, wherein the central region (110) comprises a plurality of chip regions (308) each comprising a device region (314) having one or more semiconductor devices and separated from each other by one or more scribe lines (310) configured to be removed during dicing of the stacked semiconductor substrate (101, 200); etching the III-N semiconductor material and the silicon base semiconductor substrate to form a crack-stop ring trench (116) extending around the central region (110) of the III-N semiconductor material, the crack-stop ring trench (116) separating the central region (110) of the III-N semiconductor material from the edge region (112) of the III-N semiconductor material, the crack-stop ring trench (116) being defined by sidewalls of the semiconductor material and sidewalls of the silicon base semiconductor substrate (102); forming a plurality of dielectric materials (401-408) within the crack-stop ring trench (116) and over the III-N semiconductor material; forming an upper interlayer dielectric layer (512) overlying the plurality of dielectric materials (401-408); and forming seal ring structures (312) in the chip regions each extending in a second closed path around the device region (314) and including a plurality of stacked conductive layers extending through the plurality of dielectric materials (401-408) and the upper interlayer dielectric layer (512).The method of claim 15, wherein the central region (110) is substantially free of cracks within the III-N semiconductor material.The method of claim 15 or 16, wherein the plurality of cracks extend continuously from an outermost edge of the III-N semiconductor material to the crack stop ring trench (116).

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