DIELECTRIC LAYER ON SEMICONDUCTOR DEVICE AND METHOD FOR FORMING THE SAME

Abstract

A method for forming a semiconductor device, the method comprising: Forming a semiconductor fin (60) and an isolation region (70) adjacent to the semiconductor fin (60); Forming a first layer on the semiconductor fin (60); Forming a mask (94) on the first layer, wherein the mask (94) is thicker on a top side of the semiconductor fin (60) than along a side wall of the semiconductor fin (60); Thinning of the first layer along the side wall of the semiconductor fin (60) using the mask (94), wherein the thinning of the first layer removes sections of the mask (94); Forming a second layer on the semiconductor fin (60), wherein the second layer covers the remaining sections of the mask (94) and the remaining sections of the first layer; Forming a dummy gate layer on the semiconductor fin (60); and Structuring the dummy gate layer, wherein structuring the dummy gate layer exposes an upper surface of the semiconductor fin (60).

Description

BACKGROUND

[0001] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] US 2021 / 0098458 A1 relates to a deposition method, a semiconductor device, and a method for producing the same. DE 10 2020 114 865 A1 relates to a non-conformal capping layer and a method for producing the same.

[0003] The semiconductor industry is continuously improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood by reference to the following detailed description when taken in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not drawn to scale. Indeed, the dimensions of various features may be arbitrarily exaggerated or reduced for clarity of illustration.

[0005] Fig. 1 illustrates, in a three-dimensional view, an example of a FinFET according to some embodiments.

[0006] Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9, Fig. 10, Fig. 11A, Fig. 11B, Fig. 12A, Fig. 12B, Fig. 13A, Fig. 13B, Fig. 14A, Fig. 14B, Fig. 15A, Fig. 15B, Fig. 16A, Fig. 16B, Fig. 17A, Fig. 17B, Fig. 17C, Fig. 17D, Fig. 18A, Fig. 18B, Fig. 19A, Fig. 19B, Fig. 20A, Fig. 20B, Fig. 20C, Fig. 20D, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 21E, Fig. 21F, Fig. 22A, Fig. 22B, Fig. 22C, Fig. 22D, Fig. 23A, Fig. 23B, Fig. 23C, Fig. 23D, Fig. 24A, Fig. 24B, Fig. 24C and Fig. 24D are cross-sectional views at intermediate stages in the fabrication of FinFETs, according to some embodiments. DETAILED DESCRIPTION

[0007] The following disclosure provides many different embodiments or examples for implementing different features of the invention. To simplify the present disclosure, specific examples of components and arrangements are described below. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first structural element over or on a second structural element in the following description may include embodiments in which the first and second structural elements are formed in direct contact, and may also include embodiments in which additional structural elements may be formed between the first and second structural elements such that the first and second structural elements may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples.This repetition is for simplicity and clarity and does not in itself imply any relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, spatially relative terms such as "beneath," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to another element(s) or feature(s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the components in use or operation, in addition to the orientation shown in the figures. The subject matter may be oriented differently (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may also be interpreted accordingly.

[0009] According to some embodiments, dielectric layers are formed over the semiconductor features, e.g., fins, prior to forming the dummy gates over the fins. The dielectric layers include a mask layer that allows a greater thickness of dielectric material to be formed over the top of the fins than over the sidewalls of the fins. The dielectric layers can reduce the loss of the fin from the top surface of the fins during subsequent patterning processes of the dummy gate, which can increase the performance of the device by reducing contact resistance. The process for forming the dielectric layers can be integrated with and followed by an oxidative deposition process, which is cost-effective and achieves high wafer counts per hour.

[0010] Fig. 1 illustrates, in a three-dimensional view, an example of a FinFET according to some embodiments. A FinFET includes a fin 60 extending from a substrate 50 (e.g., a semiconductor substrate). Isolation regions 70 are disposed above the substrate 50, and the fin 60 protrudes above and between adjacent isolation regions 70. Although the isolation regions 70 are described / illustrated as separate from the substrate 50, the term "substrate" as used herein may be used to refer to the semiconductor substrate alone or to a semiconductor substrate with isolation regions. Although the fin 60 is illustrated as a single, continuous material as the substrate 50, the fin 60 and / or the substrate 50 may additionally include a single material or a plurality of materials.In this context, the fin 60 refers to the portion extending between the adjacent isolation regions 70.

[0011] A gate dielectric layer 110 is located along sidewalls and above a top surface of the fin 60, and a gate electrode 112 is located above the gate dielectric layer 110. Source / drain regions 102 are arranged on opposite sides of the fin 60 with respect to the gate dielectric layer 110 and the gate electrode 112. Fig. 1 further illustrates reference cross-sections used in subsequent figures. Cross-section AA runs along a longitudinal axis of the gate electrode 112 and in a direction that is, for example, perpendicular to the direction of current flow between the source / drain regions 102 of the FinFET. Cross-section BB is perpendicular to cross-section AA and runs along a longitudinal axis of the fin 60 and in a direction, for example, of current flow between the source / drain regions 102 of the FinFET. Cross-section CC runs parallel to cross-section AA and extends through a source / drain region of the FinFET. For clarity, subsequent figures refer to these reference cross-sections.

[0012] Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Also, some embodiments consider aspects used in planar devices, such as planar FETs, nanostructure (e.g., nanosheet, nanowire, gate-all-around, or the like) field-effect transistors (NSFETs), or the like.

[0013] Fig. 2 to 23B are cross-sectional views of intermediate stages in fabricating FinFETs according to some embodiments. Fig. 2, Fig. 3, Fig. 4, Fig. 5, Fig. 6, Fig. 7, Fig. 8, Fig. 9 and Fig. 10 illustrate a reference cross-section AA, which, apart from several fins / FinFETs, is Fig. 1 is illustrated. Fig. 11A, Fig. 12A, Fig. 13A, Fig. 14A, Fig. 15A, Fig. 16A, Fig. 17A, Fig. 18A, Fig. 19A, Fig. 20A, Fig. 20C, Fig. 21A, Fig. 21D, Fig. 22A, Fig. 22C, Fig. 23A, Fig. 23C, Fig. 24A and Fig. 24C are along the Fig. 1 illustrated reference cross-section AA, and Fig. 11B, Fig. 12B, Fig. 13B, Fig. 14B, Fig. 15B, Fig. 16B, Fig. 17B, Fig. 18B, Fig. 19B, Fig. 20B, Fig. 20D, Fig. 21B, Fig. 21C, Fig. 21E, Fig. 21F, Fig. 22B, Fig. 22D, Fig. 23B, Fig. 23D, Fig. 24B and Fig. 24D are along a similar in Fig. 1 illustrated cross section BB, apart from several fins / FinFETs. Fig. 17C and Fig. 17D are illustrated along reference cross section C / DC / D, which, apart from several fins / FinFETs, is in Fig. 1 is illustrated.

[0014] In Fig. 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. In general, an SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide layer (BOX layer), a silicon oxide layer, or the like.

[0015] The insulation layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of substrate 50 may include silicon; germanium; a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium indium arsenide phosphide; or combinations thereof.

[0016] The substrate 50 includes an n-type region 50N and a p-type region 50P. The n-type region 50N may be used to form n-type devices, such as NMOS transistors, e.g., n-FinFETs. The p-type region 50P may be used to form p-type devices, such as PMOS transistors, e.g., p-FinFETs. The n-type region 50N may be physically separated from the p-type region 50P (as illustrated by divider 51), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P.

[0017] Appropriate wells (not shown) may be formed in the substrate 50. In the illustrated embodiment, a p-well is formed in the n-type region 50N and an n-type well is formed in the p-type region 50P. The wells are formed by implanting the n-type region 50N and the p-type region 50P with p-type and / or n-type impurities. After implanting the n-type regions 50N and the p-type regions 50P, an anneal may be performed to activate the implanted p-type and / or n-type impurities.

[0018] In embodiments with different well types, different implantation steps for the n-type region 50N and the p-type region 50P can be achieved using a photoresist or other masks (not shown). For example, a photoresist can be formed over the n-type region 50N of the substrate 50. The photoresist is patterned to expose the p-type region 50P of the substrate 50, such as a PMOS region. The photoresist can be formed using a spin-on technique and patterned using acceptable photolithography techniques. Once the photoresist is patterned, an n-type impurity implantation is performed in the p-type region 50P, and the photoresist can serve as a mask, substantially preventing n-type impurities from being implanted into the n-type region 50N, such as an NMOS region. The n-impurities may be phosphorus, arsenic, antimony or the like, which are in the range with a concentration equal to or less than 1018 cm -3 , such as between about 10 17 cm -3 and about 10 18 cm -3 , are implanted. After implantation, the photoresist is removed, such as by an acceptable ashing process.

[0019] After implantation of the p-type region 50P, a photoresist is formed over the p-type region 50P of the substrate 50. The photoresist is patterned to expose the n-type region 50N of the substrate 50, such as the NMOS region. The photoresist may be formed using a spin-on technique and patterned using acceptable photolithography techniques. Once the photoresist is patterned, a p-type impurity implantation may be performed in the n-type region 50N, and the photoresist may serve as a mask that substantially prevents p-type impurities from being implanted into the p-type region 50P, such as a PMOS region. The p-type impurities may be boron, BF2, indium, or the like, which may be introduced into the region at a concentration equal to or less than 10 18 cm -3 , such as between about 10 17 cm -3 and about 10 18 cm -3, implanted. After implantation, the photoresist can be removed, such as by an acceptable ashing process.

[0020] A first semiconductor region 52 is formed over the substrate 50. The first semiconductor region 52 is a semiconductor material, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. In some embodiments, the first semiconductor region 52 is silicon. The first semiconductor region 52 is grown epitaxially on the substrate 50. As further discussed below, the first semiconductor region 52 is patterned to form fins in the n-type region 50N.

[0021] In Fig. 3, a second semiconductor region 54 is formed over the substrate 50. The second semiconductor region 54 is a semiconductor material, such as silicon germanium (e.g., Si x Ge 1-x, where x can range from 0 to 1), pure or substantially pure germanium, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. For example, available materials for forming III-V compound semiconductors include, but are not limited to, InAs, AlAs, GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlP, GaP, and the like. In some embodiments, the second semiconductor region 54 is silicon germanium. The second semiconductor region 54 is epitaxially grown on the substrate 50. As an example of forming the second semiconductor region 54, an opening may be formed in the first semiconductor region 52 above the p-type region 50P of the substrate. The opening may be formed by one or more etching processes using a photoresist as an etch mask.The etching process(es) may include wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like, and may be anisotropic. The second semiconductor region is then epitaxially grown on the substrate 50 in the opening.

[0022] Silicon and silicon germanium have different lattice constants. Consequently, the second semiconductor region 54 and the substrate 50 have mismatched lattice constants. The mismatch in the lattice constants depends on the germanium concentration of the second semiconductor region 54, with a higher germanium concentration resulting in a greater mismatch in the lattice constants. The mismatch in the lattice constants causes compressive stress in the second semiconductor region 54, which can increase the carrier mobility of the second semiconductor region 54, which can improve the channel region mobility of the subsequently formed p-type devices. The channel regions formed in the second semiconductor region can be partially or fully strained channel regions.

[0023] In some embodiments, the first semiconductor region 52 and the second semiconductor region 54 are doped in situ during growth to have appropriate doped regions (e.g., wells). The doped regions of the first semiconductor region 52 and the second semiconductor region 54 may be of the same doping type as the underlying doped regions of the substrate 50. The doped regions of the first semiconductor region 52 and the second semiconductor region 54 may have the same doping concentration as the underlying doped regions of the substrate 50, or may have different doping concentrations. In some embodiments, doping the first semiconductor region 52 and the second semiconductor region 54 may avoid implantations in the substrate 50, although in situ and implantation doping may be used together.

[0024] In Fig. 4, trenches 56 are formed in the first semiconductor region 52 and the second semiconductor region 54 (and optionally in the substrate 50). The trenches 56 may be formed by one or more etching processes using a photoresist as an etch mask. The etching process(es) may include wet etching, dry etching, reactive ion etching (RIE), neutral beam etching (NBE), a combination thereof, or the like, and may be anisotropic. The trenches 56 may extend partially into the first semiconductor region 52 and the second semiconductor region 54 or extend through the semiconductor regions and into the substrate 50. Portions of the first semiconductor region 52 and the second semiconductor region 54 (and optionally the substrate 50) that remain between the trenches 56 are referred to as fins 60. The fins 60 each have a lower section 62 and an upper section 64.The lower sections 62 include lower sections 62N and 62P, with the lower sections 62N comprising the remaining sections of the n-type region 50N of the substrate 50 and the lower sections 62P comprising the remaining sections of the p-type region 50P of the substrate 50. The upper sections 64 include upper sections 64N and 64P, with the upper sections 64N comprising the remaining sections of the first semiconductor region 52 and the lower sections 64P comprising the remaining sections of the second semiconductor region 54. The fins 60 are formed with a first width W1. In some embodiments, the first width W1 is in a range of 5 nm to 15 nm. Such a fin width may allow the fin to maintain a sufficient thickness after subsequent etching process(es) (described below).

[0025] The fins may be patterned using any suitable method. For example, the fins 60 may be patterned using one or more photolithography processes, including dual or multi-patterning processes. Generally, dual or multi-patterning processes combine photolithography and self-aligning processes, allowing structures to be created that have, for example, smaller pitches than what is otherwise obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed using a self-aligning process adjacent to the patterned sacrificial layer.The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins. In some embodiments, the mask (or other layer) may remain on the fins 60.

[0026] In Fig. 5, an insulating material 68 is formed over the substrate 50 and between adjacent fins 60. The insulating material 68 may be formed such that excess portions of the insulating material 68 cover the fins 60. The insulating material 68 may be an oxide, such as silicon oxide, a nitride, the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable chemical vapor deposition (FCVD) (e.g., chemical vapor deposition (CVD)-based material deposition in a remote plasma system and post-curing to convert to another material, such as an oxide), the like, or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 68 is silicon oxide formed by an FCVD process.Once the insulating material is formed, an annealing process may be performed. Although the insulating material 68 is illustrated as a single layer, some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along a surface of the substrate 50 and the fins 60. Thereafter, a fill material, such as those discussed above, may be formed over the liner.

[0027] In Fig. 6, the isolation material 68 is recessed to form shallow trench isolation (STI) regions 70. The isolation material 68 is recessed such that the upper portions 64 of the fins 60 protrude between adjacent STI regions 70. The isolation material 68 may be recessed by performing a planarization process followed by an acceptable etch process. In some embodiments, the planarization process includes chemical mechanical polishing (CMP), an etch-back process, combinations thereof, or the like. The planarization process exposes the fins 60. After the planarization process, upper surfaces of the fins 60 and the isolation material 68 are flush. The STI regions 70 may then be recessed using an acceptable etch process, such as an etch process that is selective to the material of the isolation material 68. For example, removal of chemical oxides using a hydrogen source (e.g.Ammonia) with a fluorine source (e.g., nitrogen trifluoride) or chemical oxide removal using dilute hydrofluoric acid (dHF) may be used. The top surfaces of the STI regions 70 may be formed flat, convex, and / or concave through an etching process. The exposed portions of the fins 60 have a first height H1. In some embodiments, the first height H1 is in a range of 40 nm to 60 nm.

[0028] In the embodiment shown, upper surfaces of the STI regions 70 are flush with upper surfaces of the lower portions 62 of the fins 60, such that the upper portions 64 of the fins 60 are fully exposed. In some embodiments, the upper surfaces of the STI region 70 are disposed above upper surfaces of the lower portions 62 of the fins 60, such that the upper portions 64 of the fins 60 are partially exposed. In some embodiments, upper surfaces of the STI region 70 are disposed below upper surfaces of the lower portions 62 of the fins 60, such that the upper portions 64 of the fins 60 are fully exposed and the lower portions 62 of the fins 60 are partially exposed.

[0029] In some embodiments, protective caps (not illustrated) are formed on the exposed portions of the fins 60. Germanium oxidizes more easily than silicon, and therefore there is a greater risk of oxidation at the upper portions 64P of the fins 60 containing the germanium. Forming the protective caps may help prevent / reduce oxidation during subsequent processing. The protective caps may be a semiconductor material, such as silicon, silicon carbide, a III-V compound semiconductor, a II-VI compound semiconductor, or the like. In some embodiments, the protective caps are silicon and are epitaxially grown on the exposed portions of the fins 60.

[0030] Fig. 7 to 10 illustrate the formation of a dummy dielectric layer 80 over the fins 60 according to some embodiments. The dummy dielectric layer 80 includes dielectric sublayers and has a thickness of the dielectric material formed over the top of the fins 60 that is greater than over the sidewalls of the fins 60 (see below, Fig. 10). The greater thickness on top of the dummy dielectric layer 80 may prevent the loss of fins from the top surface of the fins 60 during subsequent removal processes of the dummy gates formed over the fins 60 (see below, Fig. 12A and Fig. 12B) without increasing the thickness of the dielectric underlayer 80A on the sidewalls of the fins 60, which may result in undesirable coalescence of subsequently formed portions of the dummy dielectric layer 80 on adjacent fins 60 and / or undesirable voids in subsequently formed portions of a dummy gate layer between adjacent fins 60 (see below, Fig. 11A-11B).

[0031] In Fig. 7, a first dielectric sublayer 80A is formed over the upper portions 64 of the fins 60 and over exposed portions of the STI regions 70. The first dielectric sublayer 80A may comprise a majority of the portions of the subsequently formed dummy dielectric layer 80 on upper surfaces of the fins 60. The first dielectric sublayer 80A may comprise one or more oxide (e.g., silicon oxide) and / or nitride (e.g., silicon nitride) layers and may be formed by a suitable process, such as CVD, PECVD, PVD, ALD, PEALD, or the like. In some embodiments, the first dielectric sublayer 80A comprises silicon oxide and is formed by PEALD with a plasma generation power in a range of 15 W to 200 W.In some embodiments, the first dielectric sublayer 80A is formed with a first thickness T1 in a range of 1.5 nm to 3.5 nm (15 Å to 35 Å), which is advantageous to reduce the loss of the fin during a subsequent patterning process of a dummy gate (see below). Fig. 12A-13B). Forming the first dielectric sublayer 80A with a thickness of less than 1.5 nm (15 Å) may result in undesirable fin loss during the subsequent dummy gate patterning process. Forming the first dielectric sublayer 80A with a thickness greater than 3.5 nm (35 Å) may result in undesirable coalescence of subsequently formed portions of the dummy dielectric layer 80 onto adjacent fins 60 and / or undesirable voids in subsequently formed portions of a dummy gate layer (see below, Fig. 11A-11B) between adjacent fins 60.

[0032] After forming the first dielectric sublayer 80A, a plasma treatment (e.g., an O2 plasma treatment) may be performed on the first dielectric sublayer 80A. The plasma treatment may further oxidize the material of the first dielectric sublayer 80A, which may reduce fin loss during a subsequent patterning process of a dummy gate. The plasma treatment may be performed using a plasma generation power in a range of 400 W to 600 W.

[0033] In Fig. 8, a mask underlayer 80B is formed on upper surfaces of the first dielectric underlayer 80A over the fins 60. The mask underlayer 80B protects portions of the first dielectric underlayer 80A during a subsequent etch-back process (see below, Fig. 9). A mask sublayer 80B is formed to cover upper surfaces of the portions of the first dielectric sublayer 80A above the fins 60. In some embodiments, the mask sublayer 80B exposes upper surfaces of portions of the first dielectric sublayer 80A on the STI regions 70. In some embodiments, sidewall portions of the mask sublayer 80B extend along upper portions of the sidewalls of the first dielectric sublayer 80A. The sidewall portions of the mask sublayer 80B may taper in thickness along the upper portions of the sidewalls of the first dielectric sublayer 80A. For example, in embodiments as shown in Fig. 8, lower portions of the sidewalls of the first dielectric sublayer 80A may be exposed, and a thickness of the mask sublayer 80B may taper, increasing as the mask sublayer 80B extends further from the substrate 50. In some embodiments where the first dielectric sublayer 80A includes silicon oxide, for example, the mask sublayer 80B may include carbon and / or nitrogen and may be formed using a suitable process, such as CVD, PECVD, PVD, ALD, PEALD, or the like.In embodiments such as those in which the first dielectric sublayer 80A includes silicon oxide and the mask sublayer 80B includes nitride, carbide, or the like, the mask sublayer 80B has a lower etch rate than the first dielectric sublayer 80A and thereby acts as an etch mask in a subsequent etch-back process to allow uncovered portions of the first dielectric sublayer 80A (e.g., on sidewalls of the fins 60) to be etched while protecting the top surface of the first dielectric sublayer 80A. For example, in some embodiments, the mask sublayer 80B is silicon nitride, silicon carbonitride, silicon oxycarbonitride, the like, or a combination thereof, and is formed using bis(diethylamino)silane (BDEAS), SiH3-N((CH-(CH3)2)2), the like, or a combination thereof as a precursor.

[0034] In some embodiments, the mask sublayer 80B is formed by a suitable process, such as ALD, wherein the process comprises cycles of relatively high pressure, short purge time, and short plasma treatment time. The high pressure, short purge time, and short plasma treatment time may result in less adsorption of precursors on the sidewalls of the first dielectric sublayer 80A and greater adsorption of precursors on upper surfaces of the first dielectric sublayer 80A. This may result in a profile of the mask sublayer 80B containing more material on upper surfaces of the first dielectric sublayer 80A than on the sidewalls of the first dielectric sublayer 80A. e.g., the thickness of the mask sublayer 80B may taper, with the thickness increasing as the mask sublayer 80B extends further from the substrate 50.In some embodiments, the ALD process uses multiple deposition cycles with alternating precursor gases. For example, the ALD process may be a cyclic deposition process, e.g., comprising a first cycle using a first precursor, such as bis(diethylamino)silane (BDEAS), followed by a second cycle using a second precursor, such as SiH3-N((CH-(CH3)2)2). In some embodiments, silicon and oxygen deposited in the first cycle may react with silicon, carbon, and nitrogen deposited in the second cycle to form a material containing silicon, oxygen, carbon, and nitrogen. Alternating first and second cycles may be repeated until the mask underlayer reaches a desired thickness, e.g., silicon oxycarbonitride. The mask underlayer 80B may be formed with a plasma generation power in a range of 15 W to 150 W.The mask underlayer 80B can be formed under a pressure ranging from 199,983 Pa to 466,627 Pa (1500 Torr to 3500 Torr). The mask underlayer 80B can be formed with a purge time for each ALD cycle ranging from 0.05 s to 0.25 s and a plasma treatment time for each ALD cycle ranging from 0.05 s to 0.25 s.

[0035] In some embodiments, a mask underlayer 80B having a second thickness T2 in a range of 0.5 nm to 1.0 nm (5 Å to 10 Å) is formed over upper surfaces of the first dielectric underlayer 80A over the fins 60, which is advantageous to maintain a sufficient thickness of the mask underlayer 80B after a subsequent etch-back process to protect upper portions of the first dielectric underlayer 80A. Forming the mask underlayer 80B with a thickness of less than 0.5 nm (5 Å) may be disadvantageous because it does not provide sufficient thickness to protect upper portions of the first dielectric underlayer 80A.Forming the mask underlayer 80B with a thickness greater than 1.0 nm (10 Å) may be disadvantageous because it may result in undesirable coalescence of subsequently formed portions of the dummy dielectric layer 80 on adjacent fins 60 and / or undesirable voids in subsequently formed portions of a dummy gate layer (see below, . Fig. 11A-11B) between adjacent fins 60.

[0036] In Fig. 9, a patterning process, such as an etch-back process, has been performed to remove portions of the first dielectric sublayer 80A and the mask sublayer 80B on sidewalls of the fins 60. By removing the sidewall portions of the first dielectric sublayer 80A and the mask sublayer 80B, the etch-back process may increase the process window for subsequent processes, such as forming a dummy gate layer between the fins 60, by increasing a distance between adjacent structures (e.g., between adjacent fins). By increasing the distance, the likelihood of unwanted coalescence of subsequently formed portions of the dummy dielectric layer 80 on adjacent fins 60 and / or unwanted voids in subsequently formed portions of the dummy gate layer (see below, Fig. 11A-11B) between adjacent fins 60. The mask underlayer 80B serves as an etch stop layer to protect upper portions of the first dielectric underlayer 80A on upper surfaces of the fins 60 from the etch-back process. The etch-back process may be a cyclic etch comprising wet etching processes, dry etching processes, or a combination thereof. In some embodiments, the etch-back process comprises a wet etch using dilute hydrofluoric acid, hydrochloric acid, or the like, or a combination thereof, as the etchant. In some embodiments, the etch-back process comprises a dry etch using NH3, HF, the like, or a combination thereof as the etchant. When the sidewall portions of the first dielectric underlayer 80A are removed, the etch-back process may be stopped, thereby exposing sidewalls of the upper portions 64 of the fins 60.

[0037] After the etch-back process, upper portions of the first dielectric sublayer 80A remain on upper surfaces of the fins 60, covered by the remaining portions of the mask sublayer 80B. In some embodiments, the remaining portions of the mask sublayer 80B have a third thickness T3 in a range of 0.2 nm to 0.5 nm (2 Å to 5 Å), which is advantageous for the etch-back process to remove sidewall portions of the first dielectric sublayer 80A and the mask sublayer 80B. The remaining portions of the mask sublayer 80B having a thickness of less than 0.2 nm (2 Å) may result in etching of the first dielectric sublayer 80A, which may cause undesirable subsequent fin loss.The remaining portions of the mask underlayer 80B having a thickness greater than 0.5 nm (5 Å) may result in sidewall portions of the first dielectric underlayer 80A remaining on the fins 60, which may reduce the process window for subsequent processes, such as dummy gate formation.

[0038] In Fig. 10, a second dielectric sublayer 80C is formed over the top portions 64 of the fins 60 and over exposed portions of the STI regions 70, covering the remaining portions of the first dielectric sublayer 80A and the mask sublayer 80B. The remaining portions of the first dielectric sublayer 80A and the mask sublayer 80B and the second dielectric sublayer 80C together form a dummy dielectric layer 80, wherein the thickness of the dielectric material formed over the top surface of the fins 60 is greater than over the sidewalls of the fins 60. This may reduce the loss of the fin from the top surface of the fin 60 during subsequent removal processes of the dummy gates formed over the fins 60 (see below, Fig. 12A and Fig. 12B). In some embodiments, the second dielectric sublayer 80C is formed from similar materials and by similar methods as the first dielectric sublayer 80A (see above, Fig. 7). Note that for illustrative purposes only, the second dielectric sublayer 80C is shown covering the STI regions 70. In some embodiments, the second dielectric sublayer 80C covers only the fins 60.

[0039] In some embodiments, the second dielectric sublayer 80C is formed with a fourth thickness T4 in a range of 1.5 nm to 3.5 nm (15 Å to 35 Å) on the sidewalls and over top surfaces of the fins 60, which is advantageous to reduce the loss of the fin during a subsequent patterning process of a dummy gate (see below, Fig. 12A-13B). Forming the second dielectric sublayer 80C with a thickness of less than 1.5 nm (15 Å) may result in undesirable fin loss during the subsequent dummy gate patterning process. Forming the second dielectric sublayer 80C with a thickness greater than 3.5 nm (35 Å) may result in undesirable coalescence of portions of the second dielectric sublayer 80C on adjacent fins 60 and / or undesirable voids in subsequently formed portions of a dummy gate layer (see below, Fig. 11A-11B) between adjacent fins 60.

[0040] In some embodiments, the dummy dielectric layer 80 has a fifth thickness T5, measured between a top surface of the fins 60 and a top surface of the dummy dielectric layer 80 above the fins 60 in a range of 4.5 nm to 6.5 nm (45 Å to 65 Å), which is advantageous to reduce the loss of the fin during a subsequent patterning process of a dummy gate (see below, Fig. 12A-13B). Dummy dielectric layer 80 having a fifth thickness T5 of less than 4.5 nm (45 Å) may result in undesirable fin loss during the subsequent dummy gate patterning process. Dummy dielectric layer 80 having a fifth thickness T5 of greater than 6.5 nm (65 Å) may reduce the process window for subsequent processes, such as dummy gate formation.

[0041] In some embodiments, the ratio of the fifth thickness T5 to the fourth thickness T4 is in a range of 2:1 to 5:1, which may be advantageous to reduce the loss of the fin from the top surfaces of the fins 60 while increasing the process window for subsequent processes, such as forming a dummy gate. The ratio of the fifth thickness T5 to the fourth thickness T4 of less than 2:1 may result in undesirable loss of the fin from the top surfaces of the fins 60 or in a reduction of the process window for subsequent processes, such as forming a dummy gate. The ratio of the fifth thickness T5 to the fourth thickness T4 of more than 5:1 may result in undesirable loss of the fin on the sidewalls of the fins 60 during a subsequent removal process of the dummy dielectric layer 80 (see below, Fig. 20A-20B).

[0042] In Fig. 11A and Fig. 11B, a dummy gate layer 82 is formed over the dummy dielectric layer 80, and a mask layer 84 is formed over the dummy gate layer 82. The dummy gate layer 82 may be deposited over the dummy dielectric layer 80 and then planarized, such as by CMP. The mask layer 84 may be deposited over the dummy gate layer 82. The dummy gate layer 82 may be made of a conductive or semiconductive material and may be selected from a group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (poly-SiGe), metal nitrides, metal silicides, metal oxides, and metals. The dummy gate layer 82 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques for depositing the selected material.The dummy gate layer 82 may be formed from other materials that exhibit high etch selectivity toward etching isolation regions, e.g., the STI regions 70 and / or the dummy dielectric layer 80. The mask layer 84 may comprise one or more layers of, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 82 and a single mask layer 84 are formed across the n-type region 50N and the p-type region 50P.

[0043] Fig. 12A to 23B illustrate various additional steps in manufacturing components according to embodiments. Although Fig. While Figures 12A to 23B illustrate structural elements in the p-type regions 50P, it should be understood that the illustrated structures can apply to both the n-type regions 50N and the p-type regions 50P. Differences (if any) between the structures of the n-type region 50N and those of the p-type region 50P are described in the text accompanying each figure.

[0044] In Fig. 12A and Fig. 12B, the mask layer 84 (see above, Fig. 11A-11B) may be patterned using acceptable photolithography and etching techniques to form masks 94. The pattern of masks 94 may then be transferred to dummy gate layer 82 to form dummy gates 92. Dummy gates 92 cover respective channel regions 58 of fins 60. The pattern of masks 74 may be used to physically separate each of dummy gates 72 from adjacent dummy gates. Dummy gates 92 may also have a longitudinal direction that is substantially perpendicular to the longitudinal direction of the respective fins 60.

[0045] In the Fig. 13A and Fig. 13B, the pattern of the masks 94 and the dummy gates 92 is transferred to the dummy dielectric layer 80 by an acceptable etching technique to form a dummy gate dielectric layer 90. In some embodiments, the dummy gate dielectric layer 90 is formed by an etching process comprising a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the etching process comprises a wet etch using dilute hydrofluoric acid, hydrochloric acid, the like, or a combination thereof as the etchant. In some embodiments, the etching process comprises a dry etch using NH3, HF, the like, or a combination thereof as the etchant.In some embodiments where the respective materials of the first dielectric sublayer 80A, the mask sublayer 80B, and the second dielectric sublayer 80C have different etch selectivities, the etching process may include a first etchant, such as O2, HBr, or the like, selected to etch the material of the first dielectric sublayer 80A, a second etchant, such as O2, HBr, or the like, selected to etch the material of the mask sublayer 80B, and a third etchant, such as O2, HBr, or the like, selected to etch the material of the second dielectric sublayer 80C. In some embodiments, the material of the first dielectric sublayer 80A is the same as the material of the second dielectric sublayer 80C, and the first etchant is the same as the third etchant.

[0046] Due to the thickness T5 of the dummy dielectric layer 80 covering upper portions 64 of the fins 60 (see above, Fig. 10), the upper portions 64 of the fins 60 can be etched with a pitch D1 in a range of 1 nm to 2 nm. The fin loss of a pitch D1 on upper portions 64 of the fins 60 can be less than a respective fin loss that occurs with a smaller thickness of the dummy dielectric layer 80 over the upper portions 64 of the fins 60. This can increase the performance of the device by reducing the contact resistance.

[0047] In Fig. 14A and Fig. 14B, gate sealing spacers 96 are formed on exposed surfaces of the dummy gate 92, the masks 94, the dummy gate dielectric layer 90, and / or the fins 60. The gate sealing spacers 96 may be formed by thermal oxidation or deposition followed by an anisotropic etch. In the illustrated embodiment, gate sealing spacers 96 are formed by thermal oxidation of sidewall portions of the dummy gates 92, the masks 94, the dummy gate dielectric layer 90, and the fins 60. The gate sealing spacers 96 may be formed from silicon oxide, silicon nitride, silicon oxynitride, or the like.

[0048] In Fig. 15A and Fig. 15B, implantations for lightly doped source / drain regions (LDD regions) 98 have been performed. In the embodiments with different device types, similar to the above-mentioned Fig. 2, a mask, such as a photoresist, may be formed over the n-type region 50N, exposing the p-type region 50P, and impurities of the appropriate type (e.g., p-type impurities) may be implanted into the exposed fins 60 in the p-type region 50P. The mask may then be removed. Subsequently, a mask, such as a photoresist, may be formed over the p-type region 50P, exposing the n-type region 50N, and impurities of the appropriate type (e.g., n-type impurities) may be implanted into the exposed fins 60 in the n-type region 50N. The mask may then be removed. The n-type impurities may be any of the previously discussed n-type impurities, and the p-type impurities may be any of the previously discussed p-type impurities. The lightly doped source / drain regions can have a concentration of impurities of about 10 15 cm -3 up to about 10 19 cm -3Annealing can be used to repair implantation damage and activate the implanted foreign materials.

[0049] In Fig. 16A and Fig. 16B, gate spacers 100 are formed on the gate sealing spacers 96 along sidewalls of the dummy gates 92 and the masks 94. The gate spacers 100 may be formed by conformally depositing an insulating material and subsequently anisotropically etching the insulating material. The insulating material of the gate spacers 100 may be silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, a combination thereof, or the like. The gate spacers 100 extend over upper portions 64 of the fins 60.

[0050] It should be noted that the above disclosure generally describes a process for forming spacers and LDD regions. Other processes and sequences may be used. For example, fewer or additional spacers may be used, or different step sequences may be used (e.g., the gate sealing spacers 96 may not be etched prior to forming the gate spacers 100, resulting in "L-shaped" gate sealing spacers, spacers may be formed and removed, and / or the like). Furthermore, the n- and p-type devices may be formed using different structures and steps. For example, LDD regions for n-type devices may be formed prior to forming the gate sealing spacers 96, while the LDD regions for p-type devices may be formed after forming the gate sealing spacers 96.

[0051] In Fig. 17A and Fig. 17B, ​​epitaxial source / drain regions 102 are formed in the fins 60. The epitaxial source / drain regions 102 are formed in the fins 60 such that each dummy gate 92 is disposed between respective adjacent pairs of the epitaxial source / drain regions 102. In some embodiments, the epitaxial source / drain regions 102 may extend into and penetrate the fins 60. In some embodiments, the gate spacers 100 are used to separate the epitaxial source / drain regions 102 from the dummy gates 92 and the dummy gate dielectric layer 90 by an appropriate lateral distance such that the epitaxial source / drain regions 102 do not short-circuit subsequently formed gates of the resulting FinFETs. A material of the epitaxial source / drain regions 102 may be selected to apply a stress in the respective channel regions 58 to improve performance.

[0052] The epitaxial source / drain regions 102 in the p-type region 50P, e.g., the PMOS region, can be formed by masking the n-type region 50N, e.g., the NMOS region, and etching the source / drain regions of the fins 60 in the p-type region 50P to form recesses in the fins 60. Then, the epitaxial source / drain regions 102 in the p-type region 50P are epitaxially grown in the recesses. The epitaxial source / drain regions 102 can include any acceptable material, such as one appropriate for p-type FinFETs. For example, if the fin 60 is silicon germanium, the epitaxial source / drain regions 102 in the p-type region 50P may include materials that exert tensile stress in the channel region 58, such as silicon germanium, boron-doped silicon germanium, germanium-tin silicon, or the like.The epitaxial source / drain regions 102 in the p-type region 50P may have surfaces elevated from respective surfaces of the fins 60 and may have facets.

[0053] The epitaxial source / drain regions 102 in the n-type region 50N, e.g., the NMOS region, can be formed by masking the p-type region 50P, e.g., the NMOS region, and etching the source / drain regions of the fins 60 in the n-type region 50N to form recesses in the fins 60. Then, the epitaxial source / drain regions 102 in the n-type region 50N are epitaxially grown in the recesses. The epitaxial source / drain regions 102 can include any acceptable material, such as one suitable for FinFETs. For example, if the fin 60 is silicon, the epitaxial source / drain regions 102 in the n-type region 50N may include materials that exert compressive stress in the channel region 58, such as silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, or the like. The epitaxial source / drain regions 102 in the n-type region 50N may have surfaces elevated from respective surfaces of the fins 60 and may have facets.

[0054] The epitaxial source / drain regions 102 and / or the fins 60 may be implanted with dopants to form source / drain regions, similar to the previously discussed process for forming lightly doped source / drain regions, followed by annealing. The source / drain regions may have an impurity concentration between about 10 19 cm -3 and about 10 21 cm -3 The n- and / or p-type impurities for source / drain regions may be any of the impurities discussed previously. In some embodiments, the epitaxial source / drain regions 102 may be doped in situ during growth.

[0055] As a result of the epitaxial processes used to form the epitaxial source / drain regions 102 in the n-type region 50N and the p-type region 50P, upper surfaces of the epitaxial source / drain regions 102 have facets that extend laterally outward beyond sidewalls of the fins 60. In some embodiments, these facets cause adjacent source / drain regions 102 of the same FinFET to grow together, as illustrated by Fig. 17C. In other embodiments, adjacent source / drain regions 102 remain separated after completion of the epitaxial process, as shown by Fig. 17D. In the Fig. 17C and Fig. In the embodiments illustrated in FIG. 17D, gate spacers 100 are formed covering a portion of the sidewalls of fins 60 and extending above STI regions 70, thereby blocking epitaxial growth. In some other embodiments, the spacer etch used to form gate spacers 100 may be adapted to remove the spacer material to allow the epitaxially grown region to extend to the surface of STI region 70.

[0056] In Fig. 18A and Fig. 18B is a first interlayer dielectric (ILD) 106 over the Fig. 17A and Fig. 17B. The first ILD 106 may be formed from a dielectric material and may be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Dielectric materials may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials formed by any acceptable process may be used. In some embodiments, a contact etch stop layer (CESL) 104 is disposed between the first ILD 106 and the epitaxial source / drain regions 102, the masks 94, and the gate spacers 100. The CESL 104 may include a dielectric material, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a lower etch rate than the material of the overlying first ILD 106.

[0057] In Fig. 19A and Fig. 19B, a planarization process such as CMP may be performed to make the top surface of the first ILD 106 flush with the top surfaces of the dummy gates 92 or the masks 94 (see above, Fig. 15A-15B). The planarization process may also remove the masks 94 on the dummy gates 92 and portions of the gate sealing spacers 96 and the gate spacers 100 along sidewalls of the masks 94. After the planarization process, top surfaces of the dummy gates 92, the gate sealing spacers 96, the gate spacers 100, and the first ILD 106 are flush. Accordingly, the top surfaces of the dummy gates 92 are exposed through the first ILD 106. In some embodiments, the masks 94 may remain, in which case the planarization process flushes the top surface of the first ILD 106 with the top surfaces of the top surfaces of the masks 94.

[0058] Fig. 20A to 24D illustrate various additional steps in fabricating devices according to embodiments in a first region 500 of a die (e.g., a core logic region) and in a second region 600 of a die (e.g., an input / output region). Fig. 20A, Fig. 20B, Fig. 21A, Fig. 21B, Fig. 21C, Fig. 22A, Fig. 22B, Fig. 23A, Fig. 23B, Fig. 24A and Fig. 24B illustrate the first area 500, and Fig. 20C, Fig. 20D, Fig. 21D, Fig. 21E, Fig. 21F, Fig. 22C, Fig. 22D, Fig. 23C, Fig. 23D, Fig. 24C and Fig. 24D illustrate the second area 600.

[0059] In Fig. 20A to 20D, the dummy gates 92 and the masks 94, if present, have been removed in one (or multiple) etching steps to form recesses 108. Portions of the dummy gate dielectric layer 90 in the recesses 108 may also be removed. In some embodiments, only the dummy gates 92 are removed, and the dummy gate dielectric layer 90 remains and is exposed through the recesses 108. In some embodiments, the dummy gate dielectric layer 90 is removed from recesses 108 in a first region 500 of a die (e.g., a core logic region) and remains in recesses 108 in a second region 600 of the die (e.g., an input / output region). In some embodiments, the dummy gates 92 are removed by an anisotropic dry etch process.For example, the etching process may include a dry etch process using a reactive gas(es) that selectively etches the dummy gates 92, with little or no etching of the first ILD 106 or the gate spacers 100. Each recess 108 exposes and / or overlies a channel region 58 of a respective fin 60. Each channel region 58 is disposed between adjacent pairs of epitaxial source / drain regions 102. During removal, the dummy gate dielectric layer 90 may be used as an etch stop layer when etching the dummy gates 92. After removal of the dummy gate 92, as shown in FIG. Fig. 20A-B, the dummy gate dielectric layer 90 may then be removed in the first region 500 and may remain in the second region 600, as shown in Fig. 20C-D. When different processes are used, different masking steps can be used to mask and expose appropriate areas.

[0060] In Fig. 21A, Fig. 21B, Fig. 21D and Fig. 21E, gate dielectric layers 110 and gate electrodes 112 for replacement gates are formed. Fig. Figure 21C illustrates a detailed view of area 12 of Fig. 21B and Fig. Figure 21F illustrates a detailed view of area 14 of Fig. 21E. Gate dielectric layers 110, comprising one or more layers, are deposited in the recesses 108. In some embodiments, in the first region 500, the gate dielectric layers 110 are deposited on the top surfaces and sidewalls of the fins 60 and on sidewalls of the gate sealing spacer 96 / gate spacer 100, as shown in Fig. 21A-B, and in the second region 600, the gate dielectric layers 110 are deposited on the top surfaces and sidewalls of the dummy gate dielectric layer 90 and on sidewalls of the gate sealing spacer 96 / gate spacer 100, as shown in Fig. 21D-E. The gate dielectric layers 110 may also be formed on the top surface of the first ILD 106. In some embodiments, the gate dielectric layers 110 comprise one or more dielectric layers, such as one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like. For example, in some embodiments, the gate dielectric layers 110 in the first region 500 comprise an interface layer of silicon oxide formed by thermal or chemical oxidation and an overlying high-k dielectric material, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof, as in Fig. 21A-B, and the gate dielectric layers 110 in the second region 600 include a high-k dielectric material, as shown in Fig. 21D-E. The gate dielectric layers 110 may include a dielectric layer having a k value greater than about 7.0. The formation methods of the gate dielectric layers 110 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0061] The gate electrodes 112 are each deposited over the gate dielectric layers 110 and fill the remaining portions of the recesses 108. The gate electrodes 112 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, or combinations thereof, or multiple layers thereof. Although, for example, in Fig. 21B and Fig. 21E illustrates a single-layer gate electrode 112, the gate electrode 112 may include any number of liner layers 112A, any number of work function adjusting layers 112B, and a fill material 112C, as shown in Fig. 21C and Fig. 21F. After filling the recesses 108, a planarization process, such as CMP, may be performed to remove the excess portions of the gate dielectric layers 110 and the gate electrode material 112, the excess portions of which lie above the top surface of the ILD 106. The remaining portions of the gate electrode material 112 and the gate dielectric layers 110 thus form replacement gates of the resulting FinFETs. The gate electrodes 112 and the gate dielectric layers 110 may collectively be referred to as a "gate stack." The gate and the gate stacks may extend along sidewalls of a channel region 58 of the fins 60.

[0062] The formation of the gate dielectric layers 110 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric layers 110 in each region are formed from the same materials, and the formation of the gate electrodes 112 may occur simultaneously, such that the gate electrodes 112 in each region are formed from the same materials. In some embodiments, the gate dielectric layers 110 in each region may be formed by different processes, such that the gate dielectric layers 110 may be made of different materials, and / or the gate electrodes 112 in each region may be formed by different processes, such that the gate electrodes 112 may be made of different materials. If different processes are used, different masking steps may be used to mask and expose appropriate areas.

[0063] In Fig. 22A to 22D, a gate mask 114 is formed over the gate stack (which includes a gate dielectric layer 110 and a corresponding gate electrode 112), and the gate mask may be disposed between opposing portions of the gate spacers 100. In some embodiments, forming the gate mask 114 includes recessing the gate stack such that a recess is formed directly above the gate stack and between opposing portions of the gate spacers 100. A gate mask 114 comprising one or more layers of dielectric material, such as silicon nitride, silicon oxynitride, or the like, is filled into the recess, followed by a planarization process to remove excess portions of the dielectric material extending beyond the first ILD 106. The gate mask 114 is optional and may be omitted in some embodiments.In such embodiments, the gate stack may remain flush with top surfaces of the first ILD 106.

[0064] As also in Fig. 22A to 22D, a second ILD 116 is deposited over the first ILD 106. In some embodiments, the second ILD 116 is a flowable film formed by a flowable CVD process. In some embodiments, the second ILD 116 is formed from a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and may be deposited by any suitable process, such as CVD and PECVD. The subsequently formed gate contacts 118 (see below, Fig. 23A to 23D) penetrate the second ILD 116 and the gate mask 114 (if present) to contact the upper surface of the recessed gate electrode 112.

[0065] In Fig. 23A to 23D, according to some embodiments, gate contacts 118 and source / drain contacts 120 are formed through the second ILD 116 and the first ILD 106 in the p-type region 50P. Openings for the source / drain contacts 120 are formed through the first and second ILDs 106 and 116, and openings for the gate contacts 118 are formed through the second ILD 116 and the gate mask 114 (if present). The openings may be formed using acceptable photolithography and etching techniques. A liner (not shown), such as a diffusion barrier layer, an adhesion layer, or the like, and a conductive material are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material can be copper, a copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel or the like.A planarization process, such as CMP, may be performed to remove excess material from a surface of the second ILD 116. The remaining liner and conductive material form the source / drain contacts 120 and the gate contacts 118 in the openings. An annealing process may be performed to form a silicide at the interface between the epitaxial source / drain regions 102 and the source / drain contacts 120. The source / drain contacts 120 are physically and electrically coupled to the epitaxial source / drain regions 102, and the gate contacts 118 are physically and electrically coupled to the gate electrodes 112. The source / drain contacts 120 and the gate contacts 118 may be formed in different processes or may be formed in the same process.Although they are shown as being formed in the same cross-section, it should be understood that each of the source / drain contacts 120 and the gate contacts 118 may be formed in different cross-sections, which may avoid shorting the contacts.

[0066] Fig. 24A to 24D illustrate gate contacts 118 and source / drain contacts 120 formed in an n-type region 50N by the second ILD 116 and the first ILD 106, according to some embodiments. Fig. The structures illustrated in Figures 24A to 24D can be seen from the Fig. 11A and Fig. 11B can be formed in the n-region 50N using similar methods as used in forming structures in the p-region 50P, as described with reference to Fig. 12A to 23D.

[0067] The disclosed FinFET embodiments could also be applied to nanostructure devices, such as nanostructure field-effect transistors (e.g., nanosheet, nanowire, gate-all-around field-effect transistors, or the like) (NSFETs). In an NSFET embodiment, the fins are replaced by nanostructures formed by patterning a stack with alternating layers of channel layers and sacrificial layers. Dummy gate stacks and source / drain regions are formed in a manner similar to the embodiments described above. After the dummy gate stacks are removed, the sacrificial layers in channel regions can be partially or completely removed.The replacement gate structures are formed in a manner similar to the embodiments described above. The replacement gate structures may partially or completely fill openings left by the removal of the sacrificial layers, and the replacement gate structures may partially or completely surround the channel layers in the channel regions of the NSFET devices. ILDs and contacts to the replacement gate structures and the source / drain regions may be formed in a manner similar to the embodiments described above. A nanostructure device may be formed as disclosed in US Patent Application Publication No. 2016 / 0365414, which is incorporated by reference into the present application.

[0068] Embodiments can achieve advantages. Before forming the dummy gates over the fins, dielectric layers comprising a mask layer are formed over the semiconductor fins. The mask layer enables the formation of dielectric material with a greater thickness over the top surfaces of the fins than on the sidewalls of the fins. The greater thickness of the dielectric layers over the top surfaces of the fins can increase the performance of the device during subsequent patterning processes of the dummy gate. Since the process for forming the dielectric layers can be integrated with and followed by a conventional oxidative deposition process, the process for forming the dielectric layers is cost-effective, and high wafer counts per hour can be achieved.

[0069] According to one embodiment, a method of forming a semiconductor device comprises: forming a semiconductor fin and an isolation region adjacent to the semiconductor fin; forming a first layer on the semiconductor fin; forming a mask on the first layer, wherein the mask is thicker on a top surface of the semiconductor fin than along a sidewall of the semiconductor fin; thinning the first layer along the sidewall of the semiconductor fin using the mask, wherein thinning the first layer removes portions of the mask; forming a second layer on the semiconductor fin, wherein the second layer covers the remaining portions of the mask and the remaining portions of the first layer; forming a dummy gate layer on the semiconductor fin; and patterning the dummy gate layer, wherein patterning the dummy gate layer exposes a top surface of the semiconductor fin.In one embodiment, forming the first layer comprises forming the first layer on the isolation region, wherein thinning the first layer removes a first portion of the first layer on the isolation region, and wherein thinning the first layer further removes a second portion of the first layer on sidewalls of the semiconductor fin. In one embodiment, the mask has a first thickness in a range of 0.5 nm to 1.0 nm (5 Å to 10 Å) before thinning the first layer. In one embodiment, the mask has a second thickness in a range of 0.2 nm to 0.5 nm (2 Å to 5 Å) after thinning the first layer. In one embodiment, the second layer is formed with a thickness in a range of 1.5 nm to 3.5 nm (15 Å to 35 Å). In one embodiment, the first layer, the mask, and the second layer have a combined thickness in a range of 4.5 nm to 6.5 nm (45 Å to 65 Å) after forming the second layer.In one embodiment, after forming the second layer, a ratio of a combined thickness of the first layer, the mask, and the second layer to a thickness of the second layer is in a range of 2:1 to 5:1. In one embodiment, patterning the dummy gate layer etches an upper portion of the semiconductor fin with a pitch of less than 2 nm. In one embodiment, depositing the first layer comprises performing plasma-enhanced atomic layer deposition of silicon oxide. In one embodiment, the method further comprises performing an O2 plasma treatment on the first layer.

[0070] According to another embodiment, the method of forming a semiconductor device comprises: depositing a first dielectric layer with plasma-enhanced atomic layer deposition over a first semiconductor fin and a second semiconductor fin, wherein the first semiconductor fin is located in a first region of a die and the second semiconductor fin is located in a second region of the die; forming a mask layer over the first dielectric layer, the mask layer covering an upper surface of a portion of the first dielectric layer over the first semiconductor fin and the second semiconductor fin, wherein a thickness of the mask layer tapers along upper portions of sidewalls of the first dielectric layer; removing exposed portions of the first dielectric layer;Depositing a second dielectric layer over the mask layer and the remaining portions of the first dielectric layer over the first semiconductor fin and the second semiconductor fin; removing a first portion of the second dielectric layer, a first portion of the mask layer, and a first portion of the first dielectric layer over the first semiconductor fin, leaving a second portion of the first dielectric layer, a second portion of the mask layer, and a second portion of the second dielectric layer on the second semiconductor fin;and forming a first gate electrode over the first semiconductor fin and forming a second gate electrode over the second portion of the second dielectric layer. In one embodiment, forming the mask layer comprises using bis(diethylamino)silane (BDEAS) or SiH3-N((CH-(CH3)2)2)2 as a precursor. In one embodiment, forming the mask layer comprises using atomic layer deposition with a plasma generation power in a range of 15 W to 150 W. In one embodiment, forming the mask layer is performed at a pressure in a range of 199983 Pa to 466627 Pa (1500 Torr to 3500 Torr). In one embodiment, forming the mask layer comprises a purge time in a range of 0.5 s to 0.25 s. In one embodiment, forming the mask layer comprises a plasma treatment time in a range of 0.5 s to 0.25 s.;

[0071] According to yet another embodiment, a semiconductor device comprises: a first semiconductor fin in a first region of a die and a second semiconductor fin in a second region of the die; a first gate dielectric on the first semiconductor fin, the first gate dielectric physically in contact with a top surface of the first semiconductor fin; a first dielectric layer on the second semiconductor fin; a second dielectric layer on the first dielectric layer, the second dielectric layer comprising carbon; a third dielectric layer on the second dielectric layer; a second gate dielectric on the third dielectric layer; a first gate electrode on the first gate dielectric; and a second gate electrode on the second gate dielectric.In one embodiment, the first dielectric layer, the second dielectric layer, and the third dielectric layer have a combined thickness in a range of 4.5 nm to 6.5 nm (45 Å to 65 Å) over a top surface of the second semiconductor fin. In one embodiment, the third dielectric layer has a thickness in a range of 1.5 nm to 3.5 nm (15 Å to 35 Å) on a sidewall of the second semiconductor fin. In one embodiment, the second dielectric layer is silicon nitride, silicon carbonitride, or silicon oxycarbonitride.

Claims

[1] A method of forming a semiconductor device, the method comprising: Forming a semiconductor fin (60) and an isolation region (70) adjacent to the semiconductor fin (60); Forming a first layer on the semiconductor fin (60); Forming a mask (94) on the first layer, the mask (94) being thicker on a top surface of the semiconductor fin (60) than along a sidewall of the semiconductor fin (60); Thinning the first layer along the sidewall of the semiconductor fin (60) using the mask (94), wherein thinning the first layer removes portions of the mask (94); Forming a second layer on the semiconductor fin (60), the second layer covering the remaining portions of the mask (94) and the remaining portions of the first layer; forming a dummy gate layer on the semiconductor fin (60); and Structuring the dummy gate layer, wherein the structuring of the dummy gate layer exposes an upper surface of the semiconductor fin (60). [2] The method of claim 1, wherein forming the first layer comprises forming the first layer on the isolation region (70), wherein thinning the first layer removes a first portion of the first layer on the isolation region (70), and wherein thinning the first layer further removes a second portion of the first layer on the sidewalls of the semiconductor fin (60). [3] The method of claim 1 or 2, wherein the mask (94) has a first thickness in a range of 0.5 nm to 1.0 nm before thinning the first layer. [4] A method according to any one of the preceding claims, wherein the mask (94) has a second thickness in a range of 0.2 nm to 0.5 nm after thinning the first layer. [5] A method according to any one of the preceding claims, wherein the second layer is formed with a thickness in a range of 1.5 nm to 3.5 nm. [6] The method of any preceding claim, wherein after forming the second layer, the first layer, the mask (94) and the second layer have a combined thickness in a range of 4.5 nm to 6.5 nm. [7] The method of any preceding claim, wherein after forming the second layer, a ratio of a combined thickness of the first layer, the mask (94) and the second layer to a thickness of the second layer is in a range of 2:1 to 5:

1. [8] The method of any preceding claim, wherein patterning the dummy gate layer etches an upper portion of the semiconductor fin (60) with a pitch of less than 2 nm. [9] A method according to any one of the preceding claims, wherein depositing the first layer comprises performing plasma-assisted atomic layer deposition of silicon oxide. [10] A method according to any one of the preceding claims, further comprising performing an O2 plasma treatment on the first layer. [11] A method of forming a semiconductor device, the method comprising: Depositing a first dielectric layer with a plasma-assisted atomic layer deposition over a first semiconductor fin (60) and a second semiconductor fin (60), wherein the first semiconductor fin (60) is located in a first region of a die and the second semiconductor fin (60) is located in a second region of the die; Forming a mask layer (84) over the first dielectric layer, the mask layer (84) covering an upper surface of a portion of the first dielectric layer over the first semiconductor fin (60) and the second semiconductor fin (60), a thickness of the mask layer (84) tapering along upper portions of the sidewalls of the first dielectric layer; Removing exposed portions of the first dielectric layer; depositing a second dielectric layer over the mask layer (84) and the remaining portions of the first dielectric layer over the first semiconductor fin (60) and the second semiconductor fin (60); Removing a first portion of the second dielectric layer, a first portion of the mask layer (84), and a first portion of the first dielectric layer over the first semiconductor fin (60), leaving a second portion of the first dielectric layer, a second portion of the mask layer (84), and a second portion of the second dielectric layer on the second semiconductor fin (60); and Forming a first gate electrode (112) over the first semiconductor fin (60) and forming a second gate electrode (112) over the second portion of the second dielectric layer. [12] The method of claim 11, wherein forming the mask layer (84) comprises using bis(dimethylamino)silane or SiH3-N((CH-(CH3)2)2) as a precursor. [13] The method of claim 11 or 12, wherein forming the mask layer (84) comprises using atomic layer deposition with a plasma generation power in a range of 15 W to 150 W. [14] A method according to any one of the preceding claims 11 to 13, wherein forming the mask layer (84) is performed at a pressure in a range of 199983 Pa to 466627 Pa. [15] The method of any one of the preceding claims 11 to 14, wherein forming the mask layer (84) has a rinsing time in a range of 0.5 s to 0.25 s. [16] The method of any one of the preceding claims 11 to 15, wherein forming the mask layer (84) has a plasma treatment time in a range of 0.5 s to 0.25 s. [17] A semiconductor device comprising: a first semiconductor fin (60) in a first region of a die and a second semiconductor fin (60) in a second region of the die; a first gate dielectric on the first semiconductor fin (60), the first gate dielectric being physically in contact with a top surface of the first semiconductor fin (60); a first dielectric layer on the second semiconductor fin; a second dielectric layer on the first dielectric layer, the second dielectric layer containing carbon; a third dielectric layer on the second dielectric layer; a second gate dielectric on the third dielectric layer; a first gate electrode (112) on the first gate dielectric; a second gate electrode (112) on the second gate dielectric, wherein the first dielectric layer, the second dielectric layer and the third dielectric layer have a combined thickness in a range of 4.5 nm to 6.5 nm above a top surface of the second semiconductor fin (60), and / or wherein the third dielectric layer has a thickness in a range of 1.5 nm to 3.5 nm on a sidewall of the second semiconductor fin (60). [18] A semiconductor device according to claim 17, wherein the second dielectric layer is silicon nitride, silicon carbonitride or silicon oxycarbonitride.

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