SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD

Abstract

A method of manufacturing a semiconductor device, comprising: Depositing a first dielectric layer (401) over a logic region (105) and an analog region (107) of a semiconductor substrate (101); Treating the first dielectric layer (401) to form a restored layer (601); after treating the first dielectric layer (401), removing a first portion of the restored layer (601) from the logic area (105); Forming a second dielectric layer (801) in the logic region (105); and Depositing a gate electrode material over a remainder of the restored layer (601) and the second dielectric layer (801), wherein treating the first dielectric layer (401) comprises: Exposing the first dielectric layer (401) to a plasma (501) to a depth of 10% to 50% into the first dielectric layer (401) to form a treated region (503), leaving an untreated region (505) of the first dielectric layer (401) between the treated region (503) and the semiconductor substrate (101); and Annealing (603) the treated region (503) to form the restored layer (601), wherein the restored layer (601) results from the treated region (503).

Description

BACKGROUND

[0001] Semiconductor devices are used in a wide variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers over a semiconductor substrate and patterning the various material layers using lithography to form circuit components and elements thereon.

[0002] The semiconductor industry is improving the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, allowing more components to be integrated into a given area. As the minimum feature size has been reduced, new problems have emerged that need to be addressed.

[0003] US 2004 / 0 067 619 A1 discloses a method for forming a gate of a high-voltage transistor, wherein a nitriding process is used to introduce nitrogen atoms into the gate dielectric layer of the high-voltage transistor to mitigate leakage, and a re-oxidation process is used to remove the surface of the gate layer damaged by the nitriding process. JP 2012-094 656 A discloses a semiconductor device for stabilizing the threshold voltage by preventing boron leakage and reducing noise in a CMOS transistor by using a gate oxide film containing nitrogen and fluorine. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. Note that, in accordance with common industry practice, various features are not drawn to scale. Indeed, the dimensions of the various features may be arbitrarily exaggerated or reduced for clarity of description. Fig. 1 shows a logic region and an analog region of a substrate according to some embodiments. Fig. 2 shows a formation of a first tub according to some embodiments. Fig. 3 shows forming a second tub according to some embodiments. Fig. 4 shows forming a first dielectric layer according to some embodiments. Fig. 5 shows a first treatment of the first dielectric layer according to some embodiments. Fig. 6 shows an annealing process according to some embodiments. Fig. 7 shows removal of the first dielectric layer from the logic area according to some embodiments. Fig. 8 shows forming a second dielectric layer in the logic region according to some embodiments. Fig. 9 shows forming a first gate electrode and a second gate electrode according to some embodiments. Fig. 10 shows forming spacers according to some embodiments. Fig. 11A illustrates forming source / drain regions and silicide regions according to some embodiments. Fig. 11B shows a diagram illustrating normalized spectral densities of current noise according to some embodiments. Fig. 12 shows a gate-last process according to some embodiments. Fig. 13 shows another gate-last process with a different sequence of process steps according to some embodiments. DETAILED DESCRIPTION

[0005] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. For example, in the following description, forming a first feature over or on top of a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features need not be in direct contact. Additionally, the present disclosure may repeat reference numbers and / or letters in the various examples.This repetition is for the purpose of simplicity and clarity and does not in itself impose any relationship between the various embodiments and / or configurations described.

[0006] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures. The spatially relative terms are intended to encompass various orientations of the device being used or operated, in addition to the orientation shown in the figures. The device may be oriented differently (rotated 90 degrees or in a different orientation), and the spatially relative terms used herein may be interpreted accordingly.

[0007] In the following, embodiments are described with reference to a specific embodiment in which flicker noise in analog devices (e.g., in a digital-to-analog device for an LCD panel) is reduced by treating a gate dielectric. However, the described embodiments are not intended to limit the ideas presented, and the ideas may be implemented in a wide variety of other embodiments. All such embodiments are intended to be fully included within the scope of the disclosure.

[0008] With reference to Fig. 1, a substrate 101 with shallow trench isolations (STIs) 103 formed therein is shown. The substrate 101 may comprise bulk silicon, doped or undoped, or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate comprises a layer of a semiconductor material such as silicon, germanium, silicon germanium, SOI, silicon germanium-on-insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.

[0009] Additionally, the substrate 101 may include a logic region 105 and an analog region 107. Devices subsequently formed in the logic region 105 are used to fabricate logic devices, while devices subsequently formed in the analog region 107 are used to fabricate analog devices. In some embodiments, the logic region 105 may be located immediately adjacent to the analog region 107, while in other embodiments, the logic region 105 may be located remotely from the analog region 107 (in Fig. 1 shown by the dashed line labeled 109).

[0010] The STIs 103 may be formed by etching the substrate 101 to form a trench and filling the trench with a dielectric, as is known in the art. For example, the STIs 103 may be filled with a dielectric such as an oxide material, a high-density plasma oxide (HDP oxide), or the like. However, any suitable material and deposition method may be used.

[0011] Fig. 2 shows forming a first well 203 in the analog region 107. Initially, forming the first well 203 in the analog region 107 first protects the logic region 105. In one embodiment, the logic region 105 may be protected by disposing a first photoresist 205 over the substrate 101 and exposing the photoresist to create a distinction between exposed regions and unexposed regions. After exposure, the first photoresist 205 is developed to remove portions of the first photoresist 205 over the analog region 107 and leave portions of the first photoresist 205 over the logic region 105 to protect the logic region 105.

[0012] After the logic region 105 is protected, the first well 203 may be created in the analog region 107 by introducing first dopants into the substrate 101. The first dopants may be dopants suitable for the type of device to be fabricated. For example, in one embodiment where the devices to be formed are n-type devices, the first dopants may be p-type dopants such as boron, aluminum, gallium, indium, combinations thereof, or the like. In further embodiments where the devices to be formed are p-type devices, the first dopants may be n-type dopants such as phosphorus, arsenic, antimony, combinations thereof, or the like. However, any suitable dopants may be used.

[0013] In one embodiment, the first dopants may be introduced into the substrate 101, for example, using a first implantation process (in Fig. 2 by the arrows labeled 201). In this embodiment, ions of the first dopants are formed and then accelerated toward the upper surface of the substrate 101, thereby implanting the ions of the first dopants into the substrate 101. However, any suitable method for implanting the first dopants may be used.

[0014] After the first dopants are implanted into the substrate 101 to form the first well 202, the first photoresist 205 is removed. In one embodiment, the first photoresist 205 may be removed using an ashing process in which a temperature of the first photoresist 205 is increased until the first photoresist 205 undergoes thermal decomposition and can be easily removed. However, any suitable method or combination of methods, such as wet etching, may also be used.

[0015] Fig. 3 shows that a second well 303 is formed in the logic region 105 after the first well 203 is formed in the analog region 107. To begin forming the second well 303 in the logic region 105, the analog region 107 is first protected. In one embodiment, the analog region 107 may be protected by disposing a second photoresist 305 over the substrate 101 and exposing the second photoresist 305 to create a distinction between exposed regions and unexposed regions. After exposure, the second photoresist 305 is developed to remove portions of the second photoresist 305 over the logic region 105 and leave portions of the second photoresist 305 over the analog region 107 to protect the analog region 107.

[0016] After the analog region 107 has been protected, the second well 303 may be created in the logic region 105 by introducing second dopants into the substrate 101. The second dopants may be dopants suitable for the type of device to be fabricated. For example, in one embodiment where the devices to be formed are n-type devices, the second dopants may be p-type dopants such as boron, aluminum, gallium, indium, combinations thereof, or the like. In further embodiments where the devices to be formed are p-type devices, the second dopants may be n-type dopants such as phosphorus, arsenic, antimony, combinations thereof, or the like. However, any suitable dopants may be used.

[0017] Furthermore, any suitable combination of devices may be used in both the logic region 105 and the analog region 107. For example, if the devices formed in the logic region 105 are n-type devices, the devices formed in the analog region 107 may be either n-type devices or p-type devices. Further, if the devices formed in the logic region 105 are p-type devices, the devices formed in the analog region 107 may be either n-type devices or p-type devices. Any suitable combination of devices may be used.

[0018] In one embodiment, the second dopants may be introduced into the substrate 101, for example, using a second implantation process (in Fig. 3 by the arrows labeled 301). In this embodiment, ions of the second dopants are formed and then accelerated towards the upper surface of the substrate 101, thereby implanting the ions of the second dopants into the substrate 101. In one embodiment, the second dopants are implanted into the logic region 105 such that they have a higher concentration than the first dopants implanted into the analog region 107. For example, the first dopants in the first well 203 may have a first concentration of between about 1.0 × 10 14 cm -3 and about 1.0 × 10 18 cm -3 while the second dopants in the second well 303 have a second concentration, which is greater than the first concentration, between about 1.0 × 10 14 cm -3 and about 1.0 × 10 18 cm -3However, any suitable method for implanting the second dopants and any suitable concentration of first dopants and second dopants may be used.

[0019] After the second dopants are implanted into the substrate 101 to form the second well 303, the second photoresist 305 is removed. In one embodiment, the second photoresist 305 may be removed using an ashing process in which a temperature of the second photoresist 305 is increased until the second photoresist 305 undergoes thermal decomposition and can be easily removed. However, any suitable method or combination of methods, such as wet etching, may also be used.

[0020] Fig. 4 shows, as a beginning of forming a gate dielectric for devices in the analog region 107, depositing a first dielectric layer 401 over the substrate 101. The first dielectric layer 401 may be a high-k dielectric, for example, silicon oxide, silicon oxynitride, silicon nitride, an oxide, a nitrogen-containing oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, a combination thereof, or the like. The first dielectric layer 401 may have a relative permittivity value greater than about 4.

[0021] In an embodiment where the first dielectric layer 401 comprises an oxide layer, the first dielectric layer 401 may be formed by any oxidation process, for example, wet or dry thermal oxidation in an environment containing an oxide, H 2O, NO, or a combination thereof, or by chemical vapor deposition (CVD) techniques using tetraethyl orthosilicate (TEOS) and oxygen as a precursor. In one embodiment, the first dielectric layer 401 may have a first thickness T 1 of between about 1 nm and about 15 nm, for example 10 nm.

[0022] In further embodiments where the first dielectric layer 401 is a metal oxide, for example, hafnium oxide, the first dielectric layer 401 may be deposited using a deposition process. For example, the first dielectric layer 401 may be deposited using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, combinations thereof, or the like. However, any suitable deposition method may be used.

[0023] Fig. 5 shows that the first dielectric layer 401 is treated after the first dielectric layer 401 has been deposited. In one embodiment, the treatment may be a plasma treatment (in Fig. 5 by the cloud labeled 501), wherein the first dielectric layer 401 is exposed to a plasma of one or more plasma precursors that help reduce flicker noise in the devices formed in the analog region 107. In certain embodiments, the plasma precursors may be precursors such as oxygen, nitrogen, fluorine, chlorine, combinations thereof, or the like, although any suitable precursors may be used.

[0024] At the beginning of the plasma treatment 501, a flow rate of the plasma precursors can be set in a range from about 10 sccm to about 100 sccm, and a pressure of the plasma treatment 501 can be set in a range from about 1,333 Pascals to 1,333 Pascals. The temperature of the plasma treatment 501 can be set in a range from about 400°C to about 800°C. A power of the plasma generator of the plasma treatment 501 can be in a range from about 5 W to about 500 W, and a frequency of the plasma generator can be about 13.56 MHz or more. The substrate 101 can be biased in a range from about 0.5 V to about 500 V during the plasma treatment 501. However, any suitable process parameters can be used.

[0025] During the plasma treatment 501, the plasma species may damage the exposed surfaces and may also diffuse into the exposed surfaces of the first dielectric layer 401, such that a treated region 503 is formed in the first dielectric layer 401, while an untreated region 505 of the first dielectric layer 401 remains between the treated region 503 and the substrate 101. For example, the species used for the plasma (e.g., oxygen, nitrogen, fluorine, chlorine, etc.) may be diffused into the materials forming the first dielectric layer 401 to a first depth D 1 of the treated surface which is less than or equal to about 100 nm, for example less than or equal to 5 nm. In some particular embodiments, for example when noise is to be better controlled, the first depth may be between about 1 / 10 and half of the first thickness T 1Finally, the species can be concentrated in a range of about 1.0 × 10 10 cm -3 up to about 1.0 × 10 15 cm -3 diffused. The concentration of the species can decrease from a peak near the respective treated surfaces to a certain depth in the material.

[0026] Fig. 6 shows that after the treated region 503 has been formed, the treated region 503 may be further treated to densify the treated region 503 and anneal fixed oxide charges and vacancies such that the treated region 503 has a different density than the rest of the first dielectric layer 401. In one embodiment, the treated region 503 may be further treated using, for example, an annealing process (in Fig. 6 by the wavy lines labeled 603) which forms a restored area 601 from the treated area 503 (see Fig. 5). However, any suitable process may be used.

[0027] In a particular embodiment, the annealing process 603 may be a thermal anneal performed in an oxygen (O 2 ), nitrogen (N 2 ), N 2 O, ammonia (NH 3 ), combinations thereof, or the like. Additionally, the thermal annealing may be performed at a temperature between about 500°C and about 1000°C for a duration between about 10 seconds and about 1 hour, although any suitable temperature and duration may be used. Additionally, although thermal annealing has been described, any suitable annealing process, such as millisecond laser annealing, flash annealing, spike annealing, or immersion annealing, may be used.

[0028] After the treated region 503 has been formed and then restored to become the restored region 601, the restored region 601 may have a second depth D 2 from the surface of the first dielectric layer 401. In one embodiment, the second depth D 2 between about 5% and about 30% of the original first thickness T 1 of the first dielectric layer 401. For example, if the first dielectric layer 401 was originally deposited with a thickness of 100 nm, the restored region may be between 5 nm and about 30 nm. If the second depth D 2 is too small, the flicker noise of the formed analog device is not improved, whereas if the second depth D 2is too large, the plasma energy during the plasma treatment 501 damages too much of the first dielectric layer 401, thereby impairing the overall quality of the subsequently formed gate dielectrics.

[0029] Furthermore, although embodiments have been described above in which both the plasma treatment 501 and the annealing process 603 are used to form the restored region 601, this is intended to be exemplary and not limiting. Rather, any suitable combination of processes may be used, such as using only the annealing process 603. All such embodiments are intended to be fully included within the scope of the embodiments.

[0030] Fig. 7 shows that after the restored region 601 is formed in the first dielectric layer 401, the first dielectric layer 401 is patterned such that the first dielectric layer 401 is removed from the logic region 105. In one embodiment, patterning the first dielectric layer 401 may begin by disposing a third photoresist 701 over the substrate 101 and exposing the third photoresist 701 to create a difference between exposed regions and unexposed regions. After exposure, the third photoresist 701 is developed to remove portions of the third photoresist 701 over the logic region 105 and to leave portions of the third photoresist 701 over the analog region 107.

[0031] After the third photoresist 701 has been disposed and patterned, those portions of the first dielectric layer 401 (e.g., the restored region 601) located in the logic region 105 are removed. In one embodiment, the first dielectric layer 401 may be removed using, for example, an anisotropic etching process, such as a reactive ion etching process. However, any suitable removal process may be used.

[0032] After the first dielectric layer 401 is removed from the logic region 105, the third photoresist 701 is further removed. In one embodiment, the third photoresist 701 may be removed using, for example, an ashing process, which increases a temperature of the third photoresist 701 until the third photoresist 701 undergoes thermal decomposition, after which the third photoresist 701 may be easily removed. However, any suitable process may be used to remove the third photoresist 701.

[0033] Fig. 8 illustrates forming a second dielectric layer 801 over the logic region 105. The second dielectric layer 801 may be a high-k dielectric, such as silicon oxide, silicon oxynitride, silicon nitride, an oxide, a nitrogen-containing oxide, aluminum oxide, lanthanum oxide, hafnium oxide, zirconium oxide, hafnium oxynitride, a combination thereof, or the like. The second dielectric layer 801 may have a relative permittivity value greater than about 4.

[0034] In an embodiment where the second dielectric layer 801 comprises an oxide layer, the second dielectric layer 801 may be formed by any oxidation process, for example, wet or dry thermal oxidation in an environment containing an oxide, H 2O, NO, or a combination thereof, or by chemical vapor deposition (CVD) techniques using tetraethyl orthosilicate (TEOS) and oxygen as a precursor. In one embodiment, the second dielectric layer 801 may have a second thickness T 2 between about 1 nm and about 15 nm, for example 10 nm.

[0035] In further embodiments where the second dielectric layer 801 is a metal oxide, such as hafnium oxide, the second dielectric layer 801 may be deposited using a deposition process. For example, the second dielectric layer 801 may be deposited using an atomic layer deposition process, a chemical vapor deposition process, a physical vapor deposition process, combinations thereof, or the like. However, any suitable deposition method may be used.

[0036] Furthermore, since the second dielectric layer 801 is not present during the treatment process 501 or the subsequent annealing process 603, the second dielectric layer 801 is not affected by these processes. Thus, the second dielectric layer 801 remains untreated and can have a constant composition and a constant density throughout the second dielectric layer 801.

[0037] Fig. 9 shows arranging and patterning a first gate electrode 901 (e.g., a logic gate electrode) and a second gate electrode 903 (e.g., an analog gate electrode). The material for the first gate electrode 901 and the second gate electrode 903 is blanket deposited over the first dielectric layer 401 and the second dielectric layer 801. In one embodiment, the first gate electrode 901 and the second gate electrode 903 may include a conductive material such as metal (e.g., tantalum, titanium, molybdenum, tungsten, platinum, aluminum, hafnium, ruthenium), a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, tantalum silicide), a metal nitride (e.g., titanium nitride, tantalum nitride), doped polycrystalline silicon, other conductive materials, or a combination thereof. In one example, amorphous silicon is deposited and recrystallized to produce polycrystalline silicon (polysilicon).Although the first gate electrode 901 and the second gate electrode 903 in . Fig. 9 as a single layer, the first gate electrode 901 and the second gate electrode 903 may further comprise any number of suitable layers.

[0038] In one embodiment, the material for the first gate electrode 901 and the second gate electrode 903 is first deposited blanket over the first dielectric layer 401 and the second dielectric layer 801. After the material for the first gate electrode 901 and the second gate electrode 903 is in place, it is then patterned into the separate gate electrodes and the desired shapes, e.g., using one or more photolithographic masking and etching processes to etch through the material of the first gate electrode 901 and the second gate electrode 903, the first dielectric layer 401, and the second dielectric layer 801. However, any suitable methods may be used.

[0039] In one embodiment, the first gate electrode 901 may be structured to have a first width W 1(e.g., a first channel length of the formed logic device) between about 0.05 µm and about 20 µm. Similarly, the second gate electrode 903 may be structured to have a second width W 2 (e.g., a second channel length of the formed analog device) that is greater than the first width W 1 is, for example, a second width W 2 between about 0.1 µm and about 20 µm. However, any suitable dimensions may be used.

[0040] Fig. 10 shows a formation of first spacers 1001 on the first gate electrode 901 and second spacers 1003 on the second gate electrode 903. The first spacers 1001 and the second spacers 1003 may be formed by depositing one or more spacer layers (not shown) over the first gate electrode 901 and the second gate electrode 903. The spacer layers may include SiN, oxynitride, SiC, SiON, oxide, and the like, and may be formed by methods such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), sputtering, combinations thereof, or the like. The spacer layers may be patterned, for example, by isotropic or anisotropic etching, thereby removing the spacer layers from the horizontal surfaces of the structure and forming the first spacers 1001 and the second spacers 1003 as in Fig. 10 shown.

[0041] However, as those skilled in the art will recognize, the process described above and the resulting shape of the first spacers 1001 and the second spacers 1003 as shown in Fig. 10 are merely exemplary and do not limit the embodiments to these descriptions. Rather, any suitable number and combination of spacer layers and shapes may be used to form the first spacers 1001 and the second spacers 1003 for the first gate electrode 901 and the second gate electrode 903, and any suitable combination of spacers may be used.

[0042] Fig. 11A shows forming first source / drain regions 1101 in the substrate 101 on opposite sides of the first gate electrode 901 and also shows forming second source / drain regions 1103 in the substrate 101 on opposite sides of the second gate electrode 903. In an embodiment in which the second well 303 in the logic region 105 contains n-type dopants, the first source / drain regions 1101 may be formed by first protecting the analog region 107 (e.g., by disposing and patterning a photoresist over the analog region 107) and then implanting suitable p-type dopants such as boron, gallium, indium, or the like. In further embodiments in which the second well 303 in the logic region 105 contains p-type dopants, the first source / drain regions 1101 may be formed by implanting suitable n-type dopants such as phosphorus, arsenic, or the like.However, any suitable combination of dopants can be used.

[0043] Similarly, with respect to the second source / drain regions 1103, in an embodiment where the first well 203 contains n-type dopants, the second source / drain regions 1103 may be formed by first protecting the logic region 105 (e.g., by disposing and patterning a photoresist over the logic region 105) and then implanting suitable p-type dopants such as boron, gallium, indium, or the like. In further embodiments where the first well 203 in the analog region 107 contains p-type dopants, the second source / drain regions 1103 may be formed by implanting suitable n-type dopants such as phosphorus, arsenic, or the like. However, any suitable combination of dopants may be used.

[0044] While the first source / drain regions 1101 may be implanted using the first gate electrode 901 and the first spacers 1001 as masks, and the second source / drain regions 1103 may be implanted using the second gate electrode 903 and the second spacers 1003 as masks, it should be noted that those skilled in the art will recognize that many other processes, steps, or the like may be used to form these first source / drain regions 1101 and second source / drain regions 1103. For example, those skilled in the art will recognize that multiple implantations may be performed using different combinations of spacers and liners to form the first source / drain regions 1101 and the second source / drain regions 1103 with a particular shape or characteristic suitable for a particular purpose.Any of these processes may be used to form the first source / drain regions 1101 and the second source / drain regions 1103, and the above description is not intended to limit the embodiments to the steps given above.

[0045] Fig. 11A further illustrates forming silicide regions 1105 over the first source / drain regions 1101, the second source / drain regions 1103, the first gate electrode 901, and the second gate electrode 903. In one embodiment, the silicide regions 1105 include a nickel silicide, although any other suitable metal silicide, such as titanium silicide, cobalt silicide, palladium silicide, platinum silicide, erbium silicide, and the like, may be used. The silicide regions 1105 may be formed by initially blanket deposition of a suitable metal layer, followed by an annealing step in which the metal reacts with the underlying material of the substrate (e.g., silicon). Unreacted metal is then removed, for example, with a selective etch process. The thickness of the silicide regions 1105 may be between about 3 nm and about 50 nm.

[0046] Furthermore, after the silicide regions 1105 have been formed, a top surface of the first gate electrode 901 may extend from the substrate 101 by less than the second gate electrode 903. For example, the first gate electrode 901 may extend by a second distance D 2 between about 25 nm and about 250 nm from the substrate 101, while the second gate electrode 903 extends a third distance D 3 can extend between about 25 nm and about 250 nm. However, any suitable spacing may be used.

[0047] Fig. Figure 11B illustrates improvements that can be achieved by using the embodiments described herein. As shown, normalized current noise spectral densities (S id / Id 2 ) are shown along the y-axis, while the frequencies are plotted along the x-axis. Compared to devices that do not use the embodiments described herein (in Fig. 11B by the line labeled 1107), devices using the embodiments described herein (in Fig. 11B (shown by the line labeled 1109), as can be seen. In some cases, the significant decrease can result in an 8-fold or greater improvement.

[0048] In particular, by improving the quality of the first dielectric layer 401 of the analog devices formed in the analog region 107, the flicker noise behavior of these MOSFETs (caused, for example, by charge carrier trapping and release in the first dielectric layer 401) can be reduced without using an additional mask. As such, a low-cost process that is fully compatible with other CMOS processes can be used to reduce flicker noise, thereby also increasing the signal-to-noise ratio of the analog devices. This can result in better overall device performance, particularly for devices used to convert digital data (e.g., from a CPU) into an analog signal (e.g., to a color display for an LCD panel).

[0049] Fig. Figure 12 shows a further embodiment similar to that described above with reference to Fig. 11A in a “gate-last” process (although the structure described with reference to the Fig. 1 to 11B may also be used without additional processing). In this embodiment, the material of the first gate electrode 901 and the second gate electrode 903 is a dummy material, for example, polysilicon, instead of a final material used, which is subsequently removed. In particular, a first interlayer dielectric (ILD) 1201 is formed over the Fig. 11A after the silicide regions 1105 have been formed. The first ILD 1201 may be formed from a dielectric and may be deposited by any suitable process, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. The dielectrics may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), or the like. Other insulating materials may be used, formed by any suitable process. In some embodiments, a contact etch stop layer (CESL - in Fig. 12 not shown separately) between the first ILD 1201 and underlying structures. The CESL may include a dielectric, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, that has a lower etch rate than the material of the overlying first ILD 1201.

[0050] After the first ILD 1201 is formed, the first ILD 1201 is planarized to expose the first gate electrode 901 and the second gate electrode 903. In one embodiment, the planarization process may be a process such as chemical mechanical polishing, grinding, combinations thereof, or the like. After the planarization process, upper surfaces of the first gate electrode 901 and the second gate electrode 903 are exposed through the first ILD 1201.

[0051] After the first gate electrode 901 and the second gate electrode 903 are exposed, the first gate electrode 901 and the second gate electrode 903 are removed in one or more etching steps to form recesses. In some embodiments, the first gate electrode 901 and the second gate electrode 903 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using one or more reactant gases that selectively etch the first gate electrode 901 and the second gate electrode 903 with little or no etching of the first ILD 1201 or the first spacers 1001 and second spacers 1003. During the removal, the first dielectric layer 401 and the second dielectric layer 801 may be used as an etch stop layer when the first gate electrode 901 and the second gate electrode 903 are etched.

[0052] After the recesses are formed, gate dielectric layers 1205 and gate electrodes 1203 are formed as replacement gates. The gate dielectric layers 1205 are one or more layers deposited in the recesses, for example, on the top surfaces of the first dielectric layer 401 and the second dielectric layer 801 and on sidewalls of the first spacers 1001 and the second spacers 1003. The gate dielectric layers 1205 may also be formed on the top surface of the first ILD 1201. In some embodiments, the gate dielectric layers 1205 comprise one or more dielectric layers, for example, one or more layers of silicon oxide, silicon nitride, metal oxide, metal silicate, or the like.For example, in some embodiments, the gate dielectric layers 1205 include a high-k dielectric, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The gate dielectric layers 1205 may include a dielectric layer with a k value greater than about 7.0. The formation methods of the gate dielectric layers 1205 may include molecular beam deposition (MBD), ALD, PECVD, and the like.

[0053] The gate electrodes 1203 are each deposited over the gate dielectric layers 1205 and fill the remaining portions of the recesses. The gate electrodes 1203 may include a metal-containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multilayers thereof. Although a single-layer gate electrode 1203 is shown, the gate electrode 1203 may further include any number of liner layers, any number of work function tuning layers, and a fill material. After filling the recesses, a planarization process such as CMP may be performed to remove the excess portions of the gate dielectric layers 1205 and the gate electrode material 1203 that lie above the top surface of the first ILD 1201.As such, the gate dielectric layers 1205 may extend along multiple sides of the gate electrodes 1203, and upper surfaces of the gate electrodes 1203 located in both the analog region 107 and the logic region 105 are at the same distance from the substrate 101, for example, a fourth distance D. 4 between approximately 20 nm and approximately 200 nm. The remaining material portions of the gate electrodes 1203 and the gate dielectric layers 1205 thus form replacement gates. The gate electrodes 1203 and the gate dielectric layers 1205 may collectively be referred to as a "gate stack."

[0054] The formation of the gate dielectric layers 1205 in the logic region 105 and the analog region 107 may occur simultaneously, such that the gate dielectric layers 1205 are formed from the same materials in each region, and the formation of the gate electrodes 1203 may occur simultaneously, such that the gate electrodes 1203 are formed from the same materials in both regions. In further embodiments, the gate dielectric layers 1205 in the two regions may be formed by different processes, such that the gate dielectric layers 1205 may be made of different materials, and / or the gate electrodes 1203 may be formed by different processes in the two regions, such that the gate electrodes 1203 may be made of different materials. Different masking steps may be used to mask and expose appropriate regions if separate processes are used.

[0055] Fig. 13 shows another "gate-last" embodiment in which the gate dielectric layers 1205 are formed before forming the first ILD 1201, rather than after forming the first ILD 1201. In this embodiment, before deposition of the material of the first gate electrode 901 and the second gate electrode 903, the material of the gate dielectric layers 1205 is deposited over the first dielectric layer 401 and the second dielectric layer 801. The gate dielectric layers 1205 in this embodiment may be formed as described above with respect to Fig. 12 described.

[0056] After deposition, the first gate electrode 901 and the second gate electrode 903 are formed and patterned. The patterning of the first gate electrode 901 and the second gate electrode 903 is also used to pattern the gate dielectric layers 1205. As such, the gate dielectric layers 1205 are patterned to have a single planar portion located directly above the first dielectric layer 401 and the second dielectric layer 801.

[0057] After the first gate electrode 901 and the second gate electrode 903 are formed, the first ILD 1201 is deposited and planarized, and the first gate electrode 901 and the second gate electrode 903 are removed. After removal, the gate electrodes 1203 (but not the gate dielectric layers 1205, since these are already formed) are deposited to replace the first gate electrode 901 and the second gate electrode 903. As such, the gate electrodes 1203 are deposited in physical contact with the first spacers 1001 (in the logic region 105) and the second spacers (in the analog region 107). In one embodiment, the gate electrodes 1203 are deposited as described above with respect to Fig. 12. However, any suitable methods and materials may be used.

[0058] By treating the first dielectric layer 401 to form the restored region 601, the charge trapping and release that typically occurs at sufficient frequencies in analog devices can be reduced. By reducing charge trapping and release, the overall flicker noise of the analog device can be reduced, thereby improving the overall device performance. These improvements can be achieved without additional masks, at low cost, and with processes that are fully compatible with the other processes used to form CMOS devices.

[0059] Furthermore, although the embodiments presented herein are described as embodiments for use in planar devices, the ideas are not intended to be limited to planar devices. Rather, the ideas may be implemented in a wide variety of devices, such as fin field-effect transistors (finFETs), nanostructure devices, combinations thereof, or the like. All such embodiments are intended to be fully included within the scope of the embodiments. The invention is defined by the main claim and the subordinate claims. Further embodiments of the invention are recited by the dependent claims.

Claims

[1] A method of manufacturing a semiconductor device, comprising: Depositing a first dielectric layer (401) over a logic region (105) and an analog region (107) of a semiconductor substrate (101); Treating the first dielectric layer (401) to form a restored layer (601); after treating the first dielectric layer (401), removing a first portion of the restored layer (601) from the logic area (105); Forming a second dielectric layer (801) in the logic region (105); and Depositing a gate electrode material over a remainder of the restored layer (601) and the second dielectric layer (801), wherein treating the first dielectric layer (401) comprises: Exposing the first dielectric layer (401) to a plasma (501) to a depth of 10% to 50% into the first dielectric layer (401) to form a treated region (503), wherein an untreated region (505) of the first dielectric layer (401) remains between the treated region (503) and the semiconductor substrate (101); and Annealing (603) the treated region (503) to form the restored layer (601), wherein the restored layer (601) results from the treated region (503). [2] The method of claim 1, wherein the restored layer (601) has a different density than the first dielectric layer (401). [3] The method of claim 1, wherein the plasma (501) comprises oxygen, nitrogen, fluorine or chlorine. [4] The method of claim 1, wherein the annealing (603) is performed at a temperature between about 500°C and about 1000°C for a duration between about 10 seconds and about 1 hour. [5] The method of claim 1, wherein the annealing is carried out in an oxygen environment. [6] The method of any preceding claim, wherein the restored layer (601) has a first thickness (D2), the first dielectric layer (401) has a second thickness (T1), and the first thickness (D2) is between 5% and 30% of the second thickness (T1). [7] The method of any preceding claim, further comprising patterning the gate electrode material into a first gate electrode (903) over the restored layer (601) and a second gate electrode (901) over the second dielectric layer (801), wherein the first gate electrode (903) has a greater width (W2) than the (W1) second gate electrode (901). [8] A method of manufacturing a semiconductor device, comprising: blanket depositing a first dielectric layer (401) over a first region (105) of a substrate (101) and a second region (107) of the substrate (101); Exposing an upper surface of the first dielectric layer (401) to a first plasma (501) to a depth of 10% to 50% into the first dielectric layer (401) such that a treated region (503) is formed in the first dielectric layer (401) over an untreated region (505) of the first dielectric layer (401), the untreated region (505) of the first dielectric layer (401) remaining between the treated region (503) and the semiconductor substrate (101); Restoring the treated region (503) with a first annealing process such that a restored region (601) is formed over the untreated region (505), the restored region (601) resulting from the treated region (503); Removing the first dielectric layer (401) from the first region (105); Forming a second dielectric layer (801) in the first region (105); Forming a first gate electrode (903) over the first dielectric layer (401) in the second region (107); and Forming a second gate electrode (901) over the second dielectric layer (801) in the first region (105). [9] The method of claim 8, further comprising replacing the first gate electrode (903) and the second gate electrode (901). [10] The method of claim 8, wherein the first plasma (501) comprises an oxygen plasma. [11] The method of claim 8, wherein the first plasma (501) comprises a chlorine plasma. [12] The method of claim 8, wherein the first plasma (501) comprises a nitrogen plasma. [13] The method of any one of claims 8 to 12, wherein a first thickness (D2) of the restored region (601) is less than 30% of a second thickness (T1) of the first dielectric layer (401). [14] Method according to one of claims 8 to 13, wherein the first region (105) is a logic region and the second region (107) is an analog region. [15] A semiconductor device comprising: a logic device located in a logic area (105) of a substrate (101), the logic device comprising: a first dielectric layer (801) having a constant density over the entire first dielectric layer (801); and a first gate electrode (901) overlying the first dielectric layer (801); and an analog device located in an analog region (107) of the substrate (101), the analog device comprising: a second dielectric layer (401), wherein the second dielectric layer (401) has a restored region (601) and an untreated region (505), wherein the untreated region (505) lies between the restored region (601) and the substrate (101), and wherein the restored region (601) has a different density than the untreated region (505); and a second gate electrode (903) lying over the second dielectric layer (401), wherein the restored region (601) has a first thickness (D2), the second dielectric layer (401) has a second thickness (T1), and the first thickness (D2) is between 10% and 50% of the second thickness (T1). [16] The semiconductor device of claim 15, wherein a first upper surface of the first gate electrode (901) is located at a first distance (D2) from the substrate (101), and wherein a second upper surface of the second gate electrode (903) is located at a second distance (D3) from the substrate (101), the second distance (D3) being greater than the first distance (D2). [17] The semiconductor device of claim 15, wherein a first upper surface of the first gate electrode (901) is located a first distance from the substrate, and wherein a second upper surface of the second gate electrode (903) is located a first distance from the substrate. [18] The semiconductor device according to any one of claims 15 to 17, further comprising a first high-k dielectric layer between the second dielectric layer (401) and the second gate electrode (903), the first high-k dielectric layer extending along a plurality of sides of the second gate electrode (903). [19] The semiconductor device of any one of claims 15 to 17, further comprising a first high-k dielectric layer between the second dielectric layer (401) and the second gate electrode (903), the second gate electrode (903) being in physical contact with a spacer. [20] A semiconductor device according to any one of claims 15 to 19, wherein the second gate electrode (903) has a width (W2) greater than that (W1) of the first gate electrode (901).

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