Semiconductor structures with defect prevention structures between a single substrate integrated semiconductor-on-insulator (SOI) region and a bulk region

Abstract

Comprehensive structure: a semiconductor-on-insulator region, SOI region, (200) and a bulk region (100, 300, 400) integrated into a single substrate (12); at least one active device in the bulk region (100, 300, 400); at least one active device in the SOI region (200); a shallow trench isolation structure (16) between the SOI region (200) and the bulk region (100, 300, 400); and a defect prevention structure (15) adjacent to the SOI region (200), wherein the defect prevention structure (15) comprises a semiconductor material extending within the shallow trench isolation structure (16).

Description

FIELD OF THE INVENTION

[0001] The present disclosure relates to semiconductor structures and, more particularly, to semiconductor structures having defect prevention structures between a semiconductor-on-insulator (SOI) region integrated in a single substrate and a bulk region, and to manufacturing methods. BACKGROUND

[0002] Silicon-on-insulator (SOI) substrates comprising a fully depleted SOI (FDSOI) or a radio frequency SOI (RFSOI) are used for various integrated circuit (IC) applications. SOI substrates comprise a thin surface crystalline or silicon layer separated from the bulk substrate by a buried oxide (BOX).

[0003] Typically, IC applications include high-voltage (HV) transistors, such as extended-drain metal oxide semiconductor (EDMOS) transistors. However, the thin surface substrate of SOI substrates is not conducive to accommodating HV transistors, such as EDMOS. This results in difficulties in integrating HV transistors on SOI substrates with other devices, such as SOI devices. For example, conventional techniques for integrating HV transistors on SOI substrates require complex processing to make them compatible with other devices. However, this complex processing results in increased costs. Also, such integration schemes can lead to defects in the active Si region, such as the channel region, of the SOI devices due to oxygen diffusion during the formation of the gate oxides for the HV or medium-voltage (MV) transistors.

[0004] US Pat. No. 8,815,701 B2 discloses a semiconductor device structure comprising an SOI substrate having a carrier layer, an oxide film, and an SOI layer in a first region and only the carrier layer in a second region. The two regions are separated from each other by trench elements. High-power circuits can be formed in the first region, and low-power circuits in the second region.

[0005] Furthermore, US 2017 / 0 287 773 A1 discloses a semiconductor structure comprising at least two semiconductor device layers stacked vertically. The first semiconductor device layer is formed on a bulk substrate and may include an ESD protection circuit; the second semiconductor device layer 24 may include a logic circuit. The at least two semiconductor device layers are formed by bonding an SOI substrate to the surface of a bulk substrate. BRIEF SUMMARY

[0006] In one aspect of the disclosure, a structure comprises: a semiconductor-on-insulator (SOI) region and a bulk region integrated in a single substrate; at least one active device in the bulk region; at least one active device in the SOI region; a shallow trench isolation structure between the SOI region and the bulk region; and a defect prevention structure adjacent to the SOI region, wherein the defect prevention structure comprises a semiconductor material extending within a shallow trench isolation structure.

[0007] In one aspect of the disclosure, a structure comprises: a semiconductor-on-insulator (SOI) region comprising at least one active SOI device; a bulk region integrated with the SOI region and comprising at least one active bulk device different from the at least one active SOI device; and a guard ring structure comprising a bulk semiconductor material adjacent to the SOI region and adapted to prevent oxygen diffusion to an active channel of the SOI device in the SOI region.

[0008] In one aspect of the disclosure, a method comprises: forming a semiconductor-on-insulator (SOI) region and a bulk region from a single substrate; forming at least one active device in the bulk region; forming at least one active device in the SOI region; and forming a defect prevention structure adjacent to the SOI region, wherein the defect prevention structure comprises a semiconductor material extending within a shallow trench isolation structure formed between the SOI region and the bulk region. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The present disclosure is described in the following detailed description with reference to the aforementioned plurality of drawings by way of non-limiting examples of exemplary embodiments of the present disclosure. Fig. 1 shows a substrate having a defect prevention structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 2 shows an SOI technology and a bulk technology from the same substrate, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 3 illustrates a first gate dielectric material and a bird's beak in the defect prevention structure, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 4 illustrates a second gate dielectric material on a patterned first gate dielectric material and the bulk technology, among other features, and respective manufacturing processes in accordance with aspects of the present disclosure. Fig. 5 shows a patterned second dielectric material, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 6 shows gate materials on SOI technology and bulk technology for gate formation, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 7 shows patterned gate materials on SOI technology and bulk technology, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 8 shows different devices with partially silicided raised source and drain regions on SOI technology and bulk technology, among other features, and respective manufacturing processes according to aspects of the present disclosure. Fig. 9A-9C illustratively depict top-down views of different configurations of the defect prevention structure according to aspects of the present disclosure. DETAILED DESCRIPTION

[0010] The present disclosure relates to semiconductor structures, and more particularly, to co-integrated high voltage (HV) and medium voltage (MV) devices with defect prevention structures and fabrication methods. More particularly, the present disclosure relates to the co-integration of HV and MV field effect transistors (FETs) with fully depleted semiconductor-on-insulator (FDSOI) technologies and structures that prevent defects in the active regions of the FDSOI technologies, i.e., SOI / cSiGe devices. Advantageously, the integration scheme prevents defects in the active regions of the SOI devices during gate oxide processes for the HV and / or MV FETs, thereby allowing the migration of applications and / or circuits from older technologies to more current technology nodes.

[0011] In embodiments, the HV-FET and the MV-FET may be integrated on a same die (in bulk technology) with fully depleted MOSFET devices. In particular, the HV and MV-FETs may be integrated, for example, on bulk technologies with SOI technologies. In one example of this integration scheme, a defect prevention structure composed of a bulk material (e.g., a Si material) may be provided at the boundary of the fully depleted MOSFET devices and the MV-FET and / or the HV-FET. From a top-down view, the bulk material (e.g., defect prevention structure) appears as a guard ring that either surrounds the fully depleted MOSFET devices or surrounds clusters of HV-FET and / or MV-FET devices. The defect prevention structure (e.g., a bulk Si material) prevents oxygen diffusion from eroding (e.g.,Causing defects) of the active region of the fully depleted MOSFET devices during gate oxide formation of the HV-FET and / or MV-FET.

[0012] The devices of the present disclosure can be fabricated in several ways using several different tools. Generally, however, the methodologies and tools are used to form structures with dimensions on the micrometer and nanometer scale. The methodologies, i.e., technologies, employed to fabricate the devices of the present disclosure have been adopted from integrated circuit (IC) technology. For example, the structures are fabricated on wafers and realized in material films that are patterned on top of a wafer by photolithographic processes. In particular, the fabrication of the devices uses three basic building blocks: (i) deposition of thin films of material on a substrate, (ii) application of a patterned mask on top of the films by photolithographic imaging, and (iii) etching the film selectively with respect to the mask.

[0013] Fig. Figure 1 shows a substrate with a defect prevention structure, among other features, and respective manufacturing processes. In particular, the structure 10 comprises Fig. 1 shows a substrate 12 comprising SOI technology. The substrate 12 may, as an example, be a fully depleted p-doped substrate. In embodiments, the substrate 12 comprises four separate regions for illustrative purposes: (i) a region 100 used for hybrid devices; (ii) a region 200 used for SOI / cSiGe devices; (iii) a region 300 used for MV-FET devices; and (iv) a region 400 used for HV-FET devices. As further described below, the substrate 12 for regions 100, 300 and 400 may be modified into a bulk wafer implementation, with a defect prevention structure 15 at a boundary of region 200 and / or region 300 and / or region 400, depending on the device fabrication (e.g., if region 300 is excluded).In embodiments, and as an illustrative and non-limiting example, the MV FET device may be an 8V FET; whereas the HV FET device may be a 20V FET.

[0014] In SOI technology, the substrate 12 comprises a semiconductor material 12c bonded or attached to an insulating layer 12b, and the insulator layer 12b bonded to a bulk wafer 12a, e.g., a bulk semiconductor material. The semiconducting material 12c may be bonded to the insulating layer 12b using wafer bonding techniques and / or other suitable methods. The insulator layer 12b may also be formed by any suitable process, such as separation by implantation of oxygen (SIMOX), oxidation, deposition, and / or another suitable process. The semiconductor materials 12a, 12c may comprise any suitable semiconductor material, e.g., Si, SiGeC, SiC, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors.The insulator layer 12b also comprises any suitable material, including silicon oxide, sapphire, other suitable insulating materials, and / or combinations thereof. An exemplary insulator layer 12b is a buried oxide (BOX) layer with a thickness of approximately 10-30 nm.

[0015] Still referring to Fig. 1, in region 200, a portion of the semiconductor material 12c may be subjected to a condensation process to form a channel region 14 of a different semiconductor material. For example, the channel region 14 may be SiGe created by SiGe condensation processes. The condensation process may be any condensation process known in the art. For example, germanium condensation may be demonstrated using a single-step or two-step wet oxidation of germanium implanted into the semiconductor material 12c. And, as should be apparent to those skilled in the art, Ge diffusion and accumulation vary with gas flow and temperature. In embodiments, a SiGe channel region 14 is used for pFET devices (e.g., cSiGe).

[0016] Fig. 1 further shows a plurality of shallow trench isolation structures 16. In embodiments, the shallow trench isolation structures 16 may be formed by conventional lithography, etching, and deposition techniques known to those skilled in the art. For example, a resist formed over the semiconductor material 12c is exposed to energy (light) to form a structure (opening). An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to form one or more trenches in the substrate 12 through the openings of the resist, extending into the bulk semiconductor material 12a. Following resist removal by a conventional oxygen ashing process or other known stripping means, an insulator material, e.g., an oxide, may be deposited by any conventional deposition process, e.g., chemical vapor deposition (CVD) processes.Any remaining material on the surface of the semiconductor material 12c, 14 can be removed by conventional chemical mechanical polishing (CMP) processes.

[0017] A defect prevention structure 15 may be provided at a boundary between the SOI region 200 and an adjacent bulk region, e.g., MV / HV device regions 300, 400. In more specific embodiments, the defect prevention structure 15 may be a bulk Si material extending through the shallow trench isolation structure 16, reaching the underlying substrate 12a. In alternative embodiments, the defect prevention structure 15 may be any semiconductor material capable of consuming an oxide.

[0018] The defect prevention structure 15 may be fabricated using conventional lithography, etching, and deposition techniques known to those skilled in the art, as previously described herein. For example, a resist formed over the structure is exposed to energy (light) to form a structure (opening) over the shallow trench isolation structure 16. An etching process with a selective chemistry, e.g., reactive ion etching (RIE), is used to provide a trench through the shallow trench isolation structure 16. The semiconductor material of the defect prevention structure 15 may be deposited within the trench using any conventional deposition process, including an epitaxial growth process, while other portions of a structure remain covered by a masking material to prevent epitaxial growth in undesired areas of the structure. Other known deposition processes are also contemplated herein.Any excess material can be removed by a planarization process, e.g. chemical mechanical polishing (CMP).

[0019] From a top-down view, the defect prevention structure 15 appears as a guard ring structure surrounding either the SOI device region 200 or the MV-FET device region 300 and / or the HV-FET device region 400, providing a barrier to oxygen diffusion. For example, in these different configurations, the defect prevention structure 15, e.g., a semiconductor material, prevents oxygen diffusion through the shallow trench isolation structure 16 and into the active channel region 14 of the devices within the region 200. As a result, the active channel region(s) 14 and / or 12a do not erode (become defective) during gate oxide formation for the devices in the regions 300, 400.

[0020] Still referring to Fig. 1, the substrate 12 may be subjected to an ion implantation process to form wells, particularly in regions 300 and 400. For example, region 300 for the MV-FET device may be subjected to an ion implantation process to create an N-well; whereas region 400 for the HV-FET device may be subjected to an ion implantation process to create both an N-well and a P-well. In embodiments, among other suitable examples, the P-well may be doped or implanted with p-type dopants, e.g., boron (B), and the N-well may be doped or implanted with n-type dopants, e.g., arsenic (As), phosphorus (P), and Sb.

[0021] In embodiments, the wells may be formed by introducing a concentration of a different dopant of an opposite conductivity type into the substrate 12. In embodiments, respective patterned implantation masks may be used to define selected regions exposed for the implantations. The implantation mask used to select the exposed region for forming the wells is stripped after implantation and before the implantation mask used to form other wells of a different type. The implantation masks may comprise a layer of a photosensitive material, such as an organic resist, applied by a spin-coating process, pre-baked, exposed to light projected through a photomask, baked after exposure, and developed with a chemical developer.Each of the implantation masks has a thickness and stopping power sufficient to block masked areas from receiving a dose of the implanted ions. Following the implantation process, an anneal may be performed to drive in the dopants, as will be understood by those skilled in the art.

[0022] In Fig. 2, the substrate 12 is subjected to a removal process, e.g., an etching process, to form a bulk semiconductor implementation in regions 100, 300, and 400. For example, after the implantation masks (and / or other masks) are removed, lithography and etching processes may be performed on the substrate 12 to remove the semiconductor material 12c and the insulator layer 12b in regions 100, 300, and 400. These processes expose the bulk semiconductor material 12a, creating a bulk implementation for hybrid devices, MV-FETs, and HV-FETs. In embodiments, the defect prevention structure 15, e.g., a bulk Si material, may be fabricated before or after the etching process that forms the bulk semiconductor implementation in regions 100, 300, and 400.

[0023] To form the bulk semiconductor implementation in regions 100, 300, and 400, a resist formed over semiconductor material 12c is exposed to energy (light) to form a structure (opening) over regions 100, 300, and 400. An etch process with a selective chemistry, e.g., RIE, is used to remove semiconductor material 12c and insulator layer 12b in regions 100, 300, and 400 while protecting region 200 (comprising channel region 14), thereby exposing bulk semiconductor material 12a in regions 100, 300, and 400. In this way, devices in regions 100, 300, and 400 can be fabricated in a bulk implementation, whereas devices in region 200 can be fabricated using SOI technologies. The resist can be removed using a conventional oxygen ashing process or other known stripping agents.

[0024] Following the etch processes, channel and extension region implants may be fabricated in regions 300 and 400. During the channel and extension region implants, regions 100 and 200 may be protected by a hard mask and / or stacks of resist materials. In this way, regions 100 and 200 are not subjected to the implant processes. Following the implantation process, the stacks of resist materials may be removed, as is known in the art. Regions 300 and 400 may also be cleaned of any masking material to expose the surface of the bulk semiconductor material 12a. As shown in Fig. 3, however, a hard mask 18 may remain on the semiconductor materials 12c, 14 in the regions 100 and 200 during the cleaning process.

[0025] Fig. 3 shows a first gate dielectric material and a resulting bird's beak 15a in the defect prevention structure 15, among other features. In particular, Fig. 3, an insulator material 20 is formed over the bulk semiconductor material 12a in regions 300 and 400, and over the hard mask 18 in regions 100 and 200. Prior to deposition of the insulator material 20, the exposed surface of the semiconductor material 12c may be cleaned, e.g., by wet processes such as RF chemistries known to those skilled in the art. The hard mask 18 protects surfaces of regions 100 and 200 during the cleaning process. In embodiments, the insulator material 20 may be a gate oxide material for the HV-FET device, e.g., region 400.

[0026] The insulator material 20 may be formed, e.g., deposited, by any conventional gate oxide deposition process, e.g., CVD, plasma vapor deposition (PVD), etc. Following the deposition process, the insulator material 20 may be subjected to a rapid thermal annealing process, as is known in the art. In embodiments, the bottom surface of the insulator material 20 may be aligned flush with the bottom surface of the insulator layer 12b. The insulator material 20 may be deposited to a thickness of up to about 45 nm; although other dimensions are contemplated herein. In preferred embodiments, the insulator material 20 is deposited to a thickness greater than the thickness of the insulator layer 12b.

[0027] As should be apparent to those skilled in the art, the insulator deposition process results in oxygen diffusion, which can erode the active channel region(s) 14 and / or 12a, e.g., for pFET or other MOSFET devices (e.g., cSiGe). This noted, the defect prevention structure 15, e.g., a bulk semiconductor material, eliminates the oxygen diffusion path into the active channel region of the SOI devices, thereby preventing erosion (defects) from occurring at the channel material, e.g., Si, SiGe, etc. For example, the semiconductor material of the defect prevention structure 15 can consume the oxygen during the oxidation process, forming a bird's beak 15a (e.g., an oxide region) extending inward from the shallow trench structure 16.In this way, the consumption of oxygen by the defect prevention structure 15 effectively prevents any erosion or defects from occurring in the semiconductor material of the active channel region(s) 14 and / or 12a of the SOI devices in the region 200.

[0028] In Fig. 4, the insulator material 20 is subjected to a patterning process, followed by a formation, e.g., deposition, of an insulator material 22 for the MV-FET device, e.g., in the region 300. In particular, as shown in Fig. As shown in Figure 4, the insulator material 20 is removed from regions 100, 200, and 300 using conventional lithography and etching processes, e.g., dry and wet etching processes. The insulator material 20 is also partially removed from region 400, leaving patterned insulator material 20 for an HV-FET device. Following resist removal, the exposed surfaces can be cleaned by RF solvents, e.g., with the hard mask 18 serving as an RF etch stop layer.

[0029] After the cleaning process, the insulator material 22 is formed, e.g., deposited, on the exposed surfaces of the insulator material 20 in region 400, the exposed surface of the bulk semiconductor material 12a in regions 300 and 400, and over the hard mask material 18 in regions 100 and 200. In embodiments, the insulator material 22 may surround the top and side surfaces of the insulator material 20 in region 400 for the HV-FET device. Furthermore, the bottom surfaces of both the insulator material 22 and the insulator material 20 may be aligned flush with the insulator layer 12b, e.g., a buried oxide layer of SOI technology. In embodiments, the insulator material 22 is a gate oxide material for the MV-FET device in region 300.

[0030] It is also contemplated that the defect prevention structure 15, e.g., a bulk semiconductor material, may block the oxygen diffusion path into the active region(s) 14 and / or 12a during this gate oxidation process. Again, the defect prevention structure 15 may consume the oxygen, resulting in a bird's beak structure 15a composed of an oxide material; whereas the active channel region(s) 14 and / or 12a are unaffected by the oxygen diffusion process.

[0031] The combination of insulator material 22 and insulator material 20 in region 400 may be thicker than insulator layer 12b, e.g., a buried oxide layer of SOI technology. For example, insulator material 22 may have a thickness of approximately 16.5 nm; although other dimensions are contemplated herein. Insulator material 22 may be deposited by any conventional gate oxide deposition process, e.g., CVD, PVD, etc., followed by a rapid thermal annealing process, as is known in the art.

[0032] In Fig. 5, the insulator material 22 is subjected to a patterning process for the MV-FET device, e.g., in the region 300, followed by removal of the hard mask in the regions 100 and 200. In particular, as shown in Fig. 5, the insulator material 22 is completely removed from regions 100 and 200, while it is patterned in regions 300 and 400 using conventional lithography and etching processes, e.g., dry and wet etching processes. As should be apparent to those skilled in the art, the pattern of the insulator materials 20, 22 in regions 300 and 400 is a result of the pattern of the resist material, i.e., preventing the removal of the insulator material 20, 22 in regions 300 and 400.

[0033] In region 300, the insulator material 22 may be partially removed, leaving the insulator material 22 for an MV-FET device. Also in region 400, the insulator material 22 may remain on the sides and top surface of the insulator material 20 for the HV-FET device. It should be understood that due to the resist structure, the insulator material 22 for the HV-FET device in region 400 may have a stepped feature or structure 23 (as shown in Fig. 5) and may also remain on portions of the exposed surface of the bulk semiconductor material 12a.

[0034] Fig. 5 further illustrates the removal of the hard mask 18 in regions 100 and 200. The hard mask 18 may be removed. Also, in embodiments, the exposed surfaces, e.g., semiconductor materials 12c, 14, may be subjected to a pre-cleaning process with a resist strip, as one example, to remove any native oxide on the surfaces of the semiconductor materials 12c, 14.

[0035] In Fig. 6, the gate patterning process for the hybrid devices, SOI devices, MV-FET devices, and HV-FET devices begins in each of the regions. Advantageously, each of the gate materials for each of the devices may be fabricated in the same processing steps. For example, a gate dielectric material 28 is deposited over the insulator material 22 for the MV-FET devices and HV-FET devices, while also being deposited over the semiconductor material 12c, 14 for the hybrid devices and SOI devices. In embodiments, the gate dielectric material 28 may be a high-k dielectric material, e.g., HfO2, Al2O3, Ta2O3, TiO2, La2O3, SrTiO3, LaAlO3, ZrO2, Y2O3, Gd2O3, and combinations comprising multilayers thereof.

[0036] Still referring to Fig. 6, a gate conductor material 30 may be deposited on the gate dielectric material 28. In embodiments, the gate conductor material 30 may include, for a gate-first process, work function metals and an optional Si layer that may be later silicided. Examples of work function materials for a p-channel FET include Ti, TiAlC, Al, TiAl, TaN, TaAlC, TiN, TiC, and Co. Examples of the work function materials for an n-channel FET include TiN, TaN, TaAlC, TiC, TiAl, TaC, Co, Al, TiAl, HfTi, TiSi, TaSi, or TiAlC. The work function materials may be formed by CVD, PVD including sputtering, atomic layer deposition (ALD), or another suitable method. A capping material (e.g., SiN) 32 is deposited on the gate conductor material 30 using any conventional deposition technique.As should be clear to those skilled in the art, the capping material 32 is used as a sidewall spacer.

[0037] In Fig. 7, the gate structures are subjected to a patterning process to form, for example, hybrid devices 36, SOI devices 38, MV-FET devices 40, and HV-FET devices 42. For example, the capping material 32, gate conductor material 30, and gate dielectric material 28 are removed from horizontal surfaces of the devices, exposing the semiconductor materials 12a, 12c, 14. In this gate patterning process, a different capping material 33 may remain on the sidewalls of each of the devices 36, 38, 40, 42 after the gate patterning process. This patterning process may define the devices 36, 38, 40, 42.

[0038] After defining each of the devices 36, 38, 40, 42, source and drain regions 34 may be formed on the exposed semiconductor materials 12a, 12c, 14. In embodiments, the source and drain regions 34 may be raised source and drain regions formed by doped epitaxial growth processes directly on the respective exposed semiconductor materials 12a (for the hybrid devices 36, MV-FET devices 40, and HV-FET devices 42) and the semiconductor materials 12c, 14 (for the SOI devices 38). The capping material 32 is then removed to expose the gate conductor material 20.

[0039] As further stated in Fig. As shown in Figure 8, a liner 43 is deposited over the capping material 32, exposed conductor material 20, and the source and drain regions 34. In embodiments, the liner is a silicide blocking material that prevents silicide from forming on the top surface of the source and drain regions 34. After partially removing the liner 43 to expose the conductor material 20 and the sides of the source and drain regions 34, a silicide 44 is formed on the exposed conductor material 20 and the source and drain regions 34.

[0040] As should be apparent to those skilled in the art, the silicide process begins with a deposition of a thin transition metal layer, e.g., nickel, cobalt, or titanium, over fully formed and patterned semiconductor devices (e.g., doped or ion-implanted source and drain regions and respective devices). After deposition of the material, the structure is heated, allowing the transition metal to react with exposed silicon (or another semiconductor material as described herein) in the active regions of the semiconductor device (e.g., source, drain, gate contact region), forming a low-resistance transition metal silicide. Following the reaction, any remaining transition metal is removed by chemical etching, leaving silicide contacts 44 in the active regions of the device.It should be clear to those skilled in the art that silicide contacts on the devices are not required when a gate structure is composed of a metal material.

[0041] A liner 46 is deposited over each of the devices 36, 38, 40, 42 in addition to the source and drain regions 34. In embodiments, the liner 46 may be a tensile stress liner composed of a tensile material, e.g., a nitride. An interlevel dielectric material 48 is deposited over the devices by CVD deposition followed by a CMP process. Although not shown in this view, contacts to the devices 36, 38, 40, 42 and the source and drain regions 34 are formed using conventional lithography, etching, and deposition processes, as known to those skilled in the art, so no further explanation is required for a complete understanding of the present disclosure.

[0042] It is also in Fig. 8 shows that each of the devices 36, 38, 40, and 42 includes different absolute heights. This is due to the different materials and manufacturing processes used to fabricate these different devices. For example, device 42 includes two layers of gate oxide material 20, 24; whereas device 40 includes one layer of gate oxide material 20, and device 36 includes no gate oxide. Also, devices 38 are fabricated on SOI wafer 12 (e.g., semiconductor material 12a, 14) without the use of gate oxide material; whereas devices 36, 40, 42 are fabricated on bulk wafers.

[0043] Fig. 9A-9C show illustrative top-down views of different configurations of the defect prevention structure 15. In particular, Fig. 9A shows that the defect prevention structure 15 surrounds the SOI device, ie, the region 200 used for SOI / cSiGe devices. In Fig. 9B shows that the defect prevention structure 15 surrounds the region 300 used for MV-FET devices. In Fig.9C shows that the defect prevention structure surrounds both region 300 and region 400 used for HV-FET devices. It should be understood that regions 200, 300, and 400 are representative of a single device or a cluster of devices. It should also be understood that defect prevention structure 15 may surround region 200 with any combination of regions 300 and 400. In each of these different configurations, defect prevention structure 15 acts as a guard ring surrounding region 200 such that the oxygen diffusion path is blocked, which in turn prevents erosion of the active channel region 14, e.g., Si, SiGe, etc., of the devices in region 200 during the gate oxide fabrication process for devices in regions 300, 400.

[0044] The devices described herein can be used in system-on-chip (SoC) technology. It should be clear to those skilled in the art that SoC is an integrated circuit (also known as a "chip") that integrates all the components of an electronic system onto a single chip or substrate. Because the components are integrated onto a single substrate, SoCs consume much less power and occupy much less space than multi-chip designs with equivalent functionality. For this reason, SoCs are becoming the dominant force in the mobile computing (such as smartphones) and edge computing markets. SoCs are also commonly used in embedded systems and the Internet of Things.

[0045] The process(es) described above is(are) used in the fabrication of integrated circuit chips. The resulting integrated circuit chips may be distributed by the manufacturer in raw wafer form (i.e., a single wafer containing multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single-chip assembly (such as a plastic carrier with leads attached to a motherboard or other higher-level carrier) or in a multi-chip assembly (such as a ceramic carrier containing one or both surface interconnects or buried interconnects). In either case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product, such as a motherboard, or (b) a final product.The end product can be any product that includes integrated circuit chips, ranging from toys and other low-end applications to advanced computer products that include a display, a keyboard or other input device, and a central processor.

Claims

[1] Structure comprising: a semiconductor-on-insulator, SOI region (200) and a bulk region (100, 300, 400) integrated in a single substrate (12); at least one active device in the bulk region (100, 300, 400); at least one active device in the SOI region (200); a shallow trench isolation structure (16) between the SOI region (200) and the bulk region (100, 300, 400); and a defect prevention structure (15) adjacent to the SOI region (200), wherein the defect prevention structure (15) comprises a semiconductor material extending within the shallow trench isolation structure (16). [2] The structure of claim 1, wherein the semiconductor material of the defect prevention structure (15) comprises a bulk semiconductor material extending within a shallow trench isolation structure (16). [3] The structure of claim 2, wherein the bulk semiconductor material extends through the shallow trench isolation structure (16) and reaches to a same semiconductor material of the SOI region (200) and the bulk region (100, 300, 400). [4] The structure of claim 2 or 3, wherein the bulk semiconductor material is a bulk Si material. [5] Structure according to one of claims 1 to 4, wherein the defect prevention structure (15) comprises an oxidized bird's beak structure (15a). [6] The structure of any one of claims 1 to 5, wherein the defect prevention structure (15) comprises a guard ring surrounding the SOI region (200). [7] Structure according to one of claims 1 to 5, wherein the defect prevention structure (15) comprises a guard ring surrounding the bulk region (100, 300, 400). [8] The structure of any one of claims 1 to 7, wherein the at least one device in the bulk region (100, 300, 400) comprises at least one high-voltage transistor (42) and the defect prevention structure (15) comprises a guard ring surrounding the at least one high-voltage transistor (42). [9] The structure of any one of claims 1 to 7, wherein the at least one device in the bulk region (100, 300, 400) comprises at least one medium voltage transistor (40) and the defect prevention structure (15) comprises a guard ring surrounding the at least one medium voltage transistor (40). [10] The structure of any one of claims 1 to 7, wherein the at least one device in the bulk region (100, 300, 400) comprises at least one medium voltage transistor (40) and at least one high voltage transistor (42), and the defect prevention structure (15) comprises a guard ring surrounding both the at least one medium voltage transistor (40) and the at least one high voltage transistor (42). [11] Structure comprising: a semiconductor-on-insulator, SOI region (200) comprising at least one active SOI device; a bulk region (100, 300, 400) integrated with the SOI region (200) and comprising at least one active bulk device different from the at least one active SOI device; and a guard ring structure comprising a bulk semiconductor material adjacent to the SOI region (200) and adapted to prevent oxygen diffusion to an active channel of the SOI device in the SOI region (200). [12] The structure of claim 11, wherein the bulk semiconductor material extends through a shallow trench isolation structure (16) adjacent to the SOI region (200) and the bulk region (100, 300, 400). [13] The structure of claim 11 or 12, wherein the bulk semiconductor material comprises a bulk Si material. [14] A structure according to any one of claims 11 to 13, wherein the guard ring structure comprises a bird's beak structure (15a) composed of an oxide. [15] The structure of any one of claims 11 to 14, wherein the guard ring structure surrounds the at least one active SOI device. [16] The structure of any one of claims 11 to 14, wherein the guard ring structure surrounds the at least one active bulk device. [17] The structure of any one of claims 11 to 14, wherein the at least one bulk device comprises a high voltage transistor (42) and a medium voltage transistor (40) and the guard ring structure surrounds both the high voltage transistor (42) and the medium voltage transistor (40). [18] The structure of any one of claims 11 to 17, wherein the bulk semiconductor material is positioned and adapted to prevent oxygen diffusion through a shallow trench isolation structure (16) to the at least one active SOI device. [19] Procedure comprising: Forming a semiconductor-on-insulator, SOI region, (200) and a bulk region (100, 300, 400) from a single substrate (12); Forming at least one active device in the bulk region (100, 300, 400); Forming at least one active device in the SOI region (200); and Forming a defect prevention structure (15) adjacent to the SOI region (200), wherein the defect prevention structure (15) comprises a semiconductor material extending within a shallow trench isolation structure (16) formed between the SOI region (200) and the bulk region (100, 300, 400).

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