DISPLAY PANEL AND DISPLAY DEVICE USING THE SAME

Abstract

A display panel, featuring: a first metal layer (ML1) which has a VDD conductor structure (M11), a bottom-gate electrode structure (M12) and a data conductor structure (M13); a first insulating layer (BUF) that covers the first metal layer (ML1); a semiconductor layer (ACT) that is arranged on top of the first insulating layer (BUF); a second insulating layer (Gl) that is arranged on top of the first insulating layer (BUF) and covers the semiconductor layer (ACT); a second metal layer (ML2) arranged on top of the second insulating layer (GI); a third insulating layer (PAS) arranged on top of the first insulating layer (BUF) in such a way that it covers the second metal layer (ML2) and the semiconductor layer (ACT); and a planarization layer (OC) arranged on the third insulating layer (PAS), wherein the bottom-gate electrode structure (M12) comprises a bottom-gate electrode (GE2) of a control element (DT) and a bottom electrode (CE1) of a storage capacitor (Cst), wherein the second metal layer (ML2) has a top-gate electrode (GE1) of the control element (DT) which is connected to the bottom-gate electrode (GE2) by means of a first contact hole (CH1) passing through the second insulating layer (GI) and the first insulating layer (BUF), and wherein the semiconductor layer (ACT) has a semiconductor channel of the control element (DT) that overlaps the top-gate electrode (GE1) and the bottom-gate electrode (GE2), the display panel further featuring: a first slot (SL1) from which the planarization layer (OC), the third insulating layer (PAS), the second insulating layer (GI) and the first insulating layer (BUF) are separated between a long side of the bottom-gate electrode structure (M12) and the data line structure (M13).

Description

BACKGROUND1. Area

[0001] The present disclosure relates to a display panel and a display device using the same. 2. Discussion of the related technology

[0002] Electroluminescent display devices can be roughly divided into inorganic light-emitting display devices and organic light-emitting display devices depending on the material of the emission layer. The active matrix type organic light-emitting display device includes an organic light-emitting diode (hereinafter referred to as "OLED") that emits light itself, and has the advantages of high response speed, good luminous efficiency and brightness, and a wide viewing angle. In the organic light-emitting display device, an organic light-emitting diode (OLED) is formed in each pixel.The organic light-emitting display device has a high response speed, is excellent in luminous efficiency, brightness and viewing angle, and provides excellent contrast ratio and color reproduction because it can express black gradations in complete black.

[0003] The organic light-emitting display device does not require a backlight unit and can be implemented on a plastic substrate, a thin glass substrate, or a metal substrate, which is a flexible material. Therefore, the flexible display can be implemented as an organic light-emitting display device.

[0004] Each pixel of an organic light-emitting display device has a drive element that drives a light-emitting element. The drive element supplies a current to the light-emitting element according to the gate-source voltage Vgs. Various methods are used to increase the current-carrying capacity of the drive element.

[0005] Crosstalk may occur due to parasitic capacitance between signal / power supply lines formed in the pixel matrix.

[0006] A pixel circuit can be formed in each of the pixels. The pixel circuit has a structure in which a plurality of thin-film layers comprising metal layers and insulating layers are stacked. Due to a large number of contact holes penetrating the insulating layers and connecting metal layers or metal layers and semiconductor layers at main nodes, it is difficult to design a pixel circuit that can increase the aperture ratio of pixels.

[0007] US 2019 / 0 027 092 A1 describes a display device with pixels, an auxiliary pixel, a control device and an emission driver, wherein the pixels are coupled to data lines and emission control lines, wherein the auxiliary pixel is coupled to an auxiliary data line and auxiliary emission control lines, wherein the control device is configured to measure an auxiliary current supplied from the auxiliary pixel via an auxiliary line and to control the width of an emission start signal based on a summation of the auxiliary current, and wherein the emission driver is configured to supply emission control signals to the pixels and the auxiliary pixel via the emission control lines and the auxiliary emission control lines based on the emission start signal.

[0008] US 2020 / 0286927 A1 describes a display device having a plurality of pixels, each coupled to scan lines and data lines crossing the scan lines, wherein at least some of the pixels comprise a drive transistor having a substrate, a first insulating layer arranged on the substrate, a first active layer arranged on the first insulating layer, a first gate electrode arranged on the first active layer, and a first source electrode and a first drain electrode electrically connected to the first active layer, the first drain electrode being arranged at a distance from the first source electrode, and a switching transistor having a second gate electrode arranged between the substrate and the first insulating layer, a second active layer arranged on the same layer as the first active layer,and a second source electrode and a second drain electrode electrically connected to the second active layer, wherein the second drain electrode is spaced from the second source electrode by a second distance different from the first distance. OVERVIEW

[0009] Accordingly, the present disclosure is intended to solve the above-mentioned need and / or problem.

[0010] The present disclosure provides a display panel that can improve the current carrying capacity of a driving element, prevent crosstalk, and reduce the number of required contact holes, and a display device using the same.

[0011] The present disclosure is not limited to the above-mentioned need and / or problem, and further features of the present disclosure will become apparent to those skilled in the art from the following descriptions.

[0012] In accordance with one aspect of the present disclosure, there is provided a display panel according to claim 1. Furthermore, in accordance with another aspect of the present disclosure, there is provided a display panel according to claim 10 and a display device according to claim 13. Further aspects are described in the dependent claims.

[0013] In one aspect of the present disclosure, there is provided a display panel comprising: a first metal layer having a VDD line pattern, a bottom gate electrode pattern, and a data line pattern; a first insulating layer covering the first metal layer; a semiconductor layer disposed on the first insulating layer; a second insulating layer disposed on the first insulating layer to cover the semiconductor layer; and a second metal layer disposed on the second insulating layer; a third insulating layer disposed on the first insulating layer to cover the second metal layer and the semiconductor layer; and a planarization layer disposed on the third insulating layer.The bottom gate electrode structure includes a bottom gate electrode of a drive element and a bottom electrode of a storage capacitor. The second metal layer includes a top gate electrode of the drive element, which is connected to the bottom gate electrode through a first contact hole penetrating the second insulating layer and the first insulating layer. The semiconductor layer includes a semiconductor channel of the drive element that overlaps the top gate electrode and the bottom gate electrode. The display panel further includes a first slot from which the planarization layer, the third insulating layer, the second insulating layer, and the first insulating layer are spaced between a longitudinal side of the bottom gate electrode structure and the data line structure.

[0014] In accordance with one or more aspects of the present disclosure, the display panel further comprises a pixel circuit connected to a data line supplied with a data voltage, a gate line supplied with a gate signal, a VDD line supplied with a pixel drive voltage, and a REF line supplied with a reference voltage.

[0015] In accordance with one or more aspects of the present disclosure, the pixel circuit includes a first switching element configured to apply the data voltage to the top gate electrode and the bottom gate electrode of the drive element in response to the gate signal, a second switching element configured to apply the reference voltage to a source electrode of the drive element in response to the gate signal, and a light-emitting element driven by the drive element, wherein the pixel drive voltage is applied to a drain electrode of the drive element.

[0016] In accordance with one or more aspects of the present disclosure, the first metal layer further comprises a first-first current line structure to which the pixel drive voltage is applied, wherein the bottom electrode of the capacitor is connected to the bottom gate electrode, wherein the data line structure includes the data line, and wherein the second metal layer includes a top gate electrode structure including the top gate electrode of the drive element and a top electrode of the capacitor connected to the top gate electrode and overlapping the first contact hole, and a gate line structure including the gate line.

[0017] In accordance with one or more aspects of the present disclosure, the semiconductor layer includes a first semiconductor structure including the semiconductor channel of the driving element, an intermediate electrode of the capacitor connected to the semiconductor channel of the driving element, the source electrode and the drain electrode of the driving element, a semiconductor channel of the second switching element, a source electrode and a drain electrode of the second switching element, and a first-second current line through which the pixel driving voltage is applied and which overlaps a second contact hole, and a second semiconductor structure including a semiconductor channel of the first switching element, a source electrode and a drain electrode of the first switching element, and overlaps the first contact hole, wherein the first-first current line and the first-second current line cross each other with the first insulating layer interposed therebetween.

[0018] In accordance with one or more aspects of the present disclosure, an anode electrode of the light-emitting element is connected to the first semiconductor structure through the second contact hole, wherein the second contact hole penetrates the planarization layer and the third insulating layer such that the first semiconductor structure is exposed, and wherein a portion of the first semiconductor structure connected to the anode electrode within the second contact hole is a metallized portion of the semiconductor layer or a metal layer formed on the semiconductor layer.

[0019] In accordance with one or more aspects of the present disclosure, the anode electrode of the light-emitting element covers a side surface and a bottom surface of the first slot.

[0020] In accordance with one or more aspects of the present disclosure, a length of the first slot is substantially the same as a length of the long side of the bottom gate electrode structure.

[0021] In accordance with one or more aspects of the present disclosure, the display panel further comprises a second slot from which the first insulating layer and the second insulating layer are removed between the long side of the bottom gate electrode structure and the first-first power line structure, and wherein the third insulating layer covers a side surface and bottom surface of the second slot.

[0022] In accordance with one or more aspects of the present disclosure, a length of the second slot is substantially the same as a length of the other long side of the bottom gate electrode structure.

[0023] In one aspect of the present disclosure, a display panel is provided, comprising: a driving element for supplying a current to a light-emitting element; a first switching element for connecting a data line through which a data voltage is applied to a gate electrode of the driving element in response to a gate signal from a gate line; a second switching element for applying a reference voltage to a source electrode of the driving element in response to the gate signal; and a capacitor connected between the gate electrode of the driving element and the source electrode of the driving element. The gate electrode of the driving element has a top gate electrode and a bottom gate electrode, the top gate electrode overlapping the bottom gate electrode with a semiconductor layer having a semiconductor channel interposed therebetween.The top gate electrode contacts the bottom gate electrode through a first contact hole that penetrates a first insulating layer between the bottom gate electrode and the semiconductor layer and a second insulating layer between the top gate electrode and the semiconductor layer. The anode electrode of the light-emitting element contacts the semiconductor layer through a second contact hole that penetrates a third insulating layer covering the drive element and the switching elements and a planarization layer disposed on the third insulating layer. The display panel further includes a first slot from which the planarization layer, the third insulating layer, the second insulating layer, and the first insulating layer between the bottom gate electrode and the data line are removed.

[0024] In accordance with one or more aspects of the present disclosure, the anode electrode of the light-emitting element covers a side surface and a bottom surface of the first slot.

[0025] In accordance with one or more aspects of the present disclosure, the display panel further comprises a power line through which a pixel driving voltage is applied, and a second slot from which the first insulating layer and the second insulating layer between the bottom gate electrode and the power line are removed, wherein the third insulating layer covers a side surface and a bottom surface of the second slot.

[0026] In one aspect of the present disclosure, a display device is provided, comprising: a display panel in which a plurality of data lines, a plurality of gate lines crossing the data lines, a plurality of first power lines through which a pixel drive voltage is applied, a plurality of second power lines through which a reference voltage is applied, and a plurality of pixels are arranged; a data driver configured to supply a data voltage of pixel data through the data lines; and a gate driver configured to supply a gate signal through the gate lines, wherein each of the pixels comprises: a drive element configured to supply a current to a light-emitting element; a first switching element configured to connect the data line,by which, in response to the gate signal from the gate line, the data voltage is applied to a gate electrode of the drive element; a second switching element configured to apply, in response to the gate signal, the reference voltage, which is lower than the pixel drive voltage, to a source electrode of the drive element; and a capacitor connected between the gate electrode of the drive element and the source electrode of the drive element, wherein the gate electrode of the drive element has a top gate electrode and a bottom gate electrode, wherein the top gate electrode overlaps the bottom gate electrode, with a semiconductor layer having a semiconductor channel interposed therebetween, wherein the top gate electrode is connected through a first contact hole,which penetrates a first insulating layer between the bottom gate electrode and the semiconductor layer and a second insulating layer between the top gate electrode and the semiconductor layer, touching the bottom gate electrode, and wherein an anode electrode of the light-emitting element touches the semiconductor layer through a second contact hole which penetrates a third insulating layer covering the drive element and the first switching element and the second switching element, and a planarization layer disposed on the third insulating layer. The display device further includes a first slot from which the planarization layer, the third insulating layer, the second insulating layer, and the first insulating layer between the bottom gate electrode and the data line are removed.

[0027] In accordance with one or more aspects of the present disclosure, the anode electrode of the light-emitting element covers a side surface and a bottom surface of the first slot.

[0028] In accordance with one or more aspects of the present disclosure, the display device further comprises a second slot from which the first insulating layer and the second insulating layer between the bottom gate electrode and the first power line are removed, wherein the third insulating layer covers a side surface and a bottom surface of the second slot.

[0029] The present disclosure can improve the current carrying capacity of a driving element by implementing the gate electrode of the driving element that drives a light-emitting element in a double-gate structure.

[0030] In the present disclosure, the number of contact holes connecting main nodes of a pixel circuit can be reduced by optimizing the planar structure and cross-sectional structure of the pixel circuit. As a result, the present disclosure can reduce the aperture ratio loss due to contact holes arranged in the pixel circuit.

[0031] In the present disclosure, in order to remove the parasitic capacitance between the adjacent bottom gate electrode and the data line, a slit covered by the anode electrode is formed between the bottom gate electrode of the driving element and the data line, thereby preventing crosstalk.

[0032] In the present disclosure, a slit is formed between the bottom gate electrode of a driving element and the data line to thereby prevent a short circuit between the adjacent bottom gate electrode and the data line and remove the parasitic capacitance.

[0033] Effects that can be achieved by means of the present disclosure are not limited to the effects mentioned above. This means that other features not mentioned can be clearly understood by those skilled in the art to which the present disclosure pertains from the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other features and advantages of the present disclosure will become more apparent to those skilled in the art by describing in detail exemplary aspects thereof with reference to the accompanying drawings in which: Fig. 1 is a block diagram schematically illustrating a display device according to one aspect of the present disclosure; Fig. 2 is a circuit diagram illustrating an example of a pixel circuit; Fig. 3 is a cross-sectional view schematically illustrating a cross-sectional structure of the pixel circuit in the display device according to an aspect of the present disclosure; Fig. 4 is a plan view illustrating a pixel circuit of a sub-pixel in a display panel according to a comparative example; Fig. 5 is a cross-sectional view showing a cross-sectional structure of the pixel circuit taken along line II' of Fig. 4 represents; Fig. 6 is a plan view showing the structures of a first metal layer formed in Fig. 3 is shown, represents; Fig. 7 is a plan view showing the structures of a semiconductor layer and a third metal layer formed in Fig. 5; Fig. 8 is a plan view showing the structures of a Fig. 3 represents the second metal layer; Fig. 9 is a plan view showing the anode electrode of a Fig. 4; Fig. 10 is a plan view illustrating a pixel circuit of a subpixel in a display panel according to an aspect of the present disclosure; Fig. 11 is a cross-sectional view showing a cross-sectional structure of the pixel circuit taken along line II-II' of Fig. 10; and Fig. 12 is a plan view showing the structures of a first metal layer formed in Fig. 10 is shown. DETAILED DESCRIPTION

[0035] The advantages and features of the present disclosure, and methods for achieving the same, will become more clearly understood from aspects described below with reference to the accompanying drawings. Rather, these aspects will complement the disclosure of the present disclosure and will allow those skilled in the art to fully understand the scope of the present disclosure.

[0036] The shapes, sizes, ratios, angles, numbers, and the like illustrated in the accompanying drawings for describing aspects of the present disclosure are merely examples, and the present disclosure is not limited thereto. Like reference numerals generally refer to like elements throughout the present application. Furthermore, in describing the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0037] Terms used herein, such as "comprise," "include," and "have," are generally intended to allow for the addition of additional components, unless these terms are used with the term "only." Any singular designation may include the plural, unless expressly stated otherwise.

[0038] Components are interpreted to have a common error range, even if this is not explicitly stated.

[0039] When the spatial relationship between two components is described using terms such as "on", "above", "below", and "adjacent", one or more components may be located between the two components, except when the terms are used with the term "immediate" or "direct".

[0040] The terms "first", "second", and the like may be used to distinguish components from one another, but the functions or structures of the components are not limited by ordinal numbers or component names in front of the components.

[0041] The same reference numerals may refer to substantially the same elements throughout the present disclosure.

[0042] The following aspects may be partially or completely bonded or combined with each other and may be interconnected and operated in various technical ways. The aspects may be executed independently of or in relation to each other.

[0043] In a display device of the present disclosure, a pixel circuit may include at least one of an n-channel transistor and a p-channel transistor. Transistors may be implemented as oxide thin-film transistors (oxide TFTs) including an oxide semiconductor, low-temperature polysilicon (LTPS) TFTs including a low-temperature polysilicon, or the like. Furthermore, each of the transistors may be implemented as a p-channel TFT or an n-channel TFT. In aspects, descriptions will be given based on an example in which the transistors of the pixel circuit are implemented as the p-channel TFTs, but the present disclosure is not limited thereto.

[0044] A transistor is a three-electrode device that has a gate, a source, and a drain. The source is an electrode that supplies charge carriers to the transistor. In the transistor, charge carriers begin to flow from the source. The drain is an electrode through which charge carriers exit the transistor. In a transistor, charge carriers flow from a source to a drain. In the case of an n-channel transistor, since charge carriers are electrons, a source voltage is a voltage lower than a drain voltage, so that electrons can flow from a source to a drain. The n-channel transistor has a direction of current flowing from the drain to the source. In the case of a p-channel transistor (p-channel metal oxide semiconductor (PMOS)), since charge carriers are holes, a source voltage is higher than a drain voltage, so that holes can flow from a source to a drain.In the p-channel transistor, since holes flow from the source to the drain, a current flows from the source to the drain. Note that a source and a drain of a transistor are not fixed. For example, a source and a drain may be changed according to an applied voltage. Therefore, the present disclosure is not limited by a source and a drain of a transistor. In the following description, a source and a drain of a transistor will be referred to as a first electrode and a second electrode.

[0045] A gate signal oscillates between a gate-on voltage and a gate-off voltage. The gate-on voltage is set to a voltage higher than a transistor's threshold voltage, and the gate-off voltage is set to a voltage lower than the transistor's threshold voltage. A transistor is turned on in response to a gate-on voltage and turned off in response to a gate-off voltage. In the case of an n-channel transistor, a gate-on voltage may be a gate-high voltage VGH, and a gate-off voltage may be a gate-low voltage VGL. In the case of a p-channel transistor, a gate-on voltage may be the gate-low voltage VGL, and a gate-off voltage may be the gate-high voltage VGH.

[0046] The driving element of the pixel circuit may be implemented as a transistor. Although electrical properties between pixels should be uniform across all pixels, differences between pixels may occur due to process variations and variations in device characteristics. The electrical properties of the pixels may deteriorate over the display drive period. To compensate for the variation in electrical properties between pixels, the display device of the present disclosure may include an external compensation circuit. The external compensation circuit may detect the threshold voltage and / or mobility of the driving element through a detection switching element in each of the pixel circuits and a REF line (or detection line) connected to the detection switching element, and transmit it to an external compensator.The compensator compensates for the variation in electrical characteristics and deterioration between pixels based on a detection result of each of the subpixels by modulating the pixel data of an input image.

[0047] In the following, various aspects of the present disclosure will be described in detail with reference to the accompanying drawings.

[0048] With reference to Fig. 1 and Fig. 2, the display device of the present disclosure includes a display panel 10 and a display panel driver for writing pixel data to pixels of the display panel 10.

[0049] The display panel driver includes a data driver 12, a gate driver 13, and a timing controller 11.

[0050] The screen of the display panel 10 includes a pixel matrix AA on which an input image is displayed. Arranged in the pixel matrix AA are a plurality of data lines DL, a plurality of gate lines GL crossing the data lines DL, a plurality of REF lines RL parallel to the data lines DL, and a plurality of pixels P arranged in a matrix.

[0051] Each of the pixels P can be divided into a red subpixel, a green subpixel, and a blue subpixel for color reproduction. Each pixel can further comprise a white subpixel. Each of the pixels can comprise a Fig. 2 shown pixel circuit.

[0052] Each of the subpixels is connected to one of the data lines DL, through which the data voltage is supplied, to one of the REF lines RL, through which the reference voltage REF is supplied, and to one of the gate lines. Furthermore, each of the subpixels is connected to the VDD line PL, through which the pixel drive voltage EVDD is supplied, and to a low-potential power supply voltage EVSS is supplied to it through the VSS electrode.

[0053] The data driver 12 includes a data channel unit 20 that supplies a data voltage to the data lines DL of the display panel 10, and a detection channel unit 30 connected to the pixel circuit of each of the subpixels for detecting driving characteristics of the pixel circuit in real time.

[0054] The data channel unit 20 includes a plurality of digital-to-analog converters (hereinafter referred to as "DACs") arranged in each of the channels. In the display mode, the DAC of the data channel unit 20 converts the pixel data input from the timing controller 11 into a gamma compensation voltage for each gray level to output a data voltage Vdata. In the detection mode, the data channel unit 20 outputs a data voltage Vdata under the control of the timing controller 11 for detection. The data voltage Vdata output from each of the channels of the data channel unit 20 can be applied directly to the data lines DL or can be applied to the data lines DL through a switching unit 40.

[0055] The display panel 10 may further include a switching unit 40. The switching unit 40 may include a demultiplexer DEMUX connected between channels through which a data voltage is output from the data channel unit 20 and the data lines DL. The demultiplexer can reduce the number of channels of the data channel unit 20 to two of the multiple data lines DL by distributing the data voltage output from each of the channels of the data channel unit 20 in a time-division multiplexing method.

[0056] The detection channel unit 30 includes a sampling circuit and an integrator connected to the REF lines RL, and an analog-to-digital converter (hereinafter referred to as "ADC") that converts the output voltage from the integrator into detection data (digital data). The detection data is transmitted to the compensation unit of the timing controller 11.

[0057] The gate driver 13 can be implemented as a gate-in-panel (GIP) circuit formed directly on the bezel area of ​​the display panel 10, together with the TFT matrix of the pixel matrix. The gate driver 13 outputs a gate signal to the gate lines GL under the control of the timing controller 11. The gate driver 13 can shift the gate signal using a shift register to sequentially supply the signals to the gate lines GL. The voltage of the gate signal oscillates between the gate-off voltage and the gate-on voltage. The gate driver 13 can be arranged on each of the left bezel and the right bezel of the display panel 10 to supply a gate signal to the gate lines GL in a dual-feed scheme.In the dual-feed scheme, under the control of the timing controller 11, the gate drivers 13 on both sides can be synchronized so that gate signals can be applied to both ends of a gate line simultaneously. In another aspect, the gate driver 13 for supplying a gate signal to the gate line can be arranged on one of the left and right bezels of the display panel 10 in a single-feed scheme.

[0058] The timing controller 11 modulates the pixel data of the input image based on the detection data received from the detection channel unit 30 and transmits it to the data channel unit 20 of the data driver 12, and controls the data channel unit 20 and the gate driver 13.

[0059] The timing controller 11 receives pixel data DATA of an input image and a timing signal synchronized with the pixel data from the host system. The timing signal may include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a master clock DCLK, and a data enable signal DE. One cycle of the vertical synchronization signal Vsync is one frame period. One cycle of the horizontal synchronization signal Hsync and the data enable signal is one horizontal period (1H). The pulse of the data enable signal DE is synchronized with data of a line to be written to the pixels of a pixel line. Since the frame period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted.

[0060] The timing controller 11 can multiply the input frame frequency (Hz) by i (where i is a positive integer greater than 0) to generate control signals (DDC, GDC) of a frame frequency fixed at the input frame frequency × i (Hz) for controlling the operation timing of the data driver 12, the gate driver 13, and the switching unit 40. The input frame frequency is 60 Hz in the National Television Standards Committee (NTSC) system and 50 Hz in the Phase Alternating Line (PAL) system. The timing controller 11 can lower the frame frequency to a frequency between 1 Hz and 30 Hz to lower the refresh rate of pixels in a low drive mode.

[0061] The voltage level of the gate timing signal output from the timing controller 11 can be shifted by a level shifter (not shown). The gate timing signal can include a start pulse, a shift timing clock, or the like. The level shifter can convert a low-level voltage of the gate timing signal into a gate low voltage and can convert a high-level voltage of the gate timing signal into a gate high voltage. The shift register of the gate driver 13 receives a gate timing signal, generates a gate signal, and shifts the gate signal.

[0062] The timing controller 11 can control a detection mode for detecting electrical characteristics of the driving element DT of each of the subpixels and updating a compensation value accordingly, and can control a display mode for displaying pixel data of an input image reflecting the compensation value. The timing controller 11 can control the data driver 12, the gate driver 13, and the switching unit 40 to separate the detection mode and the display mode according to a predetermined order, but the present disclosure is not limited to this.For example, the detection mode may be performed during a vertical blank period of the display mode in which an input image is displayed on the pixels, may be performed during a power-on sequence period when application of power to the display device is started, or may be performed during a power-off sequence period before power is completely discharged after the display device is turned off. The vertical blank period is a period in which pixel data DATA of the input image is not written to the pixels. The vertical blank period is allocated between vertical active periods in which a frame of pixel data DATA is written. The power-on sequence period includes a transition period until the input image is displayed on the pixel matrix AA after application of power to the display device is started.The power-off sequence period includes a transition period until the power of the display device is completely turned off after the data addressing of pixels is completed.

[0063] The compensation unit of the timing controller 11 may include a compensation lookup table (or compensation lookup table). This lookup table stores compensation values ​​for compensating the threshold voltage Vth and the mobility µ of the drive element DT for each subpixel. To compensate for changes in the electrical characteristics of the drive element DT in each of the subpixels, the compensation unit inputs the detection data received from the ADC of the detection channel unit 30 into the compensation lookup table and modulates the pixel data of the input image by adding or multiplying the compensation value output from the compensation lookup table and the pixel data.

[0064] The data driver 12 and the gate driver 13 can be operated in a low-speed drive mode under the control of the timing controller 11. In the low-speed drive mode, the power consumption of the display device can be reduced when the input image does not change for a predetermined period of time as a result of analyzing the input image. In the low-speed drive mode, when a still image is input for a predetermined period or longer, the refresh rate of the pixels is lowered to control the data write cycle of the pixels to be longer, thereby reducing power consumption. The low-speed drive mode is not limited to when a still image is input.For example, when the display device is operated in a standby mode or when a user command or an input image is not input to the display panel for a predetermined period of time or longer, the display panel driver may be operated in the low-speed driving mode.

[0065] The host system may be one of a television (TV) system, a set-top box, a navigation system, a personal computer (PC), a home theater system, a mobile device, a portable device, and a vehicle system.

[0066] The display device further includes a power supply 50. The power supply 50 may include a charge pump, a regulator, a buck converter, a boost converter, a programmable gamma IC, and the like. The power supply 50 adjusts the DC input voltage from the host system to generate a current required to drive the display panel driver and the display panel 10. The power supply 50 may output a DC voltage, such as a gamma reference voltage, a gate low voltage, a gate high voltage, a pixel drive voltage EVDD, a low-potential grid voltage EVSS, or a reference voltage REF. The pulse of the gate signal oscillates between the gate high voltage and the gate low voltage. The gamma reference voltage is applied to the voltage divider circuit of the data channel unit 20.The voltage divider circuit divides the gamma reference voltage to output a gamma compensation voltage for each gray level. The gamma compensation voltage for each gray level is supplied to the DAC of the data channel unit 20. The programmable gamma IC can change the voltage level of each gamma reference voltage according to a register setting.

[0067] As in Fig. As shown in Figure 2, the pixel circuit is connected to the data line DL, through which the pixel data voltage DATA is supplied, the REF line RL, through which the reference voltage REF is supplied, and the gate line GL, through which the gate signal SCAN is supplied. The reference voltage REF can be set to a DC voltage lower than the pixel drive voltage EVDD and less than or equal to the low-potential power supply voltage EVSS.

[0068] The pixel circuit includes a light-emitting element (OLED), a drive element (DT), a first switching element (ST1), a second switching element (ST2), and a storage capacitor (Cst). Each of the drive element (DT) and the switching elements (ST1 and ST2) can be implemented as a transistor.

[0069] The OLED light-emitting element can be implemented as an OLED comprising an organic compound layer formed between the anode electrode and the cathode electrode. The organic compound layer can include, but is not limited to, a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). The OLED light-emitting element is connected between a third node Ns, which is connected to the source electrode of the driving element DT, and the VSS electrode, to which the low-potential grid voltage EVSS is applied. The OLED light-emitting element is driven to emit light by a current generated by the gate-source voltage Vgs of the driving element DT.

[0070] The drive element DT has a gate electrode connected to a first node Ng, a drain electrode connected to a second node Nd, and a source electrode connected to a third node Ns. The source electrode of the drive element DT is connected to the anode electrode of the light-emitting element OLED through the third node Ns. The drive element DT controls the light-emitting element OLED by controlling the amount of current applied to the light-emitting element OLED according to the gate-source voltage Vgs. The pixel drive voltage EVDD can be applied to the drain electrode of the drive element DT.

[0071] The first switching element ST1 has a gate electrode connected to the gate line, a drain electrode connected to the data line DL, and a source electrode connected to the first node Ng. The first switching element ST1 is turned on in response to a pulse of the gate signal SCAN from the gate line GL. When the first switching element ST1 is turned on, the data line DL, through which the data voltage of the pixel data DATA is applied, is connected to the first node Ng, and the data voltage is applied to the gate electrode of the drive element DT and the storage capacitor Cst.

[0072] The second switching element ST2 has a gate electrode connected to the gate line GL, a drain electrode connected to the REF line RL, and a source electrode connected to the third node Ns. The second switching element ST2 is turned on in response to a pulse of the gate signal SCAN from the gate line GL, connecting the REF line RL and the third node Ns. When the second switching element ST2 is turned on, the reference voltage REF is applied to the third node Ns. When the second switching element ST2 is turned on in the detection mode, the electrical characteristics of the drive element DT can be detected using the current flowing through the third node Ns. The REF line RL is connected to the detection channel unit 30, and the current flowing through the third node Ns is supplied to the detection channel unit 30.

[0073] The storage capacitor Cst is connected between the first node Ng and the third node Ns and maintains the gate-source voltage Vgs of the drive element DT during the emission period of the pixel P. As the gate-source voltage Vgs increases, the amount of current flowing through the light-emitting element OLED increases, so the brightness of the pixel P increases. The brightness of the pixel P increases in proportion to the magnitude of the voltage applied to the first node Ng, i.e., the data voltage Vdata.

[0074] The gate electrode of the drive element DT can be implemented in a double-gate structure. In a transistor with a double-gate structure, since charge carriers flow on both sides of the semiconductor channel, the mobility of the charge carriers is increased. The drive element DT is operated in the saturation region and supplies a current to the light-emitting element (OLED). If the drive element DT is implemented in a double-gate structure, the current flowing between the drain and source of the drive element DT can increase by approximately three times when operated in the saturation region compared to a single-gate structure.

[0075] The switching elements ST1 and ST2 can be implemented in a single-gate or a double-gate structure. The switching elements ST1 and ST2 operate in the linear region. When the switching elements ST1 and ST2 are implemented in a double-gate structure, the mobility of the charge carriers flowing through the semiconductor channel increases. Because the switching elements ST1 and ST2 operate in the linear region, the current flow increases by approximately 1.5 times.

[0076] When the switching elements ST1 and ST2 on the display panel 10 are fabricated in a double-gate structure, the parasitic capacitance connected between the gate line and the switching elements ST1 and ST2 may increase, and they may become more susceptible to changes in the line width distribution or a change in the critical size (CD) during the manufacturing process. Therefore, the switching elements ST1 and ST2 may be configured in a single-gate structure or a double-gate structure, taking into account the effect of improving the current carrying capacity of the switching elements ST1 and ST2, the gate-drain parasitic capacitance Cgd between pixels due to line width variations, and the non-uniformity of the gate-source parasitic capacitance Cgs.

[0077] Fig. 3 is a cross-sectional view schematically illustrating a cross-sectional structure of the pixel circuit in the display device according to an aspect of the present disclosure.

[0078] With reference to Fig. 3, the cross-sectional structure of the pixel circuit includes a first metal layer ML1 disposed on the substrate of the display panel 10, a buffer layer BUF covering the first metal layer ML1, a semiconductor layer ACT disposed on the buffer layer BUF, a gate insulating layer GI disposed on the buffer layer BUF so as to cover the semiconductor layer ACT, and a second metal layer ML2 disposed on the gate insulating layer GI.

[0079] The buffer layer BUF and the gate insulating layer GI are insulating layers made of an insulating material, for example an inorganic insulating material such as SiO2 or SiNx , are educated.

[0080] The first metal layer ML includes the data line DL, the bottom gate electrode GE2 of the transistor TFT, the bottom electrode CE1 of the capacitor Cst, the VDD line PL, the REF line RL, and the like. Fig. 3 the power lines PL and RL are omitted.

[0081] The bottom gate electrode GE2 of the transistor TFT is arranged under the semiconductor channel of the transistor TFT and also serves as a light shielding layer that blocks external light so that light does not radiate onto the semiconductor channel.

[0082] The top gate electrode GE1 of the transistor TFT may be formed from metal structures divided by patterning the second metal layer ML2 disposed on the gate insulating layer GI. Here, the transistor TFT disposed on the bottom gate electrode GE2 may be the Fig. 2. The gate electrode of each of the first switching element ST1 and the second switching element ST2, which are omitted in the drawing, may be formed of metal structures patterned from the second metal layer.

[0083] The second metal layer ML2 further includes a gate line GL connected to the gate electrodes of the switching elements ST1 and ST2. The second metal layer ML2 may further include the top electrode CE3 of the storage capacitor Cst.

[0084] The semiconductor layer ACT includes the source electrode SE and the drain electrode DE of the transistor TFT, the semiconductor channel of the transistor TFT, and the intermediate electrode CE2 of the storage capacitor Cst. The semiconductor layer ACT may be metallized in at least some portions, for example, the source electrode and the drain electrode of the transistor TFT, a portion connected to the second metal layer structure, and an intermediate electrode portion of the storage capacitor Cst. The semiconductor layer ACT is not metallized in the semiconductor channel defined below the gate electrode GE1 of the transistor TFT.

[0085] In the case of indium gallium zinc oxide (IGZO), which is a characteristic oxide semiconductor, the conductivity properties vary depending on the oxygen content. As the oxygen content decreases, the conductivity of the oxide semiconductor (IGZO) increases, and it becomes metallized. Plasma treatment can be used as a method for reducing the oxygen content of the oxide semiconductor (IGZO). For example, when the oxide semiconductor is exposed to plasma (a metallization process), the oxygen present in the oxide semiconductor is removed and the resistance of the oxide semiconductor (IGZO) is lowered, so that the oxide semiconductor can be metallized. Plasma treatment is a method for generating a plasma discharge in helium (He), hydrogen (H), or argon (Ar) gas.In a dry etching process of a thin film layer disposed on the semiconductor layer ACT, the exposed portion of the semiconductor layer ACT can be metallized.

[0086] A third metal layer (MA in Fig. 5) may be partially formed on the semiconductor layer ACT. The third metal layer formed on the semiconductor layer ACT and the top gate electrode GE1 of the transistor may act as a mask in the metallization process of the semiconductor layer ACT, so that the semiconductor layer ACT under the third metal layer and the gate electrode GE1 is not metallized. The third metal layer contacts the semiconductor layer ACT between the first metal layer ML1 and the second metal layer ML2.

[0087] After the semiconductor layer ACT and the third metal layer are stacked on the buffer layer BUF, they can be patterned together in a photolithography process (hereinafter referred to as an “exposure process”) using a halftone mask so that they are formed on the same line.

[0088] The source electrode and drain electrode of the transistor TFT and the intermediate electrode CE2 of the storage capacitor Cst can be formed from the metallized portion of the semiconductor layer ACT or the third metal layer as described above. The storage capacitor Cst can include a first capacitor Cst1 between the bottom electrode CE1 and the intermediate electrode CE2, and a second capacitor Cst2 between the intermediate electrode CE2 and the top electrode CE3. Thus, by using the two capacitors Cst1 and Cst2, the storage capacitor Cst can have an increased capacitance. The size of the electrode of the storage capacitor Cst can be reduced without reducing the capacitance required by the storage capacitor Cst. Thus, since the size of the storage capacitor Cst is reduced, the aperture ratio of the pixel P can be improved.

[0089] Fig. 4 is a plan view illustrating a pixel circuit of a sub-pixel in a display device according to a comparative example. Fig. 5 is a cross-sectional view showing a cross-sectional structure of the pixel circuit taken along a line II' of Fig. 4 represents.

[0090] With reference to Fig. 4 and Fig. 5, each of the subpixels has a light-emitting section EA and a circuit section CA.

[0091] The light-emitting section EA comprises a light-emitting element OLED. A color filter can be arranged in the light-emitting section EA. Light from the light-emitting element OLED is emitted outward through the light-emitting region in the light-emitting section EA. The light-emitting region is defined by the pixel-defining layer BNK. The pixel-defining layer BNK covers the edge of the anode electrode AND of the light-emitting element OLED. Here, the planar shape of the anode electrode AND can be in the same structure as in Fig. 9, but is not limited to this. In Fig. 4 only a part of the light-emitting section EA adjacent to the circuit section CA is shown.

[0092] The circuit section CA includes the control element DT for controlling the light-emitting element OLED, the first switching element ST1, the second switching element ST2, and the storage capacitor Cst. The light-emitting element OLED is controlled by means of the pixel circuit implemented in the circuit section CA.

[0093] When viewed in the cross-sectional structure of the pixel circuit as shown in Fig. As shown in Figure 5, the first metal layer is disposed on the substrate SUBS of the display panel 10. The buffer layer is disposed on the substrate SUBS so as to cover the first metal layer. The buffer layer BUF may be formed of an inorganic insulating material, for example, an oxide layer such as SiO2, but is not limited thereto. The first metal layer may be formed of, but is not limited to, copper / molybdenum-titanium (Cu / MoTi) in which copper (Cu) and molybdenum-titanium (MoTi) are stacked.

[0094] The first metal layer includes the data line DL, the first VDD line PLV, the REF line RL, the bottom gate electrode GE2, and the bottom electrode CE1 of the storage capacitor Cst. The first VDD line PLV is a first-to-first power line arranged along a first direction (y) parallel to the data line DL and the REF line RL. The first VDD line PLV crosses the second VDD line PLH with the buffer layer BUF interposed therebetween. The REF line RL is in Fig. 4 and Fig. 5 omitted.

[0095] The bottom gate electrode GE2 and the bottom electrode CE1 of the storage capacitor Cst may be a single, integral metal structure. The bottom gate electrode GE2 is arranged on the drive element DT and the storage capacitor Cst such that it overlaps the top gate electrode GE1 and the semiconductor channel of the drive element DT. The light-shielding layer portion of the bottom gate electrode GE2 and the bottom electrode CE1 of the storage capacitor Cst may be island structures separated from the first metal layer.

[0096] The semiconductor layer ACT is arranged on the buffer layer BUF. The semiconductor layer ACT has semiconductor channels, i.e., active layers of the transistors DT, ST1, and ST2. The semiconductor channels of the transistors DT, ST1, and ST2 are not metallized. The semiconductor channel of the drive element DT is arranged between the gate insulating layer GI and the buffer layer BUF in such a way that it overlaps the top gate electrode GE1 and the bottom gate electrode GE2. The semiconductor layer ACT extends toward the storage capacitor Cst in such a way that it contains the intermediate electrode CE2 of the storage capacitor Cst. The intermediate electrode CE2 can be formed from the metallized portion of the semiconductor layer ACT or a third metal layer MA formed on the semiconductor layer ACT.

[0097] The semiconductor layer ACT may include the source and drain electrodes of the transistors DT, ST1, and ST2, portions connecting the electrodes of the transistors DT, ST1, and ST2, the metallized portion of the intermediate electrode CE2 of the storage capacitor Cst, and the second VDD line PLH that applies the pixel drive voltage EVDD to the drive element DT. The second VDD line PLH is a first-second current line arranged along a second direction (x) parallel to the gate line GL. The second VDD line PLH may be connected to the first VDD line PLV through a contact hole (omitted in the drawing). Here, the pixel drive voltage EVDD applied to the first VDD line PLV is transmitted to the pixel circuit of the subpixel through the second VDD line PLH.

[0098] The third metal layer MA may be formed on the semiconductor layer ACT. The semiconductor layer ACT may be formed of, but is not limited to, IGZO, and the metal layer MA may be formed of, but is not limited to, MoTi. The third metal layer MA directly contacts the semiconductor layer ACT at a portion where metallization of the semiconductor layer ACT is required. The source electrodes and drain electrodes of the transistors DT, ST1, and ST2 may be formed from the third metal layer MA on the semiconductor layer ACT. In this case, the semiconductor layer below the source electrodes and drain electrodes is not metallized.

[0099] The gate insulating layer GI covers the semiconductor layer ACT. The gate insulating layer GI can be an oxide layer, for example, silicon dioxide (SiO2), but is not limited to this. The gate insulating layer GI is patterned in an exposure process such that it remains beneath the structures of the second metal layer. Thus, the gate insulating layer GI is arranged between the electrodes and the semiconductor channels of the transistors DT, ST1, and ST2.

[0100] The second metal layer is arranged on the gate insulating layer GI and is patterned in an exposure process. The second metal layer comprises the gate electrodes of the transistors DT, ST1, and ST2, the top electrode CE3 of the storage capacitor Cst, and the gate line GL. Thus, the top gate electrode GE1 of the control element DT is formed from a second metal layer structure arranged on the gate insulating layer GI.

[0101] The gate electrodes of transistors DT, ST1, and ST2, which are arranged on the semiconductor layer ACT, mask the semiconductor layer below during the metallization process of the semiconductor layer ACT. Thus, the semiconductor channels of transistors DT, ST1, and ST2 are defined by the gate electrodes.

[0102] The top gate electrode GE1 and the bottom gate electrode GE2 of the drive element DT are connected by a first contact hole CH1 to form a double gate structure. The first contact hole CH1 penetrates the gate insulating layer GI and the buffer layer BUF, exposing the bottom gate electrode GE2. The buffer layer BUF, the semiconductor layer ACT, and the gate insulating layer GI are stacked between the top gate electrode GE1 and the bottom gate electrode GE2.

[0103] The passivation layer PAS is an insulating layer disposed on the buffer layer BUF so as to cover the second metal layer and the semiconductor layer ACT. The passivation layer PAS may be formed of an inorganic insulating material, for example, an oxide layer such as SiO2, but is not limited thereto. The planarization layer OC is disposed on the passivation layer PAS. The planarization layer OC covers the drive element DT, the switching elements ST1 and ST2, and the storage capacitor Cst of the circuit section CA to level the surface. The planarization layer OC may be formed of an organic material such as, but is not limited to, polyimide, benzocyclobutene series resin, or acrylate.

[0104] Components of the light-emitting section EA are arranged on the planarization layer OC. The anode electrode AND of the light-emitting element OLED contacts the metallized section of the semiconductor layer ACT or the third metal layer MA through a second contact hole CH2 that penetrates the passivation layer PAS and the planarization layer OC. The second contact hole CH2 penetrates the planarization layer OC and the passivation layer PAS such that the metallized section of the semiconductor layer ACT or the third metal layer is exposed.

[0105] The anode electrode AND of the light-emitting element OLED is connected through the metallized portion of the semiconductor layer ACT or the third metal layer MA to the source electrode of the driving element DT, the intermediate electrode CE2 of the storage capacitor Cst and the source electrode of the second switching element ST2.

[0106] When viewed in the pixel emission direction, the display panel 10 may be implemented using a bottom emission method. In this case, the anode electrode AND may be formed as a light-transmitting electrode on the planarization layer OC. For example, the anode electrode AND may be formed of a light-transmitting electrode material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO).

[0107] The pixel-defining layer BNK, which defines a light-emitting region of each of the subpixels, is arranged on the planarization layer OC such that it covers the anode electrode AND.

[0108] The pixel-defining layer BNK is formed on the organic compound layer, and the cathode electrode is in Fig. 4 and Fig. 5 is omitted. The organic compound layer is divided between adjacent subpixels by the pixel-defining layer BNK, so that a light-emitting region is defined for each subpixel. The cathode electrode of the light-emitting element OLED is arranged on the organic compound layer. The cathode electrode can be formed over the entire pixel matrix AA and can be commonly connected between subpixels. In the bottom-emission method, the cathode electrode can be implemented as a metal electrode having high reflectivity. For example, the cathode electrode can be formed of magnesium (Mg), calcium (Ca), aluminum (Al), silver (Ag), or an alloy thereof having a low work function.

[0109] The pixel circuit of the present disclosure has two contact holes CH1 and CH2. In this pixel circuit, a contact hole connecting the semiconductor layer and the second metal layer structure of the first node Ng of the Fig. 2, and a contact hole connecting the semiconductor layer and the second metal layer structure at the third node Ns of the Fig. 2 is not required. Accordingly, the present disclosure can reduce the loss of aperture ratio due to a large number of contact holes arranged in the pixel circuit.

[0110] Fig. 6 to Fig. 9 are plan views showing in detail the structural shapes of the main thin film layers, which are different from the cross-sectional view of the Fig. 4 are arranged away from the pixel circuit shown. Fig. 6 is a plan view showing the structures of the first metal layer ML1 formed in Fig. 3 is shown. Fig. Fig. 7 is a plan view showing the structures of the semiconductor layer ACT and the third metal layer MA formed in Fig. 5 is shown. Fig. 8 is a plan view showing the structures of the Fig. 3 represents the second metal layer ML2. Fig. 9 is a plan view showing the anode electrode AND of the Fig. 4 represents the light-emitting element OLED.

[0111] As in Fig. As shown in Figure 6, the first metal layer ML1 includes a VDD line pattern M11, a bottom gate electrode pattern M12, a data line pattern M13, and the like. The bottom gate electrode pattern M12 includes the bottom gate electrode GE2 of the drive element DT and the bottom electrode CE1 of the storage capacitor Cst. The bottom gate electrode pattern M12 overlaps the first contact hole CH1 and is exposed at the first contact hole CH1.

[0112] As in Fig. As shown in Figure 7, the semiconductor layer ACT has a first semiconductor structure A1 and a second semiconductor structure A2.

[0113] The first semiconductor structure A1 comprises the semiconductor channel of the drive element DT, the source electrode of the drive element DT, the drain electrode of the drive element DT, the semiconductor channel of the second switching element ST2, the source electrode of the second switching element ST2, the drain electrode of the second switching element ST2, the intermediate electrode of the storage capacitor Cst and the second VDD line PLH.

[0114] At the semiconductor channel portion of the drive element DT and the semiconductor channel portion of the second switching element ST2, the first semiconductor structure A1 is not metallized. In the first semiconductor structure A1, the source electrodes and drain electrodes of the drive element DT and the second switching element ST2 may be metallized or may have the third metal layer formed on the semiconductor layer ACT. At the intermediate electrode CE2 of the storage capacitor Cst and the second VDD line PLH, the first semiconductor structure A1 may be metallized, or the third metal layer may be formed on the first semiconductor structure A1.

[0115] The drain electrode of the second switching element ST2 is connected to a branch (omitted from the drawing). The branch is connected to the REF line RL through a contact hole (omitted from the drawing). At least a portion of the branch, for example, a portion passing through the light-emitting region, may be formed from a semiconductor layer structure that is metallized without forming the third metal layer to increase the aperture ratio and light transmittance of the light-emitting region. Thus, the drain electrode of the second switching element ST2 is connected to the REF line RL via the branch.

[0116] The first semiconductor structure A1 overlaps the second contact hole CH2 and is exposed at the second contact hole CH2. The anode electrode AND of the OLED light-emitting element is connected to the first semiconductor structure A1 through the second contact hole CH2, which overlaps the first semiconductor structure A1. A part of the first semiconductor structure A1 that is connected to the anode electrode AND at the second contact hole CH2 is a metallized portion of the semiconductor layer ACT or the third metal layer MA formed on the semiconductor layer.

[0117] The second semiconductor structure A2 includes the semiconductor channel of the first switching element ST1, the source electrode of the first switching element ST1, and the drain electrode of the first switching element ST1. The second semiconductor structure A2 is not metallized at the semiconductor channel portion of the first switching element ST1. The drain electrode of the first switching element ST1 is connected to the data line DL through a contact hole, which is omitted from the drawing. In the second semiconductor structure A2, the source electrode and drain electrode of the first switching element ST1 are metallized or include the third metal layer formed on the semiconductor layer ACT.

[0118] The second semiconductor structure A2 overlaps the first contact hole CH1 and is exposed at the first contact hole CH1. The second semiconductor structure A2 may be metallized at the first contact hole CH1, or the third metal layer may be formed on the second semiconductor structure A2.

[0119] As in Fig. As shown in Figure 8, the second metal layer ML2 includes a top gate electrode pattern M21 and a gate line pattern M22. The top gate electrode pattern M21 includes the top gate electrode GE1 of the drive element DT and the top electrode CE3 of the storage capacitor Cst. The top gate electrode pattern M21 has a "C"-shaped pattern or "⊏"-shaped pattern to connect the top gate electrode GE1 of the drive element DT and the top electrode of the storage capacitor Cst while bypassing the source electrode of the drive element DT.

[0120] The top gate electrode structure M21 overlaps the first contact hole CH1 and touches the bottom gate electrode structure M12 and the second semiconductor structure A2 through the second contact hole CH2.

[0121] Fig. 10 is a plan view illustrating a pixel circuit of a subpixel in a display panel according to an aspect of the present disclosure. Fig. 11 is a cross-sectional view showing a cross-sectional structure of the pixel circuit taken along line II-II' of Fig. 10 represents. Fig. 12 is a plan view showing structures of a first metal layer formed in Fig. 10 is shown. In Fig. 10 to Fig. 12, components substantially the same as those of the above-described comparative example are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0122] With reference to Fig. 10 and Fig. 11, the pixel circuit may further comprise a first slot SL1 and a second slot SL2.

[0123] The first slot SL1 is formed between the bottom gate electrode GE2 and the data line DL to block a parasitic capacitance that causes crosstalk between them. The first slot SL1 is formed between a long side LS1 of the adjacent bottom gate electrode GE2 and the data line DL. As shown in Fig. 10 and Fig. 12, the length L1 of the first slot SL1 may be substantially equal to the length L1 of a long side LS1 of the bottom gate electrode structure M12, which includes the bottom electrode CE1 of the storage capacitor Cst and the bottom gate electrode GE2.

[0124] In the first slot SL1, all insulating layers, such as the planarization layer OS, the passivation layer PAS, the gate insulating layer GI, and the buffer layer BUF, are removed in the etching process and are deeply ablated. The anode electrode AND covers the sidewall (or side surface) and the bottom surface within the first slot SL1, thereby minimizing the parasitic capacitance between the bottom gate electrode GE2 and the data line DL.

[0125] The second slot SL2 is formed to prevent a short circuit between the bottom gate electrode GE2 and the first VDD line PLV and to reduce parasitic capacitance between them. The second slot SL2 is formed along the other long side LS2 of the adjacent bottom gate electrode GE2 and the first VDD line PLV. As shown in Fig. 10 and Fig.12, the length L2 of the second slot SL2 may be set such that it is substantially equal to the length L2 of the other long side LS2 of the bottom gate electrode structure M12.

[0126] The length L2 of the other long side LS2 of the bottom gate electrode structure M12 can be set to be smaller than the length L1 of the one long side LS1. In the second slot SL2, insulating layers, such as the gate insulating layer GI and the buffer layer BUF, are removed during the etching process. The passivation layer PAS covers the side surface and the bottom surface of the second slot SL2, and the planarization layer OC is deposited thereon in such a way that it becomes flat.

Claims

[1] A display panel comprising: a first metal layer (ML1) having a VDD line structure (M11), a bottom gate electrode structure (M12) and a data line structure (M13); a first insulating layer (BUF) covering the first metal layer (ML1); a semiconductor layer (ACT) disposed on the first insulating layer (BUF); a second insulating layer (Gl) arranged on the first insulating layer (BUF) and covering the semiconductor layer (ACT); a second metal layer (ML2) arranged on the second insulating layer (GI); a third insulating layer (PAS) arranged on the first insulating layer (BUF) such that it covers the second metal layer (ML2) and the semiconductor layer (ACT); and a planarization layer (OC) arranged on the third insulating layer (PAS), wherein the bottom gate electrode structure (M12) comprises a bottom gate electrode (GE2) of a drive element (DT) and a bottom electrode (CE1) of a storage capacitor (Cst), wherein the second metal layer (ML2) has a top gate electrode (GE1) of the drive element (DT) which is connected to the bottom gate electrode (GE2) through a first contact hole (CH1) passing through the second insulating layer (GI) and the first insulating layer (BUF), and wherein the semiconductor layer (ACT) has a semiconductor channel of the control element (DT) which overlaps the top gate electrode (GE1) and the bottom gate electrode (GE2), the display panel further comprising: a first slot (SL1) from which the planarization layer (OC), the third insulating layer (PAS), the second insulating layer (GI) and the first insulating layer (BUF) are removed between a long side of the bottom gate electrode structure (M12) and the data line structure (M13). [2] The display panel according to claim 1, further comprising: a pixel circuit connected to a data line (DL) supplied with a data voltage, a gate line (GL) supplied with a gate signal, a VDD line (PL) supplied with a pixel drive voltage (EVDD), and a REF line supplied with a reference voltage (REF). [3] The display panel according to claim 2, wherein the pixel circuit comprises: a first switching element (ST1) configured to apply the data voltage to the top gate electrode (GE1) and the bottom gate electrode (GE2) of the drive element (DT) in response to the gate signal; a second switching element (ST2) configured to apply the reference voltage (REF) to a source electrode of the drive element (DT) in response to the gate signal; and a light-emitting element (OLED) which is controlled by the control element (DT), wherein the pixel drive voltage (EVDD) is applied to a drain electrode of the drive element (DT). [4] The display panel according to claim 3, wherein the first metal layer (ML1) further comprises: a first-first power line structure to which the pixel drive voltage (EVDD) is applied, wherein the bottom electrode (CE1) of the capacitor (Cst) is connected to the bottom gate electrode (GE2), and wherein the data line structure (M13) comprises the data line (DL); wherein the second metal layer (ML2) comprises: a top gate electrode structure (M21) comprising the top gate electrode (GE1) of the drive element (DT) and a top electrode (CE3) of the capacitor (Cst) connected to the top gate electrode (GE1) and overlapping the first contact hole (CH1); and a gate line structure (M22) comprising the gate line (GL). [5] The display panel according to claim 4, wherein the semiconductor layer (ACT) comprises: a first semiconductor structure (A1) comprising the semiconductor channel of the drive element (DT), an intermediate electrode (CE2) of the capacitor (Cst) connected to the semiconductor channel of the drive element (DT), the source electrode and drain electrode of the drive element (DT), a semiconductor channel of the second switching element (ST2), a source electrode and drain electrode of the second switching element (ST2), and a first-second current line (PLH) through which the pixel drive voltage (EVDD) is applied, and overlapping a second contact hole (CH2), and a second semiconductor structure having a semiconductor channel of the first switching element (ST1), a source electrode and drain electrode of the first switching element (ST1) and overlapping the first contact hole (CH1), wherein the first-first current line (PLV) and the first-second current line (PLH) cross each other with the first insulating layer (BUF) inserted therebetween. [6] The display panel according to claim 5, wherein an anode electrode (AND) of the light-emitting element (OLED) is connected to the first semiconductor structure (A1) through the second contact hole (CH2), wherein the second contact hole (CH2) penetrates the planarization layer (OC) and the third insulating layer (PAS) such that it exposes the first semiconductor structure (A1), and wherein a portion of the first semiconductor structure (A1) connected to the anode electrode (AND) within the second contact hole (CH2) is a metallized portion of the semiconductor layer (ACT) or a metal layer formed on the semiconductor layer (ACT). [7] The display panel according to claim 6, wherein the anode electrode (AND) of the light-emitting element (OLED) covers a side surface and bottom surface of the first slot (SL1). [8] The display panel according to claim 7, wherein a length of the first slot (SL1) is substantially equal to a length of one long side of the bottom gate electrode structure (M12). [9] The display panel according to claim 7 or 8, further comprising a second slot (SL2) from which the first insulating layer (BUF) and the second insulating layer (GI) are removed between another long side of the bottom gate electrode structure (M12) and the first-first power line structure, and wherein the third insulating layer (PAS) covers a side surface and bottom surface of the second slot (SL2). [10] The display panel according to claim 9, wherein a length of the second slot (SL2) is substantially equal to a length of the other long side of the bottom gate electrode structure (M12). [11] A display panel comprising: a control element (DT) configured to supply a current to a light-emitting element (OLED); a first switching element (ST1) configured to connect a data line (DL), through which a data voltage is applied, to a gate electrode (GE1, GE2) of the drive element (DT) in response to a gate signal from a gate line (GL); a second switching element (ST2) configured to apply a reference voltage (REF) to a source electrode of the drive element (DT) in response to the gate signal; and a capacitor (Cst) connected between the gate electrode (GE1, GE2) of the control element (DT) and the source electrode of the control element (DT), wherein the gate electrode (GE1, GE2) of the drive element (DT) has a top gate electrode (GE1) and a bottom gate electrode (GE2), and wherein a semiconductor layer (ACT) having a semiconductor channel is inserted therebetween, wherein the top gate electrode (GE1) overlaps the bottom gate electrode (GE2), and wherein the top gate electrode (GE1) is connected to the bottom gate electrode (GE2) through a first contact hole (CH1) passing through a first insulating layer (BUF) between the bottom gate electrode (GE2) and the semiconductor layer (ACT) and a second insulating layer (GI) between the top gate electrode (GE1) and the semiconductor layer (ACT), and wherein an anode electrode (AND) of the light-emitting element (OLED) is connected to the semiconductor layer (ACT) through a second contact hole (CH2) which forms a third insulating layer (PAS) covering the driving element (DT) and the first switching element (ST1) and the second switching element (ST2), and a planarization layer (OC) arranged on the third insulating layer (PAS), the display panel further comprising: a first slot (SL1) from which the planarization layer (OC), the third insulating layer (PAS), the second insulating layer (GI) and the first insulating layer (BUF) between the bottom gate electrode (GE2) and the data line (DL) are removed. [12] The display panel according to claim 11, wherein the anode electrode (AND) of the light-emitting element (OLED) covers a side surface and bottom surface of the first slot (SL1). [13] The display panel according to claim 11 or 12, further comprising: a power line (PLV, PLH) through which a pixel drive voltage (EVDD) is applied; and a second slot (SL2) from which the first insulating layer (BUF) and the second insulating layer (GI) between the bottom gate electrode (GE2) and the power line (PLV, PLH) are removed, wherein the third insulating layer (PAS) covers a side surface and bottom surface of the second slot (SL2). [14] A display device comprising: a display panel (10) in which a plurality of data lines (DL), a plurality of gate lines (GL) crossing the data lines (DL), a plurality of first power lines through which a pixel drive voltage (EVDD) is applied, a plurality of second power lines (RL) through which a reference voltage (REF) is applied, and a plurality of pixels (PX) are arranged; a data driver configured to supply a data voltage of pixel data through the data lines (DL); and a gate driver (13) arranged to supply a gate signal through the gate lines (GL), where each of the pixels (PX) has: a control element (DT) configured to supply a current to a light-emitting element (OLED); a first switching element (ST1) configured to connect the data line (DL) through which the data voltage is applied to a gate electrode (GE1, GE2) of the drive element (DT) in response to the gate signal from the gate line (GL); a second switching element (ST2) configured to apply, in response to the gate signal, the reference voltage (REF) lower than a pixel drive voltage (EVDD) to a source electrode of the drive element (DT); and a capacitor (Cst) connected between the gate electrode (GE1, GE2) of the control element (DT) and the source electrode of the control element (DT), wherein the gate electrode (GE1, GE2) of the drive element (DT) has a top gate electrode (GE1) and a bottom gate electrode (GE2), wherein a semiconductor layer (ACT) having a semiconductor channel is inserted therebetween, wherein the top gate electrode (GE1) overlaps the bottom gate electrode (GE2), wherein the top gate electrode (GE1) is connected to the bottom gate electrode (GE2) through a first contact hole (CH1) penetrating a first insulating layer (BUF) between the bottom gate electrode (GE2) and the semiconductor layer (ACT) and a second insulating layer (GI) between the top gate electrode (GE1) and the semiconductor layer (ACT), and wherein an anode electrode (AND) of the light-emitting element (OLED) is connected to the semiconductor layer (ACT) through a second contact hole (CH2) penetrating a third insulating layer (PAS) covering the drive element (DT) and the first switching element (ST1) and the second switching element (ST2), and a planarization layer (OC) arranged on the third insulating layer (PAS), the display device further comprising: a first slot (SL1) from which the planarization layer (OC), the third insulating layer (PAS), the second insulating layer (GI) and the first insulating layer (BUF) between the bottom gate electrode (GE2) and the data line (DL) are removed. [15] The display device according to claim 14, wherein the anode electrode (AND) of the light-emitting element (OLED) covers a side surface and bottom surface of the first slit (SL1). [16] The display device according to claim 14 or 15, further comprising: a second slot (SL2) from which the first insulating layer (BUF) and the second insulating layer (GI) between the bottom gate electrode (GE2) and the first power line are removed, wherein the third insulating layer (PAS) covers a side surface and bottom surface of the second slot (SL2).

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