SEMICONDUCTOR MODULE AND METHOD FOR PRODUCING A SEMICONDUCTOR MODULE

Abstract

Semiconductor module (1), comprising: a laminated substrate (2) having a circuit pattern (22) arranged on an upper surface of an insulating plate (20) and a heat dissipation plate (21) arranged on a lower surface of the insulating plate (20); a semiconductor device (3) having an upper surface and a lower surface, a collector electrode (30) arranged on the upper surface, an emitter electrode (32) and a gate electrode (31) arranged on the lower surface, wherein the emitter electrode (32) and the gate electrode (31) are each connected via a bump (B) to an upper surface of the circuit pattern (22); and a barrier electrode (4) having a collector electrode block (40) connected to the collector electrode (30) and another electrode block connected to the circuit pattern outside the collector electrode block (40) in a plan view of the semiconductor module (1), wherein the collector electrode block (40) comprises: a flat plate portion (44) covering the semiconductor device (3); and a pair of projection portions (45) projecting from both ends of the flat plate portion (44) toward the circuit pattern (22) and connected to the circuit pattern (22).

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on the priority claims of the previous Japanese patent application JP 2020 - 017 649, filed on February 5, 2020, the entire contents of which are hereby incorporated by reference. Technical area

[0002] The present invention relates to a semiconductor module and a method for manufacturing a semiconductor module. State of the art

[0003] A semiconductor device includes a substrate fabricated with a semiconductor device such as an insulated gate bipolar transistor (IGBT), a power metal oxide semiconductor field effect transistor (MOSFET), or a freewheeling diode (FWD), and is used for an inverter and the like.

[0004] For example, semiconductor devices (semiconductor modules) described in Patent Literatures 1 and 2 below each consist of a base plate, an insulating circuit board, and a semiconductor device, etc., which are arranged in a package. The insulating circuit board includes a first conductive plate (first metal layer) formed on an upper surface of an insulating substrate and a second conductive plate (second metal layer) formed on a lower surface of the insulating substrate. The semiconductor device is arranged on an upper surface of the first conductive plate; and a base plate is arranged on a lower surface of the second conductive plate. In addition, wire (bonding wire) is used as an electrical wiring element between the semiconductor device and the first conductive plate or another semiconductor device.

[0005] An interior of the package is filled with a sealing material (sealing resin) to seal the various configurations described above. In addition, a cooler is disposed on a lower surface of the base plate via a bonding material such as solder. Furthermore, Patent Literature 3 discloses another semiconductor module including a flip-chip mounted semiconductor device, wherein the emitter and gate electrodes of the device are connected to a substrate via bumps, while the collector electrode is positioned on top. Patent Literature 4 also describes a flip-chip mounted semiconductor module, wherein a semiconductor device is connected, with its emitter and gate electrodes facing downward, to wiring patterns of a substrate via bumps, and the collector electrode is positioned on top.Finally, Patent Literature 5 discloses a semiconductor package structure based on a leadframe in which a semiconductor chip is mounted on a die pad of the leadframe, the entire assembly being encapsulated with resin, with the outer leads and the bottom surface of the die pad exposed for external mounting and contacting. Citation listPatent literature Patent literature 1: JP 2017- 28 132 A Patent literature 2: JP 3 198 019 U Patent literature 3: DE 10 2020 109 347 A1 Patent literature 4: US 2004 / 159 939 A1 Patent literature 5: US 2005 / 029 651A1 Brief description of the inventionProblem to be solved by the invention

[0006] In a heat dissipation structure of conventional semiconductor modules, the heat from a chip (semiconductor device) is dissipated into the air via a cooler to reduce heat generation within the chip. In addition, the chip mainly generates heat on the emitter electrode side formed on a front side. Therefore, the heat generated by the chip is transferred to a back side (collector electrode side) and dissipated to the outside via the insulating conductor substrate, base plate, bonding material, and cooler.

[0007] As described above, the chip generates heat on the emitter electrode side, and therefore, it is necessary to transfer the heat generated on the emitter electrode side to the collector electrode side, where the cooler is located. This creates a problem in that the thermal resistance of the entire semiconductor module increases with the thermal conductivity and thickness of the chip. Another problem with conventional semiconductor modules is that the use of a single wire to connect the gate electrode side and the emitter electrode side requires a long wiring length, resulting in increased inductance.

[0008] The present invention has been made in view of the above points, and it is an object of the present invention to provide a semiconductor module and a method of manufacturing a semiconductor module which can reduce the thermal resistance as well as the inductance. Solution to the task

[0009] The invention relates to a semiconductor module comprising the features of claims 1 and 8, and to a method for producing a semiconductor module comprising the features of claim 14. Advantageous embodiments of the invention are the subject of the dependent claims Advantageous effects of the invention

[0010] According to the present invention, thermal resistance and inductance can be reduced. Brief description of the drawings Fig. 1 is a perspective view of a semiconductor module according to a present embodiment. Fig. 2 is a plan view of the semiconductor module according to the present embodiment. Fig. 3 is a plan view showing a circuit pattern of the semiconductor module according to the present embodiment. Fig. 4 is a sectional view of the semiconductor module according to the present embodiment. Fig. 5 are schematic views showing the flow of a coolant in the semiconductor module according to the present embodiment. Fig. 6 are perspective views of an example of a step of a method for manufacturing a semiconductor module according to the present embodiment. Fig. 7 are perspective views of an example of a step of the method for manufacturing a semiconductor module according to the present embodiment. Fig. 8 is a perspective view of an example of a step of the method for manufacturing a semiconductor module according to the present embodiment. Fig. 9 are perspective views of an example of a step of the method for manufacturing a semiconductor module according to the present embodiment. Embodiments of the invention

[0011] A semiconductor module to which the present invention can be applied will be described below. Fig. 1 is a perspective view of a semiconductor module according to an embodiment. Fig. 2 is a plan view of the semiconductor module according to the present embodiment. Fig. 3 is a plan view showing a circuit pattern of the semiconductor module according to the present embodiment. Fig. 4 is a sectional view of the semiconductor module according to the present embodiment. Fig. 4A is a sectional view along the line AA in Fig. 2; and Fig. 4B is a sectional view taken along line BB in Fig. 2. Fig. 5 is a schematic view showing the flow of a coolant in the semiconductor module according to the present embodiment. Fig. 5A is a schematic plan view of the semiconductor module; and Fig. Figure 5B is a schematic sectional view of the semiconductor module. Note that the semiconductor module described below is merely an example, and can be modified as appropriate without being limited thereto.

[0012] Furthermore, in the figures described below, a short direction of the semiconductor module is an X direction, a longitudinal direction is a Y direction, and a height direction is a Z direction. Further, the X direction, the Y direction, and the Z direction may be referred to as a left-right direction, a front-back direction, and a top-down direction, respectively. These directions (front-back, left-right, and top-down directions) are terms used for ease of explanation and correspond to each of the X, Y, and Z directions, and may change depending on the mounting position of the semiconductor module. For example, a heat dissipation surface (radiator) side of the semiconductor module is regarded as a lower surface side, and its opposite side is regarded as an upper surface side. Furthermore, here, a plan view refers to a view of the upper surface of the semiconductor module from the Z direction.

[0013] A semiconductor module 1 is used, for example, with a power converter such as a power module. As shown in Fig. 1 to Fig. 4, the semiconductor module 1 is formed by arranging a plurality of semiconductor devices 3 and a plurality of barrier electrodes 4 on an upper surface of a laminated substrate 2.

[0014] The laminated substrate 2 is formed by laminating a metal layer and an insulating layer, and is made of, for example, a direct copper bonding (DCB) substrate, an active metal brazing (AMB) substrate, or a metal-based substrate. Specifically, the laminated substrate 2 includes: an insulating plate 20; a heat radiation plate 21 disposed on a lower surface of the insulating plate 20; and a plurality of circuit patterns 22 disposed on an upper surface of the insulating plate 20. Furthermore, the laminated substrate 2 is formed in a rectangular shape in plan view, with a Y-direction length greater than that in the X-direction.

[0015] The insulating plate 20 has a thickness in the Z direction and is formed in a flat plate shape with an upper surface and a lower surface. The insulating plate 20 is made, for example, of a ceramic material such as aluminum oxide (Al2O3), aluminum nitride (AlN), or silicon nitride (Si2N4), of a resin material such as epoxy, or of an insulating material such as an epoxy resin with a ceramic material as a filler. The insulating plate 20 may also be referred to as an insulating layer or insulating film.

[0016] The heat dissipation plate 21 has a predetermined thickness and is designed to cover the entire lower surface of the insulation plate 20. The heat dissipation plate 21 is made of a metal plate with good thermal conductivity, such as copper or aluminum. The lower surface of the heat dissipation plate 21 is a heat dissipation surface, and a cooler 10 is mounted on the heat dissipation surface.

[0017] The cooler 10 consists of, for example, a heat sink and has a rectangular shape in plan view. The cooler 10 is made of a metal such as copper or aluminum, or of an alloy containing one or more of these metals; and, for example, electroplating has been performed on its surface. The cooler 10 is mounted on the semiconductor module 1 via, for example, a bonding with good thermal conductivity between itself and the lower surface of the semiconductor module 1 (heat dissipation plate 21). An upper surface of the cooler 10 is a smooth bonding surface to which the lower surface of the semiconductor module 1 is bonded. On one side of the lower surface of the cooler, a plurality of fins 10a are formed, projecting in the Z direction.

[0018] The plurality of fins 10a are arranged in a row at intervals in the Y direction. This creates a groove 10b between adjacent fins 10a. A coolant such as air flows through the groove 10b, thereby cooling the semiconductor module 1. Although the details will be described later, a direction in which the coolant flows (flow direction) is referred to as a cooling direction F. Note that the cooler 10 is not limited to the configuration described above and may be configured as a water cooler with a water jacket.

[0019] As in Fig. As shown in Figure 3, one main surface of the insulating plate 20 has a plurality (four in the present embodiment) of circuit patterns 22 formed in an insulated manner (in an electrically insulating state from each other). The plurality of circuit patterns 22 include: a pair of collector circuit patterns 23 connected to a collector electrode 30 of each of the semiconductor devices 3 described later; a gate circuit pattern 24 connected to a gate electrode 31 thereof; and an emitter circuit pattern 25 connected to an emitter electrode 32 thereof.

[0020] The collector circuit patterns 23 each have an elongated shape in plan view, extending in a longitudinal direction (Y direction) of the insulating plate 20 on an outer edge side of the insulating plate 20. The pair of collector circuit patterns 23 are arranged to face each other in a short direction (X direction) of the insulating plate 20.

[0021] The gate circuit pattern 24 is bent in an L-shape from an end portion on one side in the longitudinal direction of the insulating plate 20 to the center thereof and has a shape divided into four branches from the center of the insulating plate 20. Specifically, the gate circuit pattern 24 is constructed by connecting an L-section 24a having an L-shape in plan view and an H-section 24b having an H-shape in plan view. The L-section 24a extends in the X direction from a corner portion of the insulating plate 20, bends perpendicularly at approximately the middle portion in the X direction of the insulating plate 20, and extends to a central part (center) of the insulating plate 20. The H-section 24b is formed by connecting center portions of a pair of long sections extending in the Y direction to a long section extending in the X direction. The H-section 24b is arranged in the central part of the insulating plate 20.The center portion of the H-portion 24b and an end portion on one side of the center portion of the L-portion 24a are connected. Although the details will be described later, the H-portion 24a forms a region in a center portion of the insulating plate 20 where the gate electrode 31 is connected via a bump B.

[0022] The emitter circuit pattern 25 is formed approximately in a U-shape in plan view so as to surround an outer edge side of the H-portion 24b. Specifically, the emitter circuit pattern 25 includes: an emitter portion 25a extending in the X direction along one short side on the other side in the longitudinal direction of the insulating plate 20; a pair of long portions 25b and 25c extending in the Y direction from the emitter portion 24a; and a sense emitter portion 25b connected to one of the long portions 25c.

[0023] The pair of long sections 25b and 25c are connected at one end to the emitter section 25a, and the sides of the other ends extend in the Y direction. The pair of long sections 25b and 25c are arranged to oppose each other, sandwiching the H section 24b in the X direction. The long sections 25b and 25c are arranged to be sandwiched between each of the collector circuit patterns 23 and the H section 24b. The pair of collector circuit patterns 23, the pair of long sections 25b and 25c, and the pair of long sections of the H section 24b extend in parallel in the Y direction. The sense emitter portion 25d is arranged on an opposite side of the emitter portion 25a so as to sandwich one of the collector circuit patterns 23 with the emitter portion 25a.Furthermore, the sense emitter portion 25d is arranged adjacent to the L portion 24a of the gate circuit pattern 24 in the X direction and extends in the X direction. The sense emitter portion 25d is connected to the one long portion 25c. Although the details will be described later, the emitter portion 25a forms a region outside the H portion 24b, where the emitter electrodes 32 are connected via a bump B.

[0024] In the as in Fig. 3, the H-section 24b of the gate circuit pattern 24 is sandwiched between the pair of long sections 25b and 25c. In addition, the H-section 24b and the pair of long sections 25b and 25c are sandwiched between the pair of collector circuit patterns 23. Note that the double-dashed line sections in Fig. 3 represent regions in which the barrier electrodes 4 or semiconductor devices 3, which will be described below, are connected.

[0025] A plurality of semiconductor devices 3 are arranged at predetermined positions on the circuit patterns 22. Each of the semiconductor elements 3 is formed in a square shape in plan view, using a semiconductor substrate such as silicon (Si) or silicon carbonate (SiC). In the present embodiment, the semiconductor device 3 consists of a reverse-conducting insulated gate bipolar transistor (RC-IGBT) that integrates the functions of an IGBT and a freewheeling diode (FWD).

[0026] Note that the semiconductor device 3 is not limited to this embodiment and can be constructed by combining a switching device such as an IGBT or a power metal oxide semiconductor field-effect transistor (MOSFET) and a diode such as a freewheeling diode (FWD). Furthermore, a reverse blocking (RB) IGBT or the like, which has sufficient withstand voltage against a reverse bias voltage, can be used as the semiconductor device 3. Furthermore, the shape, number of arrays, and array positions of the semiconductor devices 3 can be changed as appropriate.

[0027] In the present embodiment, four pieces of semiconductor devices 3 are arranged across a plurality of bumps B on upper surfaces of the H-section 24b and the pair of long sections 25b and 25c. Specifically, the semiconductor devices 3 are arranged to straddle the ends of the branched H-section 24b and the ends or base ends of the long sections 25b and 25c. On an upper surface of each of the semiconductor devices 3, the collector electrode 30 is arranged; and on a lower surface of each of the semiconductor devices 3, the gate electrode 31 and the emitter electrode 32 are arranged. At the center of one end side of the semiconductor device 3, the gate electrode 31 is arranged; and on another end side, the emitter electrode 32 is arranged oppositely.

[0028] The semiconductor device 3 is connected to its corresponding circuit pattern 22 via bumps B by arranging the gate electrode 31 to face an upper surface of a corresponding end of the H-section 24b and by arranging the emitter electrode 32 to face an upper surface of the long section 25b or 25c. Specifically, the gate electrode 31 is electrically connected to the upper surface of the corresponding end of the branched H-section 24b via one bump B for each of the semiconductor devices 3. Further, the emitter electrode 32 is electrically connected to the upper surface of the long section 25b or 25c via three bumps B for each of the semiconductor devices 3.

[0029] As described above, gate electrode 31 and emitter electrode 32 are arranged adjacent to each other in the X direction. Specifically, gate electrode 31 is arranged further inward in the X direction than emitter electrode 32. This means that four gate electrodes 31 are arranged closer to one side of the center of the entire module than four emitter electrodes 32.

[0030] A paste-like sintered metal material can be used for the bumps B. For example, silver or another sintered material made of metal nanoparticles can be used for the bumps B. The bumps B are, for example, columnar and extend in a thickness direction (Z direction). Note that the bumps B can be made of solder and are not limited to the sintered metal material.

[0031] In addition to the circuit patterns 22, the barrier electrodes 4 are connected. Specifically, the barrier electrodes 4 include: a collector electrode block 40 connected to the collector circuit pattern 23; a gate electrode block 41 connected to the gate circuit pattern 24; and an emitter electrode block 42 and a sense emitter electrode block 43, both connected to the emitter circuit pattern 25.

[0032] The collector electrode block 40 is approximately square in plan view, covering most of the area above the laminated substrate 2. Specifically, the collector electrode block 40 includes: a flat plate portion 44 covering a portion above the semiconductor devices 3; and a pair of projection portions 45 projecting from both ends in the X direction of the flat plate portion 44 toward the collector circuit pattern 23. Thus, the collector electrode block 40 forms an approximately U-shape when viewed from the Y direction.

[0033] The flat plate portion 44 has an approximately square shape in plan view, covering a part above: the pair of collector circuit patterns 23; the pair of long portions 25b and 25c and the H portion 24b arranged between the pair of collector circuit patterns 23; and the four semiconductor devices 3. The X-direction width of the flat plate portion 44 corresponds to an opposing pitch of the pair of collector circuit patterns 23. The Y-direction width of the flat plate portion 44 corresponds to the Y-direction length of the collector circuit patterns 23. Further, a circular through-hole 46 passing through in the thickness direction is arranged in the center of the flat plate portion 44.

[0034] Each of the projection portions 45 has an approximately rectangular cuboid shape projecting downward in the Z direction from each end portion in the X direction of the flat plate portion 44. The X-direction width of the projection portion 45 is slightly smaller than the width of the collector circuit pattern 23. Furthermore, the Y-direction width of the projection portions 45 is equal to the width of the flat plate portion 44 and slightly smaller than the width of the collector circuit pattern 23. Furthermore, a chamfer is formed at each corner portion on an upper surface side of the collector electrode block 40. The pair of projection portions 45 are arranged along two opposite sides of the insulating plate 20.

[0035] On a lower surface of the flat plate portion 44, the collector electrodes 30 of the semiconductor devices 3 are electrically connected via a bonding material S. Furthermore, a lower surface of each projection portion 45 is electrically connected to each of the collector circuit patterns 23 via the bonding material S. A sheet-like sintered metal material can be used as the bonding material S. For example, it is possible to form a sintered material made of silver nanoparticles or another metal in a sheet shape and use it as the bonding material S. The bonding material S is formed, for example, in a rectangular shape with a predetermined thickness. Note that the bonding material S may be made of solder and is not limited to the sintered metal material. In addition, the bonding material S may be formed in a paste-like state, which is not limited to the sheet-like state.Furthermore, the height of the projection portions 45 in the Z direction preferably corresponds to the height obtained by adding the thickness of the semiconductor devices 3 and the height of the bumps B.

[0036] The gate electrode block 41 has a rectangular cuboid shape that is longer in the X direction. Specifically, the width of the gate electrode block 41 in the X direction corresponds to the width of the long portion 24a in the X direction. The width in the Y direction of the gate electrode block 41 is slightly smaller than the width of the L portion 24a. Furthermore, a chamfer is formed at each corner portion on the upper surface side of the collector electrode block 40. A lower surface of the gate electrode block 41 is bonded to an upper surface of the long portion in the X direction of the L portion 24a via the bonding material S.

[0037] The emitter electrode block 42 has a rectangular cuboid shape extending along the short side on the other side of the longitudinal direction of the insulating plate 20 in the X direction. Specifically, the X-direction and Y-direction widths of the emitter electrode block 42 are slightly smaller than the corresponding widths of the emitter portion 25a. Additionally, a chamfer is formed at each corner portion on an upper surface side of the emitter electrode block 42. A lower surface of the emitter electrode block 42 is bonded to an upper surface of the emitter portion 25a via the bonding material S. The emitter electrode block 42 is disposed outside the collector electrode block 40 (flat plate portion 44) in plan view.

[0038] The sense emitter electrode block 43 has a rectangular cuboid shape that is longer in the X direction. Specifically, the X-direction and Y-direction widths of the sense emitter electrode block 43 are slightly smaller than the corresponding widths of the sense emitter portion 25d. Furthermore, a chamfer is formed at each corner portion on the upper surface side of the collector electrode block 40. A lower surface of the sense emitter electrode block 43 is bonded to an upper surface of the sense emitter portion 25d via the bonding material S. The sense emitter electrode block 43 is disposed outside the collector electrode block 40 (flat plate portion 44) in plan view. The sense emitter electrode block 43 is disposed adjacent to the gate electrode block 41 in the X direction. Furthermore, a length in the X direction of the sense emitter electrode block 43 is shorter than the length of the gate electrode block 41.

[0039] The thus constructed barrier electrodes 4 are designed to have the same height in the Z direction. Furthermore, the barrier electrodes 4 are preferably made of a metal material with good thermal conductivity, such as copper or aluminum. Furthermore, the collector electrode block 40 may be formed by integrating the flat plate portion 44 and the pair of projection portions 45 therein; or it may be formed by joining the flat plate portion 44 and the pair of projection portions 45 by welding or the like.

[0040] In addition, a space above the laminated substrate 5 is filled with a sealing resin 5 (see Fig. 1). The sealing resin 5 is filled, for example, through the through-hole 46 to seal the semiconductor devices 3, the laminated substrate 2, and the barrier electrodes 4. An epoxy resin or silicone gel can be used as the sealing resin 5.

[0041] In a conventional semiconductor module, a semiconductor device is arranged on an upper surface of a laminated substrate. An emitter electrode is arranged on an upper surface of the semiconductor device; and a collector electrode is arranged on a lower surface of the semiconductor device. An emitter electrode and a circuit pattern of the laminated substrate are electrically connected, for example, by a bonding wire. In addition, a cooler is arranged on a lower surface of the laminated substrate.

[0042] In the conventional design, heat generated by the emitter electrode is dissipated to the outside through the cooler. In this case, the emitter electrode is located on a front surface side of the semiconductor device, and therefore the heat is directed to a rear surface side (collector electrode side) of the semiconductor device and dissipated to the outside through the laminated substrate and the cooler.

[0043] As described above, the semiconductor device generates heat on one side of the emitter electrode, and therefore, it is necessary to transfer the heat generated on the emitter electrode side to the collector electrode side, where the cooler is located. This creates a problem in that the thermal resistance of the entire module increases according to the thermal conductivity and thickness of the semiconductor device. In addition, there is another problem that, as described above, a wiring length must be long because the wiring is conventionally implemented by a bonding wire, resulting in increased inductance.

[0044] Then, the inventors focused their attention on the direction of an emitter electrode, which is a heat generation source of a semiconductor device, and conceived the present invention. That is, the gist of the present invention lies in reversing a connection direction of the semiconductor devices 3 from the conventional one and arranging the emitter electrodes 32 to face one side of the laminated substrate 2. Specifically, in the present embodiment, the semiconductor devices 3 are arranged on an upper surface of the laminated substrate 2. On the upper surface of each of the semiconductor devices 3, the collector electrode 30 is arranged; and on a lower surface of each of the semiconductor devices 3, the emitter electrode 32 is arranged. The emitter electrode 32 is connected to a corresponding circuit pattern 22 on the laminated substrate 2 via bumps B.

[0045] Furthermore, the barrier electrode 4 (collector electrode block 40) is connected to the collector electrode 30 on an upper surface side of the semiconductor device 3. The collector electrode block 40 includes: the flat plate portion 44 covering a portion above the semiconductor devices 3; and the projection portions 45 extending from both ends of the flat plate portion 44 to corresponding circuit patterns 22. The projection portions 45 are connected to the circuit patterns 22.

[0046] According to this embodiment, the emitter electrode 32 faces the laminated substrate 2 side and is connected to the laminated substrate 2 via bumps B, so that heat generated by the emitter electrode 32 can be directly conducted to the laminated substrate 2 (heat dissipation plate 21) via bumps B without passing through an interior of the semiconductor device. This reduces thermal resistance, thereby increasing cooling efficiency. Reducing the thermal resistance allows the module size to be brought close to a chip size, thereby achieving downsizing of the entire module. In addition, wiring the emitter electrode 32 with bumps B can reduce the wiring length compared with conventional bonding wires and also reduce inductance.

[0047] Furthermore, the electrical connection of the collector electrodes 30 through the collector electrode block 40 eliminates unnecessary wiring and allows heat to be conducted from the semiconductor devices 3 to the laminated substrate 2 via the collector electrode block 40. This means that the collector electrode block 40 can be used not only as an electrical bonding material but also as a heat conduction material. This allows for further improvement in cooling efficiency. Furthermore, by using a plurality of metal barrier electrodes 4 with high heat capacity, a module with high transient thermal characteristics and short-circuit resistance can be provided.

[0048] In the present embodiment, a direction in which the two projection portions 45 in the collector electrode block 40 face each other preferably corresponds to a direction in which a coolant flows in a region (cooling direction F) corresponding to that of the collector electrode block 40 in the cooler 10 attached to the underside of the semiconductor module 1. The direction in which the coolant flows may, for example, be parallel to the grooves 10b in the cooler 10 having the plurality of fins 10a having the grooves 10b formed in one direction (X direction), as shown in Fig. 1. Furthermore, in a radiator 10 consisting of, for example, a water jacket, a direction in which a liquid flows within the water jacket may correspond to a direction in which the pair of projection portions 45 are opposed to each other.

[0049] In particular, the pair of projection sections 45 as in Fig. 5A, each has a rectangular cuboid shape that is longer in the Y direction, and they are opposite each other in the X direction. In this case, the direction in which the coolant flows in the radiator 10 (cooling direction F) preferably runs in the X direction. According to this, as shown in Fig. 5B, the coolant flows from a part under one of the projection portions 45 to a part under the other of the projection portions 45 through a part under the flat plate portion 44. The coolant thus flows in a direction perpendicular to a longitudinal direction (long side) of the projection portions 45, so that the coolant contributes to cooling the collector electrode block 40 in a wide range.

[0050] As in Fig. As shown in Figure 5B, in a flow center of the coolant (the middle side in the X direction of the semiconductor module 1), the heat of the semiconductor devices 3 can be dissipated to one side of the cooler 10 via bumps B. Furthermore, on an upstream and downstream side of the coolant (outside in the X direction of the semiconductor module 1), the heat of the semiconductor devices 3 can be dissipated to the cooler 10 side via the flat plate portion 44 and the pair of projection portions 45. Thus, heat can be efficiently dissipated from both sides of the semiconductor devices 3. As a result, the four semiconductor devices 3 arranged between the pair of projection portions 45 in a part below the flat plate portion 44 can be uniformly cooled. Thus, temperature fluctuations of each of the semiconductor devices 3 can be prevented, enabling an improvement in cooling performance.

[0051] Furthermore, in the present embodiment, the through-hole 46, which penetrates in a thickness direction, is formed in the center of the flat plate portion 44. According to this structure, the through-hole 46 can be used as an injection port for the sealing resin 5. This allows the sealing resin 5 to be evenly filled between the flat plate portion 44 and the semiconductor devices 3. Furthermore, voids formed during the injection of the sealing resin 5 can be easily removed.

[0052] Furthermore, in the present embodiment, the gate electrodes 31 are arranged closer to a central side of the flat plate portion 44 than the emitter electrodes 32. That is, each of the gate electrodes 31 of the four semiconductor devices 3 is arranged toward the central side of the flat plate portion 44, as shown in Fig. 3 and Fig. 4, and each of the emitter electrodes 32 is positioned on an outer peripheral side as the gate electrodes 31. Specifically, the four semiconductor devices 3 are arranged in a 2x2 arrangement in plan view below the flat plate portion 44, and the gate electrodes 31 of the semiconductor devices 3 are arranged opposite each other in the center of the flat plate portion 44. According to this arrangement, the emitter electrodes 32, which are sites of heat generation, are not concentrated on the center side of the module, and a gap is allowed between the emitter electrodes 32. As a result, heat is dissipated without being concentrated in the center of the module, thereby allowing an improvement in cooling efficiency.Moreover, each of the gate electrodes 31 is arranged on a center side of the laminated substrate 2 and connected to an upper surface of each of the ends of the branched H-portion 24b via bumps B, which can make the wiring length from an outside to each of the gate electrodes 31 short and uniform and further prevent gate oscillations.

[0053] Furthermore, in the present embodiment, the gate electrode block 41, the emitter electrode block 42, and the sense emitter electrode block 43 are arranged on an outer side of the collector electrode block 40. That is, the collector electrode block 40 is arranged so that it is sandwiched in the Y direction between the gate electrode block 41, the emitter electrode block 42, and the sense emitter electrode block 43. According to this arrangement, the emitter electrode block 42 and the sense emitter electrode block 43 are arranged on the outer side of the collector electrode block 40, thereby enabling easy implementation of external connection.

[0054] In the following, a method for manufacturing a semiconductor module according to an aspect of the present embodiment will be described with reference to Fig. 6 to Fig. 9 described. Fig. 6 to 9 are perspective views each showing an example of a step of the method for manufacturing a semiconductor module according to the present embodiment. Note that the manufacturing method described below is merely an example that can be appropriately modified without being limited to this embodiment. In the following figures, the heat dissipation plate is omitted for simplified description. In addition, Figures A and B of the Fig. 6, Fig. 7 and Fig. 9 states before and after each step.

[0055] A method for manufacturing the semiconductor module 1 according to the present embodiment includes the following steps, which are carried out in the order given: a preparation step of preparing a laminated substrate 2 and barrier electrodes 4; a chip arrangement step of arranging semiconductor devices 3 on a collector electrode block 40 (see Fig. 6); a first barrier electrode disposing step of disposing a gate electrode block 41, an emitter electrode block 42 and a sense emitter electrode block 43 on the laminated substrate 2 (see Fig. 7); a bump arranging step of arranging bumps on the semiconductor devices 3 (see Fig. 8); a second barrier electrode disposing step of disposing the collector electrode block 40 and the semiconductor devices 3 on the laminated substrate 2 (see Fig. 9); and a sealing step of filling a sealing resin 5 (see Fig. 1). Note that the order of these steps can be changed as appropriate, as long as no contradiction arises.

[0056] First, the laminated substrate 2 and the barrier electrodes 5 (collector electrode block 40, gate electrode block 41, emitter electrode block 42, and sense emitter electrode block 43) described above are prepared in advance (preparation step).

[0057] Next, the chip placement step is performed. As shown in Fig. 6A and Fig. 6B, in the chip arrangement step, four semiconductor devices 3 are arranged with the collector electrodes 30 facing a lower surface of the flat plate portion 44. On an upper surface (collector surface) of each of the semiconductor devices 3, a bonding material S (see Fig. 4) and the arrangement is performed at predetermined positions of the flat plate portion 44. In this case, a gate electrode 31 of each semiconductor device 3 is arranged inward in the X direction with respect to an emitter electrode 32. Then, the collector surfaces of the semiconductor devices 3 are pressed against the flat plate portion 33 with a predetermined pressure and heated to a predetermined temperature for a predetermined time, thereby electrically connecting the semiconductor devices 3 and the flat plate portion 44 via the bonding material S. Note that, as the bonding material S, a material formed in advance into a sheet-like shape corresponding to the shape of the semiconductor devices 3 may be used; alternatively, a paste-like sintered metal material or the like may be applied to the collector surfaces.

[0058] Next, the first blocking electrode placement step is performed. As shown in Fig. 7A and Fig. 7B, in the first barrier electrode arrangement step, the gate electrode block 41, the emitter electrode block 42, and the sense emitter electrode block 43 are arranged at predetermined positions on the circuit patterns 22. Specifically, the gate electrode block 41 is arranged on an upper surface of the L-portion 24a via the bonding material S. The emitter electrode block 42 is arranged on an upper surface of the emitter portion 25a via the bonding material S. The sense emitter electrode block 43 is arranged on an upper surface of the sense emitter portion 25a via the bonding material S. Then, these barrier electrodes 4 are pressed against the laminated substrate 2 with a predetermined pressure and heated to a predetermined temperature for a predetermined time, thereby electrically connecting the circuit patterns 22 and the barrier electrodes 4 except the collector electrode block 40 via the bonding material S.

[0059] Next, the bump arrangement step is performed. As shown in Fig. As shown in Figure 8, in the bump arrangement step, bumps B with a predetermined height are arranged on the emitter electrodes 32 and the gate electrodes 31. Additionally, the bonding material S is arranged on the lower surface of the pair of projection portions 45. Note that the bumps B preferably have a height such that the bumps B protrude slightly more than the lower surfaces of the bonding material S.

[0060] Next, the arrangement step of the second blocking electrode is carried out. As shown in Fig. 9A and Fig. 9B, in the second barrier electrode disposition step, the emitter electrodes 32 are connected to a corresponding circuit pattern 22 via bumps B, and the pair of projection portions 45 are connected to corresponding circuit patterns 22 via the bonding material S. Specifically, the bumps B disposed on the emitter electrodes 32 are positioned on upper surfaces of the pair of long portions 25b and 25c; and the bumps B disposed on the gate electrodes 31 are positioned on an upper surface of the H portion 24b. In addition, the pair of projection portions 45 are disposed on upper surfaces of the pair of collector circuit patterns 23 via the bonding material S.The collector electrode block 40 is pressed against the laminated substrate 2 with a predetermined pressure and heated for a predetermined time at a predetermined temperature; and thereby, the emitter electrodes 32 are connected to their corresponding circuit patterns 22 via bumps B, and the collector electrode block 40 is connected to the collector circuit patterns 23 via the bonding material S.

[0061] Next, the sealing step is carried out. As in Fig.As shown in Figure 1, in the sealing step, a space above the laminated substrate 2 is sealed with the sealing resin 5. For example, a rectangular frame body (not shown) is arranged around the laminated substrate 2, and a space within the frame body can be uniformly filled with the sealing resin 5 through the through-hole 46. The sealing resin 5 is cured, thereby sealing the laminated substrate 2, the semiconductor devices 3, and the barrier electrodes 4. Thus, the integrated semiconductor module 1 is completed.

[0062] As described above, according to the present invention, a connection direction of the semiconductor device 3 is reversed from the conventional one, and the emitter electrode 32 is arranged on the laminated substrate 2 side, thereby achieving a reduction in thermal resistance and inductance. Furthermore, the configurations of wires and the like can be omitted compared to the prior art, enabling simplification and miniaturization of the structure of the entire module.

[0063] In the above embodiment, the number and arrangement positions of the semiconductor devices 3 are not limited to the above embodiment and can be changed as appropriate.

[0064] In the above embodiment, the number and layout of the circuit patterns 22 are not limited to the above embodiment and can be changed as appropriate.

[0065] In the above embodiment, the laminated substrate 2 and the semiconductor devices 3 are rectangular or square in plan view, but this embodiment is not limited to this. The laminated substrate 2 and the semiconductor devices 3 may be polygonal in shape other than the above.

[0066] In addition, the present embodiment and modifications have been described, but the above embodiment and modifications may also be partially or wholly combined and regarded as another embodiment.

[0067] Furthermore, the present embodiment is not limited to the above embodiment and its modifications, and various changes, substitutions, and modifications are possible without deviating from the core of the technical idea. Furthermore, if the technical idea can be implemented in other ways through technical advancements or other derived techniques, the method can be used. Therefore, the claims cover all embodiments that can be included within the scope of the technical idea.

[0068] The characteristic aspects of the above embodiment will now be described in summary.

[0069] The semiconductor module described in the above embodiment is characterized by comprising: a laminated substrate having a circuit pattern arranged on an upper surface of an insulating plate and a heat dissipation plate arranged on a lower surface of the insulating plate; a semiconductor device having a collector electrode arranged on its upper surface, an emitter electrode and a gate electrode arranged on its lower surface, the emitter electrode and the gate electrode each being connected to an upper surface of the circuit pattern via a bump; and a barrier electrode connected to the collector electrode.The barrier electrode includes: a flat plate portion covering the semiconductor device; and a pair of projection portions projecting from both ends of the flat plate portion toward the circuit pattern and connected to the circuit pattern.

[0070] The semiconductor module described in the above embodiment is further characterized in that a direction in which the pair of projection portions oppose each other corresponds to a direction in which a coolant flows.

[0071] The semiconductor module described in the above embodiment is further characterized in that the semiconductor device is arranged between the pair of cantilever portions.

[0072] The semiconductor module described in the above embodiment is further characterized in that a through hole is formed in the center of the flat plate portion.

[0073] The semiconductor module described in the above embodiment is further characterized in that the semiconductor device has a gate electrode arranged on the lower surface thereof, the gate electrode being arranged closer to a center side of the flat plate portion than the emitter electrode.

[0074] The semiconductor module described in the above embodiment is further characterized in that four pieces of the semiconductor device are arranged in a 2x2 arrangement in plan view under the flat plate portion, and the gate electrodes of the semiconductor devices are arranged opposite to each other in the center of the flat plate portion.

[0075] The semiconductor module described in the above embodiment is further characterized in that: the circuit pattern includes a collector circuit pattern connected to the collector electrode, a gate circuit pattern connected to the gate electrode, and an emitter circuit pattern connected to the emitter electrode; the barrier electrode includes a collector electrode block connected to the collector circuit pattern, a gate electrode block connected to the gate circuit pattern, an emitter electrode block connected to an emitter portion of the emitter circuit pattern, and a sense emitter electrode block connected to a sense emitter portion of the emitter circuit pattern;and the collector electrode block consists of the flat plate portion and the pair of projection portions, and outside the collector electrode block, the gate electrode block, the emitter electrode block, and the sense emitter electrode block are arranged.;

[0076] The semiconductor module described in the above embodiment is further characterized in that: the gate circuit pattern has a region where the gate electrode in the center of the insulating plate is connected via its corresponding bump; and the emitter circuit pattern has a region where the emitter electrode outside the gate circuit pattern is connected via its corresponding bump.

[0077] The semiconductor module described in the above embodiment is further characterized in that: the gate circuit pattern is arranged in the center of the insulating plate and has an H-section having an H-shape in plan view where the gate electrode is connected via its corresponding bump to an upper surface of one end of a branched H-section; and the emitter circuit pattern has a pair of long sections arranged to oppose each other between the pair of cantilever sections so as to sandwich the H-section where the emitter electrode is connected via its corresponding bump to the pair of long sections.

[0078] The semiconductor module described in the above embodiment is further characterized in that the collector circuit pattern has long shapes corresponding to the pair of projection portions, and each of the pair of long portions is arranged between the H portion and the collector circuit pattern.

[0079] The semiconductor module described in the above embodiment is further characterized in that: the emitter circuit pattern includes an emitter portion connected between one end of the long portions in the pair and a sense emitter portion connected to a long portion of the pair of long portions; the emitter electrode block is connected to an upper surface of the emitter portion; the sense emitter electrode block is connected to an upper surface of the sense emitter portion; and the emitter electrode block and the sense emitter electrode block are arranged to enclose the flat plate portion outside the flat plate portion in plan view.

[0080] The semiconductor module described in the above embodiment is further characterized in that the gate electrode block is opposed to the emitter electrode block via the flat plate portion and is arranged side by side with the sense emitter block.

[0081] Furthermore, the method for manufacturing a semiconductor module described in the above embodiment is characterized by performing: a preparation step of preparing a laminated substrate having a circuit pattern arranged on an upper surface of an insulating plate, a heat dissipation plate arranged on a lower surface of the insulating plate, and a barrier electrode including a flat plate portion covering a semiconductor device and a pair of projection portions projecting from both ends of the flat plate portion toward the circuit pattern; a chip arranging step of arranging the semiconductor device with a collector electrode thereof aligned with a lower surface of the flat plate portion;and a barrier electrode disposing step of connecting, after the chip disposing step, an emitter electrode disposed on a lower surface of the semiconductor device via a bump and also connecting the pair of projection portions to the circuit pattern.;

[0082] The method for manufacturing a semiconductor module described in the above embodiment is further characterized in that: a through hole is formed in the center of the flat plate portion; and after the barrier electrode disposing step, a sealing step is performed in which the semiconductor device is sealed by filling a sealing resin through the through hole. Industrial applicability

[0083] As described above, the present invention is effective to reduce a thermal resistance and an inductance; and it is particularly useful for a semiconductor module and a method of manufacturing a semiconductor module. LIST OF REFERENCE SYMBOLS 1 semiconductor module 2 laminated substrate 3 Semiconductor device 4 Blocking electrode 5 Sealing resin 10 coolers 10a slat 10b groove 20 Insulation plate 21 Heat dissipation plate 22 circuit patterns 23 collector circuit patterns 24 gate circuit patterns 24a L-section 24b H-section 25 emitter circuit patterns 25a Emitter section 25b long section 25c long section 25d Sense emitter section 30 collector electrode 31 Gate electrode 32 Emitter electrode 40 Collector electrode block 41 Gate electrode block 42 Emitter electrode block 43 Sense-emitter electrode block 44 flat plate section 45 cantilever section 46 through hole B Bump F Cooling direction (direction in which the coolant flows) S Bonding material

Claims

[1] Semiconductor module (1), comprising: a laminated substrate (2) having a circuit pattern (22) arranged on an upper surface of an insulating plate (20) and a heat dissipation plate (21) arranged on a lower surface of the insulating plate (20); a semiconductor device (3) having an upper surface and a lower surface, a collector electrode (30) arranged on the upper surface, an emitter electrode (32) and a gate electrode (31) arranged on the lower surface, wherein the emitter electrode (32) and the gate electrode (31) are each connected to an upper surface of the circuit pattern (22) via a bump (B); and a barrier electrode (4) having a collector electrode block (40) connected to the collector electrode (30) and another electrode block connected to the circuit pattern outside the collector electrode block (40) in a plan view of the semiconductor module (1), wherein the collector electrode block (40) comprises: a flat plate portion (44) covering the semiconductor device (3); and a pair of projection portions (45) projecting from both ends of the flat plate portion (44) toward the circuit pattern (22) and connected to the circuit pattern (22). [2] Semiconductor module (1) according to claim 1, characterized by that the pair of projection sections (45) are arranged along two opposite sides of the insulating plate (20). [3] Semiconductor module (1) according to claim 1 or 2, characterized bythat a direction in which the pair of projection portions (45) oppose each other corresponds to a direction in which a coolant flows. [4] Semiconductor module (1) according to one of claims 1 to 3, characterized by that the semiconductor device (3) is arranged between the pair of projection portions (45). [5] Semiconductor module (1) according to one of claims 1 to 4, characterized by that a through hole (46) is formed in a center of the flat plate portion (44). [6] Semiconductor module (1) according to one of claims 1 to 5, characterized by that the gate electrode (31) is arranged closer to the center of the flat plate portion (44) than the emitter electrode (32). [7] Semiconductor module (1) according to one of claims 1 to 6, characterized bythat four pieces of the semiconductor device (3) are arranged in a 2x2 arrangement in plan view under the flat plate portion (44) and the gate electrodes (31) of the semiconductor devices (3) are arranged opposite each other in the center of the flat plate portion (44). [8] Semiconductor module (1), comprising: a laminated substrate (2) having a circuit pattern (22) arranged on an upper surface of an insulating plate (20) and a heat dissipation plate (21) arranged on a lower surface of the insulating plate (20); a semiconductor device (3) having an upper surface and a lower surface, a collector electrode (30) arranged on the upper surface, an emitter electrode (32) and a gate electrode (31) arranged on the lower surface, wherein the emitter electrode (32) and the gate electrode (31) are each connected to an upper surface of the circuit pattern (22) via a bump (B); and a barrier electrode (4) connected to the collector electrode (30), the barrier electrode (4) comprising: a flat plate portion (44) covering the semiconductor device (3); and a pair of projection portions (45) projecting from both ends of the flat plate portion (44) to the circuit pattern (22) and connected to the circuit pattern (22), wherein the circuit pattern (22) comprises: a collector circuit pattern (23) connected to the collector electrode (30); a gate circuit pattern (24) connected to the gate electrode (31); and an emitter circuit pattern (25) connected to the emitter electrode (32); the blocking electrode (4) comprises: a collector electrode block (40) connected to the collector circuit pattern (23); a gate electrode block (41) connected to the gate circuit pattern (24); an emitter electrode block (42) connected to an emitter portion (25a) of the emitter circuit pattern (25); and a sense emitter electrode block (43) connected to a sense emitter portion (25d) of the emitter circuit pattern (25); the collector electrode block (40) consists of the flat plate portion (44) and the pair of projection portions (45); and the gate electrode block (41), the emitter electrode block (42), and the sense emitter electrode block (43) are arranged outside the collector electrode block (40). [9] Semiconductor module (1) according to claim 8, characterized by , that: the gate circuit pattern (24) has a region where the gate electrode (31) is connected in the center of the insulating plate (20) via its corresponding bump (B); and the emitter circuit pattern (25) has a region where the emitter electrode (32) is connected outside the gate circuit pattern (24) via its corresponding bump (B). [10] Semiconductor module (1) according to claim 9, characterized by , that: the gate circuit pattern (24) is arranged in the center of the insulating plate (20) and has an H-section (24-b) which has an H-shape in plan view, the H-section (24-b) being divided into branches and the gate electrode (31) being connected via its corresponding bump (B) to an upper surface of one end of each of the branches; and the emitter circuit pattern (25) has a pair of long sections (25b, 25c) arranged to oppose each other between the pair of projection sections (45) such that the long sections (25b, 25c) enclose the H section (24-b), the emitter electrode (32) being connected to the pair of long sections (25b, 25c) via its corresponding bump (B). [11] Semiconductor module (1) according to claim 10, characterized by , that: the collector circuit pattern (23) has a long shape corresponding to each of the pair of projection portions (45); and each in the pair of long sections (25b, 25c) is arranged between the H-section (24-b) and the collector circuit pattern (23). [12] Semiconductor module (1) according to claim 11, characterized by , that: the emitter circuit pattern (25) comprises: an emitter section connecting first ends of the pair of long sections (25b, 25c) together; and a sense-emitter section connected to a long section in the pair of long sections (25b, 25c); and the emitter electrode block (42) is connected to an upper surface of the emitter section; the sense emitter electrode block (43) is connected to an upper surface of the sense emitter section; and the emitter electrode block (42) and the sense emitter electrode block (43) are arranged so as to enclose the flat plate portion (44) outside the flat plate portion (44) in plan view. [13] Semiconductor module (1) according to claim 12, characterized by , that: the gate electrode block (41) is opposite the emitter electrode block (42) via the flat plate portion (44) and is arranged side by side with the sense emitter electrode block (43). [14] A method for producing a semiconductor module (1), comprising the steps of: a preparatory step of preparing: a laminated substrate (2) having a circuit pattern (22) arranged on an upper surface of an insulating plate (20) and a heat dissipation plate (21) arranged on a lower surface of the insulating plate (20); and a barrier electrode (4) including a collector electrode block (40) and another electrode block, the collector electrode block (40) comprising: a flat plate portion (44) covering a semiconductor device (3), and a pair of projection portions (45) projecting from both ends of the flat plate portion (44) toward the circuit pattern (22); and a chip arranging step of arranging the semiconductor device (3), wherein a collector electrode (30) of the semiconductor device (3) is aligned with a lower surface of the flat plate portion (44); and a barrier electrode arranging step of connecting, after the chip arranging step, an emitter electrode (32) to the circuit pattern (22) on the insulating plate (20) via a bump (B), the emitter electrode (32) being arranged on a lower surface of the semiconductor device (3), connecting the pair of projection portions (45) to the circuit pattern (22), and connecting the other electrode block to the circuit pattern outside the collector electrode block (40) in a plan view of the semiconductor module (1). [15] Method for producing a semiconductor module (1) according to claim 14, characterized by , that: a through hole (46) is formed in a center of the flat plate portion (44); and after the barrier electrode disposing step, a sealing step is carried out in which the semiconductor device (3) is sealed by filling a sealing resin (5) through the through hole (46).

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