Structure and device with interblock die-electric for recessed contacts and method for forming the same

Abstract

Procedure, comprehensive: Formation of a metallic region (68) in a first insulating layer (48); Forming a recess (71) in the metallic region (68); Filling the recess (71) with an intermediate block dielectric (73); Deposition of a second insulating layer (76) over the metallic region (68) and the first insulating layer (48); Forming a first conductive structure (84) that extends through the second insulating layer (76) and into the metallic region (68); and Forming a second conductive structure (94) extending through the second insulating layer (76) and into the metallic region (68), wherein the first conductive structure (84) is located on a first side of the interblock dielectric (73) and the second conductive structure (94) is located on a second side of the interblock dielectric (73), the second side being opposite to the first side.

Description

BACKGROUND

[0001] In the fabrication of integrated circuits, contact plugs are used for electrical coupling with the source and drain regions and the gates of transistors. The source / drain contact plugs were typically associated with source / drain silicide regions, the formation processes of which included creating contact orifices to expose the source / drain regions, depositing a metal layer, depositing a barrier layer over the metal layer, performing an annealing process to allow the metal layer to react with the source / drain regions, filling the remaining contact orifice with metal, and performing a chemical-mechanical polishing (CMP) process to remove excess metal.

[0002] Prior art relating to the subject matter of the invention can be found, for example, in the publications US 2004 / 0 113 279 A1, US 2019 / 0 287 851 A1, DE 10 2017 127 206 A1 and US 2018 / 0 053 721 A1. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Aspects of this disclosure are best understood with reference to the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry practice, various features are not shown to scale. In fact, the dimensions of the various features may have been arbitrarily enlarged or reduced for the sake of clarity. The Fig. 1 to 7, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 10D, 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 14D, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 19A, 19B, 22A, 22B, 22C, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, 25C, 26A, Figures 26B, 26C, 27A and 27B illustrate perspective views and cross-sectional views of intermediate stages in the formation of a fin field effect transistor (FinFET) and the corresponding contact connectors according to some embodiments of the present disclosure. The Fig. 20A, Fig. 20B, Fig. 20C and Fig. Figure 20D illustrates enlarged views of contact structures according to different embodiments. The Fig. 21A, Fig. 21B, Fig. 21C, Fig. 21D, Fig. 21E, Fig. 21F, Fig. 21G, Fig. 21H, Fig. 21I and Fig. Figures 21J are enlarged views of an intermediate block according to various embodiments. The Fig. 28A, Fig. 28B, Fig. 28°C, Fig. 28D, Fig. 28E, Fig. 28F, Fig. 28G, Fig. 28H, Fig. 28I, Fig. 28 years old, and Fig. Figures 28K are top and cross-sectional views of intermediate stages in the formation of a conductive structure and an intermediate block according to some embodiments. Fig. Figure 29 illustrates a process flow for forming a transistor and conductive structures according to some embodiments. Fig. Figure 30 illustrates a process flow for forming gate contacts according to some embodiments. Fig. Figure 31 illustrates a process flow for forming conductive structures according to some embodiments. DETAILED DESCRIPTION

[0004] The following disclosure provides many different embodiments or examples for implementing various features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, forming a first element over or on top of a second element in the following description may include embodiments in which the first and second elements are formed in direct contact, and also embodiments in which additional elements may be formed between the first and second elements, such that the first and second elements may not be in direct contact. Furthermore, the present disclosure may repeat reference numbers and / or symbols in the various examples.This repetition serves the purpose of simplicity and clarity and does not in itself dictate a relationship between the various described embodiments and / or configurations.

[0005] Furthermore, spatially relative terms such as "underlying," "below," "under," "lower," "above," "above," "upper," and the like may be used herein to facilitate discussion and describe the relationship of one element or feature to another element or feature, or to other elements or features, as illustrated in the figures. These spatially relative terms are intended to encompass, in addition to the orientation shown in the figures, various orientations of the device during its use or operation. The device may be oriented differently (rotated by 90 degrees or in other orientations), and the spatially relative descriptors used herein may likewise be interpreted accordingly.

[0006] An intermediate block is provided to separate a first recessed conductive structure from a second recessed conductive structure. Each of the recessed conductive structures extends into an underlying metallic element and up through an overlying insulating layer, such as an interlayer dielectric. The intermediate block is formed within the underlying metallic element to prevent galvanic effects between the individual recessed conductive structures and / or between the underlying metallic element and the first recessed conductive structures when the second recessed conductive structure is fabricated. The intermediate block prevents the etching process performed during the formation of the second recessed conductive structure from causing a galvanic reaction between the underlying metallic element and the first recessed conductive structure.Since the intermediate block also prevents the recessed conductive structures from coming into contact with each other, galvanic effects, such as galvanic corrosion, between the recessed conductive structures can be reduced or eliminated, so that different metals can be used for each recessed contact.

[0007] According to some embodiments, a source / drain contact connector is formed in a first intermediate dielectric, and an intermediate block is formed within the source / drain contact connector. A second intermediate dielectric is formed over the first, and one or more conductive structures are formed as recessed conductive structures in the second intermediate dielectric. For example, when etching the second intermediate dielectric to form a second opening for a recessed conductive structure, the second opening is intentionally positioned on opposite sides of the intermediate block from the first opening, thereby exposing the lower source / drain contact connector.The exposed top surface of the lower source / drain connector is etched through the first and second openings to provide an enlarged opening or depression in the top surface of the lower source / drain connector that is wider than the lateral extensions of the underside of the first and second openings. Because the intermediate block is formed within the lower source / drain connector, the enlarged opening or depression is prevented from extending laterally beyond the intermediate block. The conductive structure is then grown in a bottom-up process and has a shape resembling an inverted mushroom.

[0008] Although a fin field-effect transistor (FinFET) is used as an example, it is understood that other transistor types, such as planar transistors, gate all-around transistors (GAA transistors), or the like, can also incorporate the embodiments described in this disclosure. Furthermore, other conductive elements, including but not limited to conductive wires, conductive connectors, conductive vias, and the like, can incorporate the embodiments described in this disclosure, although source / drain contact connectors are used as examples. The embodiments described herein are intended to provide examples to facilitate the manufacture or use of the subject matter of this disclosure, and a person skilled in the art will readily recognize modifications that remain within the intended scope of different embodiments.Throughout the various views and illustrative embodiments, the same reference numbers are used to denote the same elements. Although some process implementations may be described as being executed in a specific sequence, other process implementations can be executed in any logical order.

[0009] The Fig. 1 TO 7, 8A, 8B, 8C, 9A, 9B, 9C, 10A, 10B, 10C, 10D, 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 14D, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, 19A, 19B, 22A, 22B, 22C, 23A, 23B, 23C, 24A, 24B, 24C, 25A, 25B, 25C, 26A, Figures 26B, 27A, and 27B illustrate perspective and cross-sectional views of intermediate stages in the formation of a fin field-effect transistor (FinFET) and the corresponding contact connectors according to some embodiments of the present disclosure. The corresponding processes are described in process flow 200 as set out in Fig. 29 is shown, and in the process flow 232 in Fig. 30 also shown schematically.

[0010] Fig. Figure 1 illustrates a perspective view of a starting structure formed on wafer 10. Wafer 10 has substrate 20. Substrate 20 can be a semiconductor substrate, which may be a silicon substrate, a silicon germanium substrate, or a substrate formed from other semiconductor materials. Substrate 20 can be doped with a p-type or an n-type dopant. The isolation regions 22, such as shallow trench isolation regions (STI regions), can be formed such that they extend from an upper surface of substrate 20 into the substrate 20. The corresponding process is described in Figure 1. Fig. The process flow 200 shown in Figure 29 is illustrated as process 202. The sections of substrate 20 between adjacent STI regions 22 are referred to as semiconductor strips 24. The top surfaces of the semiconductor strips 24 and the top surfaces of the STI regions 22 can be substantially level with each other. According to some embodiments of the present disclosure, the semiconductor strips 24 are parts of the original substrate 20, and therefore the material of the semiconductor strips 24 is the same as that of the substrate 20. According to alternative embodiments of the present disclosure, the semiconductor strips 24 are substitute strips formed by etching the sections of substrate 20 between the STI regions 22 to form wells and performing an epitaxial process to grow further semiconductor material in the wells.Accordingly, the semiconductor strips 24 are formed from a semiconductor material that differs from that of the substrate 20. According to some embodiments, the semiconductor strips 24 are formed from silicon germanium, silicon carbon, or a III-V compound semiconductor material.

[0011] In some embodiments, a lining such as an oxide lining can be arranged between the STI regions 22 and the semiconductor strips 24 (not shown). This lining can be a thermal oxide layer formed by the thermal oxidation of an area layer of the substrate 20. The oxide layer can also be a deposited silicon oxide layer formed using, for example, atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDPCVD), chemical vapor deposition (CVD), or the like. The STI regions 22 have a dielectric above the lining (if used), the dielectric being formed using flowable chemical vapor deposition (FCVD), spin coating, or the like.

[0012] With reference to Fig. 2. The STI regions 22 (and the lining, if used) are recessed so that the upper sections of the semiconductor strips 24 protrude higher than the upper surfaces 22A of the remaining sections of the STI regions 22 to form the projecting fins 24'. The corresponding process is described in the Fig. The process flow shown in Figure 29 is illustrated as process 200. The etching can be carried out using a dry etching process, for example, using NF3 and NH3 as etching gases. According to alternative embodiments of the present disclosure, the embedding of the STI regions 22 is carried out using a wet etching process. The etching chemical can, for example, contain a dilute HF solution.

[0013] In the embodiments illustrated above, the semiconductor strips can be structured by any suitable method. For example, the fins can be structured using one or more photolithography processes, including dual-structuring or multi-structuring processes. In general, dual-structuring or multi-structuring processes combine photolithography and self-alignment processes, making it possible to produce structures with, for example, spacings that are smaller than what is otherwise achievable using a single direct photolithography process. In one embodiment, for example, a sacrificial layer is formed over a substrate and structured using a photolithography process. Spacing elements are formed along the structured sacrificial layer using a self-alignment process.The sacrificial layer is then removed and the remaining spacers or thorns can then be used to structure the fins.

[0014] With reference to Fig. 3. The dummy gate stacks 30 are formed so that they extend onto the upper surfaces and side walls of the (projecting) fins 24'. The corresponding process is described in the Fig. The process flow 200 shown in Figure 29 is illustrated as process 206. The dummy gate stacks 30 can have dummy gate dielectrics (not shown) in the sidewalls of the projecting fins 24' and dummy gate electrodes 34 over the corresponding dummy gate dielectrics. The dummy gate dielectrics can contain silicon oxide. The dummy gate electrodes 34 can be formed, for example, using polysilicon, and other materials can also be used. Each of the dummy gate stacks 30 can also have a hard mask layer 36 (or several) over the corresponding dummy gate electrodes 34. The hard mask layers 36 can be formed from silicon nitride, silicon oxide, silicon oxynitride, or multiple layers thereof. The dummy gate stacks 30 can transition across one or more projecting fins 24' and / or STI regions 22. The dummy gate stacks 30 also have longitudinal directions perpendicular to the longitudinal directions of the projecting fins 24'.

[0015] Next, the gate spacer elements 38 are formed on the side walls of the dummy gate stack 30. The corresponding process is also described in the Fig. The process sequence 200 shown in Figure 29 is illustrated as process 206. According to some embodiments of the present disclosure, the gate spacer elements 38 are formed from one or more dielectrics such as silicon nitride, silicon carbonitride or the like and can have a single-layer structure or a multi-layer structure including several dielectric layers.

[0016] Subsequently, an etching process is carried out to etch the sections of the projecting fins 24' that are not covered by the dummy gate stack 30 and the gate spacer elements 38, as shown in the Fig. The structure shown in section 4 results. The corresponding process is described in the section on Fig. The process flow 200 shown in Figure 29 is illustrated as process 208. The recession can be anisotropic, and therefore the sections of the projecting fins 24' that lie directly beneath the dummy gate stacks 30 and the gate spacer elements 38 are protected and are not etched. According to some embodiments, the upper surfaces of the recessed semiconductor strips 24 can be lower than the upper surfaces 22A of the STI regions 22. The spaces remaining between the etched projecting fins 24' and the semiconductor strips 24 are referred to as recesses 40. The recesses 40 are located on opposite sides of the dummy gate stacks 30.

[0017] As in Fig. As shown in Figure 5, the epitaxial regions (source / drain regions) 42 are next formed by selective growth (by epitaxy) of a semiconductor material in the recesses 40. The corresponding process is described in Figure 5. Fig. The process flow shown in Figure 29 is illustrated as process 210. Depending on whether the resulting FinFET is a p-FinFET or an n-FinFET, a p- or n-dopant can be added in situ as the epitaxy progresses. For example, if the resulting FinFET is a p-FinFET, silicon germanium boron (SiGeB), silicon boron (SiB), or the like can be grown. Conversely, if the resulting FinFET is an n-FinFET, silicon phosphorus (SiP), silicon carbon phosphorus (SiCP), or the like can be grown. According to alternative embodiments of the present disclosure, the epitaxial regions 42 comprise III-V compound semiconductors, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AIP, GaP, combinations thereof, multiple layers thereof, or the like.After the recesses 40 are filled with epitaxial regions 42, further epitaxial growth of the epitaxial regions 42 causes them to expand horizontally, and facets can be formed. Further growth of the epitaxial regions 42 can also cause adjacent epitaxial regions 42 to fuse together. Cavities (air gaps) 44 can be created. According to some embodiments of the present disclosure, the formation of epitaxial regions 42 can be completed when the upper surface of the epitaxial regions 42 is still wavy, or when the upper surface of the fused epitaxial regions 42 has become planar, which is achieved by further growth on the epitaxial regions 42, as described in [reference]. Fig. 6 is shown.

[0018] Following the epitaxy process, the epitaxy regions 42 can further be implanted with a p- or n-doping agent to form source and drain regions, which are also designated by reference numeral 42. According to an alternative embodiment of the present disclosure, the implantation process is omitted if the epitaxy regions 42 are doped with the p- or n-doping agent in situ during epitaxy.

[0019] Fig. Figure 7 illustrates a perspective view of the structure after formation of the contact etch stop layer (CESL) 46 and the interlayer dielectric (ILD) 48. The corresponding process is described in Fig. The process flow shown in Figure 29 is illustrated as process 212. The CESL 46 can be formed from silicon dioxide (SiO₂), silicon nitride (SiN), silicon carbide (SiCN), silicon carbide (SiC), silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), or the like, using CVD, ALD, or the like. The ILD 48 can have a dielectric formed using, for example, FCVD, spin deposition, CVD, or another deposition process. The ILD 48 can be formed from an oxygen-containing dielectric, which may be a silicon dioxide-based dielectric, such as silicon dioxide (e.g., formed using tetraethyl orthosilicate (TEOS) as the process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like.A planarization process, such as a chemical-mechanical polishing process (CMP process) or a mechanical grinding process, can be carried out to align the upper surfaces of the ILD 48, the dummy gate stack 30 and the gate spacer elements 38.

[0020] Next, in the Fig. 8A, Fig. 8B and Fig. 8C replaces the dummy gate stacks 30 (including the hard mask layers 36, the gate electrodes 34, and the dummy gate dielectrics) with replacement gate stacks 56. The corresponding process is described in the Fig. The process flow shown in 29 is illustrated as process 214. Fig. According to some embodiments, 8B illustrates a cross-sectional view along the reference line 8B-8B in Fig. 8A and Fig. Figure 8C illustrates a cross-sectional view along the reference line 8C-8C in Fig. 8A.

[0021] When forming exchange gate stacks 56, the hard mask layers 36 and the gate electrodes 34 (as in Fig. (7 shown) and the dummy gate dielectrics are removed in one or more etching processes, resulting in trenches / openings to be formed between the spacer elements 38. The upper surfaces and side walls of the projecting semiconductor fins 24' are exposed to the resulting trenches.

[0022] Next, as in the Fig. 8A, Fig. 8B and Fig. Figure 8C shows the exchange gate dielectrics 52, which extend into the grooves between the spacer elements 38. According to some embodiments of the present disclosure, each of the gate dielectrics 52 has as its lower section an interface layer (IL) which contacts the exposed surfaces of the corresponding projecting fins 24'. The IL may comprise an oxide layer such as a silicon oxide layer formed by the thermal oxidation of the projecting fins 24', a chemical oxidation process, or a deposition process. The gate dielectrics 52 may also comprise a high-k dielectric layer formed above the IL. The high-k dielectric layer may comprise a high-k dielectric such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, silicon nitride, or the like. The dielectric constant (k-value) of the high-k dielectric is greater than 3.9 and may be greater than approximately 7.0.The high-k dielectric layer is formed as a conformal layer and extends to the side walls of the projecting fins 24' and the side walls of the gate spacer elements 38. According to some embodiments of the present disclosure, the high-k dielectric layer is formed using ALD or CVD.

[0023] With reference to the Fig. 8A, Fig. 8B and Fig. In 8C, gate electrodes 54 are formed over the gate dielectrics 52. The gate electrodes 54 have stacked conductive layers. The stacked conductive layers are not shown separately, although they may be distinguishable from one another. The deposition of the stacked conductive layers can be performed using one or more conformal deposition methods such as ALD or CVD. The stacked conductive layers may include a diffusion barrier (sometimes called an adhesive layer) and one (or more) exit function layer(s) above the diffusion barrier. The diffusion barrier may be made of titanium nitride (TiN), which may (or may not) be doped with silicon. The exit function layer determines the gate's work function and has at least one layer or several layers made of different materials.The exit work layer material is selected based on whether the corresponding FinFET is an n-type or a p-type FinFET. For example, if the FinFET is an n-type FinFET, the exit work layer can consist of a TaN layer and a titanium aluminum (TiAl) layer over the TaN layer. If the FinFET is a p-type FinFET, the exit work layer can consist of a TaN layer and a TiN layer over the TaN layer. After deposition of the exit work layer(s), an adhesive layer is formed, which may be another TiN layer. The adhesive layer may or may not completely fill the trenches left by the removed dummy gate stacks.

[0024] The deposited gate dielectric and conductive layers are formed as conformal layers extending into the trenches and exhibiting some sections above the ILD 48. If the adhesive layer does not completely fill the trenches, a metallic material is deposited to fill the remaining trenches. This metallic material can be, for example, tungsten or cobalt. Subsequently, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove the sections of the gate dielectric layers, the stacked conductive layers, and the metallic material above the ILD 48. This results in the formation of the gate electrodes 54 and gate dielectrics 52. The gate electrodes 54 and gate dielectrics 52 are collectively referred to as the exchange gate stack 56.The upper surfaces of the exchange gate stack 56, the gate spacer elements 38, the CESL 46 and the ILD 48 can be essentially coplanar at this time.

[0025] The Fig. 8A, Fig. 8B and Fig. Figure 8C also illustrates the formation of (self-aligning) hard masks 58 according to some embodiments. The corresponding process is described in the Fig. The process flow 200 shown in Figure 29 is illustrated as process 216. The formation of hard masks 58 can include performing an etching process to recess the exchange gate stacks 56, creating recesses between the gate spacer elements 38, filling the recesses with a dielectric, and then performing a planarization process such as a CMP process or a mechanical grinding process to remove excess sections of the dielectric. The hard masks 58 can be formed from silicon nitride, silicon oxynitride, silicon oxycarbonnitride, or the like.

[0026] Fig. Figure 8C further illustrates a cross-sectional view through the epitaxial regions 42 and illustrates the CESL 46 and the ILD 48 arranged over the epitaxial regions 42 according to some embodiments.

[0027] The Fig. 9A, Fig. 9B and Fig. Figures 9C show a perspective view and cross-sectional views of the formation of contact openings 60 for the epitaxial regions 42. The corresponding process is described in the Fig. The process flow shown in 29 is illustrated as process 218. Fig. 9B illustrates the reference section 9B-9B in Fig. 9A. Fig. 9C illustrates the reference section 9C-9C in Fig. 9A. Forming contact openings 60 comprises etching the ILD 48 to expose the underlying sections of the CESL 46, and subsequently etching the exposed sections of the CESL 46 to expose the epitaxial regions 42. According to some embodiments of the present disclosure, as in Fig. Figure 9A illustrates the gate spacer elements 38 spaced by some sections of the ILD 48 and the CESL 46 from the nearest contact openings 60.

[0028] With reference to the Fig. 10A, Fig. 10B, Fig. 10C and Fig. 10D forms the silicide regions 66 and the source / drain contact plugs 70. Fig. Figure 10A illustrates a perspective view, Fig. 10B illustrates the reference section 10B-10B in Fig. 10A, Fig. 10C illustrates the reference section 10C-10C in Fig. 10A, and Fig. 10D illustrates the reference section 10D-10D in Fig. 10A. According to some embodiments, the metal layer 62 (such as a titanium, titanium nitride or cobalt layer, Fig. 10C) for example, using physical vapor deposition (PVD) or a similar process. The metal layer 62 is a conformal layer and extends over the upper surface of the epitaxial regions 42 and the sidewalls of the ILD 48. A cover layer 64, such as a metal nitride layer (like a titanium nitride layer), is deposited. Subsequently, an annealing process is carried out to, as described in the Fig. 10A, Fig. 10B, Fig. 10C and Fig. Figure 10D shows the formation of the source / drain silicide regions 66. The corresponding process is shown in the Fig. The process flow 200 shown in Figure 29 is illustrated as process 220. Next, a metallic region 68, formed from a metallic material that may contain Ru, Co, Ni, Cu, Al, Pt, Mo, W, Al, Ir, Os, or combinations thereof or the like, is filled into the remaining sections of the contact openings. Then, a planarization process, such as a CMP process or a mechanical grinding process, is performed to remove excess sections of the metal layer 62, the cover layer 64, and the metallic material of the metallic region 68, leaving the source / drain contact plugs 70. The corresponding process is also shown in Figure 29. Fig. The process flow shown in Figure 29 is illustrated as process 220. Therefore, FinFET 100 is formed.

[0029] The Fig. Figures 11A, 11B and 11C to 19A and 19B illustrate further intermediate steps in forming conductive structures via the Source / Drain contact connectors 70.

[0030] With reference to the Fig. 11A, Fig. 11B and Fig. 11C are formed in the Source / Drain contact connector 70 openings 71. Fig. Figure 11A illustrates a perspective view, Fig. 11B illustrates the reference section 11B-11B in Fig. 11A and Fig. 11C illustrates the reference section 11C-11C in Fig. 11A. The corresponding process is described in the Fig. The process flow 200 shown in Figure 29 is illustrated as process 222. The openings 71 can be formed by any suitable process, such as an acceptable photolithography process, wherein a one-, two-, or three-layer photomask is formed and developed and / or structured over the source / drain contact plugs 70 to create an opening, which is then transferred to the source / drain contact plugs 70 by an etching process to form the openings 71. The etching process can be a dry or wet etching process, and the openings 71 can result in various shapes, which are described below with reference to the Fig. Sections 21A to 21J will be described in more detail. As in Fig. As shown in Figure 11B, the etching to form the opening 71 can include removing a section of the metallic region 68 as well as a section of the cover layer 64. In other embodiments, the width of the metallic region 68 removed to form the opening 71 can be smaller than the width of the metallic region 68, so that a section of the metallic region 68 remains on one or both sides of the opening 71.

[0031] Although the openings 71 are shown to be formed in the middle of the metallic region 68 of the source / drain contact 70, it is understood that the openings 71 can also be formed towards one end or the other of the metallic region 68.

[0032] With reference to the Fig. 12A, Fig. 12B and Fig. 12C a dielectric 72 is deposited over and in the openings 71 of the source / drain contact plugs 70. Fig. Figure 12A illustrates a perspective view, Fig. 12B illustrates the reference section 12B-12B in Fig. 12A and Fig. Figure 12C illustrates the reference section 12C-12C in Fig. 12A. The corresponding process is also described in the Fig. The process flow shown in Figure 29 is illustrated as process 222. The dielectric 72 can be formed from any suitable material using any suitable process. In some embodiments, the dielectric 72 can be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or combinations thereof. The dielectric 72 can be deposited in the openings 71 and over the structure by ALD, HDPCVD, CVD, FCVD, spin coating, and the like.

[0033] With reference to the Fig. 13A, Fig. 13B and Fig. 13C sections of the dielectric 72 above the source / drain contact plugs 70 are removed using a planarization process, forming the intermediate block 73. Fig. Figure 13A illustrates a perspective view, Fig. 13B illustrates the reference section 13B-13B in Fig. 13A and Fig. 13C illustrates the reference section 13C-13C in Fig. 13A. The corresponding process is also described in the Fig. Process flow 200 shown in 29 is illustrated as process 222. The planarization process can include a CMP process, a grinding process, an etching process, or combinations thereof.

[0034] With reference to the Fig. 14A, Fig. 14B, Fig. 14C and Fig. 14D the etch stop layer (ESL) 74 and the interlayer dielectric (ILD) 76 are deposited. Fig. Figure 14A illustrates a perspective view, Fig. 14B illustrates the reference section 14B-14B in Fig. 14A, Fig. Figure 14C illustrates the reference section 14C-14C in Fig. 14A, and Fig. 14D illustrates the reference section 14D-14D in Fig. 14A. The corresponding process is designated as process 224 in the Fig. The process flow shown in Figure 29 illustrates the process flow shown in Figure 200. The ESL 74 can be formed from a dielectric such as SiN, SiCN, SiC, AlO, AlN, SiOCN, SiOC, or the like, or from composite layers thereof. The formation process can include PECVD, ALD, CVD, FCVD, HDPCVD, or the like.

[0035] The ILD 76 is deposited over the ESL 74. The material and formation process of the ILD 76 can be selected from the same candidate materials and formation processes used for the formation of the ILD 48. For example, the ILD 76 can contain silicon oxide, PSG, BSG, BPSG, or the like, which contains silicon. In some embodiments, the ILD 76 is formed by PECVD, FCVD, HDPCVD, spin coating, or the like. According to alternative embodiments, the ILD 76 can be formed from a low-k dielectric.

[0036] With reference to the Fig. 15A, Fig. 15B and Fig. At 15C the first contact openings 78 for the first conductive structures 84 are formed. Fig. Figure 15A illustrates a perspective view, Fig. Figure 15B illustrates the reference section 15B-15B in Fig. 15A and Fig. 15C illustrates the reference section 15C-15C in Fig. 15A. The corresponding process is designated as process 226 in the Fig. The process flow shown in Figure 29 illustrates the process flow. An etch mask (not shown), which may be a triple layer, is formed over the ILD 76. The etch mask is textured to create openings that are then used to define the structure of the first contact openings 78 in the ILD 76. If the etch mask is a triple-layer mask, the top layer may be a photoresist textured using acceptable photolithography techniques. The top layer is then used to texture the middle layer by an etching process, and the middle layer is used to texture the bottom layer by another etching process. The bottom layer then becomes the etch mask for forming the first contact openings 78. The etch mask is used to protect areas of the ILD 76 that are not to be etched. The ILD 76 is then etched to form the first contact openings 78.According to some embodiments, the etching process includes a main etching process in which a suitable etchant is used which is selective for the ILD 76 and uses the ESL 74 as an etching stop.

[0037] Next, the ESL 74 is etched to expose the source / drain contact connector 70. The corresponding process is also described as process 226 in the Fig. The process flow shown in Figure 29 illustrates the process flow in Figure 200. Etching of the ESL 74 can be carried out using suitable etching gases, such as CHF3, C x H y F z (x=0~6, y=0~12, z=0~12), while carrier gases, such as N2 and / or He, Ar, can be added.

[0038] As in Fig. As illustrated in Figure 15B, the first contact opening 78 is arranged above and beside the intermediate block 73. Although the first contact opening 78 is illustrated as being located on the left side of the intermediate block 73, it can also be located on the right side. Furthermore, some of the first contact openings 78 can be located on the left side of the intermediate block 73 and some on the right side. In one embodiment, for example, the first contact openings 78 for each source / drain contact connector 70 can alternate between being located on the left side and the right side of the intermediate block 73.

[0039] With reference to the Fig. 16A, Fig. 16B and Fig. In 16C, an etching process 79 is performed on the first contact openings 78 to enlarge the first contact openings 78 into the metallic regions 68 of the source / drain contact plugs 70 and to form the first enlarged openings 80. The first enlarged openings 80 can also be referred to as depressions, recesses, or an inverted mushroom cap. The corresponding process is described as process 228 in the Fig. The process flow shown in Figure 29 is illustrated in Figure 200. The etching process in Figure 79 involves the use of an etchant. After etching, a subsequent cleaning process can be carried out using a cleaning agent.

[0040] The first enlarged openings 80 offer several advantages. When a subsequent metallic material is deposited in the first enlarged openings 80 and up through the first contact openings 78, the surface area available for the interface between the first enlarged openings 80 and the metallic material is larger, resulting in a bottom-up deposition process with better adhesion to the material of the source / drain contact plugs 70 and a lower resistivity. Since the first enlarged openings 80 extend laterally further than the underside of the first contact openings 78, the entire opening is shaped like an inverted mushroom, providing a lower lip that can help counteract any upward force.After the metallic material has been deposited in the first enlarged openings 80 and up through the first contact openings 78, the horizontal surface of the deposited contact also helps to block any etching agents that might seep or run between the side of the deposited contact and the lower surface of the ILD 76.

[0041] The etching process 79, used to form the first enlarged openings 80, can employ any suitable etchant that is selective for the material of the metallic regions 68 of the source / drain contact plugs 70. The etching process 79 can be a wet etching or wet cleaning process, with the etchant being applied over the entire surface of the ILD 76, filling the first contact openings 78 and reacting with the metallic material of the metallic regions 68. If the metallic regions 68 of the source / drain contact plugs 70 contain cobalt, the material composition can be, for example, CoF3 (the presence of fluorine resulting from the plasma dissociation of process gases containing one or more of CF4, C4F6, C). x H y F z(x=1~6, y=0~12, z=1-12) or C4F8 are present during the deposition process of the metallic material of the metallic regions 68 of the source / drain contact connectors 70). Aqueous solutions, pure water, deionized water, or organic etchants can be used as etching / cleaning agents. Other materials of the source / drain contact connectors 70 can be etched similarly with suitable wet etching agents.

[0042] Etching the source / drain contact plugs 70 forms the enlarged openings 80 in the metallic regions 68 of the source / drain contact plugs 70. The first enlarged openings 80 may have a shell shape. In some embodiments, the first enlarged openings may extend to and expose part of the intermediate block 73, as described below with reference to the Fig. 20A, Fig. 20B, Fig. 20C and Fig. 20D is described in more detail. Following the etching process 79, a cleaning process can be used to remove any etching byproducts. Any suitable cleaning agent, such as aqueous solutions, pure water, deionized water, or combinations thereof, can be used for the cleaning process.

[0043] In the Fig. 17A, Fig. 17B and Fig. In step 17C, a metallic material is filled into the first enlarged openings 80 and into the first contact openings 78 and can be further deposited so that it extends above and laterally over the top of the ILD 76. The corresponding process is described in the Fig. The process flow shown in Figure 29 is illustrated as process 230. According to some embodiments, the metallic material comprises a metal such as Ru, Co, Ni, Cu, Al, Pt, Mo, W, Al, Ir, Os, or combinations thereof. The metallic material is deposited in a bottom-up deposition process, which can be carried out using a thermal chemical vapor deposition (CVD) process. The temperature of the wafer 10 can be in the range between 50 °C and approximately 400 °C. The bottom-up deposition process can be carried out using WF6 and H2 as process gases (if tungsten is to be deposited), or other process gases can be used if other materials are employed. In the bottom-up deposition, the first enlarged openings 80 and the first contact openings 78 can be filled without creating an air gap.The deposition process may also include CVD, ALD, PVD, ECP, ELD or the like.

[0044] The deposition of the metallic material can be carried out in a temperature range between approximately 50 °C and approximately 500 °C, wherein the carrier gas, according to some embodiments, contains argon or nitrogen at a flow rate of approximately 10 sccm to approximately 500 sccm. Reaction gases, such as the metal-containing precursor, H₂, O₂, NH₃, or the like, can be added at flow rates of approximately 10 sccm to approximately 500 sccm and at a pressure in the range of approximately 0.00001 Torr to approximately 10 Torr, according to some embodiments.

[0045] In some embodiments, the metallic material is formed from a homogeneous material and lacks a barrier layer. According to alternative embodiments, the metallic material is formed from a homogeneous material, and a conformal barrier layer (not shown) is formed before the metallic material is deposited. The conformal barrier layer can be made of titanium, titanium nitride, tantalum, tantalum nitride, or the like.

[0046] With further reference to the Fig. 17A, Fig. 17B and Fig. 17C uses a planarization process to remove excess sections of the metallic material (which may extend laterally across the top of the ILD 76), and thus the first conductive structures 84 are formed. The corresponding process is also described in Fig. The process flow 200 shown in Figure 29 is illustrated as process 230. The first conductive structures 84 have the lower (extended) sections 84l, which extend into the metallic regions 68 of the source / drain contact connectors 70, and the upper sections 84u, which are arranged in the ILD 76 and laterally surrounded by the ILD 76. The lower sections 84l can be considered contact extensions or contact extension regions of the first conductive structures 84. The lower sections 84l of the first conductive structures 84 extend laterally beyond the corresponding upper sections 84u above them. In the illustrated embodiment of the Fig. 17A, Fig. 17B and Fig. In 17C, the upper sections 84u are aligned with the lower sections 84l of the first conductive structures 84. In other words, the side-to-side centers of the upper sections 84u are aligned with the side-to-side centers of the lower sections 84l. In other embodiments, as described with reference to the Fig. 24A, Fig. 24B, Fig. 24C and Fig. As described in more detail in Figure 24D, the upper sections 84u cannot be aligned with the lower sections 84l of the first conductive structures 84. In other words, the side-to-side centers of the upper section 84u are not aligned with (or offset from) the side-to-side centers of the lower section 84l.

[0047] Due to the lower sections 84l, the resulting first conductive structures 84 have the advantage of providing greater stability under an upward force. The lower sections 84l are wider than the underside of the upper sections 84u, thus providing a lip of the first conductive structures 84 that resists an upward force. Another advantage of the lower sections 84l of the first conductive structures 84 results from the exposed surface area of ​​the metallic regions 68. The larger surface area ensures better adhesion of the first conductive structures 84 to the metallic region 68. The larger surface area also reduces the conductive resistance between the metallic region 68 and the first conductive structures 84.

[0048] In the Fig. 18A and Fig. 18B the second contact openings 86 and the second enlarged openings 88 on the other side of the intermediate block 73 are formed by the first conductive structures 84. Fig. Figure 18A illustrates a perspective view and Fig. Figure 18B illustrates a view of the reference section 18B-18B in Fig. 18A. The corresponding process is described in the Fig. The process flow 200 shown in Figure 29 is illustrated as process 234. The second contact openings 86 can be formed using similar processes and materials to those described above in relation to the first contact openings 78. The second enlarged openings 88 can be formed using processes and materials similar to those described above in relation to the first enlarged openings 80. As described in more detail below, the second enlarged openings 88 can then be filled with second conductive structures 94 formed from a different material than the first conductive structures 84. As in Fig. As illustrated in Figure 18B, the second enlarged opening 88 can extend laterally to expose a section of the intermediate block 73. The size of the second enlarged opening 88 can be increased by increasing the etching dwell time and / or by performing multiple etching processes when forming the second enlarged opening 88.

[0049] When the etching process, such as etching process 79, is used to form the second enlarged openings 88, the intermediate block 73 prevents contact between the etchant and the first conductive structures 84, as well as between cleaning agents (if used) and the first conductive structures 84. As mentioned earlier, the first conductive structures 84 may be made of a different material than the metallic region 68, creating a situation where galvanic effects can be problematic. If the wet etchant or cleaning agent were to come into contact with the interface between the first conductive structures 84 and the metallic region 68, a galvanic reaction could occur, causing an increase in resistivity.A galvanic reaction occurs due to an exchange of electrons caused by differences in electrode potential between two dissimilar materials coupled by an electrolyte. For example, if one of the materials in metallic region 68 and the first conductive structures 84 is cobalt and the other is tungsten, then, since the difference in electrode potential between cobalt and tungsten is considerable, galvanic corrosion would occur if an electrolyte (such as a wet etching agent or a cleaning agent) is introduced into the interface. Tungsten is more reactive than cobalt.When the interface between the first conductive structure 84 and the metallic region 68 is exposed to the etching solution and / or cleaning agent, a galvanic reaction can occur between the tungsten and the cobalt, with the tungsten losing electrons to the cobalt, causing oxidation of the tungsten and galvanic corrosion at the interface. The same problem can occur with any two dissimilar metals. For example, both tungsten and cobalt have a higher electrode potential than titanium nitride.

[0050] In the Fig. 19A and Fig. 19B, the second conductive structures 94 are formed in the second contact openings 86 and in the second enlarged openings 88. Fig. Figure 19A illustrates a perspective view and Fig. Figure 19B illustrates a view of the reference section 19B-19B in Fig. 19A. The corresponding process is described in the Fig. The process flow 200 shown in Figure 29 is illustrated as process 236. The second conductive structures 94 can be formed using processes and materials similar to those used above to form the first conductive structures 84. In some embodiments, the second conductive structures 94 can be formed from a different material than the first conductive structures 84. In such embodiments, contact between the first conductive structure 84 and the second conductive structure 94 is prevented because the intermediate block 73 is located in the metallic region 68. This reduces or prevents the occurrence of a galvanic corrosion reaction between the two different metals.

[0051] The Fig. 20A, Fig. 20B, Fig. 20C and Fig. 20D illustrates close-up views of the dashed box in Fig. 19B according to various embodiments. In Fig. In 20A, the first conductive structure 84 has a lower section 84l that extends laterally towards the intermediate block 73 but does not contact it. The second conductive structure 94 has a lower section 94l that extends laterally towards the intermediate block 73 and contacts it. Since the lower section 94l contacts the intermediate block at 94s, the lower section 94l of the second conductive structure 94 is asymmetric about a center line L2. Because the second enlarged openings 88 are formed, the etchant, when it reaches the intermediate block 73, is prevented from penetrating further, thus concentrating the etchant at the intermediate block 73. However, the etchant can spread laterally further away from the intermediate block 73 than it can on the side closer to the intermediate block 73.In other words, the distance d1 can be smaller than the distance d2 for the corresponding lower section 94l. In contrast, the etching agent spreads relatively uniformly at the first enlarged opening 80, causing the lower section 84l to be symmetrical about the center line L1.

[0052] In Fig. In 20B, the first conductive structure 84 has a lower section 84l that extends laterally towards the intermediate block 73 and contacts the intermediate block 73. The second conductive structure 94 has a lower section 94l that extends laterally towards the intermediate block 73 but does not touch the intermediate block 73. Fig. In 20C, both the first conductive structure 84 and the second conductive structure 94 have lower sections 84l and 94l that extend towards and contact the intermediate block 73. Fig. 20D both the first conductive structure 84 and the second conductive structure 94 have the lower sections 84l and 94l, which extend towards the intermediate block 73, but do not contact the intermediate block 73.

[0053] In the Fig. Figures 21A to 21J illustrate views of different configurations of the intermediate block 73 according to various embodiments. For each of the views of the different configurations of the intermediate block 73, the different shapes of the intermediate block 73 are formed by controlling the etching processes used to produce the corresponding intermediate block opening 71, as described above with respect to the Fig. 11A, Fig. 11B and Fig. 11C is described. In the Fig. In blocks 21A to 21J, the intermediate block has 73 side walls with an angle between 70° and 110° with respect to a horizontal line. Fig. 21A, Fig. 21B and Fig. The side walls are approximately 90° at 21J. In the Fig. 21C, Fig. 21E, Fig. 21G and Fig. 21I The side walls have an angle between approximately 70° and 90°. In the Fig. 21D, Fig. 21F and Fig. 21H, the side walls have an angle between approximately 90° and 110°. The corresponding etching process for forming the opening or slot for the intermediate block 73 of the Fig. 21A to 21J can plasma etching gas C x H y F z (x / y / z=0~12), C x H y Cl z (x / y / z=0~12), C x H y Br z(x / y / z=0~12) to form the opening or slot for the intermediate block 73. By adjusting the ratios and process conditions of the etching, the various sidewall angles can be achieved. Depending on the ratios and process conditions of the etching, the intermediate block 73 can have a flat, convex, concave, or pointed bottom surface. After forming the opening or slot for the intermediate block 73, the opening or slot can be filled with an insulating material, such as HfO, Si3N4, SiOH, SiC, SiOC, or carbon materials, by CVD, PVD, SCVD, or PECVD. The top surfaces of the intermediate block 73 can then be planarized using a planarization process such as CMP to form the intermediate block 73.

[0054] The Fig. 22A, Fig. 22B and Fig. 22C up to the Fig. 26A and Fig. Figure 26B illustrates the fabrication of gate contacts according to some embodiments. The corresponding process is described in the Fig. The process flow shown in 29 is illustrated as process 200. As in Fig. As shown in Figure 29, the formation of the gate contacts can be carried out after the formation of the first conductive structures 84 and before the formation of the second conductive structures 94. In some embodiments, however, both the first conductive structures 84 and the second conductive structures 94 can be formed before the formation of the gate structures. In some embodiments, the formation of the gate contacts can also include the formation of an intermediate block, a first gate contact on one side of the intermediate block, and a second gate contact on the other side of the intermediate block. In other embodiments, no intermediate block is used. In some embodiments where a gate intermediate block is used, the intermediate block can be formed at the same time and using the same processes as those used to form the intermediate block 73.The process described below involves forming the gate intermediate block after the ILD 76 has been formed, although the previously described process for forming intermediate block 73 can be substituted.

[0055] In the Fig. 22A, Fig. 22B and Fig. At 22C, the openings 102 are formed in the gate electrode 54. Fig. Figure 22A illustrates a perspective view, Fig. Figure 22B illustrates the reference section 22B-22B in Fig. 22A, and Fig. 22C illustrates the reference section 22C-22C in Fig. 22A. The corresponding process is described in the Fig. The process flow shown in section 30 is illustrated as process 252. The view in Fig. 22B includes two options for forming openings to insert an opening for an intermediate block into the gate region. Openings 102 are formed by the ILD 76, the ESL 74, the hard mask 58, and partially into the gate electrode 54. Openings 102' are formed by the ILD 76, the ESL 74, and the hard mask 58, but do not extend into the gate electrode 54. Openings 102 or openings 102' can be formed using similar processes to those described above for forming openings 71. In particular, openings 102 or openings 102' can be formed by any suitable process, such as…by an acceptable photolithography process, wherein a one-, two-, or three-layer photomask can be formed and developed and / or structured over the ILD 76 to create an opening, which is then transferred to the gate electrode 54 by an etching process to form the openings 102 or the openings 102'. The etching process can be a dry etching process or a wet etching process, and the openings 102 or openings 102' can result in various shapes, which are described above in relation to the . Fig. 21A to 21J are described in more detail. In some embodiments, a section of the gate electrode 54 can remain on both sides of the openings 102 (between the openings 102 and the gate dielectrics 52), as shown in Fig. Figure 22B illustrates this, while in other embodiments the openings 102 may extend laterally further than the gate electrode 54 and into the gate dielectrics 52 and / or into the spacer elements 38. The lateral extension of the openings 102 may, for example, terminate in the spacer elements 38. In other embodiments, no intermediate block may be used in the gate region, so the openings 102 or the openings 102' may be omitted.

[0056] In the Fig. 23A, Fig. 23B and Fig. At 23C, the intermediate blocks 106 are formed in the gate electrode 54. Fig. Figure 23A illustrates a perspective view, Fig. Figure 23B illustrates the reference section 23B-23B in Fig. 23A, and Fig. 23C illustrates the reference section 23C-23C in Fig. 23A. The corresponding process is also described in the Fig. The process flow shown in Figure 30 is illustrated as process 252. The dashed outline of process 252 indicates that it is an optional process. The view in Fig. 23B includes two options for forming the intermediate blocks 106' or the intermediate blocks 106', depending on whether the opening 102 or the openings 102' were used (see Fig. 22B). The intermediate blocks 106 or the intermediate blocks 106' can be formed by depositing a dielectric in the openings 102 or the openings 102' using similar processes and materials as those used to form the dielectric 72. After depositing the dielectric, a leveling process can be used to level the upper surfaces of the dielectric with the upper surfaces of the ILD 76, thereby forming the intermediate blocks 106 or the intermediate blocks 106'. The intermediate blocks 106 or the intermediate blocks 106' can be formed using similar processes and materials as those used to form the intermediate blocks 73 from the dielectric 72. When the intermediate blocks 106 or the intermediate blocks 106' are formed in the same process as the intermediate blocks 73, the upper surface of the intermediate block 73 is level with the upper surface of the ILD 48. Fig. Figure 23C illustrates that the intermediate block 106 is arranged over the projecting fins 24' of the fin, but the intermediate block 106 can be arranged at any point along the length of the gate electrode 54 as long as space remains on both sides of the intermediate block 106 for the first and second gate contacts to be formed.

[0057] In the Fig. 24A, Fig. 24B and Fig. 24C the first openings 108 and the first enlarged openings 110 are formed in the gate electrode 54. Fig. Figure 24A illustrates a perspective view, Fig. Figure 24B illustrates the reference section 24B-24B in Fig. 24A, and Fig. 24C illustrates the reference section 24C-24C in Fig. 24A. The reference section 23B-23B is the Fig. 24A is superimposed and illustrates that the cross-section 24B-24B is located next to the cross-section 23B-23B. The corresponding process is shown in the Fig. The process flow shown in Figure 30 is illustrated as process 254. The first openings 108 can be formed using similar processes and materials as those described above in relation to the formation of the openings 102. Process 79 can be used to form the first enlarged openings 110. Process 79 of the Fig. 24A, Fig. 24B and Fig. 24C is similar to the process 79 described above.

[0058] In the Fig. 25A, Fig. 25B and Fig. At 25C the first gate contacts 114 are formed in the first openings 108 and the first enlarged openings 110. Fig. Figure 25A illustrates a perspective view, Fig. Figure 25B illustrates the reference section 25B-25B in Fig. 25A, and Fig. 25C illustrates the reference section 25C-25C in Fig. 25A. The corresponding process is described in the Fig. The process flow shown in Figure 30 is illustrated as process 256. The first gate contacts 114 can be formed using similar processes and materials as described above with respect to the first conductive structures 84. In short, the lower section 114l of the first gate contacts 114 can be formed using a bottom-up deposition process, which is continued until the first openings 108 are filled to form the upper section 114u of the first gate contacts 114. Then, a planarization process can be used to align the upper surfaces of the first gate electrode.

[0059] In the Fig. 26A and Fig. The second gate contacts 124 are formed at 26B. Fig. Figure 26A illustrates a perspective view, Fig. Figure 26B illustrates the reference section 26B-26B in Fig. 26A and Fig. Figure 26C illustrates the reference section 26C-26C in alternative embodiments of Fig. 26A. The corresponding process is described in the Fig. The process flow shown in section 30 illustrates processes 232 as well as processes 258 and 260. As in Fig. As illustrated in Figure 26B, in process 258 the ILD 76, the ESL 74, and the hard mask 58 are etched to form an opening and expose the gate electrode 54. The opening is then enlarged into the gate electrode 54 by an etching process such as etching process 79 to form an enlarged opening. The opening and the enlarged opening can be formed using materials and processes similar to those described above in relation to forming the initial contact opening 78 and the enlarged opening 80 of the Fig. 15A to 16C were described.

[0060] In Fig. At 26C, the conductive structures 114' and 124' are formed next to the intermediate block 106'. As above with regard to the Fig. 22B and Fig. As described in Section 22C, the intermediate block 106' does not extend into the gate electrode 54. Similarly, the first conductive structures 114' and the second conductive structures 124' also do not extend into the gate electrode 54. In such embodiments, the first conductive structures 114' and the second conductive structures 124' can be formed using the same processes described above with respect to the first conductive structures 114 and the second conductive structures 124, except that the enlarged openings are omitted.

[0061] Similar to what is described above with regard to the first conductive structure 84, when forming the enlarged opening for the second gate contacts 124, a galvanic reaction between the first gate contacts 114 and the gate electrode 54 is avoided because of the intermediate block 106.

[0062] Next, in process 260, the second gate contacts 124 are formed by depositing a metallic material in the enlarged opening via a bottom-up deposition process to form the lower section 124l, and continuing the deposition to form the upper section 124u. Subsequently, a planarization process can be used to remove excess sections of the metallic material above the ILD 76 and to align the upper surface of the second gate contact 124 with the upper surface of the ILD 76. The metallic material can be deposited using processes and materials similar to those described above with respect to the first conductive structures 84 of the Fig. 17A to 17C were described.

[0063] The intermediate block 106 is positioned between the first gate contact 114 and the second gate contact 124 and prevents them from coming into contact with each other, thereby preventing or reducing galvanic corrosion. The shapes of the lower sections 114l and 124l can be determined according to one of the shapes shown in the Fig. 20A to 20D, as described above, are formed. As such, the lower section 114l and / or the lower section 124l can have an interface with the intermediate block 106.

[0064] The Fig. 27A and Fig. Figure 27B illustrates a conductor 126 bridging the metallic region 68 with the gate electrode 54. The conductor 126 has an upper section 126u, laterally surrounded by the ILD 76 and the ESL 74, and lower sections 126l1 and 126l2, which are extensions of the conductor 126 into the metallic region 68 and the gate electrode 54, respectively. A via section 126v physically couples the upper section 126u to the lower section 126l2. The lower sections 126l1 and 126l2 can be formed using similar processes to those described above with respect to lower section 84l and lower section 114l of the Fig. 18B and Fig. 25B. The bridged section can be formed by removing the section of the ILD 76 and the ESL 74 between the first conductive structures 84 and the first gate contacts 114, while openings for the first conductive structures 84 and / or the first gate contacts 114 are formed, such as after forming the first enlarged openings 80 or the first enlarged openings 110 of the Fig. 16B and Fig. 24B. The ILD 76 can be masked for sections of the ILD 76 that are to be retained, and an etching process can be used to remove the ILD 76 and the ESL 74. When the metallic material 82 is deposited, it fills the bridged area of ​​the conductor 126 and couples the metallic region 68 of the source / drain contact plug 70 to the gate electrode 54. It is understood that the second conductive structure 94 can be bridged to the second gate contact 124 in a similar manner.

[0065] The Fig. Figures 28A to 28K illustrate, according to some embodiments, intermediate steps in a process for forming conductive structures on an underlying metallization. Fig. Figure 28A illustrates a substrate 211 and a dielectric layer 221 between which any number of layers and device features are arranged. The upper diagram is a top view, and the lower diagram is a cross-sectional view. The substrate 211 can be a substrate such as the substrate 20 described above. Furthermore, the substrate 211 can be a support substrate, such as a glass support, a ceramic support, and so on. The dielectric layer 221 can be any suitable dielectric layer. In some embodiments, the dielectric layer 221 can be an interlayer dielectric (ILD), an intermetal dielectric (IMD), or the like, and it can be a layer in a redistribution or interconnect structure. The dielectric layer 221 can be formed from any suitable material and by any suitable process. The appropriate process is described in Figure 28A. Fig. The process flow 270 shown in Figure 31 is illustrated as process 272. The dielectric layer 221 can, for example, be formed from an oxygen-containing dielectric, which may be a silicon oxide-based dielectric, such as silicon oxide (e.g., formed using tetraethyl orthosilicate (TEOS) as the process gas), phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), or the like. In some embodiments, the dielectric layer 221 can be formed from other insulating materials, such as silicon nitride, silicon oxycarbide, silicon oxynitride, silicon oxycarbonitride, or combinations thereof. The dielectric layer 221 can be formed by any suitable process, such as PVD, CVD, HDPCVD, PECVD, FCVD, spin coating, or any other suitable deposition process.

[0066] The metallic element 225 is arranged within the dielectric layer 221. In some embodiments, the metallic element 225 can be part of a metallization layer of an interconnect or redistribution structure. The metallic element 225 can be coupled to one or more conductive elements located beneath the metallic element 225, such as conductive vias, metallization layers, silicides, semiconductor materials, or the like. An example of forming the metallic element 225 is creating an opening in the dielectric layer 221, for example, using a suitable photomask and a photolithography process to etch the opening in the dielectric layer 221. Next, a conductive material can be deposited in the opening, for example, by depositing a seed layer and then performing a plating process to deposit the conductive material.The conductive material of the metallic element can be any suitable material, such as copper, tin, tungsten, cobalt, aluminum, gold, titanium, titanium nitride, tantalum, tantalum nitride, and so on, alloys thereof, combinations thereof, and the like. Then, a planarization process such as a CMP process can be used to align the top surface of the metallic element 225 with the top surface of the dielectric layer 221. The corresponding process is also described in [reference missing]. Fig. The process flow shown in Figure 31 is illustrated as process 270. Other processes can also be used to form the metallic element 225 in the dielectric layer 221, including, for example, forming the metallic element 225 and then forming the dielectric layer 221 around the metallic element 225 followed by a planarization process.

[0067] In Fig. In 28B, an opening 227 is formed in the metallic element 225. The corresponding process is described in the Fig. The process flow 270 shown in Figure 31 is illustrated as process 274. The upper diagram is a top view and the lower diagram is a cross-sectional view. The opening 227 can be formed by any suitable process, such as an acceptable photolithography process, wherein a one-, two-, or three-layer photomask is formed and developed and / or structured over the metallic element 225 to create an opening, which is then transferred to the metallic element 225 by an etching process to form the opening 227. The etching process can be a dry etching process or a wet etching process, and the opening 227 can have several different shapes, which differ from the above with respect to the Fig. The forms described in 21A to 21L correspond to those described in the figures. In some embodiments, the opening 227 can extend over the entire metallic element 225 and into the dielectric layer 221, as shown in the diagram above. Fig. Figure 28B illustrates this. In other embodiments, the opening 227 can extend across the metallic element 225 from side to side, but not into the dielectric layer 221. In still other embodiments, the opening 227 can extend partially across the metallic element 225. In such an embodiment, the opening 227 can be located in the center of the metallic element 225, it can be offset towards the center of the metallic element 225, or it can extend along one side of the dielectric layer 221. Although the opening 227 is illustrated as being perpendicular to the direction of the metallic element 225, it is understood that it need not be perpendicular and could have an angle of ±45 degrees.Although the opening 227 is shown to be formed in the middle of the metallic element 225, it is understood that the opening 227 can also be formed towards one end or the other end of the metallic element 225.

[0068] In Fig. In 28C, a dielectric 231 is deposited in the opening 227 and over the metallic element 225 and the dielectric layer 221. The corresponding process is also described in the Fig. The process flow 270 shown in Figure 31 is illustrated as process 274. The upper diagram is a top view and the lower diagram is a cross-sectional view. The dielectric 231 can be formed from any suitable material using any suitable process. In some embodiments, the dielectric 231 can be silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like, or combinations thereof. The dielectric 231 can be deposited in the opening 227 and over the metallic element 225 and the dielectric layer 221 by ALD, HDPCVD, CVD, FCVD, spin coating, or the like. In some embodiments, the dielectric 231 can have the same material composition as the dielectric layer 221. The upper diagram illustrates the opening 227 and the metallic element 225 in phantom form, as they would not be visible.

[0069] In Fig. In 28D, a leveling process is used to remove sections of the dielectric 231 above the metallic element 225 and the dielectric layer 221, thereby forming the intermediate block 235. The corresponding process is also described in Fig. The process flow shown in Figure 31 is illustrated as process 270, which is shown as process 274. The upper diagram is a top view and the lower diagram is a cross-sectional view. The leveling process can be a planarization process, such as a CMP process or a grinding process, an etching process, or a combination thereof. The resulting intermediate block 235 can be the one shown in the Fig. The forms of intermediate block 73 shown in figures 21A to 21J correspond to those shown.

[0070] In Fig. In 28E, a further dielectric layer 241 is formed over the dielectric layer 221 and over the metallic element 225. The corresponding process is described in the Fig. The process flow 270 shown in Figure 31 is illustrated as process 276. The upper diagram is a top view, and the lower diagram is a cross-sectional view. The upper diagram illustrates the intermediate block 235 and the metallic element 225 in phantom form, as they would not be visible. The dielectric layer 241 can be formed from the same or different materials as the dielectric layer 221. In some embodiments, an etch stop layer (for example, similar to ESL 74) can be formed between the dielectric layer 221 and the dielectric layer 241. The dielectric layer 241 can be formed using processes and materials similar to those described above with respect to the dielectric layer 221.

[0071] In Fig. In step 28F, the contact opening 245 in the dielectric layer 241 above the metallic element 225 is formed on one side of the intermediate block 235. The corresponding process is described in the Fig. The process flow 270 shown in Figure 31 is illustrated as process 278. The upper diagram is a top view, and the lower diagram is a cross-sectional view. The upper diagram illustrates the intermediate block 235 and the edges of the metallic element 225 in phantom form, as they would not be visible. The contact opening 245 can be used to form a first conductive structure to connect the metallic element 225 to another metallic element, such as an overlying metallic element (not shown), which can then be electrically coupled to a device within the substrate 211 or to another device (not shown). The contact opening 245 can be formed near the intermediate block 235. It is understood that the contact opening 245 is only one example of the contact openings that can be formed in the dielectric layer 241.

[0072] The contact opening 245 can be formed by any suitable process such as an acceptable photolithography process for forming a lacquer mask over the dielectric layer 241, structuring the lacquer mask by a light mask, developing the lacquer mask to form a structure in the lacquer mask, and etching the dielectric layer 241 through the lacquer mask.

[0073] In Fig. In 28G, an etching process 251 is carried out at the contact opening 245 to enlarge the contact opening 245 into the metallic element 225 and to form the enlarged opening 255 in the contact opening 245. The corresponding process is described in the Fig. The process flow 270 shown in Figure 31 is illustrated as process 280. The upper diagram is a top view, and the lower diagram is a cross-sectional view. The upper diagram illustrates the intermediate block 235, the edges of the metallic element 225, and the enlarged openings 255 in phantom form, as they would not be visible from above. The enlarged openings 255 can also be described as depressions, recesses, or an inverted mushroom cap. The etching process 251 can be carried out using similar processes and materials as those described above in relation to the etching process 79. Fig. 16A, Fig. 16B and Fig. were described in 16C.

[0074] The enlarged openings 255, extending from the contact openings 245, have several advantages. The enlarged openings 255 are analogous to the enlarged openings 80 of the Fig. 16A, Fig. 16B and Fig. 16C. The large volume and deep pocket formed by the enlarged openings 255 result in a better contact area with the subsequently formed conductive layer, help to resist an upward force, and provide better protection against the leakage of a reactive element of a planarization process.

[0075] In Fig. In step 28H, a conductive layer 261 is deposited in the enlarged opening 255, in the contact opening 245, and above the dielectric layer 241. The corresponding process is described in the Fig. The process flow 270 shown in Figure 31 is illustrated as process 282. The upper diagram is a top view and the lower diagram is a cross-sectional view. The upper diagram illustrates the intermediate block 235, the edges of the metallic element 225, the underside of the opening 245, and the extent of the enlarged openings 255 in phantom form, as they would not be visible from above. The conductive layer 261 can be produced using similar processes and materials to the metallic material described above in relation to the Fig. 17A, Fig. 17B and Fig. 17C was described, to be formed.

[0076] In Fig. 28I A planarization process similar to a CMP process is performed on the conductive layer 261 to align the upper surface of the conductive layer 261 with the upper surface of the dielectric layer 241, thereby forming the first conductive structure 265. The corresponding process is described in the Fig. The process flow 270 shown in Figure 31 is illustrated as process 284. The upper diagram is a top view, and the lower diagram is a cross-sectional view. The upper diagram illustrates the intermediate block 235, the edges of the metallic element 225, and the extent of the enlarged openings 255 in phantom form, as they would not be visible from above. The resulting first conductive structure 265 has an upper section 265u and a lower section 265l. The lower section 265l can be considered a contact expansion, an inverted mushroom cap, or a contact expansion region of the first conductive structure 265.

[0077] As a result of the contact extensions (lower section 265l) of the first conductive structure 265, the enlarged contact area between the material of the first conductive structure 265 and the metallic feature 225 exhibits reduced electrical resistance and increased resistance to an upward force, such as that which may be caused by deflection. The inverted mushroom cap shape of the lower section 265l reduces or eliminates the detachment and separation of the first conductive structures 265 from the metallic element 225. Furthermore, the lower section 265l resists the ingress of chemicals that might seep between the upper section 265u and the side wall of the dielectric layer 241, which can occur, for example, during the planarization of the conductive layer 261.The penetration of chemicals can, for example, reach the upper section of the inverted mushroom cap of the lower section 265l and be prevented from coming into contact with the material of the metallic element 225.

[0078] In some embodiments, the upper sections 265u are aligned with the lower sections 265l of the first conductive structures 265. In other words, the side-to-side centers of the upper sections 265u can be aligned with the side-to-side centers of the lower sections 265l. In other embodiments, the etching time can be extended, and the enlarged opening 255 can expose a side wall of the intermediate block 235 when the enlarged opening 255 is formed in the metallic element 225. In such embodiments, the enlarged opening 255 can become skewed, and the resulting lower section will not be aligned with the side-to-side center of the upper section 265u. Such an embodiment can be described, for example, with reference to the lower section 84l of Fig. 20B will be observed.

[0079] In Fig. 28J, the contact opening 275 is formed on one side of the intermediate block 235, opposite the first conductive structure 265. The corresponding process is described in the Fig. The process sequence 270 shown in Figure 31 is illustrated as process 286. Subsequently, an enlarged contact opening 285 is formed, extending from the contact opening 275 into the metallic element 225. The corresponding process is described in Figure 31. Fig. The process flow 270 shown in Figure 31 is illustrated as process 288. The upper diagram is a top view, and the lower diagram is a cross-sectional view. The upper diagram illustrates the intermediate block 235, the edges of the metallic element 225, the extent of the enlarged opening 255, and the extent of the enlarged opening 285 in phantom form, as they would not be visible from above. The contact opening 275 and the enlarged opening 285 can be used to form a second conductive structure and to connect the metallic element 225 to another metallic element, such as an overlying metallic element (not shown), which can then be electrically coupled to a device within the substrate 211 or to another device (not shown). Similar processes and materials can be used for the contact opening 275 as for forming the contact opening 245.The enlarged opening 285 can be formed using an etching process, such as the etching process 251. The resulting enlarged openings 285 can also be referred to as depressions, recesses, or inverted mushroom caps.

[0080] Similar to what has been described above with regard to the first conductive structure 84, when forming the enlarged opening 285, a galvanic reaction between the first conductive structures 265 and the metallic element 225 is avoided due to the presence of the intermediate block 235 when the etching process is used to form the enlarged opening 285.

[0081] The enlarged openings 285, which extend from the contact openings 275, have several advantages. The enlarged openings 285 are analogous to the second enlarged openings 88 of the Fig. 18A and Fig. 18B. The large volume and deep pocket formed by the enlarged openings 285 result in a better contact area with the subsequently formed conductive layer, help to resist an upward force, and provide better protection against the leakage of a reactive element of a planarization process.

[0082] In Fig. In 28K, a conductive layer is deposited in the enlarged opening 285, in the contact opening 275, and above the top surface of the dielectric layer 241. The corresponding process is described in the Fig. The process flow shown in Figure 31 is illustrated as process 270. A planarization process, such as a CMP process, can then be used to remove excess sections of the conductive layer and to align the top surface of the conductive layer with the top surface of the dielectric layer 241, thereby forming the second conductive structure 295. The corresponding process is shown in Figure 31. Fig. The process flow 270 shown in Figure 31 is illustrated as process 292. The upper diagram is a top view, and the lower diagram is a cross-sectional view. The upper diagram illustrates the intermediate block 235, the edges of the metallic element 225, and the extension of the lower sections 265l and 295 in phantom form, as they would not be visible from above. The resulting second conductive structure 295 has an upper section 295u and a lower section 295l. The lower section 295l can be viewed as a contact extension, an inverted mushroom cap, or a contact extension region of the second conductive structure 295.

[0083] The conductive layer can be produced using similar processes and materials to the metallic material described above in relation to the Fig. 17A, Fig. 17B and Fig. 17C was described. In some embodiments, the material of the first conductive structure 265 can be different from the material of the second conductive structure 295; however, since the intermediate block 235 prevents the first conductive structure 265 from coming into contact with the second conductive structure 295, the probability of galvanic corrosion is reduced or eliminated.

[0084] As a result of the contact extensions (lower section 295l) of the second conductive structure 295, the enlarged contact area between the material of the second conductive structure 295 and the metallic element 225 exhibits reduced electrical resistance and increased resistance to an upward force, such as that which may be caused by deflection. The inverted mushroom cap shape of the lower section 295l reduces or eliminates the detachment and separation of the second conductive structures 295 from the metallic element 225. Furthermore, the lower section 295l resists the ingress of chemicals that might seep between the upper section 295u and the side wall of the dielectric layer 241, which can occur, for example, during the planarization of the dielectric layer in the formation of the second conductive structure 295.The penetration of chemicals can, for example, reach the upper section of the inverted mushroom cap of the lower section 295l and be prevented from coming into contact with the material of the metallic element 225.

[0085] In some embodiments, the upper sections 295u are aligned with the lower sections 295l of the second conductive structures 295. In other words, the side-to-side centers of the upper sections 295u can be aligned with the side-to-side centers of the lower sections 295l. In other embodiments, the etching time can be extended, and the enlarged opening 285 can expose a side wall of the intermediate block 235 when the enlarged opening 285 is formed in the metallic element 225. In such embodiments, the enlarged opening 285 can become skewed, and the resulting lower section 295l will not be aligned with the side-to-side center of the upper section 295u. Such an embodiment can be described, for example, with reference to the lower section 94l of Fig. 20A will be observed.

[0086] It is understood that the shapes of the lower sections 265l and 295l correspond to the shapes of the lower sections 84l and 94l in the Fig. 20A, Fig. 20B, Fig. 20C and Fig. 20D may correspond. In particular, in some embodiments, one or both of the lower sections 265l or 295l may contact the intermediate block 235.

[0087] The embodiments of the present disclosure have several advantageous features. By using an interblock dielectric between two conductive structures, a galvanic reaction between two dissimilar metals can be avoided by preventing etching or cleaning solution from coming into contact with an interface between the two dissimilar metals. In this way, two different metals can be used to form connections that can offer different electrical properties.

[0088] One embodiment is a method comprising forming a metallic region within a first insulating layer. The method further comprises forming a cavity within the metallic region. The method further comprises filling the cavity with an interblock dielectric. The method further comprises depositing a second insulating layer over the metallic region and the first insulating layer. The method further comprises forming a first conductive structure extending through the second insulating layer and into the metallic region.The method further comprises forming a second conductive structure extending through the second insulating layer and into the metallic region, wherein the first conductive structure is located on a first side of the interblock dielectric and the second conductive structure is located on a second side of the interblock dielectric, the second side being opposite to the first side. In one embodiment, forming the first conductive structure comprises: performing a first etching process to etch the second insulating layer in order to form a first opening in the second insulating layer, the first opening exposing a portion of the metallic region; and performing a second etching process through the first opening to etch a first depression into an upper surface of the metallic region, the first depression having a larger lateral extent than a bottom surface of the first opening.In one embodiment, performing the second etching process exposes a sidewall of the interblock dielectric. In another embodiment, either the first conductive structure or the second conductive structure contacts the interblock dielectric. In another embodiment, the first conductive structure has a different material composition than the metallic region, wherein forming the second conductive structure comprises: forming a third opening in the second insulating layer; and performing a third etching process through the third opening to etch a second depression into an upper surface of the metallic region, the interblock preventing etchant from the third etching process from coming into contact with an interface between the first conductive structure and the metallic region. In another embodiment, the interblock has tapered sidewalls.In one embodiment, the recess extends over the entire width of the metallic region. In another embodiment, an upper section of the first conductive structure is laterally offset from the side-to-side center of a lower section of the first conductive structure. In another embodiment, the metallic region contains cobalt, and the first conductive structure contains tungsten.

[0089] Another embodiment is a structure comprising a first insulating layer. The structure further comprises a first metallic conductor arranged within the first insulating layer, wherein the first metallic conductor is laterally surrounded by the first insulating layer and has an upper surface that is level with an upper surface of the first insulating layer. The structure further comprises an intermediate dielectric arranged within the first metallic conductor, wherein the intermediate dielectric has an upper surface that is level with the upper surface of the first metallic conductor and a lower surface that is situated between a lower surface of the first metallic conductor and the upper surface of the first metallic conductor. The structure further comprises a second insulating layer arranged above the first insulating layer.The structure also includes a first metallic contact located in the second insulating layer and extending below the second insulating layer into the first metallic conductor. The structure also includes a second metallic contact located in the second insulating layer and extending below the second insulating layer into the first metallic conductor, with the first metallic contact located on a first side of the interblock dielectric and the second metallic contact located on a second side of the interblock dielectric. In one embodiment, either the first metallic contact or the second metallic contact has an interface with the interblock dielectric. In one embodiment, the interblock dielectric has tapered sidewalls. In another embodiment, the interblock dielectric has a non-flat bottom surface.In one embodiment, the first metallic contact has a different material than the second metallic contact. In another embodiment, an upper section of the first metallic contact is surrounded by the second insulating layer, a lower section of the first metallic contact is surrounded by the first metallic conductor, and the upper section has a side-to-side center offset from a side-to-side center of the lower section. In another embodiment, a method comprises forming a metallic region in a first insulating layer. The method further comprises forming a recess in the metallic region. The method further comprises filling the recess with an interblock dielectric. The method further comprises depositing a second insulating layer over the metallic region and the first insulating layer.The method further comprises forming a first conductive structure extending through the second insulating layer and into the metallic region. The method further comprises forming a second conductive structure extending through the second insulating layer and into the metallic region, wherein the first conductive structure is located on a first side of the interblock dielectric and the second conductive structure is located on a second side of the interblock dielectric, the second side being opposite the first side.In one embodiment, forming the first conductive structure comprises: performing a first etching process to etch the second insulating layer in order to form a first opening in the second insulating layer, the first opening exposing a portion of the metallic region; and performing a second etching process through the first opening to etch a first depression into an upper surface of the metallic region, the first depression having a larger lateral extent than a bottom surface of the first opening. In one embodiment, performing the second etching process exposes a side wall of the interblock dielectric. In one embodiment, the first conductive structure or the second conductive structure contacts the interblock dielectric.In one embodiment, the first conductive structure has a different material composition than the metallic region, wherein the formation of the second conductive structure comprises: forming a third opening in the second insulating layer; and performing a third etching process through the third opening to etch a second recess into an upper surface of the metallic region, wherein the intermediate block prevents etchant from the third etching process from coming into contact with an interface between the first conductive structure and the metallic region. In one embodiment, the intermediate block has tapered sidewalls. In one embodiment, the recess extends over the entire width of the metallic region. In one embodiment, an upper section of the first conductive structure is laterally offset from a side-to-side center of a lower section of the first conductive structure.In one embodiment, the metallic region contains cobalt, and the first conductive structure contains tungsten.

[0090] Another embodiment is a structure comprising a first insulating layer. The structure further comprises a first metallic conductor arranged within the first insulating layer, wherein the first metallic conductor is laterally surrounded by the first insulating layer and has an upper surface that is level with an upper surface of the first insulating layer. The structure further comprises an intermediate dielectric arranged within the first metallic conductor, wherein the intermediate dielectric has an upper surface that is level with the upper surface of the first metallic conductor and a lower surface that is situated between a lower surface of the first metallic conductor and the upper surface of the first metallic conductor. The structure further comprises a second insulating layer arranged above the first insulating layer.The structure also includes a first metallic contact located in the second insulating layer and extending below the second insulating layer into the first metallic conductor. The structure also includes a second metallic contact located in the second insulating layer and extending below the second insulating layer into the first metallic conductor, with the first metallic contact located on a first side of the interblock dielectric and the second metallic contact located on a second side of the interblock dielectric. In one embodiment, either the first metallic contact or the second metallic contact has an interface with the interblock dielectric. In one embodiment, the interblock dielectric has tapered sidewalls. In another embodiment, the interblock dielectric has a non-flat bottom surface.In one embodiment, the first metallic contact has a different material than the second metallic contact. In another embodiment, an upper section of the first metallic contact is surrounded by the second insulating layer, a lower section of the first metallic contact is surrounded by the first metallic conductor, and the upper section has a side-to-side center offset from a side-to-side center of the lower section. In another embodiment, the material composition of the first insulating layer is the same as the material composition of the interblock dielectric.

[0091] Another embodiment is a device comprising a source / drain region of a transistor. The device also includes a first interlayer dielectric over the source / drain region. Furthermore, the device has a source / drain contact plug over and electrically coupled to the source / drain region, the source / drain contact plug having a metallic region. The device also includes an interlayer dielectric arranged within the metallic region, the interlayer dielectric having an upper surface that is level with an upper surface of the metallic region and a lower surface arranged between the upper surface of the metallic region and a lower surface of the metallic region. The device also includes a second interlayer dielectric over the first interlayer dielectric.The device further comprises a first conductive structure above and electrically coupled to the source / drain contact connector, wherein the first conductive structure has a first upper section surrounded by the second interlayer dielectric, and the first conductive structure has a first lower section extending below the second interlayer dielectric into the source / drain contact connector. In one embodiment, the device further comprises a second conductive structure with a second lower section extending below the second interlayer dielectric into the source / drain contact connector, the second lower section contacting the interblock dielectric. In one embodiment, the first lower section and the second lower section have different material compositions.In one embodiment, the material composition of the first insulating layer is the same as the material composition of the interblock dielectric.

[0092] Another embodiment is a device comprising a source / drain region of a transistor. The device also includes a first interlayer dielectric over the source / drain region. Furthermore, the device has a source / drain contact plug over and electrically coupled to the source / drain region, the source / drain contact plug having a metallic region. The device also includes an interlayer dielectric arranged within the metallic region, the interlayer dielectric having an upper surface that is level with an upper surface of the metallic region and a lower surface arranged between the upper surface of the metallic region and a lower surface of the metallic region. The device also includes a second interlayer dielectric over the first interlayer dielectric.The device further comprises a first conductive structure above and electrically coupled to the source / drain contact connector, wherein the first conductive structure has a first upper section surrounded by the second interlayer dielectric, and the first conductive structure has a first lower section extending below the second interlayer dielectric into the source / drain contact connector. In one embodiment, the device further comprises a second conductive structure with a second lower section extending below the second interlayer dielectric into the source / drain contact connector, the second lower section contacting the interblock dielectric. In one embodiment, the first lower section and the second lower section have different material compositions.

Claims

[1] Procedure, encompassing: Formation of a metallic region (68) in a first insulating layer (48); Forming a recess (71) in the metallic region (68); Filling the recess (71) with an intermediate block dielectric (73); Deposition of a second insulating layer (76) over the metallic region (68) and the first insulating layer (48); Forming a first conductive structure (84) that extends through the second insulating layer (76) and into the metallic region (68); and Forming a second conductive structure (94) extending through the second insulating layer (76) and into the metallic region (68), wherein the first conductive structure (84) is located on a first side of the interblock dielectric (73) and the second conductive structure (94) is located on a second side of the interblock dielectric (73), the second side being opposite to the first side. [2] Method according to claim 1, wherein forming the first conductive structure (84) comprises: Performing a first etching process to etch the second insulating layer (76) in order to form a first opening (78) in the second insulating layer (76), wherein the first opening (78) exposes a section of the metallic region (68); and Performing a second etching process through the first opening (78) to etch a first depression (80) into an upper surface (22A) of the metallic region (68), wherein the first depression (80) has a larger lateral extent than a bottom surface of the first opening (78). [3] Method according to claim 2, wherein performing the second etching process exposes a side wall of the interblock dielectric (73). [4] Method according to any of the preceding claims, wherein the first conductive structure (84) or the second conductive structure (94) contacts the interblock dielectric (73). [5] Method according to any of the preceding claims, wherein the first conductive structure (84) has a different material composition than the metallic region (68), comprising forming the second conductive structure (94): Forming a third opening (86) in the second insulating layer (76); and Performing a third etching process through the third opening (86) to etch a second depression (88) into an upper surface of the metallic region (68), wherein the interblock dielectric (73) prevents etchant from the third etching process from coming into contact with an interface between the first conductive structure (84) and the metallic region (68). [6] Method according to any of the preceding claims, wherein the interblock dielectric (73) has tapered side walls. [7] Method according to any of the preceding claims, wherein the recess (71) extends through an entire width of the metallic region (68). [8] Method according to any of the preceding claims, wherein an upper section (84u) of the first conductive structure (84) is offset about a side-to-side center of a lower section (84l) of the first conductive structure (84). [9] Method according to any of the preceding claims, wherein the metallic region (68) contains cobalt, and wherein the first conductive structure (84) contains tungsten. [10] exhibiting structure: a first insulating layer (48); a first metallic conductor (68) arranged in the first insulating layer (48), wherein the first metallic conductor (68) is laterally surrounded by the first insulating layer (48) and the first metallic conductor (68) has an upper surface which is level with an upper surface of the first insulating layer (48); an intermediate block dielectric (73) arranged in the first metallic conductor (68), wherein the intermediate block dielectric (73) has an upper surface which is level with the upper surface of the first metallic conductor (68), and the intermediate block dielectric (73) has a lower surface which is arranged between a lower surface of the first metallic conductor (68) and the upper surface of the first metallic conductor (68); a second insulating layer (76) arranged above the first insulating layer (48); a first metallic contact (84) which is arranged in the second insulating layer (76) and extends below the second insulating layer (76) into the first metallic conductor (68); and a second metallic contact (94) which is arranged in the second insulating layer (76) and extends under the second insulating layer (76) into the first metallic conductor (68), wherein the first metallic contact (84) is arranged on a first side of the interblock dielectric (73) and the second metallic contact (94) is arranged on a second side of the interblock dielectric (73). [11] Structure according to claim 10, wherein the first metallic contact (84) or the second metallic contact (94) has an interface with the interblock dielectric (73). [12] Structure according to claim 10 or 11, wherein the interblock dielectric (73) has tapered sidewalls. [13] Structure according to any one of the preceding claims 10 to 12, wherein the interblock dielectric (73) has a non-flat lower surface. [14] Structure according to any one of the preceding claims 10 to 13, wherein the first metallic contact (84) has a different material than the second metallic contact (94). [15] Structure according to any one of the preceding claims 10 to 14, wherein an upper section (84u) of the first metallic contact (84) is surrounded by the second insulating layer (76), wherein a lower section (84l) of the first metallic contact (84) is laterally surrounded by the first metallic conductor (68), and wherein the upper section has a side-to-side center which is offset to a side-to-side center of the lower section (84l). [16] Structure according to any one of the preceding claims 10 to 15, wherein the material composition of the first insulating layer (48) is the same as the material composition of the interblock dielectric (73). [17] comprising a device: a source / drain region (42) of a transistor; a first interlayer dielectric (48) over the source / drain region (42); a source / drain contact connector (70) over and electrically coupled to the source / drain region (42), wherein the source / drain contact connector (70) has a metal region (68); an interblock dielectric (73) arranged in the metal region (68), wherein the interblock dielectric (73) has an upper surface which is level with an upper surface of the metal region (68) and a lower surface which is arranged between the upper surface of the metal region (68) and a lower surface of the metal region (68); a second interlayer dielectric (76) over the first interlayer dielectric (48); and a first conductive structure (84) above and electrically coupled to the source / drain contact connector (70), wherein the first conductive structure (84) has a first upper section (84u) surrounded by the second interlayer dielectric (76), and wherein the first conductive structure (84) has a first lower section (84l) extending below the second interlayer dielectric (76) into the source / drain contact connector (70). [18] Device according to claim 17, further comprising a second conductive structure (94) with a second lower section (94l) extending below the second interlayer dielectric (76) into the source / drain contact plug (70), wherein the second lower section (94l) contacts the interblock dielectric (73). [19] Device according to claim 18, wherein the first lower section (84l) and the second lower section (94l) have different material compositions. [20] Device according to claim 18 or 19, wherein the interblock dielectric (73) is wider than the width of the metallic region (68).

Images