Semiconductor structure of a cell narray with adaptive threshold voltage and method for providing the cell narray

Abstract

Semiconductor structure, exhibiting: a cell array with a layout comprising: regular cells (310a) of a first kind in which each p-transistor (P_VT1) has a first threshold voltage (Vth_p1) and each n-transistor (N_VT1) has a second threshold voltage (Vth_n1); regular cells (330b) of a second type different from the first type, in which each p-transistor (P_VT3) has a third threshold voltage (Vth_p3) and each n-transistor (N_VT3) has a fourth threshold voltage (Vth_n3); and mixed cells (465a) of a first kind, in which each p-transistor (P_VT1) has the first threshold voltage (Vth_p1) and each n-transistor (N_VT3) has the fourth threshold voltage (Vth_n3), wherein in the same row of the cell array a first mixed cell (465a) of the first type is arranged between a first regular cell (310a) of the first type and a second regular cell (330b) of the second type and is in contact with the first regular cell (310a), where, due to the use of the first mixed cell (465a) instead of a regular cell of the second type, a minimum width is achieved for a region with the first threshold voltage.

Description

BACKGROUND OF THE INVENTIONField of Invention

[0001] The invention relates to a cell array and, in particular, to a cell array formed from cells with adaptive voltages. Description of the state of the art

[0002] Integrated circuits (ICs) have become increasingly important. Devices that use ICs are used by millions of people. These applications include mobile phones, smartphones, tablets, laptops, notebook computers, PDAs, wireless email terminals, MP3 audio and video players, and portable wireless web browsers. Integrated circuits increasingly feature powerful and efficient onboard data storage and logic circuitry for signal control and processing.

[0003] As integrated circuits shrink, they become more compact. For various cells commonly used in integrated circuits, process control limitations lead to unbalanced threshold voltages between n- and p-type transistors. These unbalanced threshold voltages are further exacerbated by circuit topology (e.g., the stacked gate) and layout-dependent effects (LDE) (e.g., the diffusion barrier effect).

[0004] From US 2018 / 0 151 550 A1, a semiconductor structure is known which has a cell array which has a first regular cell, a second regular cell and a first mixed cell. In the first regular cell, each p-transistor has a first threshold voltage and each n-transistor has a second threshold voltage. In the second regular cell, each p-transistor has a third threshold voltage and each n-transistor has a fourth threshold voltage. In the first mixed cell, each p-transistor has the first threshold voltage and each n-transistor has the fourth threshold voltage. The first regular cell, the second regular cell and the first mixed cell are arranged in the same row of the cell array. The first mixed cell is arranged between the first and the second regular cell and is in contact with the first regular cell.

[0005] US 2008 / 0 010 626 A1 describes the provision in a standard cell library of first regular cells as well as mixed cells that use the type of PMOS from the first regular cell and the type of NMOS from the second regular cell. BRIEF SUMMARY OF THE INVENTION

[0006] The invention relates to a semiconductor structure according to claim 1.

[0007] In an embodiment not independently claimed, a semiconductor structure is provided. The semiconductor structure comprises a cell array. The cell array comprises a first mixed cell and a second mixed cell. The first mixed cell comprises at least one first p-type transistor with a first threshold voltage and at least one first n-type transistor with a second threshold voltage in a first row of the cell array, and at least one second p-type transistor with a third threshold voltage and at least one second n-type transistor with a fourth threshold voltage in a second row of the cell array.The second mixed cell includes at least one of the second p-type transistors having the third threshold voltage and at least one of the first n-type transistors having the second threshold voltage in the first row of the cell array, and at least one of the second p-type transistors having the third threshold voltage and at least one of the first n-type transistors having the second threshold voltage in the second row of the cell array. The first and second rows of the cell array have the same height. The first voltage difference between the first and second threshold voltages differs from the second voltage difference between the third and fourth threshold voltages.

[0008] The invention further relates to a method according to claim 7 for providing a cell array.

[0009] Further developments of the invention are specified in the dependent claims. A detailed description is given in the following embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The invention can be better understood by reading the following detailed description and examples with reference to the accompanying drawings, in which: Fig. Figure 1 is a flowchart showing a hierarchical design process of an integrated circuit (IC). Fig. 2 is a flowchart of a method for providing a cell array with adaptive threshold voltage according to an embodiment of the invention. Fig. Figure 3 shows a library of regular cells and a library of mixed cells for one embodiment of the invention. Fig. Figure 4 shows the relationship between speed and leakage current of the regular cells and the mixed cells in Fig. 3 in an embodiment of the invention. Fig. Figure 5 shows a library of regular cells and a library of mixed cells for one embodiment of the invention. Fig. 6 is a schematic diagram showing the replacement of a third regular cell according to an embodiment of the invention. Fig. 7 shows the original layout and the modified layout of a first cell array according to an embodiment of the invention. Fig. 8 shows the original layout and the modified layout of a second cell array to explain an embodiment of the invention. Fig. 9 is a schematic diagram showing a replacement of a third regular cell with a multiple height for one of the invention. Fig. 10 is a schematic diagram showing replacement of the abutting regular cells with different heights according to an embodiment of the invention. Fig. 11 shows a computer system for an embodiment of the invention. DETAILED DESCRIPTION OF THE INVENTION

[0011] The following description concerns the most preferred embodiment of the invention. This description is intended to describe the general principles of the invention. The scope of the invention is determined by the appended claims.

[0012] Some variations of the embodiments are described. Like reference numerals are used to refer to like elements throughout the various views and exemplary embodiments. It is understood that additional operations may be provided before, during, and / or after a disclosed method, and that some of the described operations may be substituted or omitted for further embodiments of the method.

[0013] Furthermore, spatially relative terms such as "below," "under," "lower," "above," "upper," and the like may be used herein for convenience of description to describe the relationship of one element or feature to one or more other elements or features as shown in the figures.

[0014] Fig. 1 is a flowchart illustrating a hierarchical design method of an integrated circuit (IC). In step S110, register transfer level (RTL) code is obtained that describes the work performed by the IC. The RTL code may indicate an execution of a design using a language that describes hardware, such as a hardware description language (HDL). In step S120, the RTL code is synthesized to generate a netlist that includes gates (or cells) of the IC. Generally, the IC includes multiple blocks, and each block provides an essential service for the IC, such as a specific processor (e.g., an application processor, a graphics processor, an audio processor, or a controller), memory (e.g., an SRAM device), and so on.In addition, each block has an associated RTL code, and thus the RTL code of each block is synthesized to generate the corresponding netlist containing the block's gates. Before the RTL code is synthesized, an RTL simulation is performed to verify the functional correctness of the RTL code. Furthermore, after obtaining the block's gates in the netlists, a gate-level simulation is performed to verify the functional correctness of the netlists. In step S130, a placement and routing process is performed according to the block gates in the netlists to generate a layout of whole blocks in a chip area of ​​the IC. Thus, a chip placement and routing process has been performed according to the placements, and a layout has been obtained. In some embodiments, the layout is a whole-chip layout.In some embodiments, the layout is part of a whole-chip layout related to some digital or analog circuitry of the IC. In some embodiments, the layout includes one or more cell arrays associated with the digital or analog circuitry. In step S140, an analysis process is performed and the layout is verified to check whether the layout violates any of the various constraints or rules. After the layout is completed, a Design Rule Check (DRC), a Layout Versus Schematic (LVS), and an Electrical Rule Check (ERC) are performed. DRC is a process for checking whether the layout has been successfully completed with a physically measured space according to the design rule, and LVS is a process for checking whether the layout conforms to an associated circuit diagram. Furthermore, ERC is a process for checking whether devices and wires / nets are electrically connected correctly.In addition, a post-simulation is performed to verify the functional completeness of the layout by extracting and simulating a parasitic component, such as a parasitic capacitance. If there are no violations in the layout, the IC is manufactured (or implemented) according to the layout (step S150). If a violation in the layout exists, the IC layout must be modified to correct the violation until no more violations exist.

[0015] Fig. 2 is a flowchart of a method for providing a cell array with adaptive threshold voltage according to an embodiment of the invention, the method of Fig. 2 is executed by a computer capable of running an electronic design automation (EDA) tool.

[0016] First, in step S210, the original layout of a cell array is obtained after the placement and routing process of step S130 of Fig. 1. In the original layout, multiple regular cells from one or more libraries of regular cells are arranged in multiple rows of the cell array. In some embodiments, the rows of the cell array may have the same height, i.e., the regular cells have the same cell height. In some embodiments, the rows of the cell array may have different heights, i.e., the regular cells have different cell heights.In some embodiments, the regular cells are selected from the group consisting of standard cells with standard threshold voltages (hereinafter referred to as the first type of regular cells), standard cells with low leakage current and low threshold voltages (hereinafter referred to as the second type of regular cells), standard cells with low threshold voltages (hereinafter referred to as the third type of regular cells), standard cells with low leakage current and ultra-low threshold voltages (hereinafter referred to as the fourth type of regular cells), standard cells with ultra-low threshold voltages (hereinafter referred to as the fifth type of regular cells), and standard cells with extremely low threshold voltages (hereinafter referred to as the sixth type of regular cells).In every regular cell, the threshold voltages of p-type transistors and the threshold voltages of n-type transistors have the same properties. For example, in the regular cell of the third type, the p-type transistors P_VT3 and the n-type transistors N_VT3 have the same threshold voltage properties.

[0017] In step S220, one or more mixed cell libraries are obtained. Each mixed cell library includes the mixed cells, and the p-type transistors and n-type transistors of each mixed cell have different threshold voltage characteristics. For example, a first mixed cell consists of the PMOS transistors P_VT3 of the third-type regular cell and the NMOS transistors N_VT2 of the second-type regular cell, and a second mixed cell consists of the NMOS transistors N_VT3 of the third-type regular cell and the PMOS transistors P_VT2 of the second-type regular cell. In other words, the threshold voltage of the p-type transistor and the threshold voltage of the n-type transistor in each mixed cell correspond to different types of regular cells.

[0018] With reference to Fig. 3 shows Fig. 3 shows a library of regular cells 300A and a library of mixed cells 400A in one embodiment of the invention. The library of regular cells 300A includes the regular cells of the first type 310, the regular cells of the second type 320, the regular cells of the third type 330, the regular cells of the fourth type 340, the regular cells of the fifth type 350, and the regular cells of the sixth type 360. In Fig. 3, the regular cells 310 to 360 have the same circuit configuration and layout size (i.e., cell size) for a standard cell, and the differences between the regular cells 310 to 360 are that the p- and n-type transistors have corresponding threshold voltages. In some embodiments, the respective threshold voltages are obtained by using different threshold voltage layers to form the transistors in certain processes. In some embodiments, the different threshold voltage layers are formed by one or more work function layers.

[0019] In some embodiments, the work function layer of the p-type transistor includes the p-type work function metal. The p-type work function metal includes titanium nitride (TiN), tungsten nitride (WN), tantalum nitride (TaN), ruthenium (Ru), or a combination thereof. In some embodiments, the work function layer of the n-type transistor includes the n-type work function metal. The n-type work function metal includes tungsten (W), copper (Cu), titanium (Ti), silver (Ag), aluminum (Al), titanium-aluminum alloy (TiAl), titanium aluminum nitride (TiAlN), tantalum carbide (TaC), tantalum carbon nitride (TaCN), tantalum silicon nitride (TaSiN), manganese (Mn), zirconium (Zr), or a combination thereof.

[0020] In some embodiments, the work function layer comprises a combination of multiple layers selected from a group consisting of TiN, TaN, TiAl, TiAlN, W, or a combination thereof. In some embodiments, the work function layer is formed by multiple patterning and multiple metal deposition steps for multiple work function schemes. Furthermore, different threshold voltages are obtained by adjusting the material and / or thickness of the work function layers.

[0021] In the library of regular cells 300A, the regular cell of the first type 310 includes the p-type transistors P_VT1 with the threshold voltage Vth_p1 and the n-type transistors N_VT1 with the threshold voltage Vth_n1. In the layout of the regular cell of the first type 310, the p-type transistors P_VT1 and the n-type transistors N_VT1 are arranged in the upper and lower regions, respectively. The threshold voltages of the p-type transistor P_VT1 and the n-type transistor N_VT1 differ and have a voltage difference VD_VT1.

[0022] The regular cell of the second type 320 includes the p-type transistors P_VT2 with the threshold voltage Vth_p2 (where Vth_p2 < Vth_p1) and the n-type transistors N_VT2 with the threshold voltage Vth_n2 (where Vth_n2 < Vth_n1). In the layout of the regular cell of the second type 320, the p-type transistors P_VT2 and the n-type transistors N_VT2 are arranged in the upper and lower regions, respectively. The threshold voltages of the p-type transistor P_VT2 and the n-type transistor N_VT2 differ and have a voltage difference VD_VT2.

[0023] The regular cell of the third type 330 includes the p-type transistors P_VT3 with the threshold voltage Vth_p3 (where Vth_p3 < Vth_p2) and the n-type transistors N_VT3 with the threshold voltage Vth_n3 (where Vth_n3 < Vth_n2). In the layout of the regular cell of the third type 330, the p-type transistors P_VT3 and the n-type transistors N_VT3 are arranged in the upper and lower regions, respectively. The threshold voltages of the p-type transistor P_VT3 and the n-type transistor N_VT3 differ and have a voltage difference VD_VT3.

[0024] The regular cell of the fourth type 340 includes the p-type transistors P_ULVTLL with the threshold voltage Vth_p4 (where Vth_p4 < Vth_p3) and the n-type transistors N_ULVTLL with the threshold voltage Vth_n4 (where Vth_n4 < Vth_n3). In the layout of the regular cell of the fourth type 340, the p-type transistors P_VT4 and the n-type transistors N_VT4 are arranged in the upper and lower regions, respectively. The threshold voltages of the p-type transistor P_VT4 and the n-type transistor N_VT4 differ and have a voltage difference VD_VT4.

[0025] The regular fifth-type cell 350 includes p-type transistors P_VT5 with threshold voltage Vth_p5 (where Vth_p5 < Vth_p4) and n-type transistors N_VT5 with threshold voltage Vth_n5 (where Vth_n5 < Vth_n4). In the layout of the regular fifth-type cell 350, the p-type transistors P_VT5 and n-type transistors N_VT5 are arranged in the upper and lower regions, respectively. The threshold voltages of the p-type transistor P_VT5 and the n-type transistor N_VT5 differ and have a voltage difference VD_VT5.

[0026] The regular cell of the sixth type 360 ​​includes the p-type transistors P_ELVT with the threshold voltage Vth_p6 (where Vth_p6 < Vth_p5) and the n-type transistors N_VT6 with the threshold voltage Vth_n6 (where Vth_n6 < Vth_n5). In the layout of the regular cell of the sixth type 360, the p-type transistors P_VT6 and the n-type transistors N_VT6 are arranged in the upper and lower regions, respectively. The threshold voltages of the p-type transistor P_VT6 and the n-type transistor N_VT6 differ and have a voltage difference VD_VT6.

[0027] In the regular cell library 300A, the p-type and n-type transistors of each regular cell have unbalanced threshold voltages, meaning there is a large difference between the threshold voltage of the p-type transistor and the threshold voltage of the n-type transistor. To prevent the unbalanced threshold voltages in the p-type and n-type transistors from limiting the minimum operating voltage (e.g., VDD) of the regular cell, mixed cells are used in the mixed cell library 400A, which have matched threshold voltages in the p-type and n-type transistors.

[0028] In the mixed cell library 400A, the mixed cells 410 to 450 have a similar circuit configuration and layout size (i.e., cell size) to the regular cells 310 to 360. Compared with the regular cells 310 to 360 of the regular cell library 300A, in each of the mixed cells 410 to 450, the threshold voltage of the p-type transistor is close to the threshold voltage of the n-type transistor. In other words, each mixed cell in the mixed cell library 400A has a smaller difference between the threshold voltage of the p-type transistor and the threshold voltage of the n-type transistor.

[0029] The mixed cell 410 includes p-type transistors P_VT2 with threshold voltage Vth_p2 and n-type transistors N_VT1 with threshold voltage Vth_n1. In other words, the mixed cell 410 is obtained by mixing the p-type transistors P_VT2 of the regular second-type cell 320 and the n-type transistors N_VT1 of the regular first-type cells 310. The threshold voltages of the p-type transistor P_VT2 and the n-type transistor N_VT1 are similar and have a voltage difference VD_MSVT. The voltage difference VD_MSVT differs from the voltage difference VD_VT1 of the regular first-type cell 310 and the voltage difference VD_VT2 of the regular second-type cell 320 (e.g., it is smaller or larger). Therefore, the mixed cell 410 has the matched threshold voltages of the p- and n-transistors compared to the regular cell of the first type 310 and the regular cell of the second type 320.

[0030] The mixed cell 420 includes p-type transistors P_VT3 with threshold voltage Vth_p3 and n-type transistors N_VT2 with threshold voltage Vth_n2. In other words, the mixed cell 420 is obtained by mixing the p-type transistors P_VT3 of the third-type regular cell 330 and the n-type transistors N_VT2 of the second-type regular cell 320. The threshold voltages of the p-type transistor P_VT3 and the n-type transistor N_VT2 are similar and have a voltage difference VD_MLVTLL, and the voltage difference VD_VT2 is smaller or larger than the voltage difference VD_VT2 of the second-type regular cell 320 and the voltage difference VD_VT3 of the third-type regular cell 330.

[0031] In some embodiments, the voltage differences VD_VT1, VD_VT3, and VD_VT2 are different. Furthermore, the voltage difference VD_MLVTLL is close to the voltage difference VD_MSVT.

[0032] In the mixed cell library 400A, the threshold voltages of the p-transistor P_VT4 and the n-transistor N_VT3 of the mixed cell 430 are similar to each other, the threshold voltages of the p-transistor P_VT5 and the n-transistor N_VT4 of the mixed cell 440 are similar to each other, and the threshold voltages of the p-transistor P_VT6 and the n-transistor N_VT5 of the mixed cell 450 are similar to each other.

[0033] With reference to Fig. 4 shows Fig. 4 the relationship between speed and leakage current of the regular cells and the mixed cells in Fig. 3 in one embodiment of the invention. As in Fig. As shown in Figure 4, the mixed cells 410 to 450 provide the circuits with more speed and leakage current options. For example, the mixed cell 430 is obtained by mixing the p-type transistors P_VT4 of the regular fourth-type cell 340 and the n-type transistors N_VT3 of the regular third-type cell 330. Thus, the leakage current and speed of the mixed cell 430 are between those of the regular fourth-type cell 340 and the regular third-type cell 330.

[0034] With further reference to Fig. 2, in step S230, the original layout of the cell array is modified according to the critical paths or special configurations in the cell array by replacing some regular cells with the mixed cells obtained in step S220. Various cell replacements are described below. After the replacement in step S230 is completed, the modified layout with adjusted threshold voltages is obtained in step S240. As described above, the modified layout is verified to check whether the layout violates any of the various constraints or rules. If there are no violations in the layout, the IC is manufactured (or implemented) according to the layout.

[0035] With reference to Fig. 5 shows Fig. 5 shows a library of regular cells 300B and a library of mixed cells 400B in one embodiment of the invention. Fig. 5, the regular cell library 300B includes the first-type regular cell 310 and the third-type regular cell 330, and the mixed cell library 400B includes the mixed cells 460 and 465. In such an embodiment, the regular cells 310 and 330 and the mixed cells 460 and 465 have the same circuit configuration and layout size (i.e., cell size). Compared to the regular cells 310 and 330 of the regular cell library 300B, in the mixed cells 460 and 465, the threshold voltage of the p-type transistor is close to the threshold voltage of the n-type transistor.

[0036] In Fig. 5, the mixed cell 460 includes p-type transistors P_VT3 with threshold voltage Vth_p3 and n-type transistors N_VT1 with threshold voltage Vth_n1. In other words, the mixed cell 460 is obtained by mixing the p-type transistors P_VT3 of the third-type regular cell 330 and the n-type transistors N_VT1 of the first-type regular cell 310. Furthermore, the mixed cell 465 includes n-type transistors N_VT3 with threshold voltage Vth_n3 and p-type transistors P_VT1 with threshold voltage Vth_p1. In other words, the mixed cell 465 is obtained by mixing the n-type transistors N_VT3 of the third-type regular cell 330 and the p-type transistors P_VT1 of the first-type regular cell 310.

[0037] Fig. 6 is a schematic diagram showing the replacement of the regular cell of the third type 330 in one embodiment of the invention. As described above, the leakage current and speed of the mixed cells 460 and 465 are between the regular cell of the first type 310 and the regular cell of the third type 330. Therefore, in the case of prioritizing power consumption (e.g., reducing leakage current), the regular cell of the third type 330 in a clock-noncritical path of the cell array can be replaced by a regular cell of the first type 310. Furthermore, the regular cell of the third type 330 in a clock-critical path of the cell array can be replaced by the mixed cell 460 or 465. In contrast, in the case of prioritizing speed, the regular cell of the third type 330 can be replaced by the mixed cell 430 of Fig. 3. In other words, only the p-type transistors in the regular cell of the third type 330 are replaced to obtain the mixed cell 430.

[0038] Fig. 7 shows the original layout 500A and the modified layout 500B of a first cell array according to an embodiment of the invention. The original layout 500A has four rows ROW1 to ROW4 of the first cell array. The regular cells of the first type 310 and the regular cells of the third type 330 with a cell height of SH1 are arranged in row ROW1. The regular cells of the third type 330 with a cell height of SH2 are arranged in row ROW2. The regular cells of the first type 310 and the regular cells of the third type 330 with a cell height of SH3 are arranged in row ROW3. The regular cells of the first type 310 with a cell height of SH4 are arranged in row ROW4. In some embodiments, the cell heights SH1 to SH4 are the same. In some embodiments, the cell heights SH1 to SH4 are different.In addition, the regular cells of the first type 310 and the regular cells of the third type 330 in the rows ROW1 to ROW4 of the first cell array may have corresponding circuit configurations for special functions (or logical operations).

[0039] In the original layout 500A, the regular first-type cell 310a, the regular third-type cell 330a, the regular first-type cell 310b, and the regular third-type cell 330b are arranged sequentially in row ROW1. In such an embodiment, the regular first-type cell 310b is surrounded by the regular third-type cells 330a and 330b. For better performance, the regular third-type cell 330a and the regular first-type cell 310b are replaced by the mixed cells 465a and 460b, respectively, to obtain the modified layout 500B. As described above, the mixed cell 465a is obtained by mixing the n-type transistors N_VT3 of the regular third-type cell 330a and the p-type transistors P_VT1 of the regular first-type cell 310.Furthermore, the mixed cell 460b is obtained by mixing the p-type transistors P_VT3 of the regular cell of the third type 330 and the n-type transistors N_VT1 of the regular cell of the first type 310. Thus, the mixed cell 465a and the regular cell of the first type 310a have the same type of p-type transistors P_VT1, which have the same work function layer, and the mixed cell 460b and the regular cell of the third type 330b have the same type of p-type transistors P_VT3, which have the same work function layer. In some embodiments, the regular cell of the first type 310a and the regular cell of the third type 330 are arranged in a clock-noncritical path of a circuit, and the mixed cell 465a and the mixed cell 460b are arranged in a clock-critical path of a circuit.

[0040] Fig. 8 shows the original layout 600A and the modified layout 600B of a second cell array for explaining an embodiment of the invention. The original layout 600A has four rows ROW1 to ROW4 of the second cell array. The regular cells of the first type 310 and the regular cells of the third type 330 with single height SH are arranged in row ROW1. The regular cells of the first type 310 with single height SH are arranged in row ROW2. The regular cells of the first type 310 and the regular cells of the third type 330 with double height DH are arranged in rows ROW3 and ROW4. Furthermore, the regular cells of the first type 310 and the regular cells of the third type 330 in each row of the second cell array can have a corresponding circuit configuration for each specific function (or logic operation).

[0041] In the original layout 600A, the third-type regular cells 330c and 330d are arranged consecutively in the row ROW1, and the third-type regular cell 330c is a filler cell. In some embodiments, the filler cell may be a dummy cell with or without a device. To satisfy design constraints or rules (e.g., avoiding layout violations), in the modified layout 600B, the third-type regular cell 330c is replaced with the mixed cell 460c after the third-type regular cell 330d is replaced with the mixed cell 460d. Similarly, the mixed cell 460c is a filler cell. Thus, the threshold voltage layer corresponding to the p-type transistors P_VT3 can be extended from the mixed cell 460d to the mixed cell 460c, thereby satisfying the minimum width rule of the threshold voltage layer corresponding to the p-type transistors P_VT1 to avoid violation.

[0042] In the original layout 600A, the third-type regular cells 330f and 330e and the first-type regular cell 310c are arranged in rows ROW3 and ROW4. In the first-type regular cell 310c, half of the p-type transistors P_VT1 are arranged in the upper region of row ROW3, ​​and the remaining half of the p-type transistors P_VT1 are arranged in the lower region of row ROW4. Furthermore, half of the n-type transistors N_VT1 are arranged in the lower region of row ROW3, ​​and the remaining half of the n-type transistors N_VT1 are arranged in the upper region of row ROW4. In the modified layout 600B, the first-type regular cell 310c is replaced by the mixed cell 480c. In the mixed cell 480c, the n-type transistors N_VT1 and the p-type transistors P_VT1 arranged in the row ROW4 are replaced by the n-type transistors N_VT3 and the p-type transistors P_VT3, respectively.Thus, half of the n- and p-transistors of the regular cell of the first type 310c are replaced to obtain the mixed cell 480c.

[0043] In the regular third-type cell 330f, half of the p-type transistors P_VT3 are arranged in the upper region of row ROW3, ​​and the remaining half of the p-type transistors P_VT3 are arranged in the lower region of row ROW4. Furthermore, half of the n-type transistors N_VT3 are arranged in the lower region of row ROW3, ​​and the remaining half of the n-type transistors N_VT3 are arranged in the upper region of row ROW4. In other words, in the regular third-type cell 330f, the p-type transistors P_VT3 are surrounded by the n-type transistors N_VT3. Similarly, in the regular third-type cell 330e, half of the p-type transistors P_VT3 are arranged in the upper region of row ROW3, ​​and the remaining half of the p-type transistors P_VT3 are arranged in the lower region of row ROW4.Furthermore, half of the n-type transistors N_VT3 are arranged in the lower region of row ROW3, ​​and the remaining half of the n-type transistors N_VT3 are arranged in the upper region of row ROW4. In other words, in the regular cell of the third type 330e, the p-type transistors P_VT1 are surrounded by the n-type transistors N_VT1.

[0044] In the modified layout 600B, the regular cells of the third type 330f and 330e are replaced by the mixed cells 470f and 490e, respectively. Note that the p-type and n-type transistors in the mixed cells 470f and 490e have different configurations. For example, in the mixed cell 470f, the n-type transistors N_VT3 and the p-type transistors P_VT3 arranged in the row ROW4 are replaced by the n-type transistors N_VT1 and the p-type transistors P_VT1, respectively. Thus, the n-type and p-type transistors arranged in the row ROW4 are replaced to obtain the mixed cell 470f. Furthermore, in the mixed cell 490e, the n-type transistors N_VT3 located in rows ROW3 and ROW4 are replaced by the n-type transistors N_VT1. Thus, only the n-type transistors are replaced to obtain the mixed cell 490e.In other words, no p-type transistors P_VT1 and no n-type transistors N_VT3 are present in the mixed cell 490e. In some embodiments, the p-type transistors P_VT3 of the regular third-type cell 330e, arranged in rows ROW3 and ROW4, are replaced by the p-type transistors P_VT1. Thus, only the p-type transistors can be replaced to obtain the mixed cell 490e.

[0045] Fig. Figure 9 is a schematic diagram showing a replacement of a regular cell of the third type 330 with a multiple height MH in one embodiment of the invention. In Fig. 9, the multiple height MH is three times the single height SH. Each single height SH corresponds to a respective row of a cell array. For example, the p-type transistors P_VT3 with m fins (m ≥ 1) and the n-type transistors N_VT3 with m fins are arranged in a first row, the p-type transistors P_VT3 with n fins (n ​​> m) are arranged in a second row, and the n-type transistors N_VT3 with n fins are arranged in a third row. In such an embodiment, the transistors with fewer fins are replaced to obtain a mixed cell 435. Thus, the p-type transistors P_VT3 and the n-type transistors N_VT3 in the first row are replaced by the p-type transistors P_VT4 and the n-type transistors N_VT4 to obtain the mixed cell 435. In some embodiments, in a mixed cell with the single height SH, only the transistors with fewer fins are replaced.

[0046] Fig. Figure 10 is a schematic diagram showing a replacement of the abutting regular cells with different heights in one embodiment of the invention. Fig. 10, the regular cell of the fourth type 340 has the single height SH, the regular cell of the third type 330_1 has the multi-height MH, and the regular cell of the third type 330_2 has the double height DH. The regular cell of the fourth type 340 and the regular cells of the third type 330_1 and 330_2 are adjacent to each other. In such an embodiment, the multi-height MH is three times the single height SH, and the double height DH is twice the single height SH. To match the regular cell of the fourth type 340, the p-type transistors P_VT3 and the n-type transistors N_VT3 in the lower region (which correspond to the single height SH) are replaced by the p-type transistors P_VT4 and n-type transistors N_VT4.

[0047] Fig.11 shows a computer system 700 for one embodiment of the invention. The computer system 700 includes a computer 710, a display device 720, and a user input interface 730, wherein the computer 710 includes a processor 740, a memory 750, and a storage device 760. The computer 710 is connected to the display device 720 and the user input interface 730, wherein the computer 710 is capable of running an electronic design automation (EDA) tool. Furthermore, the computer 710 is capable of receiving input instructions or information (e.g., timing constraints, RTL code, or storage device interface information) from the user input interface 730 and displaying simulation results, the layout of the IC, and the blocks or circuits of the layout on the display device 720. In some embodiments, the display device 720 is a GUI for the computer 710.Furthermore, the display device 720 and the user input interface 730 may be implemented in the computer 710. The user input interface 730 may be a keyboard, a mouse, etc. Within the computer 710, the storage device 760 may store the operating systems (OSs), applications, information (e.g., circuit function information and performance-related information), and data including inputs required by the applications and / or outputs generated by the applications. The processor 740 of the computer 710 may perform one or more operations (either automatically or with user input) in any method implicitly or explicitly described in this disclosure.For example, during an operation, the processor 740 may load the applications of the storage device 760 into the memory 750, and then the applications may be used by the user to generate, display, and / or edit a placement, floor plan, and physical layout for a circuit design (e.g., the cell array with adaptive threshold voltages).

[0048] The data structures and code described in this disclosure may be stored partially or entirely on a computer-readable storage medium and / or a hardware module and / or hardware device. A computer-readable storage medium may consist of volatile memory, non-volatile memory, magnetic and optical storage devices such as disk drives, magnetic tapes, CDs (compact discs), DVDs (digital versatile discs or digital video discs), or other media capable of storing code and / or data. Examples of hardware modules or units described in this disclosure include, but are not limited to, application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), dedicated or shared processors, and / or other hardware modules or units.

Claims

[1] Semiconductor structure, comprising: a cell array having a layout comprising: regular cells (310a) of a first type, in which each p-transistor (P_VT1) has a first threshold voltage (Vth_p1) and each n-transistor (N_VT1) has a second threshold voltage (Vth_n1); regular cells (330b) of a second type different from the first type, in which each p-transistor (P_VT3) has a third threshold voltage (Vth_p3) and each n-transistor (N_VT3) has a fourth threshold voltage (Vth_n3); and mixed cells (465a) of a first type, in which each p-transistor (P_VT1) has the first threshold voltage (Vth_p1) and each n-transistor (N_VT3) has the fourth threshold voltage (Vth_n3), wherein in a same row of the cell array, a first mixed cell (465a) of the first type is arranged between a first regular cell (310a) of the first type and a second regular cell (330b) of the second type and is in contact with the first regular cell (310a), where a minimum width for a region with the first threshold voltage is achieved due to the use of the first mixed cell (465a) instead of a regular cell of the second type. [2] The semiconductor structure of claim 1, wherein a first voltage difference between the first (Vth_p1) and the second threshold voltage (Vth_n1) is different from a second voltage difference between the third (Vth_p3) and the fourth (Vth_n3) threshold voltage, and wherein a third voltage difference between the first (Vth_p1) and the fourth (Vth_n3) threshold voltage is smaller or larger than the first and the second voltage difference. [3] Semiconductor structure according to claim 1 or 2, wherein the first and second regular cells (310a, 330b) are arranged in a clock-non-critical path of a circuit and the first mixed cell (465a) is arranged in a clock-critical path of the circuit and / or wherein the first mixed cell (465a) does not have an n-type transistor with a second threshold voltage. [4] A semiconductor structure according to any one of the preceding claims, wherein the n- and p-transistors of the first mixed cell (465a) are fin field effect transistors, and wherein in the first mixed cell (465a) the p-transistor has fewer fins than the n-transistor. [5] The semiconductor structure of claim 1, wherein the cell array further comprises: a second mixed cell (460b), wherein in the second mixed cell (460b) each p-transistor (P_VT3) has the third threshold voltage (Vth_p3) and each n-transistor (N_VT1) has the second threshold voltage (Vth-N1), wherein the second mixed cell (460b) is arranged between the first mixed cell (465a) and the second regular cell (330b) and is in contact with the first mixed cell (465a) and the second regular cell (330b). [6] The semiconductor structure of claim 5, wherein a first voltage difference between the first (Vth_p1) and the second (Vth_n1) threshold voltages and a second voltage difference between the third (Vth_p1) and the fourth (Vth_n3) threshold voltages is greater than a third voltage difference between the first (Vth_p1) and the fourth (Vth_n3) threshold voltages and a fourth voltage difference between the third (Vth_p1) and the second (Vth_n1) threshold voltages, preferably wherein the first voltage difference is different from the second voltage difference and the third voltage difference is close to the fourth voltage difference. [7] A method of providing a cell array, comprising: Obtaining an original layout (500A) of the cell array, the original layout (500A) comprising a first regular cell (310a) and a second regular cell (330a) arranged in a first row of the cell array and in contact with each other; Replacing the second regular cell (330a) with a first mixed cell (465a) to obtain a modified layout (500B); and Manufacturing an integrated circuit according to the modified layout (500B), wherein in the first regular cell (310a) each p-transistor (P_VT1) has a first threshold voltage (Vth_p1) and each n-transistor (N_VT1) has a second threshold voltage (Vth_n1), wherein in the second regular cell (330b) each p-transistor (P_VT3) has a third threshold voltage (Vth_p3) and each n-transistor (N_VT3) has a fourth threshold voltage (Vth_n3), wherein in the first mixed cell (465a) each p-transistor (P_VT1) has the first threshold voltage (Vth_p1) and each n-transistor (N_VT3) has the fourth threshold voltage (Vth_n3), wherein a first voltage difference between the first (Vth_p1) and the second (Vth_n1) threshold voltage is different from a second voltage difference between the third (Vth_p3) and the fourth (Vth_n3) threshold voltage, and a third voltage difference between the first (Vth_p1) and the fourth (Vth_n3) threshold voltage is smaller or larger than the first and the second voltage difference. [8] The method of claim 7, wherein the second regular cell (330a) is arranged in a clock-non-critical path of a circuit and the first regular cell (310a) is arranged in a clock-critical path of the circuit and / or wherein the third threshold voltage (Vth_p3) is higher than the first (Vth_p1) threshold voltage and the fourth (Vth_n3) threshold voltage is higher than the second (Vth_n1) threshold voltage.

Images