IMPROVED DATA RETENTION FOR A STORAGE DEVICE WITH ON-PITCH SEMI-CIRCULAR DRAIN-SIDE SELECTION GATE TECHNOLOGY

Abstract

Storage device, comprising: Memory cells (682, 683) connected to one of a plurality of word lines (WLL0-WLL10) including at least one edge word line (WLL10) and a plurality of other data word lines (WLL0-WLL9), arranged in chains (NS1, NS2) and configured to maintain a threshold voltage (Vt) corresponding to one of a plurality of data states (AG, ERASE), the chains (NS1, NS2) being organized in series; and a control instrument that is connected to and set up with the multitude of word lines (WLL0-WLL10) and chains (NS1, NS2) for: Identifying at least one marginal word lead (WLL10), and Programming the memory cells (682, 683) of the chains (NS1, NS2) in their respective rows and those assigned to the at least one edge word line (WLL10), such that a modified distribution of the threshold voltage (Vt) for one or more of the plurality of data states (AG, ERASE) is present compared to the memory cells of the chains that are not in their respective rows and are not assigned to the at least one edge word line (WLL10) during a programming operation, wherein the respective rows include semicircular rows that have memory holes (825) forming the chains, which are partially cut by a shallow hole etching.

Description

AREA

[0001] The present application relates to non-volatile storage devices and the operation of non-volatile storage devices. BACKGROUND

[0002] This section provides background information regarding the technology associated with the present disclosure and is therefore not necessarily prior art.

[0003] Semicircular drain-side select-gate (SC-SGD) memory technology offers several advantages, including a reduced chip size. SC-SGD is manufactured using etching technology to cut memory holes, giving them their semicircular shape and separating a block or row into multiple strings. Depending on the manufacturing process, certain inefficiencies can occur. For example, cutting a memory hole will remove at least some sections of the SC-SGD, such as the metal layer that otherwise shields electrical fields from the channel and / or charge-trap layer. Thus, the SC-SGD can be affected by a neighboring electrical field, potentially causing a parasitic transistor to leak along the SC-SGD transistor.In some cases, this leads to a measuring amplifier incorrectly determining that the SC-SGD is conducting, which can interfere with certain measurement operations. Due to etching variation, some chips may be cut down to an SGD layer, while others may be cut down to layers forming dummy word lines. Consequently, data retention problems can occur due to the proximity of the cut to data word lines. Accordingly, there is a need for improved non-volatile storage devices and operating procedures. Furthermore, the disclosures in US 2016 / 0099058 A1, US 2020 / 0303404 A1, and US 2015 / 0194435 A1 may be helpful for understanding the present invention.

[0004] US 2016 / 0099058 A1 concerns techniques for programming the memory cells of a drain-side edge word line of a group of word lines before programming memory cells of another word line in the group. Through voltages applied to the other word lines act as stress pulses, redistributing holes in the charge storage material of the memory cells of the other word lines to reduce short-term charge losses and a drop in threshold voltage. Additionally, one or more initial programming voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of programming error in the erased memory cells of the drain-side edge word line due to reduced channel gain.

[0005] US Patent 2020 / 0303404 A1 discloses a semiconductor storage device in which a peripheral circuit supplies a second region with a first voltage when it applies a selection potential to a region corresponding to the second region in a second conductive layer. The peripheral circuit supplies a first region with a second voltage that is higher than the first voltage when it applies a selection potential to a region corresponding to the first region in the second conductive layer.

[0006] US Patent 2015 / 0194435 A1 concerns a vertical non-volatile storage device in which the differences in the sizes of the channel bores containing channel structures are reduced. The vertical non-volatile storage device comprises a substrate with channel bore recess regions on its surface. Channel structures project vertically from the surface of the substrate on some of the channel bore recess regions, and memory cell stacks, comprising insulating and conductive layers, are stacked alternately along the sidewalls of the channel structures. On other channel bore recess regions, a common source line extends along the surface of the substrate in a word line recess region that separates adjacent memory cell stacks. SUMMARY

[0007] This section provides a general summary of the present disclosure and is not a comprehensive disclosure of its full scope of protection or all of its features and benefits.

[0008] One object of the present disclosure is to provide a storage device and a method for operating the storage device that address and overcome the aforementioned disadvantages. Accordingly, the present invention relates to a storage device according to claim 1, a control device according to claim 8, and a method according to claim 14. Advantageous embodiments may include features of dependent claims.

[0009] Accordingly, one aspect of the present disclosure is to provide a storage device comprising memory cells connected to one of a plurality of word lines, which include at least one edge word line and a plurality of other data word lines. The memory cells are arranged in chains and are configured to maintain a threshold voltage corresponding to one of a plurality of data states. The chains are organized in rows, and a control means is coupled to the plurality of word lines and the chains. The control means is configured to identify the at least one edge word line.The control device programs the memory cells of the chains in their respective rows and is assigned to at least one edge word line, so that a changed distribution of the threshold voltage for one or more of the multitude of data states is present compared to the memory cells of the chains that are not in their respective rows and are not assigned to at least one edge word line during a programming operation.

[0010] According to another aspect of the disclosure, a controller is also provided in communication with a storage device that includes memory cells connected to one of a plurality of word lines, including at least one edge word line and a plurality of other data word lines. The memory cells are arranged in chains and are configured to maintain a threshold voltage corresponding to one of a plurality of data states. The chains are organized in rows. The controller is configured to identify the at least one edge word line.The control system is also configured to instruct the memory device to program the memory cells of the chains in each of the rows that are assigned to the at least one edge word line, so that a modified distribution of the threshold voltage for one or more of the multitude of data states is present compared to the memory cells of the chains that are not in each of the rows and are not assigned to the at least one edge word line during a programming operation.

[0011] According to an additional aspect of the disclosure, a method for operating a storage device is provided. The storage device includes memory cells connected to one of a plurality of word lines, including at least one edge word line, and a plurality of other data word lines are also provided. The memory cells are arranged in chains and are configured to maintain a threshold voltage corresponding to one of a plurality of data states. The chains are organized in rows. The method includes the step of identifying the at least one edge word line.The procedure also includes the step of programming the memory cells of the chains in their respective rows and assigned to the at least one edge word line, so that a changed distribution of the threshold voltage for one or more of the multitude of data states is present compared to the memory cells of the chains that are not in their respective rows and are not assigned to the at least one edge word line during a programming operation.

[0012] Further areas of application will become apparent from the description given herein. The description and specific examples in this summary serve only for illustration and are not intended to limit the scope of protection of this disclosure. DRAWINGS

[0013] The drawings described herein serve only to illustrate selected embodiments and not all possible implementations, and are not intended to limit the scope of protection of the present disclosure. Fig. 1A is a block diagram of an exemplary storage device according to the aspects of the disclosure; Fig. Figure 1B is a block diagram of an exemplary control circuit, which includes a programming circuit, a counting circuit and a determination circuit according to the aspects of the disclosure; Fig. 2 illustrates schematic views of three types of storage architectures that use staggered storage chains according to the principles of revelation; Fig. 3A illustrates a cross-sectional view of exemplary floating-gate memory cells in NAND chains according to the aspects of the disclosure; Fig. 3B illustrates a cross-sectional view along a contact line, which is in Fig. 3A is shown, according to the aspects of revelation; Fig. 4A and Fig. Figure 4B illustrates a non-volatile memory in which a charge-trapping memory cell uses a non-conductive dielectric material instead of a conductive floating gate to store charge in a non-volatile manner according to the points of disclosure; Fig. Figure 5 illustrates an example block diagram of the data capture block of Fig. 1 according to the aspects of revelation; Fig. Figure 6A is a perspective view of a set of blocks in an exemplary three-dimensional configuration of the memory array of Fig. 1 according to the aspects of revelation; Fig. Figure 6B illustrates an exemplary cross-sectional view of a section of one of the blocks of Fig. 6A according to the aspects of revelation; Fig. Figure 6C illustrates a graphical representation of the memory hole diameter in the stack of Fig. 6B according to the aspects of revelation; Fig. 6D illustrates a detailed view of the stack region of Fig. 6B according to the aspects of revelation; Fig. 7A illustrates a schematic top view of a storage array with a plurality of storage holes according to the points of view of the disclosure; Fig. Figure 7B illustrates a cross-sectional view of the storage array according to the aspects of the disclosure; Fig. 8A and Fig. Figure 8B illustrates an alternative storage structure without dummy holes according to the principles of revelation; Fig. 9 presents an exemplary set of threshold voltage distributions according to the aspects of the disclosure; Fig. Figure 10 shows a cross-sectional plan view of storage holes taken at a drain-side selection gate layer and a marginal word-direction layer according to the points of disclosure; Fig. Figure 11 shows threshold voltage distributions and corresponding data or storage states before and after the high-temperature data retention test for an exemplary storage device according to the aspects of the disclosure; Fig. Figure 12 shows threshold voltage distributions of memory cells, illustrating an exemplary precompensation by programming memory cells that are programmed to a higher threshold voltage only in semicircular rows for the edge word line immediately after programming and after a high-temperature data retention test according to the aspects of the disclosure to the highest data state; Fig. Figure 13 shows threshold voltage distributions of memory cells, illustrating another exemplary precompensation by programming memory cells which are programmed to a higher threshold voltage for the edge word line immediately after programming and after the high-temperature data retention test in both semicircular and full-circular rows according to the disclosure for the highest data state; Fig. Figure 14 shows threshold voltage distributions of memory cells illustrating another exemplary precompensation by programming memory cells that are programmed to a higher threshold voltage for the seventh data state, the sixth data state, and the fifth data state, both in semicircular and full-circle rows for the edge word line immediately after programming and after the high-temperature data retention test according to the disclosure; Fig. Figure 15 shows threshold voltage distributions of memory cells illustrating another exemplary precompensation by programming memory cells that are programmed in both semicircular and full-circle arrays for the edge word line immediately after programming and after the high-temperature data retention test according to the disclosure to the seventh data state, the sixth data state, the fifth data state to a narrower threshold voltage distribution; and Fig. 16 illustrates steps of a procedure for operating a storage device according to the aspects of the disclosure.

[0014] For clarity, identical reference numerals have been used, where possible, to denote identical elements common to the figures. It is considered that elements disclosed in one embodiment may be advantageously used in other embodiments without specific mention. DETAILED DESCRIPTION

[0015] The following description provides details to facilitate an understanding of the present disclosure. In some cases, specific circuits, structures, and techniques have not been described or shown in detail to avoid obscuring the disclosure.

[0016] In general, this disclosure relates to non-volatile storage devices of a type well suited for use in many applications. The non-volatile storage device and the associated methods of this disclosure are described in conjunction with one or more embodiments. However, the specific exemplary embodiments disclosed serve only to describe the inventive concepts, features, advantages, and problems with sufficient clarity to enable the person skilled in the art to understand and implement the disclosure. In particular, the exemplary embodiments are presented to ensure that this disclosure is thorough and fully conveys the scope of protection to the person skilled in the art. Numerous specific details are given, such as examples of specific components, devices, and methods, to facilitate a thorough understanding of embodiments of this disclosure.It will be obvious to the person skilled in the art that specific details need not be included, that exemplary embodiments can be embodied in many different forms, and that none should be interpreted in such a way as to limit the scope of protection of the disclosure. In some exemplary embodiments, well-known processes, well-known device structures, and well-known technologies are not described in detail.

[0017] In some memory devices, memory cells are connected together in a block or subblock, as in NAND chains. A NAND chain has a number of memory cells connected in series between one or more drain-side select-gate SGD transistors on the drain side of the NAND chain, connected by a bit line, and one or more source-side select-gate SGS transistors on the source side of the NAND chain, connected by a source line. Furthermore, the memory cells can be arranged with a common control-gate line (e.g., word line) that acts on a control gate. A set of word lines extends from the source side of a block to the drain side of a block. Memory cells can also be connected in other types of chains and in other ways.

[0018] In a 3D memory structure, memory cells can be arranged in vertical chains within a stack, where the stack has alternating conductive and dielectric layers. The conductive layers act as word lines connected to the memory cells. The memory cells can include data storage cells suitable for storing user data and dummy or non-data storage cells unsuitable for storing user data.

[0019] Before programming certain non-volatile memory devices, the memory cells are typically erased. In some devices, the erasure process removes electrons from the floating gate of the memory cell being erased. Alternatively, the erasure process removes electrons from a charge-trapping layer.

[0020] Each memory cell can be assigned a data state according to write data in a programming instruction. Based on its data state, a memory cell either remains in the erased state or is programmed into a programmed state. For example, in a memory device with three bits per cell, there are eight data states, including the erased state and the programmed state.

[0021] During a programming operation, memory cells are programmed according to a word line programming sequence. For example, programming might begin on the word line at the source side of the block and continue on the word line at the drain side of the block. In one approach, each word line is fully programmed before the next one is programmed. For example, a first word line, WL0, is programmed using one or more programming pulses until programming is complete. Next, a second word line, WL1, is programmed using one or more programming pulses until programming is complete, and so on. A programming pulse might include a set of increasing programming voltages applied to the word line in appropriate programming loops or programming verification iterations.Verification processes or stages can be performed after each programming voltage to determine whether the memory cells have completed programming. Once programming is complete for a memory cell, it can be locked against further programming, while programming continues for other memory cells in subsequent programming loops.

[0022] When generating various rows and strings for a memory structure, a cutting operation (e.g., Shallow Hole Etch or SHE) can be used. The SHW cut can divide a block (in memory) into multiple chains within the block. While the SHE can form / define the chains, the SHE cut can also split a chain, i.e., cut the edge memory holes in a chain in half (or roughly into two equal halves). In this respect, both the SGD and the channel are split. Ideally, the SHE cut is only needed up to the SGD layer. However, due to process (etching) variation, it is extremely difficult to cut precisely at SGD; some may cut down to one of the dummy word line layers (e.g., the DWLD0 layer of a memory interface). Fig. 6B), but some can also be cut from another of the dummy word-line layers (e.g., the DWLD1 layer of Fig. 6B) or even an upper or a marginal word lead (e.g. WLL10 of Fig. 6B) cut. If the SHE cut is closer to the upper or edge word line (it does not have to be a physical cut), the data retention (e.g., high-temperature data retention / HTDR) will be significantly worse (unacceptable).

[0023] Several aspects of this disclosure can be implemented in the form of a device, a system, a process, or a computer program. Therefore, aspects of this disclosure can be implemented entirely in hardware or software (including, but not limited to, firmware, resident software, microcode, or the like) or be a combination of hardware and software components, which may generally be referred to as a "circuit," "module," "device," or "system." Furthermore, various aspects of this disclosure can take the form of a computer program process, which may be embodied, for example, in one or more non-transitory, computer-readable storage media that store computer-readable and / or executable program code.

[0024] Furthermore, various terms are used to refer to specific system components. Different companies may refer to the same or similar component by different names, and this description is not intended to distinguish between components that differ in name but not in function. Where various functional units described in the following disclosure are referred to as "modules," such characterization is not intended to unduly restrict the range of possible implementation mechanisms. For example, a "module" could be implemented as a hardware circuit incorporating custom VLSI (very large scale integration) circuitry or gate arrays, or commercially available semiconductors including logic chips, transistors, or other discrete components.In another example, a module can also be implemented in a programmable hardware device such as a field-programmable gate array (FPGA), programmable array logic, programmable logic device, or the like. Furthermore, a module can also be implemented, at least partially, by software executed by various types of processors. For example, a module can have a segment of executable code containing one or more physical or logical blocks of computer instructions that translate into an object, process, or function. It is also not necessary for the executable sections of such a module to be physically located together; they can also have different instructions stored in different locations which, when executed together, constitute the identified module and fulfill its stated purpose.The executable code may consist of a single instruction or a set of multiple instructions, but it may also be distributed across different code segments, different programs, multiple storage devices, etc. In a software or sub-software module implementation, the software sections may be stored on one or more computer-readable and / or executable storage media, which may include, but are not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor-based system, device, or apparatus, or any suitable combination thereof.In general, for the purposes of this disclosure, a computer-readable and / or executable storage medium can be any tangible and / or non-transitory storage medium capable of containing and / or storing a program for use by or in conjunction with a system, device, processor or instruction-executing apparatus.

[0025] Similarly, for the purposes of this disclosure, the term "component" can encompass any tangible, physical, and non-transient device. For example, a component may be in the form of a hardware logic circuit incorporating custom VLSI circuits, gate arrays, or other integrated circuits, or it may consist of commercially available semiconductors including logic chips, transistors, or other discrete components, or of other suitable mechanical and / or electronic devices. Furthermore, a component may also be implemented in programmable hardware devices such as field-programmable gate arrays (FPGAs), programmable array logic, programmable logic devices, and so forth.Furthermore, a component may comprise one or more silicon-based integrated circuit devices, such as chips, dies, die layers, and packages, or other discrete electrical devices arranged in an electrical communication configuration with one or more other components via electrical conductors, e.g., on a printed circuit board (PCB) or the like. Accordingly, a module, as defined above, may in certain embodiments be embodied by a component or implemented as a component, and in some cases, the terms module and component may be used interchangeably.

[0026] When the term "circuit" is used here, it includes one or more electrical and / or electronic components that form one or more conductive paths allowing electric current to flow. A circuit can be configured as a closed-loop or open-loop system. In a closed-loop configuration, the circuit components may provide a feedback path for the electric current. In contrast, in an open-loop configuration, the circuit components can still be considered a circuit even if they do not include a feedback path for the electric current. For example, an integrated circuit can be considered a circuit regardless of whether the integrated circuit is connected to ground (as a feedback path for electric current) or not.In certain exemplary embodiments, a circuit may comprise a set of integrated circuits, a single integrated circuit, or a section of an integrated circuit. For example, a circuit may include custom VLSI circuits, gate arrays, logic circuits, and / or other forms of integrated circuits, and may include commercially available semiconductors such as logic chips, transistors, or other discrete devices. In another example, a circuit may comprise one or more silicon-based integrated circuit devices, such as chips, dies, die layers, and packages, or other discrete electrical devices, arranged in an electrical communication configuration with one or more other components via electrical conductors, for example, a printed circuit board (PCB).A circuit could also be implemented as a synthesized circuit in terms of a programmable hardware device such as a field-programmable gate array (FPGA), programmable array logic, and / or programmable logic devices, etc. In other exemplary embodiments, a circuit may comprise a network of non-integrated electrical and / or electronic components (with or without integrated circuit devices). Accordingly, a module, as defined above, may in certain embodiments be embodied by a circuit or implemented as such.

[0027] It is understood that the embodiments disclosed herein may, in some examples, include one or more microprocessors and certain stored computer program instructions that control the one or more microprocessors to implement, in conjunction with certain non-processor circuits and other elements, some, most, or all of the functions disclosed herein. Alternatively, some or all of the functions could be implemented by a state machine that does not include any stored program instructions, or in one or more application-specific integrated circuits (ASICs) or field-programmable gate arrays (FPGAs) in which each function, or some combinations of certain functions, are implemented as custom logic. A combination of these approaches may also be used.Furthermore, subsequent references to a “controller” are defined as including individual circuit components, an application-specific integrated circuit (ASIC), a microcontroller with control software, a digital signal processor (DSP), a field-programmable gate array (FPGA) and / or a processor with control software, or combinations thereof.

[0028] Furthermore, the terms "program," "software," "software application," and the like, as they may be used herein, refer to a sequence of instructions designed to be executed on a computer-implemented system. Accordingly, a "program," "software," "application," "computer program," or "software application" may include a subroutine, a function, a procedure, an object procedure, an object implementation, an executable application, an applet, a servlet, source code, object code, a shared library / dynamic load library, and / or any other sequence of specific instructions designed to be executed on a computer system.

[0029] Furthermore, the terms "couple," "coupled," or "coupled," where used herein, are to be understood as either a direct or indirect connection. Thus, if a first device couples to, or is coupled to, a second device, this connection may be made by a direct connection or by an indirect connection via other devices (or components) and connections.

[0030] Regarding the use of expressions such as "an embodiment," "one (1) embodiment," "an exemplary embodiment," "a particular embodiment," or similar terms, these terms are intended to indicate that a specific feature, structure, function, process, or property described in connection with the embodiment is included in at least one embodiment of the present disclosure. Therefore, formulations such as "in one (1) embodiment," "in an embodiment," "in an exemplary embodiment," etc., may refer to the same embodiment, but need not; they mean "one or more, but not all, embodiments," unless expressly stated otherwise.Furthermore, the terms "including," "with," "including," and variations thereof are used in an open manner and should therefore be interpreted as meaning "including, but not limited to..." unless explicitly stated otherwise. Moreover, an element preceded by "includes..." does not, without further qualification, preclude the existence of additional identical elements in the process, procedure, system, article, or facility in question that include the element.

[0031] The terms "a" and "the" also refer to "one or more" unless expressly stated otherwise. Furthermore, the phrase "at least one of A and B," as it may be used herein and / or in the following claims, where A and B are variables indicating a particular object or attribute, indicates a choice of A or B, or both A and B, similar to the phrase "and / or." If such a phrase contains more than two variables, it is defined as including only one of the variables, any one of the variables, any combination (or subcombination) of any one of the variables, and all of the variables.

[0032] Furthermore, the terms "approximately" or "about" are applied here to all numerical values, whether explicitly stated or not. These terms generally refer to a range of numerical values ​​that a person skilled in the art would consider equivalent to the stated values ​​(e.g., because they exhibit the same function or result). In certain cases, these terms may include numerical values ​​rounded to the nearest significant figure.

[0033] Furthermore, an enumeration of elements set forth herein does not imply that some or all of the enumerated elements are mutually exclusive and / or mutually inclusive, unless expressly stated otherwise. Moreover, the term "sentence," as used herein, is to be understood as meaning "one or more," and in the case of "sentences," it is to be understood as meaning a multiple of (or a multitude of) "one or more" and / or "one or more" according to set theory, unless expressly stated otherwise.

[0034] The following detailed description refers to the accompanying drawings, which form an integral part thereof. It is understood that the foregoing summary is for illustrative purposes only and is in no way intended to be limiting. In addition to the illustrative aspects, embodiments, and features described above, further aspects, embodiments, and features will become clear with reference to the subsequent drawings and the detailed description. The description of elements in each figure may refer to elements in subsequent figures. Identical reference numbers may refer to identical elements in the figures, including alternative exemplary embodiments of the same elements.

[0035] Fig. Figure 1A is a block diagram of an exemplary storage device. The storage device 100 can include one or more memory chips 108. The memory chip 108 includes a memory structure 126 of memory cells, such as an array of memory cells, a control circuit 110, and read / write circuits 128. The memory structure 126 is addressable via word lines through a row decoder 124 and via bit lines through a column decoder 132. The read / write circuits 128 include several capture blocks SB1, SB2, ... SBp (capture circuitry) and enable the parallel reading or programming of a side of memory cells. Typically, a control unit 122 is included in the same storage device 100 (e.g., a removable memory card) as the one or more memory chips 108.Commands and data are transmitted between the host 140 and the controller 122 via a data bus 120 and between the controller and the one or more memory chips 108 via lines 118.

[0036] The memory structure 126 can be two-dimensional or three-dimensional. The memory structure 126 can comprise one or more arrays of memory cells, including a three-dimensional array. The memory structure 126 can be a monolithic three-dimensional memory structure in which multiple memory layers are formed above (and not within) a single substrate, such as a wafer, without intervening substrates. The memory structure 126 can comprise any type of non-volatile memory monolithically formed in one or more physical layers of arrays of memory cells, which have an active region located above a silicon substrate. The memory structure 126 can be contained within a non-volatile memory device that includes circuitry associated with the operation of the memory cells, regardless of whether the associated circuitry is located above or within the substrate.

[0037] The control logic 110 works in conjunction with the read / write circuits 128 to perform memory operations on the memory structure 126 and includes a state machine 112, an on-chip address decoder 114, and a power control module 116. The state machine 112 provides chip-level control of memory operations.

[0038] A storage region 113, for example, can be provided for programming parameters. These parameters can include a program voltage, a bias voltage for the program voltage, position parameters specifying the positions of the memory cells, parameters for the thickness of the contact leads, a verification voltage, and / or similar parameters. The position parameters can specify the position of a memory cell within the entire array of NAND flash memory, the position of a memory cell within a specific group of NAND flash memory, the position of a memory cell in a specific plane, and / or similar parameters. The parameters for the thickness of the contact leads can specify the thickness of the contact leads, the substrate or material from which the contact leads are made, and / or similar parameters.

[0039] The on-chip address decoder 114 provides an address interface between the address used by the host or memory controller and the hardware address used by decoders 124 and 132. The power control module 116 controls the power and voltages supplied to the word lines and bit lines during memory operations. It can include drivers for word lines, SGS and SGD transistors, and source lines. The sampling blocks can include bit line drivers in one approach. An SGS transistor is a select-gate transistor at the source end of a NAND flash memory, and an SGD transistor is a select-gate transistor at the drain end of a NAND flash memory.

[0040] In some embodiments, some of the components can be combined. In various embodiments, one or more of the components (alone or in combination), which differ from the memory structure 126, can be considered as at least one control circuit configured to perform the operations described herein. The control switching logic can, for example, include one or a combination of control switching logic 110, state machine 112, decoders 114 / 132, power control module 116, acquisition blocks SBb, SB2, ..., SBp, read / write circuits 128, controller 122, and so on.

[0041] The control circuits can include a programming circuit configured to perform a program and check operation on a set of memory cells, wherein the one set of memory cells comprises memory cells assigned to represent one data state from a plurality of data states, and memory cells assigned to represent another data state from the plurality of data states; wherein the program and check operation comprises a plurality of program and check iterations; and wherein, in each program and check iteration, the programming circuit performs programming for the one word line, after which the programming circuit applies a check signal to the one word line. The control circuits can also include a counter circuit configured to determine the number of memory cells that have passed a verification test for the one data state.The control circuits may also include a determination circuit which is set up to determine, on the basis of an amount by which the counter reading exceeds a threshold, a specific program and test iteration from the multitude of program and test iterations in which a test for a different data state is performed for the memory cells allocated to represent a different data state.

[0042] Fig. 1B is, for example, a block diagram of an exemplary control circuit 150, which includes a programming circuit 151, a counting circuit 152 and a determination circuit 153.

[0043] The off-chip controller 122 can include a processor 122c, storage devices (memory) such as ROM 122a and RAM 122b, and an error correction code engine (ECC engine) 245. The ECC engine can correct a number of read errors caused when the upper tail of a Vth distribution becomes too high. However, in some cases, uncorrectable errors may occur. The techniques provided herein reduce the probability of uncorrectable errors.

[0044] The storage device(s) 122a, 122b contain code, such as a set of instructions, and the processor 122c is operable to execute the set of instructions and provide the functionality described herein. Alternatively or additionally, the processor can access code from a storage device 126a of the memory structure 126, such as a reserved area of ​​memory cells in one or more word lines. Code can be used, for example, by the controller 122 to access the memory structure 126, such as for programming, reading, and erasing operations. The code can include boot code and control code (e.g., a set of instructions). The boot code is software that initializes the controller 122 during a boot or start-up process and enables the controller 122 to access the memory structure 126.The code can be used by the controller 122 to control one or more memory structures 126. At startup, the processor 122c retrieves the boot code from the ROM 122a or the storage device 126a for execution. The boot code initializes the system components and loads the control code into RAM 122b. Once the control code is loaded into RAM 122b, it is executed by the processor 122c. The control code contains drivers for performing basic tasks such as controlling and allocating memory, prioritizing instruction processing, and controlling input and output ports.

[0045] In general, the control code may include instructions to perform the functions described herein, including the steps of the flowcharts explained below, and to provide the voltage waveforms, including those explained below.

[0046] In one embodiment, the host is a computing device (e.g., a laptop, desktop computer, smartphone, tablet, digital camera) that includes one or more processors, one or more processor-readable storage devices (RAM, ROM, flash memory, hard disk drive, solid-state memory) that store processor-readable code (e.g., software) for programming the one or more processors to perform the procedures described herein. The host may also include additional system memory, one or more input / output interfaces, and / or one or more input / output devices that communicate with the one or more processors.

[0047] Other types of non-volatile memory in addition to NAND flash memory can also be used.

[0048] Semiconductor memory devices include volatile memory devices, such as Dynamic Random Access Memory (DRAM) or Static Random Access Memory (SRAM), non-volatile memory devices, such as Resistive Random Access Memory (ReRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory (FRAM), and magnetoresistive random access memory (MRAM), and other semiconductor elements capable of storing information. Each type of memory device can have different configurations. For example, flash memory devices can be configured in either a NAND or NOR configuration.

[0049] The memory devices can be composed of passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include a resistance-switching storage element such as an anti-fuse or phase-change material and optionally a control element such as a diode or transistor. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements containing a charge storage region, such as a floating gate, conductive nanoparticles, or a dielectric charge storage material.

[0050] Multiple memory elements can be arranged in series or such that each element is individually accessible. As a non-restrictive example, flash memory devices in a NAND configuration (NAND memory) typically contain memory elements connected in series. A NAND chain is an example of a set of transistors connected in series, comprising memory cells and SG transistors.

[0051] A NAND memory array can be configured to consist of multiple memory chains, where each chain comprises several memory elements sharing a single bit line and accessed as a group. Alternatively, memory elements can be configured so that each element is individually accessible, such as a NOR memory array. NAND and NOR memory configurations are examples, and memory elements can be configured in other ways. The semiconductor memory elements, which are placed in and / or on top of a substrate, can be arranged in two or three dimensions, such as a two-dimensional or three-dimensional memory structure.

[0052] In a two-dimensional memory structure, the semiconductor memory elements are arranged in a single plane or a single memory device plane. Typically, in a two-dimensional memory structure, memory elements are arranged in a plane (e.g., in a plane in the xy direction) that extends substantially parallel to a major face of a substrate that supports the memory elements. The substrate can be a wafer over or in which the layer of memory elements is formed, or it can be a support substrate that is attached to the memory elements after they have been formed. As a non-restrictive example, the substrate can include a semiconductor, such as silicon.

[0053] The memory elements can be arranged in an ordered array at the individual storage device level, such as in a multitude of rows and / or columns. However, the memory elements can also be arranged in irregular or non-orthogonal configurations. Each memory element can have two or more electrodes or contact lines, such as bit lines and word lines.

[0054] A three-dimensional storage array is arranged such that storage elements occupy multiple levels or multiple storage device levels, forming a structure in three dimensions (i.e. in the x, y, and z directions, with the z direction being essentially perpendicular and the x and y directions being essentially parallel to the main surface of the substrate).

[0055] As a non-restrictive example, a three-dimensional storage structure can be arranged vertically as a stack of multiple two-dimensional storage device levels. As another non-restrictive example, a three-dimensional storage array can be arranged as multiple vertical columns (e.g., columns extending substantially perpendicular to the main surface of the substrate, i.e., in the y-direction), with each column containing multiple storage elements. The columns can be arranged in a two-dimensional configuration, e.g., in an xy-plane, resulting in a three-dimensional arrangement of storage elements with elements on multiple vertically stacked storage levels. Other configurations of storage elements in three dimensions can also form a three-dimensional storage array.

[0056] As a non-restrictive example, in a three-dimensional arrangement of NAND chains, the memory elements can be interconnected to form a NAND chain within a single horizontal (e.g., xy) memory device plane. Alternatively, the memory elements can be interconnected to form a vertical NAND chain spanning multiple horizontal memory device planes. Other three-dimensional configurations can be considered, with some NAND chains containing memory elements within a single memory plane, while other chains containing memory elements spanning multiple memory planes. Three-dimensional memory arrays can also be configured in a NOR configuration and in a ReRAM configuration.

[0057] Typically, in a monolithic three-dimensional storage array, one or more storage device layers are formed on top of a single substrate. Optionally, the monolithic three-dimensional storage array can also have one or more storage layers at least partially within the single substrate. As a non-restrictive example, the substrate can be a semiconductor, such as silicon. In a monolithic three-dimensional array, the layers that form the individual storage device layers of the array are usually formed on top of the layers of the underlying storage device layers of the array. However, layers of adjacent storage device layers in a monolithic three-dimensional storage array can be shared, or there can be intermediate layers between storage device layers.

[0058] Two-dimensional arrays can also be formed separately and then packed together to create a non-monolithic, multi-layered memory device. For example, non-monolithic stacked memories can be constructed by forming memory layers on separate substrates and then stacking the memory layers on top of each other. The substrates can be thinned or removed from the memory device layers before stacking, but because the memory device layers are initially formed on separate substrates, the resulting memory arrays are not monolithic three-dimensional memory arrays. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) can be formed on separate chips and then packed together to form a stacked-chip memory device.

[0059] Fig. Figure 2 illustrates schematic views of three types of memory architectures that use staggered memory chains. For example, reference number 201 shows a schematic view of a first exemplary memory architecture, reference number 203 shows a schematic view of a second exemplary memory architecture, and reference number 205 shows a schematic view of a third exemplary memory architecture. In some embodiments, as shown, the memory architecture may include an array of staggered NAND chains.

[0060] Fig. Figure 2 illustrates blocks 200, 210 of memory cells in an exemplary two-dimensional configuration of memory array 126. Fig. 1. The memory array 126 can include many such memory blocks 200, 210. Each example block 200, 210 includes a number of NAND chains and corresponding bit lines, e.g., BL0, BL1, ..., which are shared by the blocks. Each NAND chain is connected at one end to a drain-side select gate (SGD), and the control gates of the drain-select gates are connected via a common SGD line. The NAND chains are connected at their other end to a source-side select gate (SGS), which in turn is connected to a common source line 220. Sixteen word lines, for example, WL0-WL15, extend between the SGDs and the SGSs. In some cases, dummy word lines, which do not contain user data, may also be used in the memory array alongside the select-gate transistors. Such dummy word lines can shield the marginal data word line from certain marginal effects.

[0061] One type of non-volatile memory that can be provided in the memory array is floating-gate memory, such as the type described in Fig. 3A and Fig. 3B is shown. However, other types of non-volatile memory can also be used. As discussed in more detail below, another example, shown in Fig. 4A and Fig. Figure 4B shows a charge-trapping memory cell that uses a non-conductive dielectric material instead of a conductive floating gate to store charge non-volatilely. A three-layer dielectric of silicon oxide, silicon nitride, and silicon oxide (“ONO”) is positioned between a conductive control gate and the surface of a semiconducting substrate above the memory cell channel. The cell is programmed by injecting electrons from the cell channel into the nitride, where they are trapped and stored in a confined area. This stored charge then modifies the threshold voltage of a section of the cell channel in a detectable manner. The cell is erased by injecting hot holes into the nitride.A similar cell can be provided in a split-gate configuration, where a doped polysilicon gate extends over a section of the memory cell channel, thereby forming a separate selection transistor.

[0062] Another approach uses NROM cells. Two bits, for example, are stored in each NROM cell, where a dielectric ONO layer extends across the channel between source and drain diffusion. The charge for one data bit is localized in the dielectric layer adjacent to the drain, and the charge for the other data bit is localized in the dielectric layer adjacent to the source. Multi-state data storage is achieved by separately reading binary states from the physically separated charge storage areas within the dielectric. Other types of non-volatile memory are also known.

[0063] Fig. Figure 3A illustrates a cross-section of exemplary floating-gate memory cells 300, 310, and 320 in NAND chains. In this figure, the direction of a bit line or NAND chain runs inwards, and the direction of a word line runs from left to right. As an example, the word line 324 extends across NAND chains that enclose the respective channel regions 306, 316, and 326. Memory cell 300 includes a control gate 302, a floating gate 304, a tunnel oxide layer 305, and the channel region 306. Memory cell 310 includes a control gate 312, a floating gate 314, a tunnel oxide layer 315, and the channel region 316. Memory cell 320 includes a control gate 322, a floating gate 321, a tunnel oxide layer 325, and the channel region 326. Each memory cell 300, 310, 320 is located in a separate NAND chain. An interpolar dielectric (IPD) layer 328 is also illustrated.Control gates 302, 312, and 322 are sections of the word line. A cross-sectional view along the contact line connector 329 is shown in [reference]. Fig. 3B provided.

[0064] The control gate 302, 312, 322 surrounds the floating gate 304, 314, 321, thereby increasing the surface contact area between the control gate 302, 312, 322 and the floating gate 304, 314, 321. This results in a higher IPD capacity, leading to a higher coupling ratio, which facilitates programming and erasing. However, as NAND flash memory devices are miniaturized, the distance between adjacent cells 300, 310, 320 decreases, leaving almost no space between two adjacent floating gates 302, 312, 322 for the control gate 302, 312, 322 and the IPD layer 328.

[0065] As an alternative, as in Fig. 4A and Fig. Figure 4B shows the flat or planar memory cell 400, 410, 420 developed, in which the control gate 402, 412, 422 is flat or planar; that is, it does not enclose the floating gate and only makes contact with the charge storage layer 428 from above. In this case, a tall floating gate is not advantageous. Instead, the floating gate is made significantly thinner. Furthermore, the floating gate can be used for charge storage, or a thin charge trap layer can be used to trap charge. This approach can avoid the problem of ballistic electron transport, in which an electron can migrate through the floating gate during programming after tunneling through the tunnel oxide.

[0066] Fig. Figure 4A shows a cross-section of exemplary charge-trapping memory cells 400, 410, 420 in NAND chains. The view is in a word-direction direction of memory cells 400, 410, 420, which includes a flat control gate and charge-trapping regions as a two-dimensional example of memory cells 400, 410, 420 in the memory array 126. Fig. 1. The charge-capture memory can be used in a NOR and NAND flash memory device. In this technology, an insulator such as a SiN film is used to store electrons, in contrast to a floating-gate MOSFET technology, which uses a conductor such as doped polycrystalline silicon to store electrons. For example, a word line 424 extends across NAND chains, enclosing respective channel regions 406, 416, and 426. Sections of the word line provide control gates 402, 412, and 422. Below the word lead are an IPD layer 428, charge-trapping layers 404, 414, 421, polysilicon layers 405, 415, 425, and tunnel layers 409, 407, 408. Each charge-trapping layer 404, 414, 421 extends continuously in its respective NAND chain. The flat configuration of the control gate allows for a thinner profile than a floating gate.Furthermore, the memory cells can be placed closer together.

[0067] Fig. 4B illustrates a cross-section of the structure of Fig. 4A along the contact line connector 429. The NAND chain 430 includes an SGS transistor 431, exemplary memory cells 400, 433, ... 435, and an SGD transistor 436. Through-holes in the IPD layer 428 in the SGS and SGD transistors 431 and 436 enable communication between the control gate layers 402 and the floating gate layers. The control gate 402 layers and floating gate layers can be made of polysilicon, and the tunnel oxide layer can be made of silicon oxide, for example. The IPD layer 428 can be a stack of nitrides (N) and oxides (O), as in a NONON configuration.

[0068] The NAND chain can be formed on a substrate containing a p-type substrate region 455, an n-type well 456, and a p-type well 457. N-type source / drain diffusion regions sd1, sd2, sd3, sd4, sd5, sd6, and sd7 are formed in the p-type well. A channel voltage, Vch, can be applied directly to the channel region of the substrate.

[0069] Fig. Figure 5 illustrates an example block diagram of the data acquisition block SB1 from Fig. 1. In one approach, a data acquisition block has multiple acquisition circuits. Each acquisition circuit is assigned data storage. For example, acquisition circuits 550a, 551a, 552a, and 553a are assigned to data storage 550b, 551b, 552b, and 553b, respectively. In this approach, different subsets of bit lines can be sampled using different acquisition blocks. This allows the processor load associated with the acquisition circuits to be distributed and handled by a separate processor in each acquisition block. For example, the acquisition circuit controller 560 in SB1 can communicate with the set of acquisition circuits and storage. The acquisition circuit controller 560 can include a preload circuit 561, which provides each acquisition circuit with a voltage for setting a preload voltage.In one possible approach, the voltage for each acquisition circuit is provided independently, for example, via the data bus and a local bus. In another possible approach, a common voltage is provided to each acquisition circuit simultaneously. The acquisition circuit controller 560 can also include a preload circuit 561, a memory 562, and a processor 563. The memory 562 can store codes that can be executed by the processor to perform the functions described herein. These functions can include reading the hold memories 550b, 551b, 552b, 553b associated with the acquisition circuits 550a, 551a, 552a, 553a, setting bit values ​​in the hold memories, and providing voltages to set preload levels in the acquisition nodes of the acquisition circuits 550a, 551a, 552a, 553a.Further example details for the control of the detection circuit 560 and the detection circuits 550a, 551a, 552a, 553a are provided below.

[0070] In some embodiments, a memory cell may include a flag register, which includes a set of hold memories for storing flag bits. In some embodiments, a set of flag registers may correspond to a set of data states. In some embodiments, one or more flag registers may be used to control a type of verification technique for verifying memory cells. In some embodiments, the output of a flag bit may modify the associated logic of the device, such as the address decoding switching logic, to select a specific block of cells. A bulk operation (such as an erase operation) may be performed using the flags set in the flag register, or a combination of the flag register with the address register, as in implicit addressing, or alternatively, by direct addressing using the address register alone.

[0071] Fig. Figure 6A is a perspective view of a set of blocks 600 in an exemplary three-dimensional configuration of the memory array 126. Fig. 1. The substrate contains exemplary memory cell (memory element) blocks BLK0, BLK1, BLK2, and BLK3, and a peripheral region 604 with switching logic for use by blocks BLK0, BLK1, BLK2, and BLK3. For example, the circuits can include voltage drivers 605, which can be connected to control gate layers of blocks BLK0, BLK1, BLK2, and BLK3. In one approach, control gate layers at a common level in blocks BLK0, BLK1, BLK2, and BLK3 are jointly controlled. The substrate 601 can also support switching logic beneath blocks BLK0, BLK1, BLK2, and BLK3, along with one or more lower metal layers structured in conductor tracks to transmit signals from the switching logic. Blocks BLK0, BLK1, BLK2, and BLK3 are formed in an intermediate region 602 of the memory device.In an upper region 603 of the memory device, one or more upper metal layers are structured in conductive traces to carry signals from the switching logic. Each block BLK0, BLK1, BLK2, BLK3 has a stacked memory cell area, with alternating levels of the stack representing word lines. In one possible approach, each block BLK0, BLK1, BLK2, BLK3 has opposite stepped sides from which vertical contacts extend upward to an upper metal layer to connect to conductive traces. While four blocks BLK0, BLK1, BLK2, BLK3 are illustrated by way of example, two or more blocks extending in the x and / or y direction can be used.

[0072] In one possible approach, the length of the plane in the x-direction represents a direction in which signal paths extend to word lines in one or more of the upper metal layers (a word line or SGD line direction), and the width of the plane in the y-direction represents a direction in which signal paths extend to bit lines in one or more of the upper metal layers (a bit line direction). The z-direction represents a height of the storage device.

[0073] Fig. Figure 6B illustrates an exemplary cross-section of a section from one of the blocks BLK0, BLK1, BLK2, BLK3. Fig. 6A. The block has a stack 610 consisting of alternating conductive and dielectric layers. In this example, the conductive layers have two SGD layers, two SGS layers, and four dummy word line layers DWLD0, DWLD1, DWLS0, and DWLS1, in addition to the data word line layers (word lines) WLL0–WLL10. The dielectric layers are designated DL0 to DL19. Furthermore, regions of the stack 610 are illustrated that contain the NAND chains NS1 and NS2. Each NAND chain includes a memory hole 618, 619, which is filled with materials that form memory cells adjacent to the word lines. A region 622 of the stack 610 is in Fig. 6D is shown in more detail and discussed in more detail below.

[0074] The 610 stack includes a substrate 611, an insulating layer 612 on the substrate 611, and a section of a source line SL. NS1 has a source end 613 on a bottom surface 614 of the stack and a drain end 615 on a top surface 616 of the stack 610. Contact line connectors (e.g., slots, such as metal-filled slots) 617, 620 can be periodically provided across the stack 610 as connections extending through the stack 610, such as for connecting the source line to a specific contact line above the stack 610. The contact line connectors 617, 620 can be used in forming the word lines and subsequently filled with metal. A section of a bit line BL0 is also illustrated. A conductive via 621 connects the drain end 615 to BL0.

[0075] Fig. Figure 6C illustrates a graphical representation of the memory hole diameter in the stack of Fig. 6B. The vertical axis is on the stack of Fig. 6B is aligned and illustrates a width (wMH), e.g., the diameter of memory holes 618 and 619. The word line layers WLL0-WLL10 of Fig. 6A are repeated as an example and are located at the respective heights z0-z10 in the stack. In such a storage device, the storage holes etched through the stack have a very high aspect ratio. For example, a depth-to-diameter ratio of about 25 to 30 is common. The storage holes may have a circular cross-section. Due to the etching process, the storage hole width can vary along the length of the hole. Typically, the diameter decreases from top to bottom in the storage hole. That is, the storage holes taper, narrowing at the bottom of the stack. In some cases, there is a slight narrowing at the top of the hole near the select gate, so the diameter becomes somewhat wider before decreasing from top to bottom of the storage hole.

[0076] Due to the uneven width of the memory hole, the programming speed, including the programming edge and erase speed of the memory cells, can vary depending on their position along the memory hole, e.g., their height in the stack. With a smaller memory hole diameter, the electric field across the tunnel oxide is relatively stronger, resulting in relatively higher programming and erase speeds. One approach is to define groups of adjacent word lines for which the memory hole diameter is similar, e.g., within a defined diameter range, and to apply an optimized verification scheme to each word line in a group. Different groups may have differently optimized verification schemes.

[0077] Fig. Figure 6D illustrates a close-up of region 622 of stack 610. Fig. 6B. Memory cells are formed at the various levels of the stack at the intersection of a word line layer and a memory hole. In this example, the SGD transistors 680, 681 are provided above the dummy memory cells 682, 683 and a data memory cell MC. A series of layers can be deposited along the side wall (SW) of the memory hole 630 and / or within each word line layer, for example, using atomic layer deposition. For example, each column (e.g., the column formed by the materials within a memory hole 630) can include a charge-trapping layer or film 663 such as SiN or another nitride, a tunnel layer 664, a polysilicon body or channel 665, and a dielectric core 666. A word conduction layer can include a blocking oxide / block high-k material 660, a metal barrier 661, and a conductive metal 662 such as tungsten as a control gate.For example, control gates 690, 691, 692, 693, and 694 are provided. In this example, all layers except the metal layer are provided in memory hole 630. In other approaches, some of the layers may be located in the control gate layer. Additional columns are similarly formed in the various memory holes. A column can form a columnar active area (AA) of a NAND flash memory.

[0078] When a memory cell MC is programmed, electrons are stored in a section of the charge-trapping layer 663 that is assigned to the memory cell MC. These electrons are drawn into the charge-trapping layer 663 from channel 665 and through tunneling layer 664. The Vth of a memory cell MC is increased proportionally to the amount of stored charge. During an erase operation, the electrons return to channel 665.

[0079] Each of the storage holes 630 can be filled with a variety of ring-shaped layers, comprising a blocking oxide layer, a charge-trapping layer 663, a tunneling layer 664, and a channeling layer 665. A core region of each of the storage holes 630 is filled with a body material, and the variety of ring-shaped layers is located between the core region and the word line in each of the storage holes 630.

[0080] The NAND chain can be viewed as a floating-body channel 665, since the length of the channel 665 is not formed on a substrate. Furthermore, the NAND chain is provided by a multitude of word conduction layers arranged on top of each other in a stack and separated from each other by dielectric layers.

[0081] Fig. Figure 7A shows a schematic top view of a memory array 700 with multiple memory holes 722, which may be vertical memory cell strands as described herein, and multiple dummy holes 705 that do not require a complete memory structure. A shallow trench etch or shallow etch feature (SHE) 710 extends through a plurality of word lines (e.g., five) but not completely through the chip to electrically isolate adjacent strands from one another. The SHE extends directly through a group of aligned dummy holes 705, thus preventing these dummy holes 705 from storing data or otherwise being functional memory cells.

[0082] Referring now to Fig. 8A and Fig. There are no dummy holes in 8B. Unlike the 700 memory architecture from Fig. 7A and Fig. In 7B, the SHE 810 is located in a gap between two adjacent rows of memory cells 825 and overlaps with memory holes 825, creating a working strand that has a trench etched into at least one side of the upper SGD switch of the working memory strand, shown here as memory holes 825. This configuration significantly improves the yield and memory density, as all memory holes 822 and 825 are functional, meaning fewer memory holes are wasted.

[0083] Unlike the fully circular memory holes 822, the memory holes 825 and the SGD switches, which are partially intersected by the SHE 810, have a semicircular shape, which can be either a full semicircle or more or less than a semicircle. In some cases, the memory holes 825 and SGD switches may be fewer than semicircles on one side of the SHE 810 and more than semicircles on the other side of the SHE 810.

[0084] Memory holes 822 and 825 are connected to multiple bit lines 830 (in Fig. 8A (designated as bit lines 0-7) are connected. For simplicity, only eight bit lines 830 are shown. The bit lines 830 extend across the memory holes and are connected to selected memory holes via connection points. The memory holes in each strand are also connected at one end to an SGD switch and at the other end to an SGS switch. The SHE trench 810 can be etched into a section of the SGD switch.

[0085] At the end of a successful programming process (with verification), the threshold voltages of the memory cells should be within one or more distributions of threshold voltages for programmed memory cells or within a distribution of threshold voltages for erased memory cells, as appropriate. Fig. Figure 9 illustrates exemplary distributions of the threshold voltage Vt corresponding to the data states for the memory cell array when each memory cell stores three data bits. However, other embodiments may use more or fewer than three data bits per memory cell. Fig. Figure 9 shows eight distributions of the threshold voltage Vt, corresponding to an extinguishing state and programmed states AG. In one embodiment, the threshold voltages in the extinguishing state are negative, and the threshold voltages in the programmed states AG are positive.

[0086] However, the threshold voltages in one or more of the programmed states AG can be negative. Thus, in one embodiment, at least VrA is negative. Other voltages such as VvA, VrB, VvB, etc., can also be negative.

[0087] Between each of the data states, there are read reference voltages that are used to read data from memory cells. For example, Fig. 9. The read reference voltage VrA is defined between the erase state and the A-state, and VrB between the A-state and B-state. By testing whether the threshold voltage of a given memory cell is above or below the respective read reference voltages, the system can determine the data state of the memory cell.

[0088] Verification reference voltages are present at or near the lower edge of each programmed state. For example, Fig. 9 VvA for state A and VvB for state B. When memory cells are programmed to a given state, the system tests whether these memory cells have a threshold voltage that is greater than or equal to the verification reference voltage.

[0089] As discussed above and with renewed reference to Fig. 8A and Fig. 8B, the SHE trench 810 can be etched into a section of the SGD switch of the drain-side select-gate SGD switch. Ideally, the SHE cut or trench 810 is only etched down to the drain-side select-gate SGD layer (i.e., SGD1 in Fig. 6D). However, due to process (etching) variation, it can be extremely difficult to consistently and precisely cut down to the drain-side selection gate SGD layer; some chips are cut down to a first dummy word line or layer DD0 (i.e., DWLD0 in ). Fig. 6D) cut and some even up to a second dummy word line or layer DD1 (i.e. DWLD1 in Fig. 6D). If the SHE cut or trench 810 is closer to the data word lines (i.e., deeper), data retention will be significantly worse. This is due to the physical damage induced by SHE etching / cleaning of memory cells near the physical SHE bottom. Fig. Figure 10 shows a cross-sectional plan view of storage holes (MHs) (hatched circles in Fig. 10), which is located at a drain-side selection gate SGD layer (leftmost section of Fig. 10) and a marginal word-management layer (section on the far right of Fig. 10) are included. Rows of storage holes with semicircular drain-side selection gates (SC-SGD) are indicated by dashed boxes, while the other storage holes do not include semicircular drain-side selection gates (SC-SGD). Fig. Figure 11 shows threshold voltage distributions and corresponding data or memory states before (diagram, denoted as 850) and after high-temperature data retention (HTDR) tests (diagram, denoted as 852) for an exemplary memory device. As shown, memory cells of memory holes without semicircular drain-side select gates (SC-SGD) (i.e., full-circle drain-side select gates (FC-SGD) and associated edge word line exhibit comparatively better data retention, while memory cells of memory holes with semicircular drain-side select gates (SC-SGD) and associated edge word line exhibit comparatively worse data retention.In other words, memory cells of memory holes with semicircular drain-side selection gates (SC-SGD) lose more charge due to the additional SHE-RIE damage than memory cells of memory holes without semicircular drain-side selection gates (SC-SGD), but only for the marginal word line.

[0090] One solution to the data retention problems arising from the depth of SHE Trench 810 is to incorporate one or more additional dummy word line layers to prevent this edge word line data retention loss. However, such additional dummy word lines increase processing costs. Another solution is to implement a plasma-induced oxidation (PIO) process to repair RIE damage. This has proven effective in mitigating edge word line data retention problems, but it is not a complete fix, as some states (e.g., the F / G state) may still be contaminated at best.

[0091] Consequently, this includes a storage device (e.g., storage device 100 of Fig. 1A) described the memory cells (e.g. the data memory cell MC and the dummy memory cells 682, 683 of Fig. 6D) includes one of a variety of word lines (e.g., the data word line layers (word lines) WLL0-WLL10 of Fig. 6B or WLL10 from Fig. 6D) are connected, which have at least one marginal word line (e.g. WLL10 of Fig. 6B) and a variety of other data word lines (WLL0-WLL9 of Fig. 6B). The memory cells are in chains (e.g., NAND chains NS1 and NS2 of Fig. 6B) arranged and configured to maintain a threshold voltage Vt or Vth, which indicates a variety of memory or data states ( Fig. 9) corresponds. The chains are organized in series. The storage device also includes a control circuit or means (e.g., one or any combination of the control circuit 110, the decoders 114 / 132, the power control module 116, the acquisition blocks SBb, SB2, ..., SBp, the read / write circuits 128, the control 122 of Fig. 1A, the control circuit 150 of Fig. 1B and / or the detection circuit control 560 from Fig. 5 and so on), which are coupled to the plurality of word lines and the chains. The control means is configured to identify the at least one edge word line. The control means is also configured to program the memory cells of the chains in their respective rows and is associated with the at least one edge word line such that a changed distribution of the threshold voltage Vt for one or more of the plurality of data states, compared to the memory cells of the chains, is not present in their respective rows and is not associated with the at least one edge word line during a programming operation. Thus, the objective of the memory device and method disclosed herein is to implement a novel edge word line programming technique that can help to mitigate edge word line data storage problems without adding additional dummy word line layers.According to the disclosure and as discussed below, the storage device and method disclosed herein can program higher data states to a higher threshold voltage Vt in selective series (e.g., semicircular series) for the edge word line, which allows a sufficient threshold voltage Vt margin for higher states according to HTDR.

[0092] With renewed reference to Fig. 6B, for example, encompasses the multitude of word lines (e.g., word line layers (word lines) WLL0-WLL10 of Fig. 6B) and a variety of dielectric layers (e.g. DL0-DL19 of Fig. 6B) horizontally and overlap each other alternately in a stack (e.g. stack 610) and the chains (e.g. NAND chains NS1 and NS2 of Fig. 6B) extend vertically through the stack. The memory cells are connected in series between at least one drain-side select-gate SGD transistor on a drain side of each of the chains (e.g., at SGD0 or SGD1 layers) and are connected to one of a plurality of bit lines (e.g., BL0 of Fig. 6B) and at least one source-side selection gate transistor on a source side of each of the chains (e.g., at SGS0 or SGS1 layers) connected and to a source line (e.g., SL of Fig. 6B). The at least one edge word line is arranged vertically above the multitude of other data word lines and is directly adjacent to the at least one drain-side selection-gate SGD transistor.

[0093] With renewed reference to Fig. The threshold voltage Vt, which is possible for each of the memory cells, spans a threshold window of 900. Each of the memory cells is configured to store a multitude of bits. The multitude of data states includes a cleared state (e.g., the cleared state in). Fig. 9) at a first end 902 of the threshold window 900 and a multitude of programmed data states (e.g. states A, B, C, D, E, F and G of Fig. 9) each corresponding to a threshold voltage Vt that is higher than the threshold voltage Vt associated with the erased state. The multitude of programmed data states includes a highest data state (e.g., state G of Fig. 9) at a second end 904 of the threshold window opposite the first end 902 and is assigned to the threshold voltage Vt which is higher than the threshold voltage Vt which is assigned to the erased state and at least one other of the plurality of programmed data states.

[0094] The rows of chains can include full-circle rows and semi-circle rows, which have storage holes and form chains that are partially cut by the shallow hole etching (SHE) 810, which extends vertically into the stack. Thus, from one point of view, the respective rows are the semi-circle rows. Fig. Figure 12 shows distributions of threshold voltage Vt of memory cells, illustrating an exemplary precompensation by programming memory cells that are only in semicircular rows for the edge word line immediately after programming and after a high-temperature data retention test to the highest data state (e.g., state G) to a higher threshold voltage Vt. Thus, the control mechanism is further configured to apply each of a multitude of program pulses to the at least one edge word line, the magnitude of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed for the highest data state and assigned to the full-circle rows reach a first highest verification voltage level GV_FC (low) for the highest data state.The control mechanism is also configured to apply each of a multitude of program pulses to the at least one edge word line, the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed to the highest data state associated with the semicircular rows and the at least one edge word line reach a second highest verification voltage level GV_SC (high) for the highest data state. The second highest verification voltage level GV_SC (high) is higher than the first highest verification voltage level GV_FC (low).Furthermore, the control mechanism is configured to simultaneously apply a blocking bit line voltage to one of the plurality of bit lines coupled to the chains of the full-circle rows while the memory cells associated with the at least one edge word line are being programmed, in order to slow down the programming of the memory cells in the chains associated with the full-circle rows, while a selection bit line voltage is applied to one of the plurality of bit lines coupled to the chains of the semicircle rows while the memory cells associated with the at least one edge word line are being programmed, in order to promote the programming of the memory cells in the chains associated with the semicircle rows. Thus, the memory holes or chains with semicircle SGD are programmed to the highest data state (e.g.,The G-state is pre-compensated to a higher threshold voltage Vt only in semicircular arrays for the edge word line. This technique is effective if the edge word line problem is not too severe. For example, if only semicircular G-state memory cells are contaminated, this technique is effective. It should be noted that programming full-circle arrays with GV_FC (low) and programming semicircular arrays with GV_SC (high) can occur within the same programming sequence or in different programming sequences.

[0095] Here too, the rows can include full circle rows and semicircular rows. From one perspective, the respective rows are both semicircular rows and full circle rows. Fig. Figure 13 shows distributions of threshold voltage Vt of memory cells, illustrating a further exemplary precompensation by programming memory cells that are set to a higher threshold voltage Vt for both semicircular and full-circular arrays for the edge word line immediately after programming and after a high-temperature data retention test for the highest data state (e.g., state G). Therefore, the control mechanism is further configured to apply each of a multitude of program pulses to the multitude of other data word lines, the magnitude of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed for the highest data state and associated with the multitude of other data word lines reach a low highest verification voltage level GV (low) for the highest data state.The control mechanism is also designed to apply each of a multitude of program pulses to the at least one edge word line, the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed to the highest data state associated with the at least one edge word line reach a high highest verification voltage level GV(higher) for the highest data state. The high highest verification voltage level GV(higher) is greater than the low highest verification voltage level GV(lower). Thus, all memory holes or chains with semicircular and full-circle SGD on the edge word line are pre-compensated by programming the highest data state (e.g., G-state) to a higher threshold voltage Vt. Such a technique is effective if the edge word line problem is not too severe.This technique is effective if, for example, only semicircular G-state memory cells are contaminated.

[0096] As explained above, the series can include full circle series and semicircular series. From one perspective, the respective series are both the semicircular series and the full circle series. The plurality of bits includes three bits, and the total set of the plurality of data states is eight. Thus, the plurality of programmed data states (e.g., states A, B, C, D, E, F, and G of) includes Fig. 9) in order of increasing magnitude of the threshold voltage Vt, a first data state (e.g. state A of Fig. 9) and a second data state (e.g., state B of Fig. 9) and a third data state (e.g., state C of Fig. 9) and a fourth data state (e.g., state D of Fig. 9) and a fifth data state (e.g., state E of Fig. 9) and a sixth data state (e.g., state F of Fig. 9) and a seventh data state (e.g., state G of Fig. 9) one. The highest data state is the seventh data state. Fig. Figure 14 shows distributions of threshold voltage Vt of memory cells, illustrating a further exemplary precompensation by programming memory cells that are programmed to a higher threshold voltage Vt for both semicircular and full-circle rows for the edge word line immediately after programming and after a high-temperature data retention test for the seventh data state (e.g., state G), the sixth data state (e.g., state F), and the fifth data state (e.g., state E).Therefore, the control mechanism for the memory cells assigned to the multitude of other data word lines, which are programmed to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state during the programming process, is further configured to apply each of a multitude of program pulses to the multitude of other data word lines, the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells assigned to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, and the sixth data state, respectively, are reached.The seventh data state can be programmed to reach one of a low first voltage level for the first data state, a low second voltage level for the second data state, a low third voltage level for the third data state, a low fourth voltage level for the fourth data state, a low fifth voltage level EV (low) for the fifth data state, a low sixth voltage level FV (low) for the sixth data state, and a low seventh voltage level GV (low) for the seventh data state.For the memory cells that are assigned to the at least one edge word line and are programmed to one of the first data states, the second data states, the third data states, and the fourth data states during the programming process, the control means is arranged to apply each of the plurality of program pulses, the size of which gradually increases, to the plurality of other data word lines to each of the plurality of loops during the programming process, until the memory cells that are programmed to one of the first data states, the second data states, the third data states, and the fourth data states each reach one of the low first voltage levels for the first data state, one of the low second voltage levels for the second data state, one of the low third voltage levels for the third data state, and one of the low fourth voltage levels for the fourth data state.For the memory cells that are assigned to the at least one edge word line and are programmed during the programming process to one of the fifth data state, the sixth data state, and the seventh data state, the control means is arranged to apply each of the plurality of program pulses, the size of which gradually increases, to the plurality of other data word lines during the programming process until the memory cells that are programmed to one of the fifth data state, the sixth data state, and the seventh data state, respectively, each reach one of a high fifth voltage level EV (higher) for the fifth data state, a high sixth voltage level FV (higher) for the sixth data state, and a high seventh voltage level GV (higher) for the seventh data state.The high fifth voltage level EV (higher) is greater than the low fifth voltage level EV (low), the high sixth voltage level FV (higher) is greater than the low sixth voltage level FV (low), and the high seventh voltage level GV (higher) is greater than the low seventh voltage level GV (low). Thus, all memory holes or chains with semicircular and full-circle SGD on the edge word line are precompensated by programming the seventh data state (e.g., G-state), the sixth data state (e.g., F-state), and the fifth data state (e.g., E-state) to a higher threshold voltage Vt. Although only three of the states are shown as precompensated, it should be noted that memory cells programmed to other states can also be precompensated.

[0097] Here too, the respective rows are both the semicircular rows and the full circle rows. Fig. Figure 15 shows distributions of threshold voltage Vt of memory cells, illustrating a further exemplary precompensation by programming memory cells that are configured for both semicircular and full-circular arrays for the edge word line immediately after programming and after a high-temperature data retention test to the seventh data state (e.g., state G), the sixth data state (e.g., state F), and the fifth data state (e.g., state E) to a narrower distribution of the threshold voltage Vt. Thus, the control mechanism for the memory cells that are assigned to the multitude of other data word lines and are programmed to one of the multitude of programmed data states during the programming process is still configured to apply a multitude of program pulses to the multitude of other data word lines.The size of the multitude of program pulses increases stepwise in each of the multitude of loops by a first program step voltage DVPGM (large). For the memory cells that are assigned to the at least one edge word line and are programmed to the third data state, the second data state, and the first data state during the programming process, the control device is also configured to apply a multitude of program pulses to the at least one edge word line, the size of the multitude of program pulses increasing stepwise in each of the multitude of loops by the first program step voltage DVPGM (large).For the memory cells assigned to the at least one edge word line and programmed during the programming process to the seventh, sixth, fifth, and fourth data states, the control mechanism is configured to apply the plurality of program pulses to the at least one edge word line. The magnitude of the plurality of program pulses increases stepwise in each of the plurality of loops by a second program step voltage, which is smaller than the first program step voltage DVPGM (large). Thus, all memory holes or chains with semicircular and full-circle SGDs on the edge word line are pre-compensated by programming the seventh data state (e.g., G-state), the sixth data state (e.g., F-state), and the fifth data state (e.g., E-state) using a reduced program step voltage (DVPGM) to narrower distributions of the threshold voltage Vt.Such compensation using narrower distributions of the threshold voltage Vt can lead to a negligible increase in programming time (i.e., Tprog can be slower), but only for one word line (e.g., the edge word line). While only three of the states are shown as precompensated, it should be noted that memory cells programmed to other states can also be precompensated.

[0098] Fig. Figure 16 shows an example of a method for operating a storage device. As discussed above, the storage device (e.g., the storage device 100 of Fig. 1A) Memory cells (e.g. the data memory cell MC and dummy memory cells 682, 683 of Fig. 6D) which are connected to one of a multitude of word lines (e.g. the data word line layers (word lines) WLL0-WLL10 of Fig. 6B or WLL10 from Fig. 6D). The memory cells are arranged in one or more chains (e.g., NAND chains NS1 and NS2 of Fig. 6B) arranged and configured to maintain a threshold voltage Vt or Vth corresponding to one of a plurality of memory states. The chains are organized in rows. The method includes step 1100, which identifies the at least one edge word line. The method also includes step 1102, which programs the memory cells of the chains in each of the rows and associated with the at least one edge word line, such that a modified distribution of the threshold voltage Vt for one or more of the plurality of data states, compared to the memory cells of the chains not in each of the rows and not associated with the at least one edge word line, is present during a programming operation.

[0099] With renewed reference to Fig. 6B, for example, encompasses the multitude of word lines (e.g., word line layers (word lines) WLL0-WLL10 of Fig. 6B) and a variety of dielectric layers (e.g. DL0-DL19 of Fig. 6B) horizontally and overlap each other alternately in a stack (e.g. stack 610) and the chains (e.g. NAND chains NS1 and NS2 of Fig. 6B) extend vertically through the stack. The memory cells are connected in series between at least one drain-side select-gate SGD transistor on a drain side of each of the chains (e.g., at SGD0 or SGD1 layers) and are connected to one of a plurality of bit lines (e.g., BL0 of Fig. 6B) and at least one source-side selection gate transistor on a source side of each of the chains (e.g., at SGS0 or SGS1 layers) connected and to a source line (e.g., SL of Fig. 6B). The at least one edge word line is arranged vertically above the multitude of other data word lines and is directly adjacent to the at least one drain-side selection-gate SGD transistor.

[0100] As discussed above, spanning with renewed reference to Fig. 9. The threshold voltage Vt, which is possible for each of the memory cells, has a threshold window of 900. Each of the memory cells is configured to store a multitude of bits. The multitude of data states includes a cleared state (e.g., the cleared state in). Fig. 9) at a first end 902 of the threshold window 900 and a multitude of programmed data states (e.g. states A, B, C, D, E, F and G of Fig. 9) each corresponding to a threshold voltage Vt that is higher than the threshold voltage Vt associated with the erased state. The multitude of programmed data states includes a highest data state (e.g., state G of Fig. 9) at a second end 904 of the threshold window opposite the first end 902 and is assigned to the threshold voltage Vt which is higher than the threshold voltage Vt which is assigned to the erased state and at least one other of the plurality of programmed data states.

[0101] As described, one example of precompensation involves programming the highest data state (e.g., G-state) to a higher threshold voltage Vt only in semicircular rows for the edge word line. Again, the rows include full-circle rows and semicircular rows, which have memory holes forming the chains that are partially cut by a shallow perforated cut (e.g., SHE cut 810) extending vertically into the stack. The respective rows are the semicircular rows.From one perspective, the method further includes the step of applying each of a plurality of program pulses to the at least one edge word line, the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed for the highest data state and assigned to the full-circle rows reach a first highest verification voltage level GV_FC (low) for the highest data state. The method continues with the step of applying each of the plurality of program pulses to the at least one edge word line, the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed for the highest data state, assigned to the semi-circle rows, and the at least one edge word line reach a second highest verification voltage level GV_SC (high) for the highest data state.The second highest verification voltage level GV_SC (high) is higher than the first highest verification voltage level GV_FC (low). The procedure also includes the step of simultaneously applying a blocking bit line voltage to one of the plurality of bit lines coupled to the chains of full-circle rows while the memory cells associated with the at least one edge word line are being programmed, in order to slow down the programming of the memory cells in the chains associated with the full-circle rows, while a select bit line voltage is applied to one of the plurality of bit lines coupled to the chains of semicircle rows while the memory cells associated with the at least one edge word line are being programmed, in order to promote the programming of the memory cells in the chains associated with the semicircle rows.

[0102] As discussed above, another example of precompensation involves programming the highest data state (e.g., G state) to a higher threshold voltage Vt for both semicircular and full-circle rows on the edge word line. Thus, the respective rows are both the semicircular and full-circle rows. From one perspective, the procedure further includes the step of applying each of a multitude of program pulses to the multitude of other edge word lines, the magnitude of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed to the highest data state and associated with the multitude of other data word lines reach a low highest verification voltage level GV (low) for the highest data state.The next step of the procedure is to apply each of the multitude of program pulses to the at least one edge word line, the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed to the highest data state associated with the at least one edge word line reach a high highest verification voltage level GV (higher) for the highest data state. The high highest verification voltage level GV (higher) is greater than the low highest verification voltage level GV (lower).

[0103] As mentioned previously, another example of precompensation involves programming the seventh data state (e.g., G-state), the sixth data state (e.g., F-state), and the fifth data state (e.g., E-state) to a higher threshold voltage Vt for both semicircular and full-circle series for the edge word line. Thus, the respective series are both the semicircular and full-circle series. Again, the set of bits includes three bits, and the total set of data states is eight. The set of programmed data states (e.g., states A, B, C, D, E, F, and G of Fig. 9) closes a first data state (e.g., state A of) in the order of the threshold voltage Vt, the magnitude of which increases. Fig. 9) and a second data state (e.g., state B of Fig. 9) and a third data state (e.g., state C of Fig. 9) and a fourth data state (e.g., state D of Fig. 9) and a fifth data state (e.g., state E of Fig. 9) and a sixth data state (e.g., state F of Fig. 9) and a seventh data state (e.g., state G of Fig.9), the highest data state being the seventh data state. From one point of view, the procedure further includes the step of applying each of a multitude of program pulses to the multitude of other data word lines, the size of which incrementally increases in each of the multitude of loops during the programming process, to the memory cells assigned to the multitude of other data word lines and programmed to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, the sixth data state, and the seventh data state, respectively, until the memory cells assigned to one of the first data state, the second data state, the third data state, the fourth data state, the fifth data state, and the sixth data state, respectively, are assigned to the first data state, the second data state, the third data state, the fourth data state, the fifth data state, and the sixth data state, respectively.The seventh data state can be programmed to reach one of a low first voltage level for the first data state, a low second voltage level for the second data state, a low third voltage level for the third data state, a low fourth voltage level for the fourth data state, a low fifth voltage level EV (low) for the fifth data state, a low sixth voltage level FV (low) for the sixth data state, and a low seventh voltage level GV (low) for the seventh data state.The next step of the procedure consists of the memory cells assigned to the at least one edge word line and programmed to one of the first data state, the second data state, the third data state, and the fourth data state during the programming process applying each of the plurality of program pulses, the size of which increases, to the plurality of other data word lines during the programming process, until the memory cells programmed to one of the first data state, the second data state, the third data state, and the fourth data state each reach one of the low first voltage level for the first data state, the low second voltage level for the second data state, the low third voltage level for the third data state, and the low fourth voltage level for the fourth data state.The procedure continues with the step of creating, for the memory cells that are assigned to the at least one edge word line and are programmed during the programming process to one of the fifth data state, the sixth data state, and the seventh data state, each of the plurality of program pulses onto the plurality of other data word lines, the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells that are programmed to one of the fifth data state, the sixth data state, and the seventh data state each reach one of a high fifth voltage level EV (higher) for the fifth data state, a high sixth voltage level FV (higher) for the sixth data state, and a high seventh voltage level GV (higher) for the seventh data state.The high fifth voltage level EV (higher) is greater than the low fifth voltage level EV (low), the high sixth voltage level FV (higher) is greater than the low sixth voltage level FV (low), and the high seventh voltage level GV (higher) is greater than the low seventh voltage level GV (low).

[0104] As discussed above, another example of precompensation involves programming the seventh data state (e.g., G-state), the sixth data state (e.g., F-state), and the fifth data state (e.g., E-state) onto narrower distributions of the threshold voltage Vt for both semicircular and full-circle series for the edge word line. Again, the respective series are both semicircular and full-circle series. From one perspective, the procedure further includes the step of applying a multitude of program pulses to the multitude of other data word lines for the memory cells assigned to the multitude of other data word lines and programmed to one of the multitude of programmed data states during the programming process. The magnitude of the multitude of program pulses increases stepwise in each of the multitude of loops by a first program step voltage DVPGM (large).The procedure also includes the step of applying a plurality of program pulses to the at least one edge word line for the memory cells that are assigned to the at least one edge word line and are programmed to the third data state, the second data state and the first data state during the programming process, wherein the size of the plurality of program pulses incrementally increases in each of the plurality of loops around the first program step voltage DVPGM (large).The procedure continues with the step of allocating, for the memory cells that are assigned to the at least one edge word line and are programmed during the programming process to the seventh data state, the sixth data state, the fifth data state, and the fourth data state, the plurality of program pulses to the at least one edge word line, wherein the size of the plurality of program pulses in each of the plurality of loops increases stepwise by a second program step voltage that is smaller than the first program step voltage.

[0105] The advantages of the storage device and method disclosed herein include mitigating the edge word line HTDR problem without adding additional dummy word line layers. Furthermore, since the storage device and method disclosed herein program a higher data state onto a higher of selective rows (e.g., semicircular rows) for the edge word line, a sufficient margin for the threshold voltage Vt for higher states is also provided after the HTDR.

[0106] Of course, modifications may be made to what is described and illustrated herein, without, however, deviating from the scope of protection defined in the appended claims. The foregoing description of the embodiments serves the purposes of illustration and description. It is not intended to be exhaustive or to limit the disclosure. Individual elements or features of a particular embodiment are generally not limited to that particular embodiment, but are interchangeable as appropriate and may be used in a selected embodiment, even if this is not specifically shown or described. They may also be varied in many ways. Such variations are not to be considered a deviation from the disclosure, and all such modifications are intended to be included within the scope of protection of the disclosure.

Claims

[1] Storage device comprising: Memory cells (682, 683) connected to one of a plurality of word lines (WLL0-WLL10) including at least one edge word line (WLL10) and a plurality of other data word lines (WLL0-WLL9), arranged in chains (NS1, NS2) and configured to maintain a threshold voltage (Vt) corresponding to one of a plurality of data states (AG, ERASE), the chains (NS1, NS2) being organized in series; and a control instrument that is connected to and set up with the multitude of word lines (WLL0-WLL10) and chains (NS1, NS2) for: Identifying at least one marginal word lead (WLL10), and Programming the memory cells (682, 683) of the chains (NS1, NS2) in their respective rows and those assigned to the at least one edge word line (WLL10), such that a modified distribution of the threshold voltage (Vt) for one or more of the plurality of data states (AG, ERASE) is present compared to the memory cells of the chains that are not in their respective rows and are not assigned to the at least one edge word line (WLL10) during a programming operation, wherein the respective rows include semicircular rows that have memory holes (825) forming the chains, which are partially cut by a shallow hole etching. [2] Memory device according to claim 1, wherein the plurality of word lines (WLL0-WLL10) and a plurality of dielectric layers (DL0-DL19) extend horizontally and alternately overlap each other in a stack (610), wherein the chains (NS1, NS2) extend vertically through the stack (610), wherein the memory cells (682, 683) are connected in series between at least one drain-side select gate transistor (SGD0, SGD1) on a drain side of each of the chains and are connected to one of a plurality of bit lines (BL0, BL1, ...) and at least one source-side select gate transistor (SGS0, SGS1) on a source side of each of the chains and are connected to a source line (SL), wherein the at least one edge word line (WLL10) is arranged vertically above the plurality of other data word lines (WLL0-WLL9) and is directly connected to the at least one drain-side adjacent to the selection gate transistor (SGD0, SGD1). [3] Storage device according to claim 2, wherein the possible threshold voltage (Vt) for each of the memory cells (682, 683) spans a threshold window (900), wherein each of the memory cells is configured to store a plurality of bits, wherein the plurality of data states (AG, ERASE) includes a cleared state (ERASE) at a first end (902) of the threshold window (900) and a plurality of programmed data states (AG), each corresponding to a threshold voltage (Vt) higher than the threshold voltage associated with the cleared state (ERASE), wherein the plurality of programmed data states (AG) includes a highest data state (G) at a second end (904) of the threshold window (900) opposite the first end (902) and is associated with a threshold voltage higher than the threshold voltage.which is assigned to the erased state (ERASE) and at least one other of the multitude of programmed data states (AF). [4] Storage device according to claim 3, wherein the rows include full circle rows and semicircular rows having storage holes (822, 825) forming the chains (NS1, NS2) which are partially cut by the flat hole etching extending vertically into the stack (610), wherein the control means is further configured to: Applying each of a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), the size of which gradually increases in each of a multitude of loops during the programming process, until the memory cells programmed to the highest data state (G) and assigned to the full circle rows reach a first highest verification voltage level for the highest data state (G); Applying each of the plurality of program pulses to the at least one edge word line (WLL10), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed to the highest data state (G) associated with the semicircular rows and the at least one edge word line (WLL10) reach a second highest verification voltage level for the highest data state (G), the second highest verification voltage level being higher than the first highest verification voltage level; and Simultaneously applying a blocking bit line voltage to one of the plurality of bit lines coupled to the chains of the full-circle rows while the memory cells associated with the at least one edge word line (WLL10) are being programmed to slow down the programming of the memory cells in the chains associated with the full-circle rows, while applying a selection bit line voltage to one of the plurality of bit lines coupled to the chains of the semi-circle rows while the memory cells associated with the at least one edge word line (WLL10) are being programmed to promote the programming of the memory cells in the chains associated with the semi-circle rows. [5] Storage device according to claim 3, wherein the rows include full circle rows and semicircular rows, wherein the respective rows are both the semicircular rows and the full circle rows and wherein the control means is further configured to: Applying each of a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed to the highest data state (G) and assigned to the multitude of other data word lines (WLL0-WLL9) reach a low highest verification voltage level for the highest data state (G); and Applying each of the plurality of program pulses to the at least one edge word line (WLL10), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed to the highest data state (G) associated with the at least one edge word line (WLL10) reach a high highest verification voltage level for the highest data state, where the high highest verification voltage level is greater than the low highest verification voltage level. [6] Storage device according to claim 3, wherein the rows include full-circle rows and semi-circle rows, wherein the respective rows are both the semi-circle rows and the full-circle rows, the plurality of bits includes three bits, the total set of states of the plurality of data states (AG, ERASE) is eight, wherein the plurality of programmed data states comprises, in order of increasing threshold voltage, a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G), wherein the highest data state is the seventh data state (G), and the control means is further configured to: Creating, for the memory cells that are assigned to the multitude of other data word lines (WLL0-WLL9) and are programmed to one of the first data state (A) and the second data state (B) and the third data state (C) and the fourth data state (D) and the fifth data state (E) and the sixth data state (F) and the seventh data state (G) during the programming process, each by a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells that are assigned to one of the first data state (A) and the second data state (B) and the third data state (C) and the fourth data state (D) and the fifth data state (E) and the sixth data state (F) respectively.the seventh data state (G) can be programmed, each reaching one of a low first voltage level for the first data state (A) and a low second voltage level for the second data state (B) and a low third voltage level for the third data state (C) and a low fourth voltage level for the fourth data state (D) and a low fifth voltage level for the fifth data state (E) and a low sixth voltage level for the sixth data state (F) and a low seventh voltage level for the seventh data state (G); Applying, for the memory cells that are assigned to the at least one edge word line (WLL10) and are programmed to one of the first data state (A), the second data state (B), the third data state (C), and the fourth data state (D) during the programming process, each of the plurality of program pulses to the plurality of other data word lines (WLL0-WLL9), until the memory cells that are programmed to one of the first data state (A), the second data state (B), the third data state (C), and the fourth data state (D) each reach one of the low first voltage level for the first data state (A), the low second voltage level for the second data state (B), the low third voltage level for the third data state (C), and the low fourth voltage level for the fourth data state (D); and To create, for the memory cells that are assigned to the at least one edge word line (WLL10) and are programmed during the programming process to one of the fifth data state (E), the sixth data state (F), and the seventh data state (G), each of the plurality of program pulses is applied to the plurality of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells that are programmed to one of the fifth data state (E), the sixth data state (F), and the seventh data state (G) each reach one of a high fifth voltage level for the fifth data state (E), a high sixth voltage level for the sixth data state (F), and a high seventh voltage level for the seventh data state (G).where the high fifth voltage level is greater than the low fifth voltage level, the high sixth voltage level is greater than the low sixth voltage level, and the high seventh voltage level is greater than the low seventh voltage level. [7] Storage device according to claim 3, wherein the rows include full-circle rows and semi-circle rows, wherein the respective rows are both the semi-circle rows and the full-circle rows, the plurality of bits includes three bits, the total set of states of the plurality of data states (AG, ERASE) is eight, wherein the plurality of programmed data states (AG) comprises, in order of increasing threshold voltage, a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G), wherein the highest data state is the seventh data state (G), and the control means is further configured to: To provide, for the memory cells that are assigned to the multitude of other data word lines (WLL0-WLL9) and are programmed to one of the multitude of programmed data states (AG) during the programming process, a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), wherein the size of the multitude of program pulses in each of the multitude of loops incrementally increases by a first programming step voltage; To apply a plurality of program pulses to the memory cells assigned to the at least one edge word line (WLL10) and programmed to the third data state (C), the second data state (B), and the first data state (A) during the programming process, wherein the magnitude of the plurality of program pulses in each of the plurality of loops incrementally increases by the first program step voltage; and Provision, for the memory cells that are assigned to the at least one edge word line (WLL10) and are programmed during the programming process to the seventh data state (G) and the sixth data state (F) and the fifth (E) data state and the fourth data state (D), of the plurality of program pulses on the at least one edge word line, wherein the size of the plurality of program pulses in each of the plurality of loops increases stepwise by a second program step voltage that is smaller than the first program step voltage. [8] Controller in communication with a storage device comprising memory cells (682, 683) connected by one of a plurality of word lines (WLL0-WLL10) comprising at least one edge word line (WLL10) and a plurality of other data word lines (WLL0-WLL9) arranged in chains (NS1, NS2) and configured to maintain a threshold voltage (Vt) corresponding to one of a plurality of data states (AG, ERASE), wherein the chains (NS1, NS2) are organized in series, the controller being configured to: Identifying at least one marginal word line (WLL10); and Instructing the memory device to program the memory cells (682, 683) of the chains (NS1, NS2) in their respective rows and those assigned to the at least one edge word line (WLL10), such that a modified distribution of the threshold voltage (Vt) for one or more of the plurality of data states (AG, ERASE) is present compared to the memory cells of the chains that are not in their respective rows and are not assigned to the at least one edge word line (WLL10) during a programming operation, wherein the respective rows include semicircular rows that have memory holes (825) forming the chains, which are partially cut by a shallow hole etching. [9] Controller according to claim 8, wherein the plurality of word lines (WLL0-WLL10) and a plurality of dielectric layers (DL0-DL19) extend horizontally and alternately overlap each other in a stack (610), wherein the chains (NS1, NS2) extend vertically through the stack (610), wherein the memory cells (682, 683) are connected in series between at least one drain-side select gate transistor (SGD0, SGD1) on a drain side of each of the chains and are connected to one of a plurality of bit lines (BL0, BL1, ...) and at least one source-side select gate transistor (SGS0, SGS1) on a source side of each of the chains and are connected to a source line (SL), wherein the at least one edge word line (WLL10) is arranged vertically above the plurality of other data word lines (WLL0-WLL9) and is located immediately adjacent to the at least one drain-side The selection gate transistor (SGD0, SGD1) is arranged.wherein the possible threshold voltage (Vt) for each of the memory cells (682, 683) spans a threshold window (900), wherein each of the memory cells is configured to store a plurality of bits, the plurality of data states (AG, ERASE) including a cleared state (ERASE) at a first end (902) of the threshold window and a plurality of programmed data states (AG), each corresponding to a threshold voltage higher than the threshold voltage associated with the cleared state (ERASE), the plurality of programmed data states (AG) including a highest data state (G) at a second end (904) of the threshold window (900) and associated with a threshold voltage higher than the threshold voltage associated with the cleared state (ERASE) and at least one other of the plurality of programmed data states (AF). [10] Control according to claim 9, wherein the rows include full circle rows and semicircular rows having storage holes (822, 825) forming the chains (NS1, NS2) which are partially cut by the flat hole etching extending vertically into the stack (610), wherein the control means is further configured to: Instructing the memory device to apply each of a plurality of program pulses to the plurality of other data word lines (WLL0-WLL9) during the programming process, the size of which incrementally increases in each of the plurality of loops until the memory cells programmed to the highest data state (G) and assigned to the full circle rows reach a first highest verification voltage level for the highest data state (G); Instructing the memory device to apply each of the plurality of program pulses to the at least one edge word line (WLL10) during the programming process, the size of which incrementally increases in each of the plurality of loops until the memory cells programmed to the highest data state (G) associated with the semicircular rows and the at least one edge word line (WLL10) reach a second highest verification voltage level for the highest data state (G), the second highest verification voltage level being higher than the first highest verification voltage level; and Instructing the memory device to simultaneously apply a blocking bit line voltage to one of the plurality of bit lines coupled to the chains of the full-circle rows while the memory cells associated with the at least one edge word line (WLL10) are being programmed to slow down the programming of the memory cells in the chains associated with the full-circle rows, while a selection bit line voltage is applied to one of the plurality of bit lines coupled to the chains of the semi-circle rows while the memory cells associated with the at least one edge word line (WLL10) are being programmed to promote the programming of the memory cells in the chains associated with the semi-circle rows. [11] Control according to claim 9, wherein the rows include full circle rows and semicircular rows, wherein the respective of the rows are both the semicircular rows and the full circle rows and wherein the control is further configured to: Instructing the memory device to apply each of a plurality of program pulses to the plurality of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed to the highest data state (G) and assigned to the plurality of other data word lines (WLL0-WLL9) reach a low verification voltage level for the highest data state; and Instructing the memory device to apply each of the plurality of program pulses to the at least one edge word line (WLL10), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed to the highest data state (G) associated with the at least one edge word line (WLL10) reach a high highest verification voltage level for the highest data state (G), wherein the high highest verification voltage level is greater than the low highest verification voltage level. [12] Controller according to claim 9, wherein the rows comprise full-circle rows and semi-circle rows, wherein the respective rows are both the semi-circle rows and the full-circle rows, the plurality of bits includes three bits, the total set of states of the plurality of data states (AG, ERASE) is eight, wherein the plurality of programmed data states comprises, in order of increasing threshold voltage, a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G), wherein the highest data state is the seventh data state (G), and the controller is further configured to: Instruct the memory device to apply each of a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the multitude of loops during the programming process, for the memory cells that are assigned to the plurality of other data word lines (WLL0-WLL9) and are programmed to one of the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), the sixth data state (F), and the seventh data state (G) during the programming process, until the memory cells that are assigned to one of the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), and the sixth data state (F), respectively, are programmed to the memory device to apply each of a plurality of program pulses to the plurality of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells that are assigned to one of the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), and the sixth data state (F), respectively, are programmed to one of the first data state (A), the second data state (B), the third data state (C), the fourth data state (D), the fifth data state (E), and the sixth data state (F), respectively.the seventh data state (G) can be programmed, each reaching one of a low first voltage level for the first data state (A) and a low second voltage level for the second data state (B) and a low third voltage level for the third data state (C) and a low fourth voltage level for the fourth data state (D) and a low fifth voltage level for the fifth data state (E) and a low sixth voltage level for the sixth data state (F) and a low seventh voltage level for the seventh data state (G); Instruct the memory device to apply each of the plurality of program pulses to the plurality of other data word lines (WLL0-WLL9) for the memory cells assigned to the at least one edge word line (WLL10) and programmed to one of the first data state (A), the second data state (B), the third data state (C), and the fourth data state (D) during the programming operation, until the memory cells programmed to one of the first data state (A), the second data state (B), the third data state (C), and the fourth data state (D) each reach one of the low first voltage level for the first data state (A), the low second voltage level for the second data state (B), the low third voltage level for the third data state (C), and the low fourth voltage level for the fourth data state (D); and Instruct the memory device to apply each of the plurality of program pulses to the plurality of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the plurality of loops during the programming process, for the memory cells assigned to the at least one edge word line (WLL10) and programmed during the programming process to one of the fifth data state (E), the sixth data state (F), and the seventh data state (G), until the memory cells programmed to one of the fifth data state (E), the sixth data state (F), and the seventh data state (G) each reach a high fifth voltage level for the fifth data state (E), a high sixth voltage level for the sixth data state (F), and a high seventh voltage level for the seventh data state (G).where the high fifth voltage level is greater than the low fifth voltage level, the high sixth voltage level is greater than the low sixth voltage level, and the high seventh voltage level is greater than the low seventh voltage level. [13] Controller according to claim 9, wherein the rows comprise full-circle rows and semi-circle rows, wherein the respective rows are both the semi-circle rows and the full-circle rows, the plurality of bits includes three bits, the total set of states of the plurality of data states (AG, ERASE) is eight, wherein the plurality of programmed data states (AG) comprises, in order of increasing threshold voltage, a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G), wherein the highest data state is the seventh data state (G), and the controller is further configured to: Instruct the memory device to apply a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9) for the memory cells that are assigned to the multitude of other data word lines (WLL0-WLL9) and are programmed to one of the multitude of programmed data states (AG) during the programming process, wherein the multitude of program pulses in each of the multitude of loops increases stepwise by a first programming step voltage. Instruct the memory device to apply a plurality of program pulses to the at least one edge word line (WLL10) for the memory cells that are assigned to the at least one edge word line (WLL10) and are programmed to the third data state (C), the second data state (B), and the first data state (A) during the programming process, wherein the size of the plurality of program pulses increases stepwise by the first program step voltage in each of the plurality of loops; and Instruct the memory device to apply the plurality of program pulses to the plurality of program pulses to the plurality of program pulses to the plurality of program pulses in each of the plurality of loops by a second program step voltage that is smaller than the first program step voltage. [14] Method for operating a storage device comprising memory cells (682, 683) connected by one of a plurality of word lines (WLL0-WLL10) including at least one edge word line (WLL10) and a plurality of other data word lines (WLL0-WLL9) arranged in chains (NS1, NS2) and configured to maintain a threshold voltage (Vt) corresponding to one of a plurality of data states (AG, ERASE), wherein the chains (NS1, NS2) are organized in series, the method comprising the following steps: Identifying at least one marginal word line (WLL10); and Programming of the memory cells (682, 683) of the chains (NS1, NS2) in the respective rows and those assigned to the at least one edge word line (WLL10), such that a modified distribution of the threshold voltage (Vt) for one or more of the plurality of data states (AG, ERASE) is present compared to the memory cells of the chains that are not in the respective rows and are not assigned to the at least one edge word line (WLL10) during a programming operation, wherein the respective rows include semicircular rows that have memory holes (825) forming the chains, which are partially cut by a shallow hole etching. [15] Method according to claim 14, wherein the plurality of word lines (WLL0-WLL10) and a plurality of dielectric layers (DL0-DL19) extend horizontally and alternately overlap each other in a stack (610), wherein the chains (NS1, NS2) extend vertically through the stack (610), wherein the memory cells (682, 683) are connected in series between at least one drain-side select gate transistor (SGD0, SGD1) on a drain side of each of the chains and are connected to one of a plurality of bit lines (BL0, BL1, ...) and at least one source-side select gate transistor (SGS0, SGS1) on a source side of each of the chains and are connected to a source line (SL), wherein the at least one edge word line (WLL10) is arranged vertically above the plurality of other data word lines (WLL0-WLL9) and is directly connected to the at least one drain-side adjacent to the selection gate transistor (SGD0, SGD1). [16] Method according to claim 15, wherein the possible threshold voltage (Vt) for each of the memory cells (682, 683) spans a threshold window (900), wherein each of the memory cells is configured to store a plurality of bits, the plurality of data states (AG, ERASE) including a cleared state (ERASE) at a first end (902) of the threshold window (900) and a plurality of programmed data states (AG), each corresponding to a threshold voltage higher than the threshold voltage associated with the cleared state (ERASE), the plurality of programmed data states (AG) including a highest data state (G) at a second end (904) of the threshold window (900) opposite the first end (902) and associated with a threshold voltage higher than the threshold voltage.which is assigned to the erased state (ERASE) and at least one other of the multitude of programmed data states (A_F). [17] Method according to claim 16, wherein the rows include full circle rows and semicircular rows having storage holes (822, 825) forming the chains which are partially cut by the flat hole etching extending vertically into the stack (610), the method further comprising the following steps: Applying each of a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed to the highest data state (G) and assigned to the full circle rows reach a first highest verification voltage level for the highest data state; Applying each of the plurality of program pulses to the at least one edge word line (WLL10), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed to the highest data state (G) associated with the semicircular rows and the at least one edge word line (WLL10) reach a second highest verification voltage level for the highest data state (G), the second highest verification voltage level being higher than the first highest verification voltage level; and Simultaneously applying a blocking bit line voltage to one of the plurality of bit lines coupled to the chains of the full-circle rows while the memory cells associated with the at least one edge word line (WLL10) are being programmed to slow down the programming of the memory cells in the chains associated with the full-circle rows, while applying a selection bit line voltage to one of the plurality of bit lines coupled to the chains of the semi-circle rows while the memory cells associated with the at least one edge word line (WLL10) are being programmed to promote the programming of the memory cells in the chains associated with the semi-circle rows. [18] The method of claim 16, wherein the rows include full circle rows and semicircular rows, wherein the respective rows are both the semicircular rows and the full circle rows, and wherein the method further includes the following steps: Applying each of a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells programmed to the highest data state (G) and assigned to the multitude of other data word lines (WLL0-WLL9) reach a low highest verification voltage level for the highest data state (G); and Applying each of the plurality of program pulses to the at least one edge word line (WLL10), the size of which incrementally increases in each of the plurality of loops during the programming process, until the memory cells programmed to the highest data state (G) associated with at least one edge word line (WLL10) reach a high highest verification voltage level for the highest data state, wherein the high highest verification voltage level is greater than the low highest verification voltage level. [19] Method according to claim 16, wherein the rows comprise full-circle rows and semi-circle rows, wherein the respective rows are both the semi-circle rows and the full-circle rows, the plurality of bits includes three bits, the total set of states of the plurality of data states (AG, ERASE) is eight, wherein the plurality of programmed data states (AG) comprises, in order of increasing threshold voltage, a first (A) data state, a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G), wherein the highest data state is the seventh data state (G), and the method further comprises the following steps: Creating, for the memory cells that are assigned to the multitude of other data word lines (WLL0-WLL9) and are programmed to one of the first data state (A) and the second data state (B) and the third data state (C) and the fourth data state (D) and the fifth data state (E) and the sixth data state (F) and the seventh data state (G) during the programming process, by each of a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), the size of which incrementally increases in each of the multitude of loops during the programming process, until the memory cells that are assigned to one of the first data state (A) and the second data state (B) and the third data state (C) and the fourth data state (D) and the fifth data state (E) and the sixth data state (F) respectively.the seventh data state (G) can be programmed, each reaching one of a low first voltage level for the first data state (A) and a low second voltage level for the second data state (B) and a low third voltage level for the third data state (C) and a low fourth voltage level for the fourth data state (D) and a low fifth voltage level for the fifth data state (E) and a low sixth voltage level for the sixth data state (F) and a low seventh voltage level for the seventh data state (G); Applying, for the memory cells that are assigned to the at least one edge word line (WLL10) and are programmed to one of the first data state (A), the second data state (B), the third data state (C), and the fourth data state (D) during the programming process, during the programming process, each of the plurality of program pulses, the size of which increases, is applied to the plurality of other data word lines (WLL0-WLL9) until the memory cells that are programmed to one of the first data state (A), the second data state (B), the third data state (C), and the fourth data state (D) each reach one of the low first voltage level for the first data state (A), the low second voltage level for the second data state (B), the low third voltage level for the third data state (C), and the low fourth voltage level for the fourth data state (D). Applying, for the memory cells assigned to the at least one edge word line (WLL10) and programmed during the programming process to one of the fifth data state (E), the sixth data state (F), and the seventh data state (G), each of the plurality of program pulses, the size of which gradually increases, to the plurality of other data word lines (WLL0-WLL9) during the programming process, until the memory cells programmed to one of the fifth data state (E), the sixth data state (F), and the seventh data state (G) each reach one of a high fifth voltage level for the fifth data state (E), a high sixth voltage level for the sixth data state (F), and a high seventh voltage level for the seventh data state (G),where the high fifth voltage level is greater than the low fifth voltage level, the high sixth voltage level is greater than the low sixth voltage level, and the high seventh voltage level is greater than the low seventh voltage level. [20] Method according to claim 16, wherein the rows comprise full-circle rows and semi-circle rows, wherein the respective rows are both the semi-circle rows and the full-circle rows, the plurality of bits includes three bits, the total set of states of the plurality of data states (AG, ERASE) is eight, wherein the plurality of programmed data states (AG) comprises, in order of increasing threshold voltage, a first data state (A), a second data state (B), a third data state (C), a fourth data state (D), a fifth data state (E), a sixth data state (F), and a seventh data state (G), wherein the highest data state is the seventh data state (G), and the method further comprises the following steps: To provide, for the memory cells that are assigned to the multitude of other data word lines (WLL0-WLL9) and are programmed to one of the multitude of programmed data states (AG) during the programming process, a multitude of program pulses to the multitude of other data word lines (WLL0-WLL9), wherein the size of the multitude of program pulses in each of the multitude of loops incrementally increases by a first programming step voltage; To apply a plurality of program pulses to the memory cells assigned to the at least one edge word line (WLL10) and programmed to the third data state (C), the second data state (B), and the first data state (A) during the programming process, wherein the magnitude of the plurality of program pulses in each of the plurality of loops incrementally increases by the first program step voltage; and Provision, for the memory cells that are assigned to the at least one edge word line (WLL10) and are programmed during the programming process to the seventh data state (G) and the sixth data state (F) and the fifth data state (E) and the fourth data state (D), of the plurality of program pulses to the at least one edge word line (WLL10), wherein the size of the plurality of program pulses in each of the plurality of loops increases stepwise by a second program step voltage that is smaller than the first program step voltage.

Images