Programmable ECC for MRAM mixed read scheme

Abstract

Facility, showing: a memory array (502) comprising a plurality of memory cells (701) with reversible resistivity; and a control circuit in communication with the memory array (502), wherein the control circuit (502) is configured to: to read a group of selected memory cells (701) using a referenced read; Decode data read from the group using referenced reading with a first error correction code (ECC) mode capable of correcting up to a first number of bits in the group; to read the group of selected memory cells (701) using a self-referencing read in response to an error, in order to decode the data in the group using the first ECC mode; and Decoding data read from the group using self-referencing with a second ECC mode capable of correcting up to a second number of bits in the group, where the second number of bits is greater than the first number of bits, characterized in that: the first ECC mode exhibits an initial error correction rate for a given raw bit error rate; and The second ECC mode has a second error correction rate that is greater than the first error correction rate for the given raw bit error rate, with data read using self-referenced read having a lower raw bit error rate than data read using referenced read, and a reduction in the raw bit error rate reducing the error correction rate in the second ECC mode.

Description

PRIORITY CLAIM

[0001] The present application claims priority from US patent application No. 17 / 485,129, entitled “MIXED CURRENT-FORCE READ SCHEME FOR RERAM ARRAY WITH SELECTOR”, by Tran et al., filed on September 24, 2021. BACKGROUND

[0002] Memory is used in various electronic devices such as mobile phones, digital cameras, personal digital assistants, medical electronics, mobile computing devices, stationary computing devices, and data servers. Memory can be either non-volatile or volatile. Non-volatile memory allows information to be stored and retained even when the memory is not connected to a power source (such as a battery).

[0003] The memory cells can be located in a crosspoint memory array. In a memory array with a crosspoint architecture, a first set of conductive traces runs across the surface of a substrate, and a second set of conductive traces is formed on top of the first set, the latter running across the substrate in a direction perpendicular to the first set of conductive traces. The memory cells are located at the intersection contacts of the two sets of conductive traces.

[0004] A memory cell with reversible resistivity is made from a material with programmable resistance. In a binary approach, the memory cell can be programmed at each intersection point to one of two resistance states: high and low. Some approaches can use more than two resistance states. One type of memory cell with reversible resistivity is a magnetoresistive random-access memory cell (MRAM cell). An MRAM cell uses magnetization to represent stored data, unlike some other memory technologies that use electronic charges to store data.A bit of data is written to an MRAM cell by changing the direction of magnetization of a magnetic element (“the free layer”) within the MRAM cell, and a bit is read by measuring the resistance of the MRAM cell (a low resistance usually represents a “0” bit and a high resistance usually represents a “1” bit).

[0005] Reading memory cells with reversible resistivity, including but not limited to MRAM cells, presents a challenge. One technique for reading reversible resistive cells is referenced reading, in which the state of the memory cell is compared to a reference signal, such as a reference voltage. A signal is applied to the memory cell to determine its state. For example, a voltage can be applied to the memory cell, resulting in a current whose magnitude is representative of the cell's resistance. This current can be converted into a probe voltage, which is then compared to the reference voltage. The state of the memory cell is determined by whether the probe voltage is higher or lower than the reference voltage.

[0006] Another technique for reading reversible resistance cells is self-referencing (SRR). An SRR technique involves an initial read, a write to a known state, and a second read. One technique for the initial read is to apply a read voltage to the memory cell, resulting in a current whose magnitude is representative of the cell's resistance, and this current is stored. The stored voltage can be adjusted for comparison with a later measurement (e.g., increased by 150 mV). A technique for the second read is to apply the read voltage to the memory cell, resulting in a current whose magnitude is representative of the cell's resistance. A voltage sample from the initial read is stored and compared with a voltage sample from the second read.Determining the original state of the memory cell depends on the difference between the first adjusted read voltage and the second read voltage after destructive writing to a known state. If the second read shows that the bit's state has not changed, it was in the state of the destructive write before the destructive write. If the bit's state changes, it was moved by the destructive write from a different state to the state to which the destructive write places the bit. Furthermore, the disclosures in US 2014 / 0 269 029 A1 and US 2017 / 0 139 769 A1 may be helpful for understanding the present invention. US 2014 / 0 269 029 A1 relates to the selective execution of a read operation with increased accuracy, for example, a self-reference read operation, from a memory.In one aspect, data is read from memory cells, such as magnetoresistive random-access memory (MRAM) cells, of a memory array. In response to the detection of a condition associated with reading from the memory cells, a self-reference read operation can be performed from at least one of the memory cells. The condition might indicate, for example, that the data read from the memory cells cannot be corrected by decoding error correction codes (ECC). Selectively performing self-reference read operations can reduce the power consumption and / or latency associated with reading from memory compared to continuously performing self-reference read operations. US 2017 / 0139769 A1, in turn, discloses a memory system comprising a memory controller and a memory device.The storage device comprises a memory cell array, and the memory cell array comprises at least one first memory page with a plurality of memory cells that store a plurality of stored bits. The memory controller is configured to perform an initial hard read operation on the first memory page to generate a plurality of read bits corresponding to the plurality of stored bits. When the memory controller determines that the value of a bit from a first group of bits within the plurality of read bits needs to be modified, the memory controller selects one of the bits from the first group of bits based on log-likelihood ratio (LLR) values, each corresponding to a bit from the first group of bits, and modifies the value of the selected bit. BRIEF DESCRIPTION OF THE DRAWING

[0007] Elements with the same number refer to common components in the different figures. Fig. Figure 1 is a block diagram representing an embodiment of a non-volatile storage system connected to a host. Fig. Figure 2 is a block diagram of an embodiment of a front-end processor circuit. In some embodiments, the front-end processor circuit is part of a memory controller. Fig. Figure 3 is a block diagram of an embodiment of a back-end processor circuit. In some embodiments, the back-end processor circuit is part of a memory controller. Fig. Figure 4 is a block diagram of an embodiment of a memory package. Fig. 5A is a block diagram of an embodiment of a memory chip. Fig. Figure 5B is a block diagram of an embodiment of an integrated memory arrangement that includes a control chip and a memory structure chip. Fig. Figure 6A shows a side view of an embodiment of an integrated memory arrangement stacked on a substrate. Fig. Figure 6B shows a side view of an embodiment of an integrated memory arrangement stacked on a substrate. Fig. Figure 7A represents an embodiment of a section of a storage array forming a cross-point architecture in an oblique view. Fig. 7B and Fig. Figures 7C show side views and top views of the intersection structure in Fig. 7A. Fig. Figure 7D represents an embodiment of a section of a two-stage storage array that forms a cross-point architecture in an oblique view. Fig. Figure 8 illustrates an embodiment for the structure of an MRAM memory cell; here, for example, the selected cell is controlled by a power source for reading or writing. Fig. Figure 9 illustrates in more detail an embodiment for an MRAM memory cell design as it would be implemented in a crosspoint array. Fig. 10A and Fig. Figure 10B illustrates writing to an MRAM memory cell by a current flow that generates a spin-torque transfer (STT). Fig. 11A and Fig. Figure 11B illustrates embodiments for the integration of threshold switching selectors into an MRAM memory array with a crosspoint architecture. Fig. Figure 12 represents an embodiment of a storage array with a cross-point architecture. Fig. Figure 13 is a flowchart of an embodiment of a mixed current-force reading process. Fig. Figure 14 is a flowchart of an embodiment of a mixed current-force read process in which an ECC engine is used to test whether a current-force-referenced read is successful. Fig. 15A is a flowchart of an embodiment of a mixed current-force read process in which memory cells are tested to determine whether they are in an uncertainty range. Fig. Figure 15B represents two resistance distributions of memory cells, with an uncertainty range between the two resistance distributions. Fig. 15C represents the concept of the uncertainty range, where the horizontal axis is the stress. Fig. 15D represents a circuit that can be used to determine whether a memory cell is located within the uncertainty range. Fig. Figure 16 is a flowchart that represents one embodiment of a current-force-referenced reading process. Fig. Figure 17 is a flowchart that represents one embodiment of a current-power SRR process. Fig. 18A represents the current as a function of time for a retrieved bitstream that is passed through a selected word line during an embodiment of the current-power SRR. Fig. Figure 18B represents the voltage as a function of time for the voltage at a selected MRAM cell during one embodiment of the current force, where the dashed lines represent a bit that is already in the AP state and the solid line represents a bit in the P state that is written to the AP state during waveform 1822. Fig. Figure 19 is a flowchart that represents an embodiment of a process in which a value of a current-force referenced read is stored and used in a current-force SRR. Fig. Figure 20 is a block diagram of components for forcing a current in a word line. Fig. Figure 21 is a schematic diagram of an embodiment of a current generator that reduces the fluctuations of the current from tile to tile despite different distances to the reference and power supply. Fig. Figure 22 is a flowchart of an embodiment of a process for a deterministic return time using a mixed current-force reading scheme. Fig. 23 and Fig. Figure 24 represents timing diagrams of the interface for an embodiment of mixed current-power reading. Fig. Figure 25 is a flowchart of an embodiment of a process for notifying that a reread attempt is to be made in a mixed current-force reading scheme. Fig. Figure 26A is a diagram illustrating components of an embodiment of a memory chip with a programmable ECC engine. Fig. Figure 26B is a diagram illustrating components of an embodiment of an integrated memory arrangement with a programmable ECC engine. Fig. Figure 27 is a flowchart of an embodiment of a process for reading data stored in non-volatile memory cells using a programmable ECC engine. Fig. Figure 28 is a block diagram illustrating further details of an embodiment of a programmable ECC decoder. Fig. Figure 29 is a graph that illustrates an example of correction performance in the probabilistic user bit error rate (PUBER) versus the raw bit error rate (RBER). Fig. Figure 30 is a graph that represents an example of a probabilistically undetectable error rate (PUER) versus error count. DETAILED DESCRIPTION

[0008] The present invention relates to a device according to claim 1, a method according to claim 12, and a storage system according to claim 13. Advantageous embodiments may include features of dependent claims. Accordingly, a technology for a fast ECC engine for mixed reading of memory cells with reversible resistivity, such as magnetoresistive random-access memory cells (MRAM cells), is disclosed. In one embodiment, a codeword is read from a group of memory cells using a referenced read. The codeword is decoded using a first error correction code mode (ECC mode) capable of correcting a first set of bits in the codeword. If the referenced read decoding is successful, the results of the referenced read are provided to a host. If the decoding fails, a self-referenced read (SRR) is performed.In one embodiment, pass or fail is determined by an ECC decoder executing the ECC mode. An uncorrectable error occurs when the ECC decoder reports that decoding the data was unsuccessful (or failed). The data read using the SRR is decoded with a second ECC mode capable of correcting a second number of bits in the codeword, greater than the first number of bits. In some embodiments, the first ECC mode has a first error-fail correction rate, and the second ECC mode has a second error-fail correction rate, both greater than the first error-fail correction rate (for the same raw error rate). A miscorrection occurs when the ECC decoder reports that decoding was successful (passed) even though there are one or more errors in the data. A miscorrection may also be referred to here as an undetectable error.In one embodiment, however, the raw bit error rate will be lower when using the second ECC mode than when using the first ECC mode. The lower raw bit error rate when using the second ECC mode significantly reduces the error correction rate. Therefore, given the actual raw bit error rates observed when using both the first and second ECC modes, the second ECC mode can exhibit approximately the same error correction rate as the first ECC mode.

[0009] Therefore, in one embodiment, using the ECC mode with the higher correction capability for the SRR results in a lower probability of an uncorrectable error relative to the mode with the lower correction capability. For example, self-referencing using an ECC mode that can correct up to nine bits results in a lower probability of an uncorrectable error than using the ECC mode that can correct up to six bits. Furthermore, although the second ECC mode may have a higher probability of an uncorrectable error than the first ECC mode for the same raw bit error rate, the raw bit error rate present when using the second ECC mode may be lower than the raw bit error rate when using the first ECC mode.Therefore, taking into account the lower raw bior error rate for the second ECC mode (during SRR), the second ECC mode may have approximately the same probability of an uncorrectable error as the first ECC mode.

[0010] In some embodiments, the referenced read and the SRR are both current-force reads. In a current-force read, a current is forced through the memory cell, and a voltage is measured that appears as a result across the cell and the selector circuit. The measured voltage is representative of the memory cell's resistance. The memory cells can be arranged in a crosspoint memory array. In one embodiment, each memory cell has a resistive random-access memory element in series with a two-pole selector element. The two-pole selector element can be a threshold switch selector such as an ovonic threshold switch (OTS). In another embodiment, the resistive random-access memory element includes a magnetoresistive random-access memory element (MRAM element).

[0011] As mentioned earlier, the reading can be current-force reading. In one embodiment of current-force reading, a memory cell is accessed by forcing a current through the selected word line while a selection voltage is applied to a selected bit line. The access current flows through a segment of the selected word line, through the selected memory cell, and also through a segment of the selected bit line; and through each of the corresponding decoding circuits. In response to the access current, a voltage appears across the selected memory cell. The voltage across the selected memory cell depends on the magnitude of the access current and the resistance of the memory cell. The voltage across the selected memory cell is thus representative of the resistance of the memory cell.

[0012] In some embodiments, the memory cells are arranged in a crosspoint array and are magnetoresistive random-access memory (MRAM) cells. An MRAM cell uses magnetization to represent stored data, unlike some other memory technologies that use electronic charges to store data. A bit of data is written to an MRAM cell by changing the direction of magnetization of a magnetic element (the "free layer") within the MRAM cell, and a bit is read by measuring the resistance of the MRAM cell (a low resistance typically represents a "0" bit, and a high resistance typically represents a "1" bit). As used here, the magnetization direction is the direction in which the magnetic moment is aligned with respect to a reference direction set by another element of the MRAM (the "reference layer").In some embodiments, the low resistance is referred to as a parallel or P-state, and the high resistance is referred to as an antiparallel or AP-state. MRAM can utilize the spin-transfer torque effect to change the direction of magnetization from the P-state to the AP-state and vice versa, which typically requires a bipolar (bidirectional writing) process.

[0013] A conventional approach forces a voltage across a memory cell and samples the resulting current to read memory cells with reversible resistivity, such as MRAM cells. In some embodiments, the MRAM cell has a threshold switch selector in series with the programmable resistive element. An example of a threshold switch selector is an ovonic threshold switch (OTS). The electrical characteristics of the OTS can vary considerably from one memory cell to the next, which can reduce read tolerance. Using such a voltage-controlled approach to read an MRAM cell in series with a threshold switch selector can be problematic. One issue is that the voltage-controlled read technique does not compensate for fluctuations in the voltage drops across the threshold switch selectors when they are in the on state.The voltage drop in the switched-on state is also referred to as the "offset voltage." A current-force approach can compensate for fluctuations in the offset voltage in such threshold switching selectors. A current-force approach can also compensate for problems such as the voltage drop across the selected word line and the selected bit line, which arises from the variation in the resistances of the word and bit lines depending on the decoded position in the array.

[0014] As mentioned earlier, problems such as fluctuations in the OTS (electrical properties) can reduce read tolerance. One way to address this is to use a stronger signal to read the memory cell. For example, to successfully read an MRAM cell, a sufficiently large current must flow through it. Alternatively, a sufficiently high voltage must be applied across the memory cell to successfully read an MRAM cell. Both the current-force and voltage-force techniques result in a voltage across the memory cell, which will be referred to as the cell voltage. If the cell voltage is not high enough, the bit error rate may be higher than can be corrected by the error correction circuitry. However, if the cell voltage is too high, the reversible resistive memory cell will be subjected to excessive stress, reducing its lifespan.In some embodiments, the current-force read limits the voltage that can occur at the memory cell by clamping the voltage that can occur at the MRAM cell.

[0015] The terms “top” and “bottom”, “upper” and “lower”, “vertical” and “horizontal”, and forms thereof as they may be used herein, are merely exemplary and illustrative and are not intended to limit the description of the technology, since the object in question may be interchangeable in position and orientation. Likewise, as used herein, the terms “essentially” and / or “approximately” mean that the specified dimension or parameter may vary within an acceptable tolerance for a given application.

[0016] Fig. Figure 1 is a block diagram of an embodiment of a non-volatile memory system (or, in short, "memory system") 100 connected to a host system 120. The memory system 100 can implement the technology presented herein for a mixed current-power read scheme. Many different types of memory systems can be used with the technology proposed herein. Examples of memory systems include dual inline memory modules (DIMMs), solid-state drives ("SSDs"), memory cards, and embedded storage devices; however, other types of memory systems can also be used.

[0017] The storage system 100 from Fig. The device 1 comprises a controller 102, non-volatile memory 104 for storing data, and local memory 106 (e.g., MRAM, ReRAM, DRAM). In one embodiment, the memory controller 102 provides access to memory cells in a crosspoint array in the local memory 106. For example, the memory controller 102 can provide access to a crosspoint array of MRAM cells in the local memory 106. In another embodiment, the controller 102 or the interface 126, or both, are omitted, and the memory packets are directly connected to the host 120 via a bus such as DORN. The local memory 106 can also be referred to as a memory system. The combination of the memory controller 102 and the local memory 106 can be referred to here as a memory system.In some embodiments, the resistive direct access memory elements in the local memory 106 are read using a mixed current-force read, which includes performing a current-force referenced read followed by a current-force SRR if the current-force referenced read is unsuccessful.

[0018] The memory controller 102 comprises a front-end processor circuit (FEP circuit) 110 and one or more back-end processor circuits (BEP circuits) 112. In one embodiment, the FEP circuit 110 is implemented on a single ASIC. In another embodiment, each BEP circuit 112 is implemented on a separate ASIC. In other embodiments, a single controller ASIC can combine both the front-end and back-end functions. In yet another embodiment, the FEP and BEP are eliminated in favor of directional control by the host 120, and all functions required for the memory, such as ECC and wear compensation, are generated on the memory chip.Further details of on-chip memory maintenance are described in US patent US 10,545,692 B2 entitled "Memory Maintenance Operations During Refresh Window" and US patent US 10,885,991 B2 entitled "Data Rewrite During Refresh Window," both of which are hereby incorporated by reference in full. If the time available for reading the memory is consistently the same (thus enabling both the initial read / sample / write operation and SRR), the memory is synchronous. If a handshake is used, the memory is asynchronous and requires a handshake to signal the improved latency of forced current-force referenced reads for lower latency.In another embodiment, forced current-referenced read is always used without any SRR cycles so that the chip can be used synchronously at this faster latency as a direct replacement for DRAM in the DORN interface directly to the host; then the BER must be sufficiently low so that all errors are within the correction capacity of the ECC engine.

[0019] The ASICs for each of the BEP circuits 112 and the FEP circuit 110 are implemented on the same semiconductor such that the memory controller 102 is manufactured as a system-on-a-chip (“SoC”). Alternatively, such a circuit can be placed on each memory chip, thus eliminating the need for an external controller and / or a BEP or FEP. The FEP circuit 110 and the BEP circuit 112 each include their own processors. In one embodiment, the FEP circuit 110 and the BEP circuit 112 operate in a master-slave configuration, with the FEP circuit 110 being the master and each BEP circuit 112 being a slave. For example, the FEP circuit 110 implements a media management layer (MML) which handles memory management (e.g., garbage collection, wear compensation, etc.).The BEP circuit 112 handles the translation of logical to physical addresses, communication with the host, management of local memory 106, and management of the overall operation of the SSD (or other non-volatile storage system). The BEP circuit 112 manages memory operations in the memory packages / memory chip at the request of the FEP circuit 110. For example, the BEP circuit 112 can perform read, erase, and program operations. Additionally, the BEP circuit 112 can perform buffer management, set specific voltage levels required by the FEP circuit 110, perform error correction (ECC), control the toggle-mode interfaces to the memory packages, and so on. In one embodiment, each BEP circuit 112 is responsible for its own set of memory packages.

[0020] In one embodiment, the non-volatile memory 104 comprises a plurality of memory packages. Each memory package includes one or more memory chips. Therefore, the memory controller 102 is connected to one or more non-volatile memory chips. In one embodiment, the memory package can include memory types such as memory class memory (SCM) based on resistive random-access memory (such as ReRAM, MRAM, FeRAM, or RRAM) or phase-change memory (PCM). In one embodiment, the memory controller 102 provides access to memory cells in a crosspoint array within a memory package 104.

[0021] The memory controller 102 communicates with the host system 120 via an interface 130 that implements a protocol such as Compute Express Link (CXL). Alternatively, such a controller can be omitted, and the memory packets can be placed directly on the host bus, for example, DORN. For operation with the memory system 100, the host system 120 includes a host processor 122, host memory 124, and an interface 126 connected via the bus 128. The host memory 124 is the host's physical memory and can consist of DRAM, SRAM, ReRAM, MRAM, non-volatile memory, or another type of memory. In one embodiment, the host memory 124 comprises a crosspoint array of non-volatile memory cells, each memory cell having a resistive random-access memory element and a two-pole selector element connected in series with the memory element.In some embodiments, the resistive random access memory elements in host memory 124 are read using a mixed current-force read, which includes performing a current-force referenced read followed by a current-force SRR if the current-force referenced read is unsuccessful.

[0022] The host system 120 is located outside of and separate from the storage system 100. In one embodiment, the storage system 100 is embedded within the host system 120. The host memory 124 can be referred to herein as a storage system. The combination of the host processor 122 and the host memory 124 can be referred to herein as a storage system. In one embodiment, such host memory can be a crosspoint memory using MRAM.

[0023] Fig. Figure 2 is a block diagram of an embodiment of the FEP circuit 110. Fig. Figure 2 shows an interface 150 for communicating with the host system 120 and a host processor 152 that communicates with this interface. The interface 150 can be, for example, CXL, DDR, or PCIe. The host processor 152 can be any processor type known in the technology that is suitable for implementation. The host processor 152 communicates with a network-on-chip (NOC) 154. An NOC is a communication subsystem on an integrated circuit, usually between cores in a system-on-a-chip (SoC). NOCs can span synchronous and asynchronous clock domains or use unclocked asynchronous logic. NOC technology applies network theory and techniques to on-chip communications, bringing significant improvements over conventional bus and crossbar connections. NOC improves the scalability of SoCs and the power efficiency of complex SoCs compared to other designs.The wires and connections of the NOC are shared by many signals. High parallelism is achieved because all connections in the NOC can work on different data packets simultaneously. Therefore, as the complexity of integrated subsystems increases, an NOC provides improved performance (such as throughput) and scalability compared to earlier communication architectures (e.g., dedicated point-to-point signal wires, shared buses, or segmented buses with bridges). Connected to and communicating with the NOC 154 are the memory processor 156, SRAM 160, and a local memory controller 162. The local memory controller 162 is used for operation and communication with the local memory 106 (e.g., the local memory 106 in ). Fig. 1) In one embodiment, the local memory controller 162 is an MRAM controller for operation and communication with the MRAM in local memory 106. In another embodiment, the local memory controller 162 is a ReRAM controller for operation and communication with the ReRAM in local memory 106. SRAM 160 is a local RAM memory used by the memory processor 156. The memory processor 156 is used to operate the FEP circuit and to perform the various memory operations. Furthermore, two interfaces 164 and 166 are connected to the NOC, which can be, for example, CXL, DDR, or PCIe. In the embodiment of Fig. 2. The SSD controller includes two BEP circuits 112; therefore, there are two interfaces 164 / 166. Each interface 164 / 166 communicates with one of the BEP circuits 112. In other embodiments, there may be more or fewer than two BEP circuits 112; therefore, there may be more than two interfaces 164 / 166.

[0024] The FEP circuit 110 can also include a Media Management Layer (MML) 158, which performs memory management (e.g., memory cleanup, wear leveling, load balancing, etc.), logical-to-physical address conversion, communication with the host, DRAM (local volatile memory) management, and overall operation management of the SSD or other non-volatile storage system. The Media Management Layer (MML) 158 can be integrated as part of the memory management system, capable of handling memory errors and interacting with the host. Specifically, the MML can be a module within the FEP circuit 110 and be responsible for the internals of memory management. In particular, the MML 158 can include an algorithm in the storage device's firmware that converts write operations from the host to writes to the memory structure (e.g., 502 of the Fig. 5A and Fig. 5B) of a chip. MML 158 may be necessary because: 1) the memory may have a limited duration; 2) the memory structure can only be written to in multiples of pages; and / or 3) the memory structure cannot be written to unless it is erased as a block. The MML 158 understands these potential limitations of the memory structure, which may not be visible to the host. Accordingly, the MML 158 attempts to translate the write operations from the host into write operations to the memory structure.

[0025] Fig. Figure 3 is a block diagram of an embodiment of the BEP circuit 112. Fig. Figure 3 shows an interface 200 (e.g., CXL, DDR, or PCIe) for communicating with the FEP circuit 110 (e.g., for communicating with one of the interfaces 164 and 166 of Fig. 2) The interface 200 is connected to two NOCs 202 and 204. In one embodiment, the two NOCs can be combined into one large NOC. Each NOC (202 / 204) is connected via an XOR engine (224 / 254) and an ECC engine (226 / 256) to the SRAM (230 / 260), a buffer (232 / 262), a processor (220 / 250), and a data path controller (222 / 252). The ECC engines 226 / 256 are used to perform error correction as known in the art. The XOR engines 224 / 254 are used to XOR the data so that data can be combined and stored in a way that can be recovered in the event of a programming error. The data path controller 222 is connected to an interface module to communicate with memory packets via four channels.Thus, the upper NOC 202 is assigned to an interface 228 for four channels for communicating with memory packets, and the lower NOC 204 is assigned to an interface 258 for four additional channels for communicating with memory packets. Each interface 228 / 258 includes four toggle-mode (TM) interfaces, four buffers, and four schedulers. There is one scheduler, one buffer, and one TM interface for each channel. The processor can be any standard processor known in the art. The data path controllers 222 / 252 can be a processor, an FPGA, a microprocessor, or another type of controller. The XOR engines 224 / 254 and ECC engines 226 / 256 are dedicated hardware circuits known as hardware accelerators. In other embodiments, the XOR engines 224 / 254 and ECC engines 226 / 256 can be implemented in software. The schedulers, buffers, and TM interfaces are hardware circuits.In another embodiment, such circuits and software, or parts thereof, are placed on the chip in each memory.

[0026] Fig. Figure 4 is a block diagram of an embodiment of a memory package 104, which includes a plurality of memory chips 292 connected to a memory bus 294 (data lines and chip activation lines). The memory bus 294 is equipped with a toggle-mode interface 296 for communication with the TM interface of a BEP circuit 112 (see, for example, Figure 4). Fig. 3) connected. In some embodiments, the memory package may include a controller connected to the memory bus and the TM interface. The memory package may include one or more memory chips. In one embodiment, each memory package includes eight or 16 memory chips; however, other numbers of memory chips may also be implemented. The technology described herein is not limited to a specific number of memory chips.

[0027] Fig. Figure 5A is a block diagram illustrating an example of a memory chip 292 that can implement the technology described herein. In one embodiment, the memory chip 292 is enclosed in local memory 106. In another embodiment, the memory chip 292 is enclosed in host memory 124. The memory chip 292 includes a memory array 502, which can contain any of the memory cells described below. The array connection lines of the memory array 502 include the various layers of word lines, organized as rows, and the various layers of bit lines, organized as columns. However, other orientations can also be implemented. The memory chip 292 includes a row control circuit 520, the outputs 508 of which are connected to the respective word lines of the memory array 502.The line control circuit 520 receives a group of M line address signals and one or more different control signals from the system control logic circuit 560 and can typically include circuits such as line decoders 522, line drivers 524, and block selector circuits 526 for both read and write operations. The line control circuit 520 can also include a read / write circuit. In one embodiment, the line decoding and control circuit 520 has read amplifiers 528, each containing a circuit for sensing a state (e.g., the voltage) of a word line of the memory array 502. In one embodiment, sensing a word line voltage determines the state of a memory cell in a crosspoint array. The memory chip 292 also includes a column decoding and control circuit 510, the inputs / outputs 506 of which are connected to the respective bit lines of the memory array 502.Although only a single block for the array 502 is shown, a memory chip can contain multiple arrays or "tiles" that can be accessed individually. The column control circuit 510 receives a group of N column address signals and one or more different control signals from the system control circuit 560 and can typically include circuits such as column decoder 512, column decoder and driver 514, a block selector circuit 516, as well as read / write circuits and I / O multiplexers.

[0028] The system control logic 560 receives data and commands from a host system and provides output data and a status to the host system. In other embodiments, the system control logic 560 receives data and commands from a separate controller circuit and provides output data to this controller circuit, which communicates with the host system. In another embodiment, this data and these commands are sent and received directly from the memory packages to and from the host without the need for a separate controller, and any required controller is located on each chip or on a chip added to a multi-chip memory package. In some embodiments, the system control logic 560 may include a state machine 562, which provides chip-level control of the memory operations. In one embodiment, the state machine 562 is software-programmable.In other embodiments, the state machine 562 uses no software and is fully implemented in hardware (e.g., electrical circuits). In another embodiment, the state machine 562 is replaced by a microcontroller or microprocessor. The system control logic 560 may also include a power control module 564, which controls the power and voltages supplied to the rows and columns of the memory 502 during memory operations, and may include charge pumps and a control circuit for generating control voltages. The system control logic 560 includes a memory 566 in which parameters for the operation of the memory array 502 can be stored. Such system control logic can be instructed by the host 120 or the memory controller 102 to the refresh logic 572, which loads a row and column address (pointer) stored on the chip that can be incremented after the refresh.This address bit(s) can only be selected (to reload the OTS). Alternatively, such an address can be read, corrected by the ECC 569 engine, and then stored in a "reserve" memory location that is also incremented (so that all codewords are periodically read, corrected, and moved around the chip). This process can be controlled more directly by the host of an external controller, such as a PCIe or CXL controller.

[0029] Commands and data are transferred between the memory controller 102 and the memory chip 292 via the memory controller interface 568 (also referred to as the "communication interface"). Such an interface can be, for example, PCIe, CXL, or DORN. The memory controller interface 568 is an electrical interface for communication with the memory controller 102. Examples of the memory controller interface 568 include a toggle-mode interface. Other I / O interfaces can also be used. For example, the memory controller interface 568 can implement a toggle-mode interface that is connected to the toggle-mode interfaces of the memory interfaces 228 / 258 for the memory controller 102. In one embodiment, the memory controller interface 568 includes a set of input and / or output pins (I / O pins) connected to the controller 102.In another embodiment, the interface supports the JEDEC standard DDRn or LPDDRn, e.g. DDR5 or LPDDR5, or a subset thereof with a smaller side and / or more relaxed timing.

[0030] The system control logic 560, located in an external controller on the memory chip within the memory packages, can include the error correction code engine (ECC engine) 569. The ECC engine 569 can be referred to as an on-die ECC engine because it is located on the same semiconductor chip as the memory cells. This means that the on-die ECC engine 569 can be used to encode data to be stored in the memory array 502 and to decode the decoded data and correct errors. The encoded data can be referred to here as a codeword or ECC codeword. The ECC engine 569 can be used to perform a decoding algorithm and to perform error correction. Therefore, the ECC engine 569 can decode the ECC codeword.In one embodiment, the ECC Engine 569 is capable of decoding data very quickly, facilitating mixed current-power reading of MRAM and other memory element technologies with two-pole selectors, such as OTS. In another embodiment, the ECC Engine 569 is programmable with a selection of different ECC modes. The different ECC modes are provided for varying correction capabilities. For example, the number of bits in the codeword that can be corrected differs between the modes. In some embodiments, there is a trade-off where higher correction capability corresponds to a greater probability of miscorrection.

[0031] Because the ECC Engine 569 is located on the same chip as the memory cells, very fast decoding is possible, which facilitates embodiments with mixed current-force read operations. The ECC Engine 569 can use a variety of decoding algorithms, including, but not limited to, Reed-Solomon, Bose-Chaudhuri-Hocquenghem (BCH), and low-density parity checking (LDPC). In one embodiment, the ECC Engine 569 is able to determine or estimate the number of bit errors in a codeword before the codeword is decoded. In another embodiment, the ECC Engine 569 computes the codeword syndrome to estimate the number of bit errors in the codeword. In one embodiment, the syndrome is based on the number of unsatisfied parity-checking equations.In one embodiment, the ECC engine 569 is able to decode a codeword, provided that no more than a certain number of bits in the codeword are faulty.

[0032] In some embodiments, all elements of the memory chip 292, including the system control logic 560, can be configured as part of a single chip. In other embodiments, part or all of the system control logic 560 can be configured on a separate chip.

[0033] In one embodiment, the memory structure 502 comprises a three-dimensional memory array of non-volatile memory cells in which multiple memory layers are formed on a single substrate, such as a wafer. The memory structure can include any type of non-volatile memory monolithically formed in one or more physical layers of memory cells, each having an active region arranged on a silicon (or other type) substrate. In another embodiment, the memory structure 502 comprises a two-dimensional memory array of non-volatile memory cells.

[0034] The exact type of memory array architecture or memory cell enclosed in memory structure 502 is not limited to the preceding examples. Many different types of memory array architectures or memory technologies can be used to form memory structure 326. No special non-volatile memory technology is required for the purposes of the new claimed embodiments proposed herein. Other examples of suitable technologies for memory cells of memory structure 502 include ReRAM (resistive random-access memory), magnetoresistive memory (e.g., MRAM, spin-transfer torque MRAM, spin-orbit torque MRAM), FeRAM, phase-change memory (e.g., PCM), and the like.Examples of suitable technologies for the memory cell architectures of the 502 memory structure include two-dimensional arrays, three-dimensional arrays, crosspoint arrays, stacked two-dimensional arrays, vertical bit line arrays, and the like.

[0035] An example of a ReRAM or MRAM crosspoint memory includes reversible resistive switching elements in series with an OTS selector, arranged in crosspoint arrays accessed via X lines and Y lines (e.g., word lines and bit lines). In another embodiment, the crosspoint is a PCM in series with an OTS selector. In yet another embodiment, the memory cells may include conductive bridge memory elements. A conductive bridge memory element may also be referred to as a programmable metallization cell. A conductive bridge memory element can be used as a state-change element based on the physical displacement of ions within a solid electrolyte. In some cases, a conductive bridge memory element may include two solid metal electrodes, one relatively inert (e.g., tungsten) and the other electrochemically active (e.g., ferrous).silver or copper), with a thin film of solid electrolyte between the two electrodes. As the temperature increases, the mobility of the ions also increases, which causes the programming threshold for the conductive bridge memory cell to decrease. Thus, the conductive bridge memory element can exhibit a wide range of programming thresholds as a function of temperature.

[0036] Magnetoresistive random-access memory (MRAM) stores data using magnetic memory elements. These elements consist of two ferromagnetic layers separated by a thin insulating layer, each capable of holding a magnetization. In field-controlled MRAM, one of the two layers is a permanent magnet set to a specific polarity; the magnetization of the other layer can be changed to match that of an external field to store memory. Other types of MRAM cells are possible. A memory device can be constructed from a grid of MRAM cells. In one programmable embodiment, each memory cell is sandwiched between a pair of write lines arranged parallel to the cell at right angles to each other, one above and one below the cell. When current flows through some of the MRAM cells, an induction magnetic field is generated.MRAM-based memory implementations are discussed in more detail below.

[0037] Phase-change memory (PCM) devices exploit the unique behavior of chalcogenide glass. One embodiment uses a GeTe-Sb₂Te₃ superlattice to achieve non-thermal phase changes simply by altering the coordination state of the germanium atoms with a laser pulse (or light pulse from another source). The memory cells are programmed by current pulses, which can change the coordination of the PCM material or switch it between amorphous and crystalline states. It should be noted that the use of "pulse" in this document does not require a rectangular pulse, but includes any (continuous or discontinuous) oscillation or pulse of sound, current, voltage light, or other wave. For example, the current forced for the write operation can be rapidly ramped up to a peak value and then linearly ramped down at an edge rate of, say, 500 ns.This peak current may be limited by a zoned voltage conformity that varies depending on the position of the memory cell along the word line or bit line.

[0038] The average person skilled in the art will recognize that the technology described herein is not limited to a single specific storage structure, storage design or material composition, but covers many relevant storage structures in accordance with the spirit and scope of the technology as described herein and as known to a person skilled in the art.

[0039] The elements of Fig. The 5A can be grouped into two parts: the memory structure 502 and the peripheral circuits, including all other elements. An important property of a memory circuit is its capacity, which can be increased by increasing the area of ​​the memory chip 292 allocated to the memory structure 502; however, this reduces the area available on the memory chip for the peripheral circuits. This can impose quite significant limitations on these peripheral elements. For example, the need to fit read amplifier circuits into the available area can be a significant constraint on read amplifier design architectures. With respect to the system control logic 560, a reduced availability of area can limit the functionalities that can be implemented on the chip.Consequently, a fundamental trade-off in the design of a memory chip 292 is how much area should be devoted to the memory structure 502 and how much area to the peripheral circuitry. These trade-offs can lead to more IR voltage drops when larger xy arrays of memory are used between driver circuitry on the word line and the bit line, which in turn yields greater benefits from the use of voltage limiting and the zone division of voltage compliance by memory cell position along the word line and the bit line.

[0040] Another area where the 502 memory architecture and peripheral circuitry often conflict is the manufacturing process. This is because these regions often involve different processing technologies and the trade-off of having different technologies on a single chip. For example, elements such as read amplifier circuits, charge pumps, logic elements in a state machine, and other peripheral circuitry in the 560 system control logic often use PMOS devices. In some cases, the memory architecture is based on CMOS devices. The processing operations for manufacturing a CMOS chip will differ in many respects from those optimized for NMOS technologies.

[0041] To improve upon these limitations, the embodiments described below can modify the elements of Fig. Divide the 5A into separately formed chips, which are then connected together. Fig. 5B represents an integrated memory arrangement 570 comprising a memory structure chip 580 and a control chip 590. The memory structure 502 is formed on the memory structure chip 580, and some or all of the peripheral circuitry, including one or more control circuits, is formed on the control chip 590. For example, a memory structure chip 580 can consist solely of the memory elements, such as the array of memory cells of an MRAM memory, a PCM memory, a ReRAM memory, or another type of memory. Some or all of the peripheral circuitry, even including elements such as decoders and read amplifiers, can then be located on the control chip. This allows each of the semiconductor chips to be individually optimized according to its technology.This allows more space for the peripheral elements, which can now accommodate additional capabilities that could not be readily included if they were confined to the edges of the same chip containing the memory cell array. The two chips can then be bonded together into a bonded integrated multi-chip memory arrangement, with the array on one chip connected to the peripheral elements on the other. Although the following discussion focuses on an integrated memory arrangement consisting of one memory chip and one control chip, other embodiments can use additional chips, such as two memory chips and one control chip.

[0042] As with 502 of Fig. The 580 memory chip can handle 5A. Fig. 5B include several independently accessible arrays or "tiles". The system control logic 560, the row control circuit 520, and the column control circuit 510 are located in the control chip 590. In some embodiments, all or part of the column control circuit 510 and all or part of the row control circuit 520 are located on the memory structure chip 580. In some embodiments, part of the circuitry in the system control logic 560 is located on the memory structure chip 580.

[0043] Fig. Figure 5B shows the column control circuit 510 on the control chip 590, which is coupled to the memory structure 502 on the memory structure chip 580 via electrical paths 592. For example, the electrical paths 592 can provide an electrical connection between the column decoder 512, the column driver circuit 514, and the block selector circuit 516 and the bit lines of the memory structure 502. The electrical paths can extend from the column control circuit 510 on the control chip 590 through pads on the control chip 590 that are connected to corresponding pads on the memory structure chip 580, which are connected to bit lines of the memory structure 502. Each bit line of the memory structure 502 can have a corresponding electrical path in the electrical paths 592, including a pair of bonded pads connected to the column control circuit 510.Similarly, line control circuits 520, including the line decoder 522, the line driver 524, the block selector 526, and the read amplifier 528, are connected to the memory structure 502 via electrical paths 594. Each of the electrical paths 594 can, for example, correspond to a word line. Additional electrical paths can also be provided between the control chip 590 and the memory chip 580.

[0044] For the purposes of this document, the term "a control circuit" may include one or more of the following components: memory controller 102, system control logic 560, column control circuit 510, row control circuit 520, a microcontroller, a state machine, host processor 122, and / or other control circuits or other analog circuits used to control non-volatile memory. The control circuit may include only hardware or a combination of hardware and software (including firmware). For example, a controller programmed by firmware to perform the functions described herein is an example of a control circuit. A control circuit may include a processor, FPGA, ASIC, integrated circuit, or any other type of circuit.This control circuit can include drivers, such as direct control via a node connection through fully switched-on transistors (gate to power supply) driven by a fixed voltage such as a power supply. This control circuit can also include a current source driver.

[0045] For the purposes of this document, the term "installation" may include, but is not limited to, one or more of the following: Host system 120, the combination of host processor 122 and host memory 124, Storage system 100, Storage controller 102, Local memory 106, the combination of storage controller 102 and local memory 106, Memory package 104, Memory chip 292, Integrated memory assembly 570 and / or Control chip 590.

[0046] In the following discussion, the memory array 502 of the Fig. 5A and Fig. Section 5B discusses a crosspoint architecture. In a crosspoint architecture, a first set of conductors or wires, such as word lines, runs in a first direction relative to the underlying substrate, and a second set of conductors or wires, such as bit lines, runs in a second direction relative to the underlying substrate. The memory cells are located at the intersection of the word lines and bit lines. The memory cells at these intersections can be formed according to any number of technologies, including those described above. The following discussion will focus mainly on embodiments based on a crosspoint architecture with MRAM memory cells, each connected in series with a two-pole selector, such as an ovonic threshold switch (OTS), to contain a selectable memory bit.Therefore, one embodiment includes a mixed current-force reading scheme in a crosspoint architecture with MRAM cells, each having a series OTS selector. However, embodiments of a mixed current-force reading scheme are not limited to a crosspoint architecture with MRAM cells, each with a series OTS selector.

[0047] In some embodiments, there is more than one control chip 590 and more than one memory structure chip 580 in an integrated memory assembly 570. In some embodiments, the integrated memory assembly 570 includes a stack of multiple control chips 590 and multiple memory structure chips 580. Fig. Figure 6A shows a side view of an embodiment of an integrated memory assembly 570 stacked on a substrate 602 (e.g., a stack comprising control chips 590 and memory structure chips 580). The integrated memory assembly 570 comprises three control chips 590 and three memory structure chips 580. In some embodiments, there are more than three memory structure chips 580 and more than three control chips 590.

[0048] Each control chip 590 can be attached (e.g., bonded) to at least one of the memory structure chips 580. The control chip 590 has a number of bond pads 674 on a main area of ​​the control chip 590. Each memory structure chip 580 has a number of bond pads 670 on a main area of ​​the memory structure chip 580. It should be noted that there are bond pad pairs 670 / 674. In one embodiment, the pattern of the bond pads 670 corresponds to the pattern of the bond pads 674. In some embodiments, the bond pads 670 and 674 are flip-chip bond pads, respectively. Thus, the bond pads 670 and 674 electrically and physically couple the memory chip 580 to the control chip 590. Furthermore, the bond pads 670 and 674 enable internal signal transmission between the memory chip 580 and the control chip 590. Therefore, the memory chip 580 and the control chip 590 are bonded together by bond pads.

[0049] The bond pads 670, 674 can be made, for example, of copper, aluminum, and alloys thereof. A lining 648 can be located between the bond pads 670, 674 and the main surfaces. The lining can be made, for example, of a titanium / titanium nitride stack. The bond pads 670, 674 and the lining can be applied by vapor deposition and / or plating. The bond pads and the linings together can have a thickness of 720 nm, although this thickness can be greater or lesser in other embodiments.

[0050] The bond pads enable internal signal transmission. "Internal signal transmission" here refers to signal transmission between the control chip 590 and the memory chip 580. This internal signal transmission allows the circuits on the control chip 590 to control the memory operations on the memory chip 580. Therefore, the bond pads 670 and 674 can be used for transmitting memory operation signals. Here, "transmission of memory operation signals" refers to all signals associated with a memory operation on a memory chip 580. Memory operation signal transmission could include, but is not limited to, supplying a voltage, supplying a current, receiving a voltage, receiving a current, sampling a voltage, and / or sampling a current.

[0051] There can be many more bond pads than shown. Fig. Figure 6A shows that a space between two bonded chips 580 and 590 is filled with a solid layer 648, which may consist of epoxy or another resin or polymer. This solid layer 648 protects the electrical connections between the chips 580 and 590 and also holds the chips together. Various materials can be used as the solid layer 648; however, in the embodiments shown, it may be Hysol epoxy resin from Henkel Corp., which has facilities in California, USA.

[0052] The integrated memory array 570 can, for example, be stacked with a stepped offset, with the bond pads on each level remaining uncovered and accessible from above. Wire bonds 606, connected to the bond pads, connect the control chip 590 to the substrate 602. A number of such wire bonds can be placed across the width of each control chip 590 (i.e., into the side of Fig. 6A) are formed.

[0053] A memory structure chip silicon via (TSV) 612 can be used to conduct signals through a memory structure chip 580. A controller chip silicon via (TSV) 614 can be used to conduct signals through a controller chip 590. The TSVs 612 and 614 can be formed before, during, or after the formation of the integrated circuits in the semiconductor chips 580 and 590. The TSVs can be formed by etching holes through the wafers. The holes can then be lined with a barrier against metal diffusion. The barrier layer can, in turn, be lined with an inoculation layer, and the inoculation layer can be coated with an electrical conductor such as copper, although other suitable materials such as aluminum, tin, nickel, gold, doped polysilicon, and alloys or combinations thereof can be used.

[0054] The solder balls 608 can optionally be attached to the contact pads 610 on the underside of the substrate 602. Solder balls 608 can be used to electrically and mechanically couple the integrated memory assembly 570 to a host device, such as a printed circuit board. The solder balls 608 can be omitted if the integrated memory assembly 570 is to be used as an LGA package. The solder balls 608 can form part of the interface between the integrated memory assembly 570 and the memory controller 102.

[0055] Fig. Figure 6B shows a side view of an embodiment of an integrated memory assembly 570 stacked on a substrate 602. The integrated memory assembly 570 has three control chips 590 and three memory structure chips 580. In some embodiments, there are many more than three memory structure chips 580 and many more than three control chips 590. In this example, each control chip 590 is bonded to at least one memory structure chip 580. Optionally, a control chip 590 can be bonded to two memory structure chips 580.

[0056] Some of the bond pads 670, 674 are shown. There can be many more bond pads. A gap between two chips 580, 590 that are bonded together is filled with a solid layer 648, which can consist of epoxy or another resin or polymer. In contrast to, for example, in Fig. 6A has the integrated memory arrangement 570 in Fig. 6B has no stepped offset. A memory structure chip silicon via (TSV) 612 can be used to pass signals through a memory structure chip 580. A controller chip silicon via (TSV) 614 can be used to pass signals through a controller chip 590.

[0057] The solder balls 608 can optionally be attached to the contact pads 610 on the underside of the substrate 602. Solder balls 608 can be used to electrically and mechanically couple the integrated memory assembly 570 to a host device, such as a printed circuit board. The solder balls 608 can be omitted if the integrated memory assembly 570 is to be used as an LGA package.

[0058] As briefly discussed above, the control chip 590 and the memory structure chip 580 can be bonded together. Bond pads on each chip 580 and 590 can be used to bond the two chips together. In some embodiments, the bond contact points are directly connected in a so-called copper-to-copper bonding process without solder or other added material. In a copper-to-copper bonding process, the bond pads are controlled to be very flat and are formed in a tightly controlled environment that is largely free of environmental particles that could otherwise settle on a bond pad and prevent a tight bond. Under such appropriately controlled conditions, the bond pads are aligned and pressed against each other to form a mutual bond based on surface tension. Such bonds can be formed at room temperature, although heat can also be applied.In embodiments using Cu-to-Cu bonding, the bond pads can be spaced approximately 6 µm square and with a pitch of 6 µm to 6 µm. Although this process is referred to herein as Cu-to-Cu bonding, this term can apply even when the bond pads are made of materials other than Cu.

[0059] When the area of ​​the bond pads is small, it can be difficult to connect the semiconductor chips together. The size of the bond pads, and the spacing between them, can be further reduced by applying a film layer to the surfaces of the semiconductor chips, including the bond pads. The film layer is applied around the bond pads. When the chips are brought together, the bond pads can connect to each other, and the film layers on the respective chips can bond to each other. Such a bonding technique can be called hybrid bonding. In embodiments using hybrid bonds, the bond pads can be spaced approximately 6 µm square and with a pitch of 1 µm to 6 µm. Interconnection techniques can be used to provide bond pads with even smaller sizes and pitches.

[0060] Some embodiments may include a film on the surface of chips 580, 590. If no such film is initially provided, a space between the chips may be underfilled with an epoxy resin or another resin or polymer. The underfill material may be applied as a liquid that then hardens to form a solid layer. This underfilling step protects the electrical connections between chips 580, 590 and additionally holds the chips together. Various materials may be used as the underfill material, but in embodiments, it may be Hysol epoxy resin from Henkel Corp., which has facilities in California, USA.

[0061] Fig. Figure 7A represents an embodiment of a section of a memory array forming a cross-point architecture in an oblique view. The memory array 502 of Fig. 7A is an example of an implementation for the 502 memory array in Fig. 5A or Fig. 5B, where a memory chip 292 or memory structure chip 580 can enclose several of these array structures. The memory array 502 can be enclosed in local memory 106 or host memory 124. The bit lines BL1-BL5 are arranged in a first direction relative to an underlying substrate (not shown) (represented as running into the page), and the word lines WL1-WL5 are arranged in a second direction perpendicular to the first direction. Fig. 7A is an example of a horizontal cross-point structure where both the word lines WL1-WL5 and BL1-BL5 run in a horizontal direction relative to the substrate, while the memory cells, two of which are labelled 701, are oriented such that the current flows in a vertical direction through one memory cell (as through I cell (shown). In a memory array with additional layers of memory cells as shown below in relation to Fig. 7D discusses that there would be corresponding additional layers of bit lines and word lines.

[0062] As in Fig. As shown in Figure 7A, the memory array 502 includes a plurality of memory cells 701. The memory cells 701 can include rewritable memory elements, which can be implemented, for example, using ReRAM, MRAM, PCM, or another material with programmable resistance. A memory cell that includes an MRAM memory element is simply called an MRAM memory cell. The memory cells 701 can also include selector elements, such as an ovonic threshold switch (OTS), a volatile conductive bridge (VCB), metal-insulator-metal (MIM), or another material that provides a highly nonlinear dependence of the current on the selection voltage. The following discussion focuses on memory cells consisting of MRAM memory elements connected in series with an ovonic threshold switch, although many of the descriptions can be applied more generally.The current in the memory cells of the first storage level is represented as flowing upwards, as indicated by arrow I. cell However, current can flow in both directions, as explained in more detail below.

[0063] Fig. 7B and Fig. Figures 7C show side views and top views of the intersection structure in Fig. 7A. The side view of Fig. 7B shows a lower wire or word line WL1 and the upper wires or bit lines BL1-BL n . At the intersection between the upper wires and the lower wires is an MRAM memory cell 701, although PCM, ReRAM, FeRAM or other technologies can also be used as the memory element. Fig. 7C is a top view showing the intersection structure for M lower wires WL1-WL M and N upper wires BL1-BL NThis is illustrated. In a binary embodiment, the MRAM cell can be programmed at each intersection point to one of two resistance states: high and low. Further embodiments of MRAM memory cells and techniques for reading the MRAM memory cells are described below. In some embodiments, sets of these wires are arranged continuously as a "tile," and these tiles can be paired side-by-side in the word line (WL) direction and orthogonally in the bit line direction to create a module. Such a module can consist of 2 x 2 tiles to form a four-tile combination, with the WL drivers being "center-driven" between the tiles, the WL running continuously over the driver at approximately the center of the line.Similarly, BL drivers can be positioned between pairs of tiles aligned in the BL direction for center-driven operation, with the driver and its area shared between a pair of tiles. An embodiment of a four-tile module is shown in [reference]. Fig. Figure 12B is shown, which is discussed below.

[0064] The intersection array of Fig. Figure 7A illustrates an embodiment with a layer of word lines and bit lines, wherein the MRAM or other memory cells are arranged at the interface of the two sets of conductors. To increase the storage density of a memory chip, multiple layers of such memory cells and conductors can be formed. A two-layer example is shown in Fig. 7D illustrated.

[0065] Fig. Figure 7D represents an embodiment of a section of a two-stage storage array that forms a cross-point architecture in an oblique view. As in Fig. 7A shows Fig. 7D a first layer 718 of memory cells 701 of an array 502, which are located at the intersections of the first layer of word lines WL 1,1 -WL 1,4 and bit lines BL1-BL5 are connected. Above the bit lines BL1-BL5 and between these bit lines and a second set of word lines WL 2,1 -WL 2,4 A second layer of memory cells 720 is formed. Although Fig. As shown in 7D, which has two layers 718 and 720 of memory cells, the structure can be extended upwards by additional alternating layers of word lines and bit lines. Depending on the embodiment, the word lines and bit lines of the array can be Fig. 7D can be biased for read or program operations, so that current flows in each layer from the word line layer to the bit line layer or vice versa. The two layers can be structured so that the current for a given operation flows in the same direction in each layer, or so that the current flows in opposite directions, through driver selection, in the positive or negative direction.

[0066] The use of a crosspoint architecture enables arrays with a small footprint, and several such arrays can be formed on a single chip. The memory cells formed at each crosspoint can be resistive-type memory cells, with data values ​​encoded as different resistance levels. Depending on the embodiment, the memory cells can be binary, with either a low-resistance state or a high-resistance state, or multilevel cells (MLCs), which can have an additional resistance between the low-resistance and high-resistance states. The crosspoint arrays described here can be implemented in the 292 memory chip from Fig. 4, the local storage 106 in Fig. 1 and / or the host memory 124 in Fig. 1. Resistive-type memory cells can be formed according to many of the technologies mentioned above, such as ReRAM, PCM, FeRAM, or MRAM. The following discussion is presented mainly in the context of memory arrays that use a crosspoint architecture with binary-valued MRAM memory cells, although much of the discussion is more generally applicable.

[0067] Fig. Figure 8 illustrates one embodiment of the structure of an MRAM cell. The MRAM cell includes a lower electrode 801, a spacer 812, a threshold switching selector 802, a spacer 814, a pair of magnetic layers (reference layer 803 and free layer 807) separated by a separating or tunneling layer of, in this example, magnesium oxide (MgO) 805, and an upper electrode 811 separated from the free layer 807 by a spacer 809. In another embodiment, the positions of the reference layer 803 and the free layer 807 are reversed, such that the reference layer 803 is on top of MgO 805 and the free layer 807 is below MgO 805. In yet another embodiment, the threshold switching selector 802 is located between the free layer 807 and the upper electrode 811.

[0068] In some embodiments, the lower electrode 801 is referred to as a word line and the upper electrode 811 is referred to as a bit line. In other embodiments, the lower electrode 801 is referred to as a bit line and the upper electrode 811 is referred to as a word line. The state of the memory cell is based on the relative orientation of the magnetizations of the reference layer 803 and the free layer 807: when the two layers are magnetized in the same direction, the memory cell is in a parallel (P) low-resistance state (LRS); and when they have the opposite orientation, the memory cell is in an antiparallel (AP) high-resistance state (HRS). An MLC embodiment would include additional intermediate states. The orientation of the reference layer 803 is fixed and, in the example of Fig. 8 facing upwards. Reference layer 803 is also known as the fixed layer or pinned layer. Reference layer 803 can consist of multiple ferromagnetic layers that are antiferromagnetically coupled in a structure commonly referred to as a synthetic antiferromagnet, or SAF for short.

[0069] Data is written to an MRAM memory cell by programming the free layer 807 to have either the same or the opposite orientation. An array of MRAM memory cells can be set to an initial or erased state by setting all MRAM memory cells to the low-resistance state, in which all free layers have a magnetic field orientation that matches that of their reference layers. Each of the memory cells is then selectively programmed (also called "written") by setting its free layer 807 to the high-resistance state by reversing the magnetic field opposite to that of the reference layer 803. The reference layer 803 is configured to maintain its orientation while the free layer 807 is being programmed.The reference layer 803 can have a more complex structure, including synthetic antiferromagnetic layers and additional reference layers. For the sake of simplicity, these additional layers are omitted in the figures and discussion, and only the solid magnetic layer, which is primarily responsible for the tunnel magnetic resistance in the cell, is considered.

[0070] The threshold switching selector 802 has a high resistance (in the off or non-conducting state) until it is biased to a voltage above its threshold voltage, or a current above its threshold current, and until its voltage bias falls below Vhold (“Voffset”) or its current falls below Ithreshold. After Vt is exceeded and while Vhold is exceeded across the switching selector, the switching selector has a low resistance (in the on or conducting state). The threshold switching selector remains on until its current falls below a holding current Ihold or its voltage falls below a holding voltage Vhold. When this occurs, the threshold switching selector returns to the off state (higher resistance).Accordingly, to program a memory cell at a crossover point, a voltage sufficient to turn on the associated threshold switch selector and set or reset the memory cell is applied; and to read a memory cell, the threshold switch selector is also activated by turning it on before the resistance state of the memory cell can be determined. A set of examples of a threshold switch selector is an ovonic threshold switch material of an ovonic threshold switch (OTS). Exemplary threshold switch materials include Ge-Se, Ge-Se-N, Ge-Se-As, Ge-Se-Sb-N, Ge58Se42, GeTe6, Si-Te, Zn-Te, C-Te, B-Te, Ge-As-Te-Si-N, Ge-As-Se-Te-Si, and Ge-Se-As-Te, with the atomic percentages for each element ranging from a few percent to more than 90 percent. In one embodiment, the threshold switching selector is a two-pole device.The threshold switching selector 802 may also include additional conductive layers at the interface with the reference layer 803. For example, the spacer 814 between the switching selector 802 and the reference layer 803 is shown. The spacer layer 814 at the interface with the reference layer 803 may be a single conductive layer or consist of multiple conductive layers. The threshold switching selector 802 may also include additional conductive layers at the interface with the lower electrode 801. For example, the spacer 812 between the switching selector 802 and the reference layer 803 is shown. The spacer layer 812 at the interface with the lower electrode 801 may be a single conductive layer or consist of multiple conductive layers.Examples of conductive layers adjacent to the OTS include carbon, carbon nitride, carbon silicide, tungsten carbide, titanium, titanium nitride, tungsten, tungsten nitride, tantalum, tantalum nitride, and others. Threshold voltage switches have a threshold voltage (Vt) above which the resistance of the device essentially changes from insulating or quasi-insulating to conductive.

[0071] In the embodiment of Fig. 8. A current-force approach is used for accessing the MRAM cell. The current-force approach can be used to read or write to the MRAM cell. In the current-force approach, an access current (e.g., I) is used. read or I write A current from a current source 813 is passed through electrode 801. The current source 813 is part of the line driver circuit for electrode 801. A voltage (e.g., V) is applied to electrode 811. select) provided. An access stream is routed through a section of a first conductive line (e.g., word line), through a selected memory cell, and through a section of a second conductive line (e.g., bit line). The terms "read stream" (I) are used here to refer to the access stream. read ) and “write stream” (I write ) in conjunction with access currents driven through MRAM cells. The write current changes the state of the MRAM cell. As an example, a write current of approximately 30 µA for 50 ns for an MRAM cell with a critical dimension (CD) of approximately 20 nanometers with RA10 Ω.µm 2The read currents can be about half the write currents if they are applied for a limited time, such as < 20 ns. A write current flowing through the MRAM cell in one direction changes an MRAM cell in the AP state from the AP state to the P state. A write current flowing through the MRAM cell in the other direction changes an MRAM cell in the P state from the P state to the AP state. In general, a read current is preferably set so low and the read duration so short that the state of an MRAM cell does not change from the P state to the AP state or vice versa.

[0072] As further below in connection with Fig. As further explained in Section 10B, in some embodiments a read stream can be applied in the P2AP direction or, alternatively, in the AP2P direction. In some embodiments, the MRAM cell is read by performing a self-referenced read (SRR). The SRR operation can include two read and two write operations, which allow a direct comparison of the initial bit state resistance with the resistance of the bit in a known programmed state, followed by a restoration of the initial bit state by rewriting if it differs from the initial state after the first write. In one embodiment, an SRR has a first read (Read1 in the P2AP direction), a first write (Write 1 to the AP state), and a second read (Read2 in the P2AP direction), followed by an optional second write (Write 2 to the P state for bits that were originally in the P state).The voltage level of the memory cell due to Read1 in the P2AP direction is stored, for example, on a capacitor; or by conversion to digital bits by an analog-to-digital converter, and the bits are stored in memory, for example, in SRAM, until after use in Read2. The state stored on a capacitor can be set positively or negatively by 150 mV by applying a voltage to one terminal of a capacitor connected to the storage capacitor. Alternatively, the digitally stored level can be adjusted by digitally adding or subtracting 150 mV from the stored bits.

[0073] Next, the memory cell is written to the AP state (Write 1). The voltage level measured by Read 2 in the P2AP direction (after a Write 1) is compared to the voltage level stored and adjusted by Read 1, with both Read 1 and Read 2 being performed in the P2AP direction. A sufficient change in the voltage level between Read 2 and Read 1, for example, more than 150 mV, indicates that the MRAM cell was originally in the P state. If the voltage change is less than 150 mV, the MRAM cell was originally in the AP state (into which the write directed the bit state). An optional Write 2 of the bit AP2P is performed if the bit was originally in the P state and was switched to the AP state by Write 1. Alternatively, the SRR has a first read (Read1 in AP2P direction), a first (Write 1 into the P-state) and a second read (Read2 in AP2P direction).The voltage level of the memory cell due to Read1 in the AP2P direction is stored and adjusted, for example, by -150 mV. Next, the memory cell is written to the P state (Write 1). The voltage level due to Read2 in the AP2P direction is compared to the adjusted voltage level due to Read1 in the AP2P direction. A significant change in the voltage level indicates that the MRAM cell was originally in the AP state. An optional Write 2 is performed if the bit was originally in the AP state and was switched to the P state by Write 1. In some embodiments, the same polarity is used for Read1, Write 1, and Read 2 so that the selector does not need to be turned off between Read1 and Read 2. In some embodiments, Write 2 is delayed and performed only after other operations have been completed.In some embodiments, Write 1 is performed by extending the duration of the read stream applied during Read 1.

[0074] In one embodiment, the MRAM cell is read by applying, for example, 0 V to electrode 811 while a current of, for example, 15 microamperes (µA) is passed through electrode 801. This read current flows from electrode 801 to electrode 811. Note that the read operation (Read1 or Read2) can be performed in the P2AP direction. P2AP means that the current flows in the direction that would write the bit from P to AP or AP to AP. In some embodiments, data is written to the MRAM cell using a bipolar write operation. In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, 3 V to electrode 811 while a write current of, for example, -30 µA is passed through electrode 801. This write current flows from one electrode 811 to the other electrode 801.In one embodiment, the MRAM cell is written from the P state to the AP state by, for example, applying 0 V to one electrode 811 while a current of, for example, 30 µA is passed through the other electrode 801. This write current flows from electrode 801 to electrode 811.

[0075] As an alternative to the procedure in Fig. 8. The selection voltage can be applied to electrode 801, with the access current being applied through electrode 811. In such an embodiment, the MRAM cell is read by applying, for example, 3 V to one electrode 801, while a read current of, for example, -15 µA is passed through the other electrode 811. This read current flows from electrode 801 to the upper electrode 811.

[0076] In one embodiment, the MRAM cell is written from the AP state to the P state by applying, for example, -3 V to the lower electrode 801 while a write current of, for example, 30 µA is passed through the upper electrode 811. This electron current flows from the lower electrode 801 to the upper electrode 811. In another embodiment, the MRAM cell is written from the P state to the AP state by applying, for example, 0 V to the lower electrode 801 while a current of, for example, -30 µA is passed through the upper electrode 811. The electron current flows from the upper electrode 811 to the lower electrode 801. The duration of the read current can differ significantly from the duration of the write current.The read current can be applied for 20 ns, for example, while the write current can be applied for 50 ns, before the current flowing through the cell is reduced to zero or to a value where the probability of cell disturbance for the duration of the current is negligible. The duration of the write and read currents can also be the same or substantially similar, such as 20 ns. Each read operation can be performed with a significantly lower current than the write operation, such as 10 µA and 40 µA, respectively. This discussion also assumes that the direction of the current polarity for switching the bit's magnetization to the P or AP state can vary depending on the design of the reference layer and its position relative to the free layer.

[0077] Fig. Figure 9 illustrates in more detail an embodiment of an MRAM memory cell design as it can be implemented in a crosspoint array. In the arrangement in a crosspoint array, the upper and lower electrodes of the MRAM memory cells are the upper and lower wires of the array. In the embodiment shown here, the lower electrode is the word line 901 and the upper electrode is the bit line 911 of the memory cell, but these can be reversed in some embodiments. Between the word line 901 and the bit line 911 are the reference layer 903 and the free layer 907, which in turn are separated by the MgO barrier 905. In the embodiment shown in Fig. In the embodiment shown in Figure 9, an MgO cap 908 is also formed on the free layer 907, and a conductive spacer 909 is formed between the bit line 911 and the MgO cap 908. The reference layer 903 is separated from the word line 901 by another conductive spacer 902. A threshold switching selector 802 may be located between the reference layer 903 and the conductive spacer 902. On each side of the memory cell structure, there is a lining 921 and 923, which may be part of the same structure but have a cross-section of Fig. 9 appear separate. On both sides of the lining 921, 923 shows a portion of the filler material 925, 927, which is used to fill the otherwise empty areas of the intersection structure.

[0078] Regarding the design of the free layer 907, embodiments include a CoFe or CoFeB alloy with a thickness on the order of ~1-2 nm, wherein an Ir layer may be interspersed with a free layer near the MgO barrier 905, and the free layer 907 may be doped or interspersed with Ta, W, or Mo. Embodiments for the reference layer 903 may include a double layer of CoFeB and a Co / Pt multilayer coupled with an Ir or Ru spacer, or a combination or alloy of both 902. The MgO cap 908 is optional but may be used to increase the anisotropy and reduce the critical switching current of the free layer 907. The conductive spacers may be, among others, conductive metals such as Ta, W, Ru, CN, TiN, and TaN₂.The free layer can also be a composite free layer consisting of several free layers with intervening conductive layers such as W, Ta, W or intervening tunnel layers such as MgO.

[0079] The following discussion is mainly in relation to a vertical spin-transfer torque MRAM memory cell, where the free layer 807 / 907 of the Fig. 8 and Fig. 9 has a switchable magnetization direction that is perpendicular to the plane of the free layer. Spin-transfer torque (STT) is an effect by which the orientation of a magnetic layer in a magnetic tunnel junction (MJT) can be modified using a spin-polarized current. Charge carriers (such as electrons) have a property known as spin, which is a small amount of angular momentum intrinsic to the carrier. An electric current is generally unpolarized (e.g., consisting of 50% spin-up and 50% spin-down electrons). A spin-polarized current is one with more electrons with one of the spins (e.g., a majority of spin-up electrons or a majority of spin-down electrons). A spin-polarized current can be generated by passing a current through a thick magnetic layer (the reference layer).When this spin-polarized current is directed into a second magnetic layer (the free layer), an angular momentum can be transferred to this second magnetic layer, thereby changing the magnetization direction of the second magnetic layer. This is called spin-transfer torque. Fig. 10A and Fig. Figure 10B illustrates the use of spin-transfer torque for programming or writing to MRAM memory. Spin-transfer torque random access memory (STT-MRAM) offers advantages over other MRAM variants, including lower power consumption and better scalability. Compared to other MRAM implementations, such as toggle MRAM, STT switching technology requires relatively low power, virtually eliminates the problem of adjacent bit interference, and exhibits more favorable scalability for higher memory cell densities (reduced MRAM cell size). The latter also benefits STT-MRAM, where the magnetizations of the free and reference layers are oriented perpendicular to the film plane rather than in the plane.

[0080] Since the STT phenomenon is more easily described in terms of electron behavior, the Fig. 10A and Fig. 10B and its discussion are given as electron current, where the direction of the writing current is defined as the direction of the electron flow. Therefore, the term writing current refers to Fig. 10A and Fig. 10B on an electron current. Since electrons are negatively charged, the electron current will be opposite to the conventionally defined current, so that an electron current flows from a lower voltage level to a higher voltage level instead of the conventional current flow from a higher voltage level to a lower voltage level.

[0081] Fig. 10A and Fig. Figure 10B illustrates the writing of an MRAM memory cell using the STT mechanism, showing a simplified schematic representation of an example of an STT-switching MRAM memory cell 1000 in which the magnetization of both the reference layer and the free layer is perpendicular. The memory cell 1000 includes a magnetic tunnel contact (MTJ) 1002, which has an upper ferromagnetic layer 1010, a lower ferromagnetic layer 1012, and a tunnel barrier (TB) 1014 as an insulating layer between the two ferromagnetic layers. In this example, the upper ferromagnetic layer 1010 is the free layer FL, and the direction of its magnetization can be reversed. The lower ferromagnetic layer 1012 is the reference (or fixed) layer RL, and the direction of its magnetization cannot be reversed.If the magnetization in the free layer 1010 is parallel to the magnetization in the reference layer RL 1012, the resistance across memory cell 1000 is relatively low. If the magnetization in the free layer FL 1010 is antiparallel to the magnetization in the reference layer RL 1012, the resistance across memory cell 1000 is relatively high. The data ("0" or "1") in memory cell 1000 is read by measuring the resistance of memory cell 1000, for example, by force-reading. In this context, the electrical conductors 1006 / 1008 connected to memory cell 1000 are used to read the MRAM data. By default, both the parallel and antiparallel configurations remain stable in the idle state and / or during a read operation (at a sufficiently low read current).

[0082] For both the reference layer RL 1012 and the free layer FL 1010, the direction of magnetization is the perpendicular direction (i.e., perpendicular to the plane defined by the free layer and perpendicular to the plane defined by the reference layer). For example, the Fig. 10A and Fig. 10B, that the magnetization direction of the reference layer RL 1012 is upwards and the magnetization direction of the free layer FL 1010 is switchable between upwards and downwards, which in turn is perpendicular to the plane.

[0083] In one embodiment, the tunnel barrier 1014 consists of magnesium oxide (MgO); however, other materials can also be used. The free layer 1010 is a ferromagnetic metal capable of changing / reversing its magnetization direction. Multiple layers based on transition metals such as Co, Fe, and their alloys can be used to form the free layer 1010. In one embodiment, the free layer 1010 comprises an alloy of cobalt, iron, and boron. The reference layer 1012 can be many different types of materials, including (but not limited to) multiple layers of cobalt and platinum or an alloy of cobalt and iron.

[0084] To “set” the bit value of the MRAM cell (i.e., to choose the direction of magnetization of the free layer), an electron current 1050 is applied from conductor 1008 to conductor 1006, as shown in Fig. 10A is shown (therefore, the current flows in the opposite direction). To generate the electron current 1050, the upper conductor 1006 is set to a higher voltage level than the lower conductor 1008 due to the negative charge of the electron. The electrons in the electron current 1050 become spin-polarized as they pass through the reference layer 1012, since the reference layer 1012 is a ferromagnetic metal. As the spin-polarized electrons move through the tunnel barrier 1014, the conservation of angular momentum can impart a torque to both the free layer 1010 and the reference layer 1012, but this torque is (intentionally) insufficient to affect the magnetization direction of the reference layer 1012.In contrast, this spin-transfer torque is (intentionally) sufficient to change the magnetization orientation in the free layer 1010 so that it becomes parallel (P) to that of the reference layer 1012, when the initial magnetization orientation of the free layer 1010 was antiparallel (AP) to the reference layer 1012, a process known as antiparallel-to-parallel (AP2P) writing. The parallel magnetizations then remain stable both before and after the electron current is switched off.

[0085] In contrast, if the magnetizations of the free layer 1010 and the reference layer 1012 are initially parallel, the magnetization of the free layer 1010 can be switched to be antiparallel to the reference layer 1012 by applying an electron current in the opposite direction to the case described above. For example, an electron current 1052 is applied from conductor 1006 to conductor 1008, as shown in Fig. 10B is represented by applying the higher voltage level to the lower conductor 1008. This writes a free layer 1010 from a P-state to an AP-state, a process known as parallel-to-antiparallel writing (P2AP). Thus, using the same STT physics, the direction of magnetization of the free layer 1010 can be deterministically set to one of two stable orientations by selectively choosing the electron current direction (polarity).

[0086] The data (“0” or “1”) in memory cell 1000 can be read by measuring the resistance of memory cell 1000. A low resistance usually represents a “0” bit, and a high resistance usually represents a “1” bit, although occasionally the other convention occurs. A read current can be applied across the memory cell (e.g., via the magnetic tunnel contact 1002) by applying an electron current from conductor 1008 to conductor 1006, as for 1050 in Fig. 10A is shown flowing (the “AP2P direction”); alternatively, the electron current can be applied from conductor 1006 to conductor 1008, which, as for 1052 in Fig. 10B (the "P2AP direction") shows the flow of electrons. It is understood that the electron current flows in the opposite direction to the conventional definition. During a read operation, if the electron current is too high, this can disrupt data stored in a memory cell and change its state. For example, if the electron current Read1 is in the P2AP direction of Fig. In 10B, an excessively high current or voltage level can switch any memory cell in the low-resistance P-state to the high-resistance AP-state before the bit voltage is stored during Read1. Consequently, although the MRAM memory cell can be read in both directions, the directional property of the write operation may favor one read direction over the other in different implementations. For example, for a given read current, the SRR error rate may be lower in the P2AP direction.

[0087] Although the discussion of Fig. 10A and Fig. Whereas 10B was discussed in relation to electron current for the read and write currents, the following discussion will be in relation to conventional current unless otherwise stated.

[0088] Whether for reading or writing selected memory cells in the array structures of Fig. 7A-7D, the bit line and the word line corresponding to a selected memory cell, are biased to apply a voltage across the selected memory cell or to pass a current through it and to control the electron flow, as with regard to Fig. 10A or Fig. Figure 10B illustrates how to induce write currents. It is important to note that here, a "selected memory cell" means that the memory cell is selected for access (e.g., read access, write access). A "non-selected memory cell" means that the memory cell is not selected for access by applying either its WL or its BL, or both, to a voltage approximately midway between the maximum positive and minimum negative voltages at the memory cell. A given process may result in write currents that are approximately the same for forward and reverse writing of the MRAM, or it may be that writing from the low-resistance state (LRS) to the high-resistance state (HRS) requires 20% more current for a CD of approximately 20 nm and RA10 Ω.µm. 2 requires.

[0089] Some biasing techniques can introduce a voltage across unselected memory cells in the array, which can induce currents in these cells. While this power dissipation can be mitigated to some extent by designing the memory cells to exhibit relatively high resistance levels for both high and low resistance states, this still results in increased current and power consumption, as well as additional design constraints for the memory cells and the array. One approach to addressing this unwanted leakage current is to place a selection element in series with each MRAM or other resistive (e.g., ReRAM, PCM) memory cell. For example, a selection transistor can be placed with each resistive memory cell element in the Fig. 7A-7D can be connected in series, so that the 701 memory cells now consist of a selection transistor and a programmable resistor. However, using a selection transistor requires the introduction of additional control lines and an additional cell area to turn on the corresponding transistor of a selected memory cell. Furthermore, transistors often do not scale in the same way as the write current of the resistive memory element, so with increasingly smaller memory arrays, the use of transistor-based selectors can be a limiting factor, for example, in reducing costs. An alternative approach to transistor selection is to use a threshold switching selector (e.g., threshold switching selector 802) in series with the programmable resistor element.A two-pole threshold switching selector does not require any of the aforementioned additional control lines or cell areas to switch on the corresponding selection transistor of a selected memory cell.

[0090] Fig. 11A and Fig. Figure 11B illustrates embodiments for the integration of threshold switching selectors into an MRAM memory array with a crosspoint architecture. The examples of Fig. 11A and Fig. Figure 11B shows two MRAM cells (layer 1 cell, layer 2 cell) in a two-layer crosspoint array, as in Fig. 7D shown, but in a side view. Fig. 11A and Fig. Figure 11B shows a lower first conductive line of word line 1 1100, an upper first conductive line of word line 2 1120, and an intermediate second conductive line of bit line 1110. In these figures, all these lines are shown running diagonally across the page from left to right for the sake of simplicity; however, in a crosspoint array, they would be arranged as in the oblique view of Fig. 7D is shown in more detail, with the word lines, or first conductive lines or wires, running in one direction parallel to the surface of the underlying substrate, and the bit lines, or second conductive lines or wires, running in a second direction parallel to the surface of the substrate, which is largely orthogonal to the first direction. The MRAM memory cells are also shown in a simplified form, showing only the reference layer, the free layer, and the inter-tunnel barrier, but in an actual implementation would typically include the additional structure described above in relation to Fig. 9 is described.

[0091] An MRAM element 1102, which includes the free layer 1101, the tunnel barrier 1103, and the reference layer 1105, is formed above the threshold switching selector 1109, with this series connection of the MRAM element 1102 and the threshold switching selector 1109 together forming the layer 1 cell between the bit line 1110 and the word line 1100. The series combination of the MRAM element 1102 and the threshold switching selector 1109 operates essentially as described above. Fig. 10A and Fig. 10B describes when the threshold selector 1109 is switched on. Initially, however, the threshold selector 1109 must be switched on by applying a voltage above the threshold voltage V. thof the threshold selector 1109, and then the bias current or bias voltage must be kept sufficiently high above the holding current or holding voltage of the threshold selector 1109 so that it remains switched on during the subsequent read or write operation.

[0092] At the second layer, an MRAM element 1112 encloses the free layer 1111, the tunnel barrier 1113, and the reference layer 1115 is formed above the threshold switching selector 1119, with the series connection of the MRAM element 1112 and the threshold switching selector 1119 together forming the layer 2 cell between the bit line 1110 and the word line 2 1120. The layer 2 cell operates like the layer 1 cell, except that the lower conductor now corresponds to a bit line 1110 and the upper conductor is now a word line, word line 2 1120. Additional paired layers can similarly have a different bit line between them, with a pattern of WL1, BL1, WL2; WL3, BL2, WL4; or separate bit lines in a pattern such as WL1, BL1, WL2, BL2.

[0093] In the embodiment of Fig. In 11A, the threshold switching selector 1109 / 1119 is configured below the MRAM element 1102 / 1112, but in alternative embodiments, the threshold switching selector for one or both layers can be configured above the MRAM element. As with respect to the Fig. 10A and Fig. As discussed in section 10B, the MRAM memory cell is directional. Fig. In 11A, the MRAM elements 1102 and 1112 have the same orientation, with the free layer 1101 / 1111 lying above (relative to the substrate, which is not shown) the reference layer 1105 / 1115. Forming the layers between the conductor tracks with the same structure can have a number of advantages, particularly with regard to processing, since each of the two layers, as well as subsequent layers in multi-layer embodiments, can be formed according to the same processing sequence.

[0094] Fig. 11B illustrates an alternative embodiment, similar to that of Fig. 11A is arranged, except that in layer 2 cell the positions of the reference layer and the free layer are reversed. More precisely, layer 1 is located between word line 1150 and bit line 1160 as shown in Fig. 11A, an MRAM element I, and has a free layer 1151 formed above the tunnel barrier 1153, which in turn is formed above the reference layer 1155, wherein the MRAM element 1152 is formed above the threshold switching selector 1159. The second layer of the embodiment of Fig. 11B in turn has an MRAM element 1162 formed via a threshold switching selector 1169 between the bit line 1160 and the word line 2 1170, but with respect to Fig. In 11A, the MRAM element 1162 is inverted, with the reference layer 1161 now formed above the tunnel barrier 1163 and the free layer 1165 now formed below the tunnel barrier 1163. Alternatively, the configuration of MRAM cell 1162 can be used for the layer 1 cell and the configuration of MRAM cell 1152 can be used for the layer 2 cell.

[0095] Although the design of Fig. Although 11B requires a different processing sequence for layer formation, it may offer advantages in some embodiments. In particular, the directionality of the MRAM structure may be advantageous in the embodiment of Fig. This makes 11B attractive because, when writing or reading in the same direction (with respect to the reference and free layers), the bit line is biased equally for both the lower and upper layers, and both word lines are biased equally. For example, when both layer 1 and layer 2 memory cells are read in the P2AP direction (with respect to the reference and free layers), the bit line layer 1160 is biased as in the P2AP direction, with the bit line 1160 biased low (e.g., 0 V) ​​for both the upper and lower cells, while both word line 1 (1150) and word line 2 (1170) are biased to a higher voltage level. Similarly, for writing to the high-impedance AP state, the bit line 1160 is biased low (e.g., 0 V) ​​for both the upper and lower cells.0 V), wherein word line 1 1150 and word line 2 1170 are both biased to a higher voltage level; and to write to the low-resistance state P, bit line 1160 is biased to the high voltage level, wherein word line 1 1150 and word line 2 1170 are both biased to the low voltage level. In contrast, for the embodiment of . Fig. 11A The bit lines and word lines have their bias levels reversed to perform one of these operations at the upper level relative to the lower level. It should be noted that in one embodiment of a current-force approach, the word lines are biased to a target voltage by passing a current through the word line.

[0096] Reading data from or writing data to an MRAM memory cell involves the flow of current through the memory cell. In embodiments where a threshold switching selector is placed in series with the MRAM element, the threshold switching selector must be turned on before the current can flow through the MRAM element by applying a sufficient voltage to the series connection of the threshold switching selector and the MRAM element, thus allowing current to flow through it.

[0097] Fig. Figure 12 describes an embodiment of a memory array 502 having a crosspoint architecture. The array 502 has a set of first conductors 1206a-1206h and a set of second conductors 1208a-1208d. In one embodiment, the set of first conductors 1206a-1206h are word lines and the set of second conductors 1208a-1208b are bit lines. For simplicity, the set of first conductors 1206a-1206h can be referred to as word lines and the set of second conductors 1208a-1208b as bit lines. However, the set of first conductors 1206a-1206h could be bit lines and the set of second conductors 1208a-1208b could be word lines.

[0098] The array 502 has a number of memory cells 701. Each memory cell 701 is connected between one of the first conductor tracks 1206 and one of the second conductor tracks 1208. Each memory cell 701 has a magnetoresistive random-access memory (MRAM) element 1202 in series with a threshold switching selector element 1204. Therefore, each memory cell (“bit”) 701 can be referred to as an MRAM cell or a bit. The threshold switching selector 1204 is configured to conduct with lower resistance in response to the application of a voltage level exceeding a threshold voltage of the threshold switching selector 1204, and to remain conducting with lower resistance until the current through the threshold switching selector 1204 is reduced below the selector holding current, Ihold. The threshold switching selector element 1204 is a two-terminal device. In one embodiment, the threshold switching selector element 1204 has an OTS.

[0099] Each first conductive line 1206 is driven by one of the WL drivers 1210a-1210h. For example, the first conductive line 1206a is driven by WL driver 1210a, the first conductive line 1206b is driven by WL driver 1210b, and so on. Each second conductive line 1208 is driven by one of the BL drivers 1212a-1212d. For example, the second conductive line 1208a is driven by BL driver 1212a, the second conductive line 1208b is driven by BL driver 1212b, and so on. In one embodiment, the word lines and bit lines are driven from one end of the word line or the bit line. Fig. Figure 12A represents such an embodiment in which the word lines and the bit lines are driven from one end. In an alternative embodiment, the bit lines and / or the word lines are driven from a midpoint. Driving a word line or a bit line from a midpoint reduces the worst-case IR voltage drop.

[0100] Although a separate driver 1210 is shown connected to each word line 1206, it is not necessary to have a separate driver 1210 for each word line. In one embodiment, the same driver can be used to provide the access stream to any currently selected word line. This driver can be connected to the selected word line by a decoding circuit that selects the drive to the WL 1206. The driver and the decoding circuit can be connected to a "global node" (see global node VX in [reference]). Fig. 20). The locations of the WL drivers 1210a-1210 h in Fig. However, 12A can still indicate the location (e.g., end) of the word line being addressed.

[0101] For the purpose of discussion, memory cell 701a is selected for access. This could be a read or a write access. The selected memory cell 701a is located at the intersection of the selected word line 1206g and the selected bit line 1208b. The other memory cells are not selected for access (i.e., unselected memory cells). All other word lines and all other bit lines are unselected by forcing them to a non-selection voltage such as Vmid, for example, 1.65 V, at approximately half the driver compliance voltage, for example, 3.3 V. To select a memory cell 701, a selection voltage (Vmid) is applied. select_BL), how close to ground, is provided to the selected bit line (e.g., bit line 1208b), and an access current is driven (or forced) through a selected word line (e.g., word line 1206g). The access current can flow between a segment of the selected word line through the selected memory cell and through a segment of the selected bit line. A non-selection voltage (V) unsel_BL ) is applied to the unselected bit lines (e.g., bit lines 1208a, 1208c, 1208d). In one embodiment, V select_BL such a size that the threshold switching selector 1204 is switched on in a selected memory cell, for example V select_BL approximately 0 V. On the other hand, V unsel_BL such a size that the threshold switching selector 1204 is not switched on in an unselected memory cell, for example V select_BL approximately 1.65 V. The 1210g word line driver conducts an access current (Iaccess ) through at least one section of the selected word line 1206g. This access current can also flow through the selected memory cell 701a and in a section of the selected bit line 1208b. Such a selected word line can, for example, be driven high by 15 µA for reading or 30 µA for writing by a current source with a reference voltage of, for example, 3.3 V.

[0102] The WL drivers 1210 are configured to either supply current or reduce current. Thus, I could accessCurrent flows in both directions through the selected word line (as well as the selected bit line). By the convention used herein, when a current driver 1210 is used as a current source, the magnitude of the access current is positive. By the convention used herein, when a current driver 1210 is used as a current sink, the magnitude of the access current is negative. Whether a current driver 1210 generates or sinks a current is referred to herein as forcing the current through the selected word line. In one embodiment, no current other than leakage current is forced through unselected word lines (e.g., 1206a, 1206b, 1206c, 1206d, 1206e, 1206f, and 1206h).It should be noted that here, a "selected word line," driven, for example, for a 20 nm CD with a forced current of 15 µA for reading or 30 µA for writing with a voltage conformance of approximately 3.3 V, means that the word line is connected to a selected memory cell, so that this cell is further defined by its connection to a "selected" bit line at approximately 0 V. To write the opposite polarity, the selected word line is forced, for example, with -15 µA. A selected word line can also be connected to unselected memory cells if the other cell terminal is connected to an unselected bit line at Vmid, such as 1.65 V. An "unselected word line" means that the word line is only connected to unselected memory cells.In other words, all memory cells connected to an unselected word line are unselected memory cells, for example, if the unselected WL is forced to Vmid at 1.65 V; or if the unselected BL is forced to Vmid at 1.65 V. It is important to note that here, a "selected bit line" means the bit line that is close to 0 V when reading and writing P2AP, or close to Vp (-3.3 V) when writing AP1P, and is connected to at least one selected memory cell. An "unselected bit line" means that the bit line is connected only to unselected memory cells. In other words, all memory cells connected to an unselected bit line are unselected memory cells. As stated above, a selected memory cell is a memory cell that is selected for access.A selected memory cell is connected between a selected word line and a selected bit line.

[0103] In one embodiment, the voltage of the selected word line is clamped to a voltage limit (voltage conformity), while an access current (current intensity) is passed through a segment of the selected word line and a segment of the selected bit line into the selected memory cell. In other words, the voltage can be clamped so that it does not exceed a certain value. Clamping the selected word line voltage during current-force reads can lead to a lower bit error rate while simultaneously reducing the load on the memory cells.

[0104] In the example of Fig. In 12, there are more word lines than bit lines in the crosspoint array. In one embodiment, there are more bit lines than word lines in the crosspoint array. In another embodiment, the number of bit lines corresponds to the number of word lines in the crosspoint array. In the example of Fig. In the 12th case, there are twice as many word lines as bit lines in the crosspoint array; however, a different ratio could also be used. This allows for different tile sizes. For example, a tile can have 1024 BL by 2048 WL, which can be combined into a module of 2048 x 4096 cells by addressing the WL and BL in the center between the four tiles.

[0105] In embodiments of a mixed-read scheme, a current-force approach is used to access memory cells in a crosspoint memory array. A current-force approach helps to automatically correct IR voltage drops caused by varying word line resistance and / or varying bit line resistance. Threshold switching selectors can be used in series with the memory cells. The threshold switching selector is connected in series with the memory element between the word line and the bit line. Thus, any voltage across the switching selector reduces the voltage across the memory element. Typically, there is some variation in the offset voltage between switching selectors. A current-force approach helps to mitigate variations in the offset voltage between threshold switching selectors.

[0106] Fig. Figure 13 is a flowchart of an embodiment of Process 1300 for mixed current-force reading. Process 1300 can be used for non-volatile memory cells, each comprising a resistive random-access memory element and a two-pole selector element in series with the memory element. The non-volatile memory cells can be arranged in a crosspoint array. In one embodiment, the memory cells are MRAM cells. In another embodiment, the selector is an OTS.

[0107] Step 1302 involves reading a group of memory cells using a current-force-referenced read. In a current-force-referenced read of a specific memory cell, a current is forced through the cell to be read. A voltage generated by forcing the current through the cell is measured. This voltage is compared to a reference voltage. Note that Step 1302 is performed on a group of memory cells that may be located in different tiles of the memory array. The memory cells may collectively store an ECC codeword. Further details of an embodiment of a current-force-referenced read are discussed below in conjunction with Fig. 16 explained.

[0108] Step 1304 includes determining whether a condition relating to current-force referenced reads is satisfied. In one embodiment, the condition is whether the data read from the memory cells has been successfully decoded by an ECC engine. In one embodiment, the ECC engine is located on the same semiconductor chip as the memory cells, allowing for a rapid determination of whether the data has been successfully decoded. Further details of an embodiment where the condition is whether the data read from the memory cells has been successfully decoded by an ECC engine are described below in connection with Fig. 14 explained. In one embodiment, the condition is based on how many of the memory cells in the group exhibit a resistance that falls within an uncertainty range. Further details of an embodiment in which the condition is based on how many of the memory cells in the group exhibit a resistance that falls within an uncertainty range are explained below in connection with Fig. 15A explained.

[0109] If the condition is not met, step 1306 is executed. Step 1306 includes returning data based on the current-force referenced read. In one embodiment, step 1306 is executed if the data read from the group has been successfully decoded. Therefore, step 1306 can include returning the successfully decoded data.

[0110] If the condition is met, step 1308 is executed. Step 1308 involves reading the group of memory cells using a current-force SRR. Further details of an embodiment of a current-force SRR are given below in connection with Fig. 17 explained.

[0111] Step 1310 includes returning data read using the Strom-Kraft SRR. The ECC engine can be used to decode and correct the data read using the Strom-Kraft SRR. Therefore, the data returned in step 1310 may be decoded and corrected. Since the Strom-Kraft SRR can be significantly more accurate and error-free than the Strom-Kraft-referenced read before the ECC engine is applied, the ECC engine should be able to successfully decode the data in almost all cases. In the very rare case that the data is not successfully decoded, an error message may be returned.

[0112] Fig. Figure 14 is a flowchart of an embodiment of Process 1400 of a mixed current-force read using an ECC engine. Process 1400 provides further details of an embodiment of Process 1300. Step 1402 involves reading a group of memory cells using a current-force referenced read. Step 1402 is similar to Step 1302 and is not described in detail. In Step 1404, an ECC algorithm is run on the data acquired by the current-force referenced read. Step 1406 determines whether the decoding was successful. If the decoding was successful, the decoded data is returned in Step 1408. If the decoding failed, the group of memory cells is read using a current-force SRR in Step 1410. Step 1410 is similar to Step 1308 and is not described in detail.Step 1412 involves running an ECC algorithm on the data to decode and correct it. Step 1414 involves returning data read using the current-power SRR. As mentioned earlier, the data can be decoded and corrected by an ECC engine.

[0113] As an alternative to step 1404, in one embodiment an ECC engine is used to determine or estimate the number of bit errors in a codeword before the codeword is decoded. In one embodiment, the ECC engine 569 calculates the codeword syndrome to estimate the number of bit errors in the codeword. In one embodiment, the syndrome is based on the number of unfulfilled parity-checking equations. In one embodiment, the ECC engine 569 is able to decode a codeword, provided that no more than a certain number of bits in the codeword are faulty. In step 1406, a determination is made as to whether to attempt to decode the codeword or to proceed to step 1410. This determination may be based on whether the decoding of the codeword is likely to be successful.For example, if the estimated number of bit errors in the codeword is less than or equal to the number of bits that can be corrected by the ECC engine 569, then the codeword is decoded and corrected. If the estimated number of bit errors in the codeword is greater than the number of bits that can be corrected, the current-force SRR is performed, and then the resulting read data can be decoded, corrected, and then returned.

[0114] Fig. Figure 15A is a flowchart of an embodiment of Process 1500, a mixed current-force read, in which memory cells are tested to determine whether they are within an uncertainty range. Process 1500 provides further details of an embodiment of Process 1300. Step 1502 involves reading a group of memory cells using a current-force-referenced read. Step 1502 is similar to Step 1302 and is not described in detail.

[0115] Step 1504 is a determination of how many memory cells have a resistance within a range of uncertainty. Fig. Figure 15B represents two resistance distributions of memory cells, with an uncertainty range between the two resistance distributions. Fig. Figure 15B shows the distribution of the low resistance 1540 and the distribution of the high resistance 1542. In one embodiment, distribution 1540 corresponds to the memory cells programmed to a 0, and distribution 1542 corresponds to the memory cells programmed to a 1. Memory cells with a resistance below R_demarcation are assumed to store a "1". Memory cells with a resistance above R_demarcation are assumed to store a "0". Although Fig. Since 15B shows a clear gap between the two distributions, in practice some memory cells may have a resistance in the uncertainty range. Fig. Figure 15C represents the concept of the uncertainty range, but the horizontal axis is the voltage measured across the memory cell during cell reading, as opposed to the cell's resistance. Thus, there is a lower voltage distribution (1550) and a higher voltage distribution (1552). In one embodiment of current-force reading, a higher measured voltage corresponds to a higher cell resistance. Memory cells measured at a voltage below V_demarcation are assumed to store a "1". Memory cells measured at a voltage above V_demarcation are assumed to store a "0". The voltage Vref_low corresponds to R1, and the voltage Vref_hi corresponds to R2.Therefore, in one embodiment, to determine how many memory cells have a resistance in the uncertainty range, the system determines how many memory cells have a measured voltage between Vref_low and Vref_high. This measured voltage can vary, for example, with the CD of the MRAM or its position along the word line or bit line.

[0116] Fig. Figure 15D represents a circuit used to determine whether a memory cell is located within the uncertainty region. The circuit includes a first read amplifier 1562 and a second read amplifier 1564, as well as an XOR logic gate 1566. The first read amplifier 1562 inputs Vref_hi, which is compared to Vrd (the voltage sampled from the memory cell). The second read amplifier 1562 inputs Vref_low, which is also compared to Vrd. The output of each read amplifier is fed into the XOR logic gate 1566. If the output of the XOR logic gate 1566 is true (e.g., "1"), this indicates that the memory cell falls within the uncertainty region.

[0117] Returning to Fig. 15A includes step 1506, which determines whether the number of memory cells exceeds a permissible number. In one embodiment, the permissible number is predetermined. In another embodiment, the permissible number corresponds to the number of bits that can be corrected by the ECC engine 569. For example, the ECC engine can correct up to 9 bits of errors in the codeword. If the number is less than or equal to the permissible number, step 1508 is executed. In step 1508, the data is decoded using the ECC engine, and the decoded and corrected data is returned. It should be noted that step 1508 can also be executed if some memory cells are in the uncertainty range, provided that the number is within the permissible number.This allows process 1500 to be completed based on the current-power referenced read, without having to perform the current-power SRR with its additional latency. This saves a significant amount of time and energy. It should also be noted that in some very rare cases, the data decoding in step 1508 may fail. In this case, the process can continue with step 1510.

[0118] If the number from step 1504 exceeds the permissible number, step 1510 is performed. Step 1510 is the reading of the group of memory cells using the current-power SRR. Step 1512 is the return of (decoded and corrected) data from the current-power SRR. Steps 1510 and 1512 may be similar to steps 1308 and 1310, respectively.

[0119] Fig. Figure 16 is a flowchart that represents an embodiment of Process 1600 of current-force-referenced read. Process 1600 can be used in steps 1302, 1402, or 1502. Process 1600 describes the reading of a memory cell. The process can be performed in parallel on the different memory cells of the group. The group can store an ECC codeword. Step 1602 includes applying a selected voltage to a selected second conductive line. With reference to Fig. Voltage 12A is supplied to the selected bit line 1208b. Unselected voltages are supplied to the unselected bit lines.

[0120] Step 1604 involves applying a read stream to a selected word line in order to force the read stream through the selected memory cell. With reference to Fig. 12A becomes I accessAccess currents are directed into the selected word line 1206g. Access currents are not provided to the unselected word lines. The access current can flow through a segment of the selected word line, through the selected memory cell, and through a segment of the selected bit line. In particular, the access current can flow into the selected memory cell through the segment of the selected word line from which the word line is driven (by a current driver). The access current can flow from the selected memory cell through the segment of the selected bit line to where the bit line is driven by the voltage driver.

[0121] Step 1606 involves sensing a voltage generated by the selected memory cell. In one embodiment, the voltage between the selected word line and the selected bit line is sensed at the selected bit, either directly or at a global node that includes the driver circuitry. The measured voltage is between ground and the current source that supplies current to the array decoding circuitry.

[0122] Step 1608 involves comparing the measured voltage with a reference voltage to determine the state of the memory cell. The reference voltage could, for example, be V_demarcation, which is defined in Fig. Figure 15C illustrates this. The reference voltage level is independent of the physical state (e.g., resistance) of the memory cell. A common reference voltage can be used for the various memory cells of the array. However, in some embodiments, the reference voltage level can depend on a factor such as the position of the memory cell in the array. Therefore, the reference voltage need not be the same for all memory cells in the array.

[0123] Fig. Figure 17 is a flowchart representing an embodiment of Process 1700 of the current-force SRR. The SRR can be described as a destructive SRR, meaning that the initial state of the memory cell can be changed during the SRR. Process 1700 can be used in steps 1308, 1410, or 1510. Process 1700 describes the reading of a memory cell and can be performed in parallel on the memory cells in the codeword group (which may be located in different tiles or groups of tiles). In one embodiment, Process 1700 is performed by a control circuit in the memory chip 292. In another embodiment, Process 1700 is performed by a control circuit in the control chip 590. In yet another embodiment, Process 1700 is performed by a control circuit (e.g., host processor 122) in the host 122. Process 1700 is described with reference to Fig. 18A and Fig. 18B explained. Fig. 18A represents the current intensity as a function of time for the access current that is passed through a selected word line during an embodiment of the current force. Fig. Figure 18B represents the voltage as a function of time for the voltage across a selected MRAM cell during one embodiment of the current force.

[0124] Step 1702 involves driving an initial read stream through the selected word line while a selection voltage is applied to a selected bit line to force the initial access stream through the selected MRAM cell. With reference to Fig. 12 becomes I access driven by the current driver 1210g through the selected first conductive line 1206g to I access to drive memory cell 701a with a current of, for example, 15 µA. With reference to Fig. 12 becomes V select_BLapplied to the second conductive line 1208b by the voltage driver 1212b. In one embodiment, for example, I access 15 µA and V select_BL 0 V. In another embodiment, the current is -15 µA and V select_BL 3.3 V is for 20 nm CD MRAM with RA 10, which can have a low resistance state of about 25 K Ohm and a high resistance state of about 50 K Ohm.

[0125] Fig. 18A and Fig. 18B will now be discussed in relation to an MRAM cell 701 in order to further execute step 1702. With reference to Fig. 18A the current at time t1 is reduced to I read increased and up to t3 on I read held. As in Fig. As shown in Figure 18B, the voltage across memory cell 701 rises from t1 to t2. The threshold switching selector 1204 is switched off between t1 and t2. Between t1 and t2, the current causes the voltage across the word line to rise. The current also compensates for any leakage in the path. As soon as the voltage across the threshold switching selector 1204 exceeds the threshold voltage V th When the threshold switching selector 1204 reaches its operating point, it switches on and (at t2) enters a low-resistance state. Therefore, the voltage across the series circuit consisting of the threshold switching selector 1204 and the resistive MRAM element 1202 increases when the threshold switching selector is in the off state.

[0126] As soon as the threshold switching selector 1204 is in the switched-on state (at t2), the I flows read -Current through the selected memory cell 701a. Since the access current to I readWhen the signal is held, the voltage across the memory cell drops to a level that depends on the series resistance of the MRAM element 1202 and the on-resistance of the threshold switching selector 1204. In a binary embodiment, where a memory cell stores only two states, the memory cell has a high resistance, the AP state, for example 50 kΩ, and a low resistance, the P state, for example 25 kΩ. The voltage across the MRAM element 1202 connected in series with the threshold switching selector 1204 in response to the signal is... readThe voltage resulting from the current for the high-resistance state (HRS) and the low-resistance state (LRS), respectively, is shown as lines 1810 and 1812. Although the discussion here is in the context of an MRAM-based memory cell connected in series with the threshold switching selector, this read technique can be similarly applied to other programmable-resistance memory cells, such as PCM or ReRAM devices.

[0127] Returning to Fig. Step 1704 includes measuring a voltage across the selected memory cell. Step 1704 may also include storing the measured voltage, for example, in a capacitor. Step 1705 includes adjusting the stored voltage by adding (Deck 1) or subtracting (Deck 2) a voltage of 150 mV.

[0128] Step 1706 involves driving a write current through the selected word line while a selection voltage is applied to the selected bit line to force the write current through the selected MRAM cell. With reference to Fig. 12 becomes I access driven by the current driver 1210g through the selected first conductive line 1206g to I access to force through memory cell 701a. With reference to Fig. 12 becomes V select_BL applied to the second conductive line 1208b by the voltage driver 1212b. In one embodiment, I is access for writing 30 µA and V select_BL is 0 V. In another embodiment, I is access for writing -30 µA and V select_BL is 3.3 V

[0129] Fig. 18A and Fig. 18B will now be discussed in relation to an MRAM cell 701 in order to further execute step 1706. With reference to Fig. 18A the access current at time t3 is set to I write increased and up to t5 on I write held. With reference to Fig. At time t3, the voltage across MRAM cell 701 rises. If MRAM cell 701 was in HRS (line 1810), then the voltage across the MRAM cell at t3 rises to the level indicated by line 1820 and remains there until t5. It is worth noting that HRS is the AP state. Thus, this MRAM cell remains in the AP state.

[0130] If MRAM cell 701 was in the LRS (line 1812), then the voltage across the MRAM cell rises at t3 to the level indicated by line 1822. It is worth noting that the LRS is the P-state. If MRAM cell 701 was in the P-state, it transitions to the AP-state. Fig. Figure 18B shows that line 1822 rises at t4 and intersects with line 1820. This indicates that the MRAM cell has transitioned from the P state (LRS) to the AP state (HRS).

[0131] Returning to Fig. 17 Step 1708 includes driving a second read stream through the selected word line while a selection voltage is applied to the selected bit line to force the second access stream through the selected MRAM cell. In one embodiment, the second access stream has the same direction and substantially the same magnitude as the first access stream. With reference to Fig. 12 becomes I access driven by the current driver 1210g through the selected first conductive line 1206g to I access to force through memory cell 701a. With reference to Fig. 12 becomes V select The voltage driver 1212b is applied to the second conductive line 1208b. In one embodiment, Iaccess 15 µA and V select is 0 V.

[0132] The Fig. 18A and Fig. 18B will now be discussed in relation to an MRAM cell 701 in order to further execute step 1708. With reference to Fig. 18A will be the access current at time t5 of I write on I read reduced and down to t6 on I read held. With reference to Fig. At step 18B, the voltage across memory cell 701 drops to the level specified as 1830 at time t5 and remains at this level until time t6. It should be noted that line 1830 is at the HRS level. It should also be remembered that the MRAM cell was switched to the HRS state (AP state) in step 1708, regardless of its initial state.

[0133] Returning to Fig. Step 1710 includes measuring the voltage across the selected memory cell. Step 1710 also includes comparing the voltage measured in step 1710 with the voltage stored in step 1704.

[0134] Step 1712 involves determining the state of the selected MRAM cell prior to reading, based on a comparison of the stored voltage from driving the first read current through the selected memory cell with the voltage from forcing the second read current through the selected memory cell. After step 1712, the data from each memory cell of the group to be read can be provided to the ECC engine, which can then begin decoding the data. In some embodiments, the ECC engine 569 is located on the same semiconductor chip as the memory cells, providing faster decoding by reducing the data transfer time.

[0135] The Fig. 18A and Fig. Step 18B will now be discussed in relation to an MRAM cell 701, in order to proceed to step 1712. The first voltage on the selected word line from the application of the first read current is the voltage between t2 and t3. Thus, the first voltage is either the HRS level 1810 or the LRS level 1812. It should be noted that this first voltage can be stored in step 1704, for example, by charging a read capacitor using the word line voltage. The second voltage on the selected word line from the application of the second read current is the voltage between t5 and t6. This second voltage is typically around the HRS level 1810. However, the second voltage may differ slightly from the HRS level 1810. By comparing the first voltage with the second voltage, it is possible to determine whether the MRAM cell was at the HRS level 1810 or at the LRS level 1812 between t2 and t3.To facilitate comparison, the level generated by the Read1 current in the AP state can be stored and shifted upwards by approximately half the voltage difference between HRS and LRS, for example, 150 mV. Alternatively, the level can also be shifted negatively when the Read1 current is in the P state. These decisions can be reversed depending on the orientation of the MRAM cells, as is obvious to an expert.

[0136] Returning to Fig. In step 1712, a determination is made as to whether a writeback is required (step 1714). As mentioned earlier, process 1700 is a destructive SRR, where the original state of the memory cell may be lost in step 1706. The writeback is used to restore the original state of the memory cell if necessary. Therefore, step 1716 is performed if a writeback is required. Step 1716 involves driving a write stream through the selected word line to write back the original state of the memory cell, if necessary. It should be recalled that step 1706 put all MRAM cells into the AP state. Thus, in step 1716, all MRAM cells that were originally in the P state are written back to the P state. All MRAM cells that were originally in the AP state are left in the AP state in step 1716.It should be noted that, as described above, the ECC engine can begin decoding and correcting the data in step 1712. Therefore, the data can be decoded, corrected, and made available to a requester before the write-back process is completed in step 1716.

[0137] In some embodiments, the current-force SRR is shortened by storing a value from the current-force referenced read and using that value, thus eliminating the need for the first read in the current-force SRR. Fig. Figure 19 is a flowchart depicting an embodiment of Process 1900 in which a value from a current-force referenced read is stored and used in a current-force SRR. Step 1902 involves storing a value from a current-force referenced read. In one embodiment, a voltage is stored in a capacitor. Step 1902 can be performed during Step 1502. Fig. 15 will be carried out.

[0138] Step 1904 involves changing the stored voltage by, for example, 150 mV. However, it should be noted that the initial reading of the current-force SRR can be skipped. Referring to process 1700 of Fig. Steps 1702 and 1704 can be skipped. Step 1906 includes writing the MRAM cell to a known state. Referring to process 1700 of Fig. Step 1706 can be performed. Step 1908 includes the current-power reading of the MRAM cell. With reference to process 1700 of Fig. Steps 1708 and 1710 can be performed. Step 1910 involves determining a pre-read state of the MARM cell based on a comparison of the stored voltage (from the current-force referenced read) with a voltage from the current-force read in the SRR (e.g., a sampled voltage from step 1908). In this way, process 1900 saves time and / or energy by eliminating the need for the initial read in the SRR.

[0139] Fig. Figure 20 is a block diagram of components for driving a current to a word line to force a current through a memory cell. The current source generator 2010 generates and outputs a current control signal, which is provided to the current source 2020. In one embodiment, the current control signal is a high-precision voltage. The current source 2020 outputs a current of a fixed magnitude in response to the current control signal. The current source 2020 could be used to generate a read current or a write current, which can be called an access current. The access current is provided to the selected word line via the line decoding and driver circuit 2040. The line decoding and driver circuit 2040 inputs a WL address and provides the access current for the selected word line. The state machine 562 can provide the WL address to the line decoding and driver circuit 2040.In one embodiment, there are separate current sources 2020 for generating the read current and the write current, with the selection logic choosing the appropriate current source for the storage operation. In one embodiment, there is a first current source for generating a positive write current and a second current source for generating a negative write current. Not in . Fig. Figure 20 shows a bitline driver that can provide a selection voltage for the selected bitline. The access current can flow through a segment of the selected word line, through the selected memory cell, and through a segment of the selected bitline. In one embodiment, the voltage is clamped at node VX so that it does not exceed a certain value. Clamping the voltage at node VX limits the voltage on the word line, thereby reducing the load on the memory cells (e.g., MRAM cells). Simultaneously, a low bit error rate is maintained by choosing the clamping voltage high enough not to reduce the read tolerance, but low enough to reduce the load on some smaller CD-MRAM bits.

[0140] Fig. Figure 21 is a schematic diagram of an embodiment of the current source generator 2010. The current source generator 2010 outputs the voltage Read_1G (between transistors 2120 and 2130), which is supplied to the current source 2020. In some embodiments, Read_1G can be supplied by several types of current sources, such as a current read source, a positive write current source, and a negative write current source.

[0141] Voltages are supplied to the gates of transistors 2130 and 2122 by resistors 2112 and 2114, respectively. These resistive voltages are generated by the left-hand circuit, which includes current source 2102, transistor 2104, transistor 2106, transistor 2108, and transistor 2110, as well as capacitors 2116 and 2118. Current source 2102 can be approximately 5 microamperes. The right-hand circuit includes transistors 2120, 2130, 2122, 2124, 2126, and 2128. In some embodiments, the left-hand circuit is used for an entire bank, with a separate version of the right-hand circuit used for each tile. The current source 2102, for example 5 µA, can generate a voltage of approximately 2 Vt across ground on the drain of transistor 2104, which is distributed across the tiles. V_PA into the gate of transistor 2110 can be high (e.g.,V_P) can be used to activate the circuit, or it can be used to turn the circuit off by setting the gate of transistor 2110 to ground, thus eliminating current when the circuit is not in use. The gate of transistor 2104 can be distributed across the tiles, driving only the gates of the transistors and not the source or drains, to eliminate voltage drops across the tiles and make the resulting current in each tile relatively equal. The two distributed voltages of approximately 1.5 V and 0 V are, in turn, connected to the generators on the right side of each tile. That is, the gate of transistor 2130 is at approximately 1.5 V and the gate of transistor 2122 is at approximately 0 V. These mirrored circuits can, in turn, be turned on by setting Step1T, Read1T, or Read1T_NX high to V_P.The result is that the current from the power source 2102 is driven into the drain of transistor 2120 and the gate of transistor 2120 is at V_P - Vt, or about 2.5 V when V_P is 3.3 V.

[0142] One of the challenges of a mixed current-power read scheme is the interface timing between the storage device and a data requester, such as a storage controller. Since, for example, current-power SRR can take longer than current-power-referenced reads, from the storage controller's perspective, there is a possibility that the data will be returned at a non-deterministic time after the storage controller has issued the read request. In one embodiment, the data is returned to the storage controller at a deterministic time after the read request has been issued, regardless of whether current-power-referenced reads or current-power SRRs are used to read the data. Furthermore, storage protocols such as the DDR protocol have very strict timing requirements.Therefore, it is challenging and less effective in reducing latency to operate a mixed current-power read scheme of the MRAM within a DDR protocol.

[0143] Fig. Figure 22 is a flowchart of an embodiment of Process 2200 for a deterministic retrace time using a mixed current-power read scheme. Process 2200 includes a communication interface between a memory controller and a storage device. In one embodiment, the communication interface is a DDR interface. Step 2202 involves a memory controller issuing a read request to a storage device. In one embodiment, the memory controller 102 issues the read request to local memory 106. In another embodiment, the memory controller 102 issues the read request to a memory packet 104. In yet another embodiment, the host processor 122 issues the read request to host memory 124.

[0144] Step 2204 involves the storage device performing a current-force referenced read (CFRR). In one embodiment, process 1600 is performed. Step 2206 involves determining whether the CFRR was successful. In one embodiment, an ECC algorithm is applied to the data in step 2206. In one embodiment, the CFRR is a success if the data was successfully decoded and corrected. If the CFRR was successful, the storage device returns the corrected data to the storage controller in step 2208. In step 2210, the storage device indicates to the storage controller that it is not necessary to repeat the read instruction.

[0145] If the CFRR was unsuccessful, then in step 2212 the storage device indicates to the memory controller that a re-read attempt is required. In one embodiment, the storage device sends a signal with a value of either 0 or 1. The signal can be sent over a communication line between the storage device and the memory controller. In one embodiment, a new communication line (or pin) is added to the interface (e.g., the DDR interface). However, it is not necessary to add a new line, as an existing line can be used for the re-read signal. Further details are provided in connection with Fig. 23 and Fig. 24. In one embodiment, the storage device sends a cyclic redundancy check (CRC), which is the opposite of what the CRC should be to signal repetition. Further details are discussed in connection with Fig. 25 explained.

[0146] In step 2214, the storage device performs a current-force SRR to read the data from the group of memory cells. In one embodiment, process 1700 is performed. In another embodiment, some steps of process 1700 (e.g., steps 1702, 1704, 1706) can be skipped because of the read performed in step 2204. In other words, the voltage from the read of step 2204 can be stored, as described in process 1900.

[0147] In step 2216, the storage controller reissues the read request after waiting a predetermined time interval following a notification that a re-read attempt is required. The predetermined time interval is based on how long the storage device takes to perform the current-force SRR. In one embodiment, the storage device informs the storage controller of the desired duration of the predetermined time interval. This can be done only once, as the predetermined interval can be predefined.

[0148] In step 2218, the storage device returns the data to the storage controller. That is, the storage device decodes the data from the current-power SRR and returns the decoded data to the storage controller.

[0149] In step 2220, the storage device indicates to the storage controller that no further read attempt is required.

[0150] Fig. 23 and Fig. Figure 24 represents timing diagrams of the interface for an embodiment of mixed current-power reading. Fig. Figure 23 shows a case where only a current-force-referenced reading is required. Fig. Figure 24 shows a case in which the storage device performs both current-force referencing and current-force SRR. Fig. 23. The data is available after the first read request, while in Fig. 24. The data is only available after a second read request. However, the data is always returned to the storage controller within tRL after the storage device successfully responds to a read request. Therefore, the data return time is deterministic. The various instructions (enable, read, PRE) can be DDR instructions. Likewise, the various timings (tRCD, tRTP, tRP, tRL) can be DDR timings. The actual values ​​for the different timings (tRCD, tRTP, tRP, tRL) depend on the protocol used. Fig. 23 and Fig. 24 provide further details for an embodiment of process 2200.

[0151] Now, referring to Fig. 23. The memory controller issues an activation instruction to the storage device. As mentioned earlier, this can be a DDR activation instruction. Next, the memory controller issues a read instruction to the storage device. This can be a DDR read instruction. The timing tRCD (Row Column Delay) refers to the delay between the row address and the column address. Following the read instruction, the memory controller issues a PRE instruction to the storage device. The PRE instruction refers to a "preload instruction," which can be used in RAM as well as DDR. The timing tRTP refers to the delay between the read instruction and the PRE instruction. The timing tRL refers to the latency for read instructions (or the delay of data output), which is common in RAM as well as DDR. In other words, tRL is the time from the read instruction until the storage device makes the data available. Significantly, in Fig. 23, the storage device makes the data available to the memory controller within tRL from the moment the read command is received. Furthermore, the storage device indicates to the memory controller that it is not necessary to repeat the read command by sending a value (e.g., 0) on a retry line. The retry line can be any communication line between the storage device and the memory controller that is not currently in use. The retry signal is provided in one embodiment of step 2210 by Fig. 22 is used. In an alternative embodiment, the retry attempt is encoded in a CRC that is appended to the data.

[0152] Now, referring to Fig. 24. The memory controller issues an activation command and a read command in a similar manner to that used in conjunction with Fig. This is described in section 23. However, in this example, the storage device does not return valid data. This corresponds to a case where the current-force-referenced read fails. The storage device sends a "1" on the retry line to indicate to the memory controller that it should repeat the read instruction. The PRE after the first read instruction is shown in a dashed box to indicate that the PRE instruction does not need to be issued by the memory controller. After receiving the retry signal, the memory controller waits a predetermined time (tDelay) before issuing the read instruction again. Note that the activate instruction does not need to be issued again.

[0153] However, it should be noted that the storage device can begin the current-force SRR as soon as it determines that the current-force-referenced read was unsuccessful. Thus, the storage device does not have to wait for the memory controller to reissue the read instruction. Significantly, the storage device sends the data back to the memory controller within tRL from the moment the memory controller reissues the read instruction. This applies to both the read instruction in Fig. 23 as well as in the case of the reissued read order in Fig. 24. The storage device returns the data within tRL. Therefore, the time until valid data is returned is deterministic, which significantly simplifies the logic of the memory controller. Thus, an implementation of mixed current-force read of the MRAM can be integrated with a DDR controller. In other words, an implementation of mixed current-force read of the MRAM can be integrated with a DDR protocol. Finally, it should be noted that after the reissued read instruction, the memory controller handles the next read instruction in a similar manner to the example of Fig. can continue in 23.

[0154] Fig. Figure 25 is a flowchart of an embodiment of Process 2500, which indicates that a repetition of a read is to be performed in a mixed current-force reading scheme. The process is an alternative to sending a repetition signal (e.g., 1 or 0), as in Figure 25. Fig. 23 and Fig. Figure 24 illustrates this. Process 2500 is initiated when the storage controller determines that the current-force-referenced read has failed. Step 2502 involves the storage device calculating a cycle redundancy check (CRC) for a data pattern. This can be any data pattern. Step 2504 involves the storage controller inverting the CRC. Inverting the CRC means changing each 1 to a 0 and each 0 to a 1. Step 2506 involves the storage device sending the data pattern and the inverted CRC to the storage controller. In one embodiment, the timing diagram of Fig. 24 after the first read, modified by the storage device sending the data pattern on the DQ lines and sending the inverted CRC signal instead of the repeat signal of 1.

[0155] Step 2508 involves the memory controller calculating the CRC for the data pattern it received. Step 2510 involves the memory controller comparing the calculated CRC with the CRC it received from the storage device. The memory controller determines that the calculated CRC value is inverted compared to the received CRC value. Step 2512 therefore involves the memory controller determining that it should reissue the read instruction.

[0156] Fig. Figure 26A is a diagram illustrating components of an embodiment of a memory chip 292 with a programmable ECC engine. The memory chip 292 comprises a memory array 502 and a programmable ECC engine 569. The programmable ECC engine 569 includes a data register 2602, which stores data, and a codeword register 2604, which stores a codeword. In one embodiment, the codeword includes the data and parity bits (or ECC). Data from the host is received via a host bus 2610 and temporarily stored in the data register 2602. The data is encoded by the ECC engine 569 into a codeword, which is temporarily stored in the codeword register 2604. The codeword (or ECC codeword) is transferred from the codeword register 2604 via a memory bus 2612 and programmed into the memory array 502.When reading from memory array 502, a codeword read from memory array 502 is transferred via memory bus 2612 and temporarily stored in codeword register 2604. The data read from memory array 502 is decoded by the ECC engine 569 into corrected data, which is temporarily stored in data register 2602. The corrected data is provided to the host via host bus 2610. In one embodiment, data register 2602 is capable of storing 256 bits, and codeword register 2604 is capable of storing 256 bits plus a number of check (or parity) bits. Host bus 2610 can have a width of, for example, 8, 16, or 32 bits. Memory bus 2612 can, for example, have a width equal to or greater than the number of bits in the codeword. In one embodiment, the host bus 2610 is a DDR bus.

[0157] The ECC Engine 569 outputs a Valid / Err signal indicating whether the ECC Engine determines that decoding was successful (Valid) or failed (Err). Depending on the ECC mode, the ECC Engine 569 can correct up to a limited number of errors in the codeword. If the codeword contains too many errors, the ECC Decoder 569 is unable to remove them all. Furthermore, the ECC Decoder determines that decoding was unsuccessful and reports this as an uncorrectable error. In some cases, the ECC Decoder 569 may report that decoding was successful (Valid) even though the decoding was actually unsuccessful; this is referred to here as miscorrection (or undetectable error).

[0158] The programmable ECC engine 569 has two or more decoding modes. The programmable ECC engine 569 has an input that allows selection of the ECC mode. The different ECC modes have different rates of uncorrectable bit errors. In one embodiment, for example, the ECC modes can be selected by choosing the number of correctable bits in the codeword. Thus, selecting from the different ECC modes allows selection of the correction power. For example, the input can allow a selection of anything between correcting two and nine erroneous bits in the codeword. However, there can be a trade-off between correction power and the rate of uncorrectable bit errors. That is, a decoding mode with more correction power may have a higher probability of miscorrecting.For example, a first mode can correct up to six faulty bits in the codeword with a first probability of miscorrection at a given raw bit error rate (RBER). A second ECC mode can correct up to nine faulty bits in the codeword with a second probability of miscorrection at the given RBER, where the second probability of miscorrection is greater than the first. However, the RBER can be lower when the second ECC mode is used. For example, the RBER might be approximately 10⁻³ when the first ECC mode is used and approximately 10⁻⁴ when the second ECC mode is used. The lower RBER when using the second ECC mode can result in approximately the same miscorrection rate when both the first and second ECC modes are used.In one embodiment, the choice of decoding mode is based on the target raw bit error and a compromise between a tolerable known ECC error and an undetected ECC error. In another embodiment, both error correction modes use a Bose-Chaudhuri-Hocquenghem (BCH) decoding process.

[0159] Fig. Figure 26B is a diagram illustrating components of an embodiment of an integrated memory assembly 570 with a programmable ECC engine. The integrated memory assembly 570 includes a memory structure chip 580 and a control chip 590. The control chip 590 includes a programmable ECC engine 569. The programmable ECC engine 569 can be programmed in the same way as the programmable ECC engine 569 on the memory chip 292 in Figure 26B. Fig. 26A. One difference is that the codeword is transmitted between the ECC engine 569 and the memory array 502 via signal paths 594, which were discussed above.

[0160] Fig. Figure 27 is a flowchart of an embodiment of a process 2700 for reading data stored in reversible resistive memory cells using a programmable ECC engine. In one embodiment, the memory cells are MRAM cells. In one embodiment, each memory cell has a two-pole selector element in series with a reversible resistive memory element. In another embodiment, each memory cell has a two-pole selector element in series with an MRAM memory element. In one embodiment, the memory cells (e.g., MRAM cells) are located in a crosspoint memory array having first and second traces, with each respective non-volatile memory cell connected between one of the first traces and one of the second traces. In one embodiment, the process 2700 is performed by an ECC engine on the same chip as the memory cells, as shown in Figure 27. Fig. 26A. In one embodiment, the process 2700 is performed by an ECC engine on a control chip connected to a chip containing the memory cells, as in Fig. 26B.

[0161] Step 2702 involves reading a codeword from a group of memory cells using a referenced read. In one embodiment, a current-force referenced read is used. The memory cells collectively store an ECC codeword. In one embodiment, the ECC codeword is transferred from the memory array 502 to a codeword register 2604. In one embodiment, there is a first RBER for this ECC codeword. For example, the first RBER might be approximately 10⁻³.

[0162] Step 2704 includes executing an ECC decoder 529 on the codeword acquired using the referenced read. The ECC decoder 529 is executed using a first ECC mode with a first correction rate capable of correcting an initial number of bits in the codeword. For example, the first ECC mode may be capable of correcting up to six erroneous bits in the codeword. In one embodiment, the system control logic 560 on chip 292 selects the correction rate. In one embodiment, the system control logic 560 sends a control signal to the ECC decoder 529 to select the correction rate. The first ECC mode has a first probabilistic user bit error rate (PUBER) when a certain raw bit error rate (RBER) is present. The PUBER relates to the probability of an uncorrectable error and could also be referred to as the uncorrectable bit error rate.It should be noted that the PUBER corresponds to the cases in which the ECC decoder 529 reports that decoding has failed. For example, with an RBER of 3*10^-3, the PUBER might be approximately 10^-6.6 for the first ECC mode. The first mode has a first probability of an undetectable error (PUER) given a certain raw bit error rate (RBER). For example, with an RBER of 3*10^-3, the PUER might be approximately 10^-22.4 for the first ECC mode. It should be noted that the PUER corresponds to cases in which the ECC decoder 529 reports that decoding was successful, even though there are one or more bit errors in the data output by the ECC decoder 529.

[0163] Step 2706 determines whether the decoding was successful. This determination is made by the programmable ECC Engine 569. It is possible for the ECC Engine 569 to report that the decoding was successful even though one or more bits in the data are faulty, referred to here as either a miscorrection or an undetectable error. If the decoding was successful (as reported by the ECC Engine), the decoded data is provided to the host in step 2708. The decoded data in step 2708 refers to the data that the ECC Engine 569 outputs when it reports that the decoding was successful (or valid). As mentioned earlier, in the case of a miscorrection (or an undetectable error), the data output by the ECC Engine 569 will contain one or more faulty bits. In one embodiment, the data is provided to the host via a DDR bus.

[0164] If decoding fails (as reported by the ECC engine), the group of memory cells is read using an SRR in step 1710. In one embodiment, the SRR is a current-force SRR. In one embodiment, step 2710 is similar to step 1308. In one embodiment, process 1700 is used for the SRR. In one embodiment, there is a second RBER for this ECC codeword. For example, the second RBER might be approximately 10⁻⁴. Note that one embodiment of the SRR in step 2710 is more accurate than an embodiment of the read referenced in step 2704, resulting in a lower RBER.

[0165] Step 2712 includes running the ECC decoder 569 on the codeword to decode and correct the data read using the SRR. The ECC decoder is run using a second ECC mode with a second correction rate, which can correct a second number of bits in the codeword. The second correction rate can correct a larger number of bits than the first correction rate used in step 2704. For example, the first correction rate could correct up to six erroneous bits in the codeword, whereas the second correction rate could correct up to nine erroneous bits in the codeword. The second ECC mode has a second probability of an uncorrectable error (PUBER) at a given raw bit error rate (RBER). The second PUBER is lower than the first PUBER of the first ECC mode (i.e., the second ECC mode has more correction power than the first ECC mode).For example, with an RBER of 3*10^-3, the PUBER could be approximately 10^-9.5 for the second ECC mode (compared to approximately 10^-6.6 for the first ECC mode). However, it should be noted that the RBER in step 2712 could be better than the RBER in step 2704, resulting in an even greater improvement in the PUBER. The second ECC mode has a second probability of an undetectable error (PUER) given the same raw bit error rate mentioned in step 2704. The second probability of an undetectable error is greater than the first probability for the first ECC mode—assuming the same RBER. For example, with a PUER of 3*10^-3, the PUBER could be approximately 10^-14.3 for the second ECC mode (compared to approximately 10^-22.4 for the first ECC mode). However, the RBER may be lower when using the second ECC mode than when using the first ECC mode.For example, the RBER might be approximately 10^-3 when the first ECC mode is used (step 2704), but approximately 10^-4 when the second ECC mode is used (step 2712). This lower RBER for the second ECC mode can offset the higher probability of PUER for the second ECC mode (assuming the same RBER). Thus, the PUER for steps 2704 and 2712 can be approximately the same.

[0166] Thus, data read using self-referencing reads has a lower RBER than data read using referenced reads. Furthermore, a reduction in the RBER reduces the error error correction rate in the second ECC mode. In one embodiment, the PUER when using the second ECC mode in step 2712 is essentially the same as the PUER when using the first ECC mode in step 2704. In another embodiment, the PUER when using the second ECC mode in step 2712 is lower than the PUER when using the first ECC mode in step 2704. However, it is not an absolute requirement that the PUER when using the second ECC mode in step 2712 be equal to or lower than the PUER when using the first ECC mode in step 2704. As explained in more detail below in conjunction with the Fig. 29 and Fig. As discussed in section 30, the lower RBER in an embodiment of SRR in step 2710 (relative to the read mentioned in step 2702) can substantially attenuate the higher PUER for the second ECC mode (assuming the same RBER as the first ECC mode).

[0167] In one embodiment, the ECC decoder is executed on the data derived from step 1712 of the SRR. Fig. 17 are generated. That is, in one embodiment, the ECC decoder is executed with the data after the second read of the SRR and the comparison of the stored value from the first read (see steps 1710 and 1712 of Fig. 17). Optionally, the ECC decoder can be run in second ECC mode on the data from the first SRR read (see steps 1702 - 1705 of Fig. 17).

[0168] Step 2714 determines whether the decoding of step 2712 was successful. As with step 2706, this determination is based on whether the ECC engine 569 reports that the decoding was successful. Note that there is a small probability of error correction, meaning that even though the decoding was successful, an error may still be present in the data. If the decoding was successful, the decoded (and in most cases fully error-corrected) data is provided to the host in step 2716. In one embodiment, the data is provided to the host via a DDR bus. If the decoding of step 2712 failed (as determined by the ECC decoder), an error message may be returned to the host in step 2718.

[0169] Fig. Figure 28 is a block diagram illustrating further details of an embodiment of a programmable ECC decoder 529. The one in Fig. The ECC decoder 529, shown in Figure 28, uses a Bose-Chaudhuri-Hocquenghem (BCH) decoding process. The ECC decoder 529 inputs a codeword (which includes data and ECC bits). The codeword is fed into input flops 2802. The input flops 2802 provide the codeword to the syndrome generator 2804, the syndrome validator 2810, and the XOR gate 2812. The ECC decoder 529 also inputs a mode selection signal, which specifies the number of bits to be corrected. The mode selection signal is provided to the error localizer polynomial (ELP) generator 2806. The ECC decoder 529 outputs corrected data from the output flops 2814. The ECC decoder 529 also outputs a "Valid / Error" signal, indicating whether the data output from output flops 2814 is valid or whether the codeword was uncorrectable. The ECC decoder 529 also outputs an error pattern, which could contain up to 9 bit errors.In one embodiment, the ECC decoder 529 outputs an error count, which indicates the number of bit errors in the data output by the output flops 2814.

[0170] The syndrome generator 2804 is capable of calculating syndromes for the input codeword. Techniques for syndrome generation are known to the average person skilled in the art. In one embodiment, the syndrome generator 2804 generates multiple syndromes, which are passed on in parallel to the ELP generator 2806. Furthermore, in one embodiment, there is no clock signal to be controlled when the syndromes are passed on to the ELP generator 2806. This parallel and asynchronous operation achieves fast decoding. In another embodiment, there is a clock signal used for control when each syndrome is passed on to the ELP generator 2806.

[0171] The ELP Generator 2806 computes one or more fault localizer polynomials from the syndromes. A fault localizer polynomial contains information about the fault locations. Example algorithms that could be executed by the ELP Generator 2806 include, but are not limited to, the Peterson-Gorenstein-Zieler algorithm, the Euclid algorithm, the Berlekamp-Massey algorithm, and the inversionless Berlekamp-Massey algorithm (iBMA). In one embodiment, the ELP Generator 2806 is capable of generating a number of fault localizer polynomials, each of a different degree. More precisely, the ELP Generator 2806 is capable of generating coefficients for such fault localizer polynomials. In one embodiment, the ELP Generator 2806 is capable of generating coefficients for fault localizer polynomials of degrees two through nine.The degree of the error-locator polynomial output by the ELP Generator 2806 is selectable. For example, the ELP Generator 2806 could output an error-locator polynomial of degree six, degree nine, and so on. Table I shows a format of an example output from the ELP Generator. Table I shows a format for various sets of coefficients that the ELP Generator 2806 can provide for the Root Finder 2808. The non-zero entries are coefficients generated by the ELP Generator 2806. In one embodiment, each coefficient is a sequence of nine bits. Table I ELP2: {0, 0, 0, 0, 0, 0, c33, c32, c31, 0} ELP3: {0, 0, 0, 0, 0, 0, c33, c32, c31, c30} ELP4: {0, 0, 0, 0, c55, c54, c53, c52, c51, 0} ELP5: {0, 0, 0, 0, c55, c54, c53, c52, c51, c50} ELP6: {0, 0, c77, c76, c75, c74, c73, c72, c71, 0} ELP7: {0, 0, c77, c76, c75, c74, c73, c72, c71, c70} ELP8: {c99, c98, c97, c96, c95, c94, c93, c92, c91, 0} ELP9: {c99, c98, c97, c96, c95, c94, c93, c92, c91, c90}

[0172] The examples in Table I can be used to correct between two and nine bits in the codeword. Thus, Table I corresponds to an example where there are eight ECC modes. For example, ELP6 is used to correct up to six error bits in the codeword, while ELP9 is used to correct up to nine error bits in the codeword. There are a total of ten values ​​for each set of coefficients in Table I, based on the maximum case of ELP9. That is, ELP9 has ten non-zero coefficients. In an embodiment corresponding to the example in Table I, the Root Search 2808 has ten inputs, so each input receives one of the ten values ​​in Table I. The ELP Generator 2806 has one input that receives a value (i.e., a mode selection signal) for the number of bits to be corrected. For example, the value could be a four-bit code to indicate one of the ELP2 modes by ELP9.The state machine 562 can provide the four-bit code to the ELP generator 2806.

[0173] As mentioned above, the ELP generator 2806 operates asynchronously in one embodiment. That is, the ELP generator 2806 has no clock input. Instead, in an asynchronous embodiment, the ELP generator 2806 receives and processes all syndromes in parallel, which provides fast operation. In an asynchronous embodiment, the ELP generator 2806 uses recursion to generate the coefficients for the fault localizer polynomials. In a synchronous embodiment, the ELP generator 2806 has a clock input and operates synchronously. For example, in a synchronous embodiment, the syndromes can be fed into the ELP generator 2806 individually.

[0174] The Root Finder 2808 is capable of locating roots in the error-locator polynomial whose coefficients are received by the ELP Generator 2806. In one embodiment, the Root Finder 2808 uses the Chien search algorithm, but other techniques could be used to locate roots in the error-locator polynomial. The same hardware can be used regardless of the degree of the error-locator polynomial due to the position of the zeros in Table I.

[0175] The syndrome validator 2810 recalculates the syndrome after the roots of the error-locator polynomial have been found by the root search 2808. The syndrome validator 2810 outputs a "Valid / Err" signal to indicate whether the syndromes are correct.

[0176] Thus, the ECC modes corresponding to ELP2 through ELP9 provide progressively higher error correction capabilities. However, the error correction rate can increase from ELP2 to ELP9. For example, ELP6 corrects up to six error bits in the codeword, while ELP9 corrects up to nine error bits in the codeword. ELP9 may, however, have a higher probability of error correction than ELP6 for a given RBER (Reference Rate of Error). An error correction means that the Syndrome Validator 2810 will report that the result is valid, even though one or more errors are still present in the "corrected data." As mentioned above, however, the RBER may be lower when the ECC mode with the higher probability of error correction is used. This lower RBER can result in the probability of error correction being approximately the same for both ECC modes.

[0177] In one embodiment, the programmable ECC decoder 529 is fully implemented in hardware. In another embodiment, the syndrome generator 2804, the ELP generator 2806, the root search 2808, and the syndrome validator 2810 are each implemented with logic gates such as AND, NAND, OR, NOR, XOR, etc. Therefore, the syndrome generator 2804, the ELP generator 2806, the root search 2808, and the syndrome validator 2810 can all be implemented as combinational logic circuits. In another embodiment, the programmable ECC decoder 529 operates asynchronously (i.e., without a clock). Thus, the syndrome generator 2804, the ELP generator 2806, the root search 2808, and the syndrome validator 2810 can all operate asynchronously. In another embodiment, the programmable ECC decoder 529 operates synchronously (i.e., with one clock).

[0178] Fig. Figure 29 is a graph illustrating an example of a probabilistic user bit error rate (PUBER) versus a raw bit error rate (RBER). The PUBER can also be referred to as the uncorrectable bit error rate. The uncorrectable bit error rate refers to errors that remain after decoding. The x-axis, representing raw bit errors, is labeled -Log10(RBER). The y-axis, representing the probability of the uncorrectable bit error rate, is labeled -Log10(PUBER). Plots 2910 and 2920 represent two modes with different numbers of correctable bits. Plot 2910 represents an ECC mode that can correct more bits than the ECC mode in Plot 2920.For example, plot 2910 could represent an ECC mode in which the ECC engine is able to correct up to nine error bits (t = 9) in the codeword, while plot 2920 could represent an ECC mode in which the ECC engine is able to correct up to six error bits (t = 6) in the codeword. The plots show that the ECC mode with the greater correction capability has a lower probability of a decoding error (or PUBER) given the same raw bit error rate (RBER).

[0179] Fig. Figure 30 is a graph that illustrates an example of a probabilistic undetectable error (PUER) versus an error count. As mentioned above, PUER can be described as the undetectable error rate. The x-axis represents the error count. The y-axis, representing the probabilistic undetectable error, is labeled -Log10(PUER). The two plots, 3101 and 3020, represent different RBERs. Plot 3010 represents an RBER of 10⁻⁴, and plot 3020 represents an RBER of 10⁻³. In one embodiment, the RBER for the SRR will be lower (e.g., step 2710 in process 2700) than for the referenced read (e.g., step 2702 in process 2700). For example, the RBER for the referenced read might be approximately 10⁻³, but decrease to approximately 10⁻⁴ for the SRR. Plots 3010 and 3020 show that as the number of errors increases, so does the probability of an undetectable error.Furthermore, a comparison of 3010 with plot 3020 indicates that the error-incorrection rate (PUER) will decrease in response to a lower raw bit error rate in the codeword.

[0180] An ECC engine mode capable of correcting more errors may therefore have a higher probability of an undetected error (or miscorrecting) when the same RBER is assumed. However, the RBER may be lower when SRR is performed than when the referenced read is performed. The lower RBER in practice can compensate for the higher probability of an undetected error at the same RBER. The dashed line 3030 corresponds to an error count of 9 for plot 3010, which may correspond to running the programmable ECC engine in an ECC mode with up to 9 correctable bits (and an RBER of 10⁻⁴). In one embodiment, this 9-bit correctable mode is described in step 2712 in Fig. 17 is used. The dashed line 3040 corresponds to an error count of 6 for plot 3020, which may correspond to running the programmable ECC engine in an ECC mode with up to 6 correctable bits (and an RBER of 10^-3). In one embodiment, this 6-bit correctable mode is used in step 2704 in Fig. 27. It should be noted that the PUER in ECC mode, used for both referenced reads and SRR, may be approximately the same. For example, the PUER may be different in both ECC modes (e.g., in steps 2704 and 2712 in Fig.27) for both are approximately 10^-29. Depending on factors such as the RBER when applying each ECC mode, the PUER for the second ECC mode could be better (i.e., lower) than the PUER for the first ECC mode; the PUER for the second ECC mode could be essentially the same as the PUER for the first ECC mode; or the PUER for the second ECC mode could be slightly worse (i.e., higher) than the PUER for the first ECC mode. However, the significantly better (lower) RBER when using an embodiment of the second ECC mode leads to a substantial reduction in the PUER for an embodiment of the second ECC mode. For example, a comparison of the PUER for plots 3010 and 3020 for an error count of 9 shows that there is approximately 10 orders of magnitude between these two cases (10^-19 vs. 10^-29).

[0181] Therefore, using the second ECC mode with its higher self-reference read correction capability results in a lower probability of an uncorrectable error relative to the first ECC mode with its lower correction capability. For example, using an ECC mode that can correct nine bits for self-reference reads results in a lower probability of an uncorrectable error than using the ECC mode that can correct up to six bits. Furthermore, although the second ECC mode may have a higher PUER than the first ECC mode for the same RBER, the RBER present when using the second ECC mode may be lower than the RBER when using the first ECC mode. Therefore, considering the lower RBER, the second ECC mode may have approximately the same PUER as the first ECC mode (or even a slightly better PUER).

[0182] In light of the foregoing, it is evident that, from a first perspective, a device comprises a memory array having a plurality of memory cells with reversible resistivity and a control circuit connected to the memory array. The control circuit is configured to read a group of selected memory cells using a referenced read. The control circuit is configured to decode data read from the group using a referenced read with a first error correction code (ECC) mode capable of correcting up to a first number of bits in the group. The control circuit is configured to read the group of selected memory cells using a self-referenced read in response to an error, in order to decode the data in the group using the first ECC mode.The control circuit is set up to decode data read from the group using self-referencing read with a second ECC mode capable of correcting up to a second number of bits in the group, where the second number of bits is greater than the first number of bits.

[0183] Secondly, to support the first point, the first ECC mode has a lower initial error correction rate for a given raw bit error rate, while the second ECC mode has a higher initial error correction rate for the same raw bit error rate. Data read using self-referenced reads has a lower raw bit error rate than data read using referenced reads. A reduction in the raw bit error rate reduces the error correction rate in the second ECC mode.

[0184] In a third aspect, the control circuitry, to support the first or second aspect, includes a programmable ECC engine. The programmable ECC engine is configured to compute coefficients for a fault localizer polynomial of degree n when the first ECC mode is executed, where n is an integer. The programmable ECC engine is configured to compute coefficients for a fault localizer polynomial of degree m when the second ECC mode is executed, where m is an integer greater than n.

[0185] In a fourth aspect, to support the third aspect, the programmable ECC engine is located on the same semiconductor chip as the memory array.

[0186] In a fifth aspect, the programmable ECC engine is located on a control semiconductor chip to support the third aspect. The memory array is located on a memory structure chip that is connected to the control semiconductor chip.

[0187] In a sixth aspect, the control circuitry supporting the first five aspects includes a programmable ECC engine configured to generate syndromes for a codeword formed from data read from memory cells. This programmable ECC engine is also configured to compute coefficients for a fault localizer polynomial based on parallel processing of the syndromes.

[0188] In a seventh aspect, the programmable ECC engine is set up to support one of the first to sixth aspects by operating asynchronously to calculate the coefficients.

[0189] In an eighth aspect, to support one of the first to seventh aspects, each memory cell with reversible resistivity has a magnetoresistive direct access memory element (MRAM).

[0190] In a ninth aspect, to support one of the first to eighth aspects, each memory cell with reversible resistivity has a bipolar selector element in series with a memory element with reversible resistivity.

[0191] In a tenth aspect, the two-pole selector element features an ovonic threshold switch (OTS) to support the ninth aspect.

[0192] In an eleventh aspect, the memory array, to support any one of the first through ninth aspects, has a plurality of first traces and a plurality of second traces. Each of the plurality of traces is connected between a corresponding first trace and one of the second traces.

[0193] One embodiment includes a method for reading memory cells. The method involves reading a codeword from a group of magnetoresistive random-access memory (MRAM) cells in a crosspoint memory array on a semiconductor chip using a current-force referenced read. The method involves inputting the codeword read by the current-force referenced read into an error correction (ECC) engine located on the semiconductor chip. The method involves providing decoded data from the ECC engine to a host, which responds to the ECC engine reporting a successful decoding of the codeword read using the current-force referenced read.The procedure involves reading the codeword from the group of MRAM cells in the crosspoint memory array using a current-force self-referencing read in response to the ECC engine reporting an error decoding the codeword read using the current-force self-referencing read. The procedure involves inputting the codeword read by the current-force self-referencing read into the ECC engine. The procedure involves providing decoded data from the ECC engine to the host, which responds to the ECC engine reporting a successful decoding of the codeword read using the current-force self-referencing read.

[0194] One embodiment includes a memory system comprising a crosspoint memory array, a programmable error correction (ECC) engine, and a control circuit. The crosspoint memory array has a plurality of first traces, a plurality of second traces, and a plurality of non-volatile memory cells. Each individual memory cell is connected between one of the first traces and one of the second traces. Each memory cell has a magnetoresistive random-access memory (MRAM) element and a threshold switching selector connected in series with the MRAM element. The programmable ECC engine is configured to decode a codeword while correcting up to a selectable number of bits in the codeword. The control circuit reads a codeword from a group of memory cells using a referenced read.The control circuit instructs the programmable ECC engine to decode the codeword read using the referenced read operation, correcting up to n bits in the codeword. The control circuit returns decoded data in response to the decoding of the codeword read from the group using the referenced read operation. The control circuit reads the codeword from the group of memory cells using a self-referenced read operation in response to the ECC engine's inability to decode the codeword read from the group using the referenced read operation. The control circuit instructs the programmable ECC engine to decode the codeword read using the self-referenced read operation, correcting up to m bits in the codeword, where m is then greater than n.The control circuit returns decoded data in response to decoding the codeword read from the group using self-referencing reading.

[0195] For the purposes of this document, reference in the description to “one embodiment”, “some embodiments” or “another embodiment” may be used to describe different embodiments or the same embodiment.

[0196] For the purposes of this document, a connection can be a direct connection or an indirect connection (e.g., via one or more other parts). In some cases, when an element is described as connected or coupled to another element, the element may be directly connected to the other element or indirectly connected to the other element via intermediate elements. When an element is described as directly connected to another element, there are no intermediate elements between the element and the other element. Two devices are "in communication" when they are connected to each other, directly or indirectly, such that they can transmit electronic signals to each other.

[0197] For the purposes of this document, the term “based on” can be read as “at least partially based on”.

[0198] For the purposes of this document, without additional context, the use of numerical expressions such as a "first" object, a "second" object, and a "third" object may not imply a sorting of objects, but may instead be used for identification purposes to distinguish between different objects.

[0199] The preceding detailed description has been provided for illustrative and descriptive purposes. It is not intended to be exhaustive or to limit the exact form disclosed. Many modifications and variations are possible, taking into account the teaching stated above. The described embodiments have been chosen to best explain the principles of the proposed technology and its practical application, and thus to enable other skilled persons to best utilize it in various embodiments and with various modifications suitable for their respective intended uses. It is intended that the scope is defined by the claims included herein.

Claims

[1] facility, having: a memory array (502) comprising a plurality of memory cells (701) with reversible resistivity; and a control circuit in communication with the memory array (502), wherein the control circuit (502) is configured to: to read a group of selected memory cells (701) using a referenced read; Decode data read from the group using referenced reading with a first error correction code (ECC) mode capable of correcting up to a first number of bits in the group; to read the group of selected memory cells (701) using a self-referencing read in response to an error, in order to decode the data in the group using the first ECC mode; and Decode data read from the group using self-referencing with a second ECC mode capable of correcting up to a second number of bits in the group, where the second number of bits is greater than the first number of bits. characterized by , that: the first ECC mode exhibits an initial error correction rate for a given raw bit error rate; and The second ECC mode has a second error correction rate that is greater than the first error correction rate for the given raw bit error rate, with data read using self-referenced read having a lower raw bit error rate than data read using referenced read, and a reduction in the raw bit error rate reducing the error correction rate in the second ECC mode. [2] Device according to claim 1, wherein the control circuit comprises a programmable ECC engine (569), wherein the programmable ECC engine (569) is configured to: To compute coefficients for an error-locator polynomial of degree n when the first ECC mode is executed, where n is an integer; and To compute coefficients for an error localizer polynomial of degree m when the second ECC mode is performed, where m is an integer greater than n. [3] Device according to claim 2, wherein the programmable ECC engine (569) is located on the same semiconductor chip (292) as the memory array (502). [4] Device according to claim 2, wherein: the programmable ECC engine (569) is located on a control semiconductor chip (590); and the memory array (502) is located on a memory structure chip (580) which is connected to the control semiconductor chip (590). [5] Device according to claim 1, wherein the control circuit comprises a programmable ECC engine (569) configured to: to generate syndromes for a codeword formed from data read from memory cells (701); and To calculate coefficients for an error localizer polynomial based on parallel processing of the syndromes. [6] Device according to claim 5, wherein the programmable ECC engine (569) is configured to operate asynchronously to compute the coefficients. [7] Device according to claim 1, wherein each memory cell (701) with reversible resistivity comprises a magnetoresistive direct access memory element (MRAM) (1202). [8] Device according to claim 1, wherein each memory cell (701) with reversible resistivity has a two-pole selector element (1204) in series with a memory element (701) with reversible resistivity. [9] Device according to claim 8, wherein the two-pole selector element (1204) comprises an ovonic threshold switch (OTS). [10] Device according to claim 1, wherein the storage array (502) comprises: a large number of first leading lines (1206a - 1206h); and a plurality of second conductive lines (1208a - 1208d), wherein each of the plurality of memory cells (701) is connected between one of the first conductive lines (1206a - 1206h) and one of the second conductive lines (1208a - 1208d). [11] Device according to claim 1, wherein: the referenced reading exhibits a current-power reading; and Self-referencing reading exhibits a current-power-self-referencing reading. [12] Method for controlling a storage system (100) comprising the method: Reading a codeword from a group of magnetoresistive random access memory cells (MRAM cells) (701) in a crosspoint memory array (502) on a semiconductor chip (292) using a current-force referenced read; Input of the codeword, which is read by current-force referenced read, into an error correction code engine (ECC engine) (569) located on the semiconductor chip (292); Providing decoded data from the ECC engine (569) to a host (120) that responds to the ECC engine (569) reporting a successful decoding of the codeword read using current-power-referenced reading; Reading the codeword from the group of MRAM cells (701) in the crosspoint memory array (502) using a current-force self-referenced read in response to the ECC engine (569) reporting an error while decoding the codeword read using the current-force referenced read; Entering the codeword, read by the current-power self-referencing read, into the ECC engine (569); and Providing decoded data from the ECC engine (569) to the host (120), which responds when the ECC engine (569) reports a successful decoding of the codeword read using current-force referenced reading, wherein the procedure further comprises: Selecting a first mode for the ECC engine (569) that is capable of correcting up to a first number of bits in the codeword; Executing the ECC engine (569) in first mode on the codeword read using current-force referenced reading; Selecting a second mode for the ECC engine (569) that is capable of correcting up to a second number of bits in the codeword, the second number being greater than the first number; and Executing the ECC engine (569) in second mode on the codeword read using self-referencing read. [13] Storage system (100), comprising: a crosspoint memory array (502) comprising a plurality of first conductive lines (1206a - 1206h), a plurality of second conductive lines (1208a - 1208d) and a plurality of non-volatile memory cells (701), wherein each respective memory cell (701) is connected between one of the first conductive lines (1206a - 1206h) and one of the second conductive lines (1208a - 1208d), wherein each memory cell (701) comprises a magnetoresistive random access memory element (MRAM element) (1202) and a threshold switching selector (1204) connected in series with the MRAM element (1202); a programmable error correction code engine (ECC) (569) configured to decode a codeword while correcting up to a selectable number of bits in the codeword; and a control circuit that: reads a codeword from a group of memory cells (701) using a referenced reader; instructs the programmable ECC engine (569) to decode the codeword read by the referenced read, while correcting up to “n” bits in the codeword; returns decoded data in response to decoding the codeword read from the group using referenced reading; the codeword from the group of memory cells (701) using a self-referencing read in response to the fact that the ECC engine (569) cannot decode the codeword read from the group using the referenced read; the programmable ECC engine (569) is instructed to decode the codeword read by the self-referencing read, while correcting up to 'm' bits in the codeword, where m is greater than n; and returns decoded data in response to decoding the codeword read from the group using self-referencing reading, where: The programmable ECC engine (569) has a first error correction rate when decoding the codeword while correcting up to "n" bits in the codeword for a given raw bit error rate in the codeword; and the programmable ECC engine (569) has a second error correction rate when decoding the codeword while correcting up to "m" bits in the codeword for the given raw bit error rate in the codeword, wherein the second error correction rate is greater than the first error correction rate, wherein data read using self-referencing reads have a higher bit error rate than data read using self-referencing reads, and wherein the error correction rate decreases when correcting up to "m" bits in the codeword in response to a lower raw bit error rate in the codeword. [14] Storage system (100) according to claim 13, wherein the programmable ECC engine (569) is configured to: to generate syndromes for a codeword read from the group of memory cells (701); and To calculate coefficients for an error localizer polynomial based on parallel processing of the syndromes. [15] Storage system (100) according to claim 14, wherein the programmable ECC engine (569) is configured to operate asynchronously to compute the coefficients. [16] Memory system (100) according to claim 13, wherein the programmable ECC engine (569) is located on the same semiconductor chip (292) as the crosspoint memory array (502). [17] Storage system (100) according to claim 13, wherein: the programmable ECC engine (569) is located on a control semiconductor chip (590); and the memory array (502) is located on a memory structure semiconductor chip (580) which is bonded to the control semiconductor chip (590).

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