DISPLAY FIELD AND DISPLAY DEVICE

Abstract

Display panel with an array substrate (100), wherein the array substrate (100) comprises: multiple pixel circuits (10), wherein the multiple pixel circuits (10) are arranged in an array in a row direction (X) and a column direction (Y), each of the multiple pixel circuits (10) having a pixel driver semiconductor section (11), the pixel driver semiconductor section (11) having two fixed-potential connection nodes (N) and the row direction (X) intersecting the column direction (Y); multiple reference signal lines (Vref), wherein the two fixed-potential connection nodes (N) are electrically connected to at least one of the multiple reference signal lines (Vref);and several pixel interconnect semiconductor sections (12), wherein two interconnect nodes (N) adjacent in a first direction are electrically connected at a fixed potential via one of the several pixel interconnect semiconductor sections (12), and the first direction is parallel to a plane in which the array substrate (100) is arranged; and wherein the several reference signal lines (Vref) comprise a first reference signal line (Vref1) and a second reference signal line (Vref2) extending in series direction (X); the two interconnect nodes (N) at a fixed potential comprise a first node (N1) and a second node (N2); and in one and the same pixel drive semiconductor section (11), the first node (N1) is electrically connected to the first reference signal line (Vref1) and the second node (N2) is electrically connected to the second reference signal line (Vref2);and two pixel control semiconductor sections (11) adjacent in series direction (X) comprise a first pixel control semiconductor section (11-1) and a second pixel control semiconductor section (11-2); and the first node (N1) in the first pixel control semiconductor section (11-1) is electrically connected to the first node (N1) in the second pixel control semiconductor section (11-2) via one of the multiple pixel interconnect semiconductor sections (12), or the second node (N2) in the first pixel control semiconductor section (11-1) is electrically connected to the second node (N2) in the second pixel control semiconductor section (11-2) via one of the multiple pixel interconnect semiconductor sections (12).

Description

CROSS-REFERENCE TO RELATED REGISTRATION The present application claims priority over Chinese patent application No. 202110736811.8, which was filed on June 30, 2021, and whose disclosure is incorporated herein in full by reference. Area Embodiments of the present disclosure relate to the field of display technologies and in particular to a display field and a display device. BACKGROUND Organic light-emitting diodes (OLEDs) are a major focus of research in the field of displays. Compared to liquid crystal displays (LCDs), OLED displays offer the advantages of low energy consumption and production costs, self-illuminating properties, wide viewing angles, and fast response times. Currently, OLED array substrates are beginning to replace conventional LCD array substrates in display applications such as mobile phones, PDAs (Personal Digital Assistants), and digital cameras. The OLED array substrate contains pixel circuits for controlling the light-emitting OLED elements, and these pixel circuits still need improvement. From CN 110 335 564 A, an array substrate is known which includes a pixel circuit containing a driver module whose control end is electrically connected to a first node. CN 105 336 295 A shows a display device comprising a thin-film transistor with a source electrode, a drain electrode and a gate electrode. SUMMARY According to embodiments of the present disclosure, a display field and a display device are provided. The display field comprises a pixel circuit, and the pixel circuit is improved in such a way as to improve the performance of the pixel circuit and thereby the display performance. In a first aspect, according to one embodiment of the present disclosure, a display field is provided. The display field comprises an array substrate, and the array substrate comprises several pixel circuits, a reference signal line, and a pixel interconnect semiconductor section. The multiple pixel circuits are arranged in an array in a row direction and a column direction, each of the multiple pixel circuits has a pixel control semiconductor section, the pixel control semiconductor section has two fixed potential nodes, and the row direction intersects the column direction. The nodes with a fixed potential are electrically connected to the reference signal line. Two nodes adjacent in a first direction with a fixed potential are electrically connected via the pixel link semiconductor section, and the first direction is parallel to a plane in which the array substrate is arranged. In a second aspect, according to an embodiment of the present disclosure, a display device is further provided, and the display device comprises the display field described in the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS To more clearly describe the technical solutions in the embodiments of the present disclosure or the related prior art, the drawings to be used in describing the embodiments or the related prior art are briefly described below. Although the drawings in the following description represent some embodiments of the present disclosure, it is obvious to the person skilled in the art that these drawings can be extended and adapted to other structures and drawings in accordance with the basic concepts of the device structure, the drive method, and the manufacturing method disclosed and specified in the embodiments of the present disclosure. These undoubtedly all fall within the scope of the claims of the present disclosure. Fig. 1 is a structural diagram of a display field according to one embodiment of the present disclosure; Fig.Figure 2 is a schematic diagram of a structural design of a pixel circuit according to an embodiment of the present disclosure; Figure 3 is a structural diagram of a pixel control semiconductor section according to an embodiment of the present disclosure; Figure 4 is a schematic diagram of a circuit structure of a pixel circuit according to an embodiment of the present disclosure; Figure 5 is a schematic diagram of time sequences of a sampling signal and a light emission control signal in the pixel circuit of Figure 4; Figure 6 is a structural diagram of a pixel control semiconductor section, a pixel interconnect semiconductor section, and a reference signal line according to an embodiment of the present disclosure; FigureFigure 7 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 8 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 9 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 10 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; FigureFigure 11 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 12 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 13 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 14 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; FigureFigure 15 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 16 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure; Figure 17 is a structural diagram of a further display field according to an embodiment of the present disclosure; Figure 18 is an enlarged exemplary view of region A in Figure 17; Figure 19 is a further enlarged exemplary view of region A in Figure 17; Figure 20 is a further enlarged exemplary view of region A in Figure 17; Figure 21 is a further enlarged exemplary view of region A in Figure 17; and Figure 22 is a further enlarged exemplary view of region A in Figure 17.Figure 22 is a structural diagram of a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION To clarify the subject matter, the technical solutions, and the advantages of this disclosure, the technical schemes of this disclosure are described clearly and completely below with reference to the drawings and the embodiments. It is obvious that the embodiments described below represent a part, but not the entirety, of the embodiments of this disclosure. All further embodiments that a person skilled in the art obtains based on the basic concepts disclosed and suggested in the embodiments of this disclosure fall within the scope of protection of this disclosure. Fig. 1 is a structural diagram of a display array according to an embodiment of the present disclosure, Fig. 2 is a schematic diagram of a structural layout of a pixel circuit according to an embodiment of the present disclosure, and Fig. 3 is a structural diagram of a pixel driver semiconductor section according to an embodiment of the present disclosure. As shown in Fig. 1, Fig. 2, and Fig. 3, the display array according to the embodiment of the present disclosure comprises an array substrate 100, and the array substrate 100 comprises several pixel circuits 10, a reference signal line Vref, and a pixel interconnect semiconductor section.The multiple pixel circuits are arranged in an array in a row direction (a direction X, as shown in the figures) and in a column direction (a direction Y, as shown in the figures), each of the pixel circuits 10 includes a pixel drive semiconductor section 11 with two nodes N with fixed potential (N1 and N2, as shown in the figures), and the row direction intersects the column direction. The nodes N with fixed potential are electrically connected to the reference signal line Vref. Two nodes adjacent in a first direction with fixed potential N are connected via the pixel link semiconductor section, and the first direction is parallel to a plane in which the array substrate is arranged. First, the basic structure of the display field is described with reference to the structure diagram of the display field shown in Fig. 1. As shown in Fig. 1, the array substrate 100, according to the embodiment of the present application, has several pixel circuits 10 which can be arranged in an array. The several pixel circuits 10 can, for example, be arranged in an array in the row direction X and in the column direction Y, which intersect. For example, the array substrate 100 can also include a driver chip IC, a first gate driver circuit VSR1, a second gate driver circuit VSR2, a power signal line PVDD, a data signal line Vdata, a reference signal line Vref, sampling signal lines Scan1 and Scan2 and a light emission control signal line Emit. The first gate driver circuit VSR1 can have several cascaded shift registers S-VSR, each shift register S-VSR being connected to the pixel circuits 10 via a sampling signal line, and the first gate driver circuit VSR1 being configured to supply a sampling signal to the pixel circuits 10. The driver chip IC supplies a first start signal STV1 to the first gate driver circuit VSR1. Furthermore, as shown in Fig. 1, in the several cascaded shift registers S-VSR, with the exception of a first stage of the shift register S-VSR and a last stage of the shift register S-VSR, the other shift registers S-VSR can supply sampling signals for two adjacent rows of pixel circuits. In this case, two rows of dummy pixel circuits (in Fig.(1 not shown) are provided on the array substrate, each connected to a sampling line of the first stage of the shift register S-VSR and a sampling line of the last stage of the shift register S-VSR, but the dummy pixel circuits are not used for display. The second gate driver circuit VSR2 can have several cascaded shift registers E-VSR, each shift register E-VSR being connected to the pixel circuits 10 via a light emission control signal line Emit, and the second gate driver circuit VSR2 being configured to supply a light emission control signal to the pixel circuits 10. The driver chip IC supplies a second start signal STV2 to the second gate driver circuit VSR2. Furthermore, a clock signal line (not shown in Fig. 1), a high-level signal line (VGH) (not shown in Fig. 1), and a low-level signal line (VGL) (not shown in Fig. 1) can be connected between the first gate driver circuit VSR1 and the driver chip IC, and between the second gate driver circuit VSR2 and the driver chip IC. The driver chip IC supplies clock signals, high-level signals, and low-level signals to the first gate driver circuit VSR1 and the second gate driver circuit VSR2 to ensure that the first gate driver circuit VSR1 can output normal sampling signals and the second gate driver circuit VSR2 can output normal light emission control signals. Several different arrangements are possible for the first gate driver circuit VSR1 and the second gate driver circuit VSR2. As shown in Fig. 1, the array substrate 100 can, for example, have one first gate driver circuit VSR1 and one second gate driver circuit VSR2. The first gate driver circuit VSR1 and the second gate driver circuit VSR2 can be arranged on two opposite sides of the array substrate 100 in a second direction Y. The first gate driver circuit VSR1 and the second gate driver circuit VSR2 can also be arranged on the same side. In another example, the array substrate 100 can have two first gate driver circuits VSR1 and two second gate driver circuits VSR2.Each of the two ends of the sampling signal line is electrically connected to a first gate driver circuit VSR1, and each of the two ends of the light emission control signal line Emit is electrically connected to a second gate driver circuit VSR2, thus ensuring good consistency between the sampling signal in the sampling signal line and the light emission control signal in the light emission control signal line. In another example, the array substrate 100 has two first gate driver circuits VSR1, one of which is electrically connected via sampling signal lines to pixel circuits in odd rows, and the other of which is electrically connected via sampling signal lines to pixel circuits in even rows, thus ensuring that each first gate driver circuit VSR1 has a simple structure.In another example, the array substrate 100 has two second gate driver circuits VSR2, one of which is electrically connected to pixel circuits in odd rows via light emission control signal lines, and the other of which is electrically connected to pixel circuits in even rows via light emission control signal lines, thus ensuring that each of the second gate driver circuits VSR2 has a simple structure. The specific arrangements of the first gate driver circuit VSR1 and the second gate driver circuit VSR2 are not described in the embodiments of this disclosure. The above description of the first gate driver circuit VSR1 and the second gate driver circuit VSR2 merely presents some examples and is not intended to limit the present application.It simply needs to be ensured that the sampling signal and the light emission control signal can be provided normally. For example, a gate driver circuit can be provided that can generate both a sampling signal and a light emission control signal. Furthermore, Fig. 4 is a structural diagram of a pixel circuit according to an embodiment of the present disclosure, and Fig. 5 is a schematic diagram of the time sequences of a sampling signal and a light emission control signal in the pixel circuit in Fig. 4. With reference to Fig. 2, Fig. 4, and Fig. 5, each pixel circuit can have several thin-film transistors. In Fig. 2 and Fig. 4, for illustrative purposes, it is assumed that the pixel circuit has seven thin-film transistors and a storage capacitor, i.e., a 7T1C circuit. With reference to Fig. 2, Fig. 4, and Fig. 5, the operating process of the pixel circuit is briefly described below. With reference to Fig. 2 and Fig.4, where an arbitrary series of pixel circuits is used as an example, a first sampling line Scan1 controls a first reset transistor T5 of the pixel circuit to be switched on or off, and resets a gate potential of a driver transistor T3 when the first reset transistor T5 is switched on. A second sampling line Scan2 controls a data write transistor T2 and a threshold compensation transistor T4 of the pixel circuit to be switched on and off, and stores a data signal on the data signal line Vdata in a gate of the driver transistor T3 and compensates a threshold voltage of the driver transistor T3 when the data write transistor T2 and the threshold compensation transistor T4 are switched on.In some pixel circuit configurations, the scan signal Scan n can also be used to control a second reset transistor T7 of the pixel circuit, turning it on or off, and to reset the anode potential of a light-emitting element when the second reset transistor T7 is turned on. In this case, it is not necessary to provide a separate scan signal line for the second reset transistor T7. In other words, the first sampling signal line can be understood as the sampling signal line connected to a control terminal of the first reset transistor in pixel circuit 10, and the second sampling signal line can be understood as the sampling signal line connected to a control terminal of the data write transistor, a control terminal of the compensation transistor, and a control terminal of the second reset transistor in pixel circuit 10. In general, each array of pixel circuits 10 is connected to at least the first and second sampling signal lines for display purposes. The power signal line PVDD is designed to supply a power voltage to the driver transistor T3, and the voltage at the power signal line PVDD can be a positive voltage. The voltage at a common power signal terminal PVEE can be a negative voltage. The reference signal line Vref is designed to supply a reset voltage signal, and the voltage at the reference signal line Vref can be a negative voltage. The embodiment described above is further described by assuming, as an example, that each transistor in the pixel circuit 10 is a P-transistor. In another optional embodiment, each transistor in the pixel circuit 10 can be an N-transistor, or some of the transistors in the pixel circuit 10 can be P-transistors and some of the transistors in the pixel circuit 10 can be N-transistors. Different enable levels can be provided according to the different transistor types, where the enable level is a level at which the transistor can be switched on. By way of example, the enable level is a high level for an N-transistor and a low level for a P-transistor. As shown in Fig. 5, a control process for the pixel circuit 10 can comprise an initialization stage, a data write stage, and a light emission stage. In the initialization stage, the first sampling signal line, Scan1, provides a low-level signal, and the first reset transistor, T5, is switched on, thus resetting the gate potential of the driver transistor, T3. In the data write stage, the second sampling signal line, Scan2, provides a low-level signal, switching on the data write transistor, T2, and the threshold compensation transistor, T4. The data signal on the data signal line, Vdata, is stored in the gate of the driver transistor, thus compensating the threshold voltage of the driver transistor, and the second reset transistor, T7, is switched on, resetting the anode potential of the light-emitting element.In the light emission stage, the light emission control signal line Emit provides a low-level signal, the light emission control transistors T1 and T6 are switched on, a driver current generated by the driver transistor T3 is passed to the light-emitting element, and the light-emitting element emits light. It should be noted that Fig. 2, Fig. 4 and Fig. 5 are merely examples and are not intended to restrict the present application. Based on the embodiment described above and with further reference to Fig. 2 and Fig. 3, the pixel-driver semiconductor section 11 can be an active layer in a thin-film transistor. Fig. 3 shows, by way of example, the pixel-driver semiconductor section 11 in 2 rows × 3 columns of pixel circuits 10. With reference to Fig. 2 and Fig. 3, the pixel-driver semiconductor section 11 has two fixed-potential nodes N such as N1 and N2, as shown in Fig. 2 and Fig. 3, and the two fixed-potential nodes N1 and N2 can be connected to input terminals of different thin-film transistors, wherein, for example, the first node N1 is connected to an input terminal (source or drain) of the first reset transistor T5 and the second node N2 is connected to an input terminal (source or drain) of the second reset transistor T7.The two fixed-potential nodes N1 and N2 are electrically connected to the reference signal line Vref and configured to receive a reference signal provided by the reference signal line Vref. This resets the gate of the driver transistor T3 in the pixel circuit and the light-emitting element D in the display field, ensuring that the current display state of the display field is not affected by the previous display state and ensuring a good display effect. In this embodiment of the present disclosure, the pixel driver semiconductor section 11 comprises two fixed-potential nodes N1 and N2, thus ensuring a large adjustment range when setting the pixel driver semiconductor section by adjusting the two fixed-potential nodes N1 and N2.Thus, the performance of the pixel driver semiconductor section can be improved in multiple dimensions, which facilitates the improvement of the pixel driver semiconductor section's performance in multiple dimensions and the improvement of the overall pixel circuit and display field. Furthermore, according to the embodiment of the present disclosure, the display field also includes the pixel interconnect semiconductor section (not shown in Figs. 2 and 3), wherein two adjacent fixed-potential nodes arranged in the first direction are electrically connected via the pixel interconnect semiconductor section, thereby simplifying signal transmission between the two fixed-potential nodes, improving signal consistency in the pixel driver semiconductor section, and enhancing the display effect of the display field. It should be noted that the specific orientation of the first direction is not limited in the embodiment of the present disclosure, and the first direction may be the row direction, the column direction, or a direction whose included angle with the row direction or the column direction is an acute angle. The first direction is described in detail below according to specific arrangements of the pixel interconnect semiconductor section. In summary, the display field according to the embodiment of the present disclosure provides two fixed-potential nodes for the pixel driver semiconductor section, and both fixed-potential nodes are electrically connected to the reference signal line, so that the light-emitting element and some nodes in the pixel circuit are reset, ensuring that the current display state of the display field is not affected by the previous display state and that the display effect is good. Furthermore, the pixel driver semiconductor section has two fixed-potential nodes, so that the adjustment range for subsequent adjustment of the pixel driver semiconductor section is relatively large, which facilitates the improvement of the performance of the pixel driver semiconductor section in several dimensions and the improvement of the performance of the entire pixel circuit and the display field.Furthermore, according to the embodiment of the present disclosure, the display field also comprises the pixel interconnect semiconductor section, and two adjacent fixed-potential nodes arranged in the first direction are electrically connected via the pixel interconnect semiconductor section, thus simplifying the signal transmission between the two fixed-potential nodes and improving the signal consistency in the pixel drive semiconductor section and the display effect of the display field. Based on the embodiment described above and with further reference to Fig. 2 and Fig. 4, the pixel circuit 10 comprises the driver transistor T3, the light-emitting element D, the first reset transistor T5, and the second reset transistor T7. The driver transistor T3 is configured to control the light-emitting element D to illuminate, the first reset transistor T5 is configured to control the reference signal to reset the gate potential of the driver transistor T3, and the second reset transistor T7 is configured to control the reference signal to reset the anode potential of the light-emitting element D. The array substrate 100 further comprises the first scanning signal line Scan1, which extends in series direction, wherein two overlapping regions are present between the first scanning signal line Scan1 and the pixel drive semiconductor sections 11 in a direction perpendicular to a plane in which the array substrate 100 is arranged, and a channel of the first reset transistor T5 and a channel of the second reset transistor T7 each have pixel drive semiconductor sections in which the two overlapping regions are located. The two fixed-potential nodes N comprise the first node N1 and the second node N2. One terminal of the first reset transistor T5 is electrically connected to the first node N1, and another terminal of the first reset transistor T5 is electrically connected to the gate of the driver transistor T3. One terminal of the second reset transistor T7 is electrically connected to the second node N2, and another terminal of the second reset transistor T7 is electrically connected to the anode of the light-emitting element D. As shown in Fig. 2, the areas where the first scanning signal line Scan1 overlaps with the pixel drive semiconductor sections 11 in the direction perpendicular to the plane in which the array substrate 100 is arranged are, for example, the first reset transistor T5 and the second reset transistor T7. It should be noted that the first reset transistor T5 and the second reset transistor T7 are the first reset transistor T5 and the second reset transistor T7 in two pixel circuits that are adjacent in the column direction; that is, the first reset transistor T5 is the first reset transistor T5 in the pixel circuit in the current stage, and the second reset transistor T7 is the second reset transistor T7 in the pixel circuit in the previous stage.When a sampling signal is transmitted on the first sampling signal line Scan1, the first reset transistor T5 in the pixel circuit in the current stage is configured to reset the gate of the driver transistor T3 in the pixel circuit in the current stage according to a received reference signal, and the second reset transistor T7 in the pixel circuit in the previous stage is configured to reset the anode of the light-emitting element according to the pixel circuit in the previous stage according to a received reference signal. Next, in accordance with the preceding description of the pixel circuit and the pixel drive semiconductor section, the specific arrangements of the reference signal line and the pixel interconnect semiconductor section will be described in detail. Fig. 6 is a structural diagram of a pixel-driver semiconductor section, a pixel-connector semiconductor section, and a reference signal line according to an embodiment of the present disclosure as an implementable embodiment. With reference to Fig. 2 and Fig. 6, the reference signal line Vref comprises a first reference signal line Vref1 and a second reference signal line Vref2, which extend in series and are parallel to each other; the two fixed-potential nodes comprise the first node N1 and the second node N2; and in one and the same pixel-driver semiconductor section 11, the first node N1 is electrically connected to the first reference signal line Vref1 and the second node N2 is electrically connected to the second reference signal line Vref2. The pixel control semiconductor section 11 has the pixel interconnect semiconductor section 12, and the first node N1 and the second node N2 in one and the same pixel control semiconductor section 11 are electrically connected via the pixel interconnect semiconductor section 12. For example, it may be known from the above description that the reference signal received by the first node N1 is used to reset the gate of the driver transistor T3, and the reference signal received by the second node N2 is used to reset the anode of the light-emitting element. Therefore, the first node N1 and the second node N2 must receive different reference signals due to the different structures that need to be reset. Accordingly, in the embodiment of the present disclosure, the reference signal line Vref comprises the first reference signal line Vref1 and the second reference signal line Vref2, which extend in series and are parallel to each other, and the two fixed-potential nodes comprise the first node N1 and the second node N2.and in one and the same pixel control semiconductor section 11, the first node N1 is electrically connected to the first reference signal line Vref1, the second node N2 is electrically connected to the second reference signal line Vref2, and the first reference signal line Vref1 and the second reference signal line Vref2 can provide different reference signals to ensure separate reset of the gate of the driver transistor T3 and the anode of the light-emitting element and to ensure a good effect of the reset of the gate of the driver transistor T3 and the anode of the light-emitting element. With further reference to Fig. 2 and Fig. 6, the pixel driver semiconductor section 11 can also include the pixel interconnect semiconductor section 12, i.e., the pixel interconnect semiconductor section 12 is a part of the pixel driver semiconductor section 11. In particular, the pixel interconnect semiconductor section 12 is part of the same pixel driver semiconductor section 11 for connecting the first node N1 and the second node N2. In this way, it is not necessary to add a process for fabricating the pixel interconnect semiconductor section 12; the pixel interconnect semiconductor section 12 is provided in a simple manner, and the fabrication process is straightforward. As a further implementable embodiment, Fig. 7 is a structural diagram of a further pixel-driver semiconductor section, a further pixel-connector semiconductor section, and a further reference signal line according to an embodiment of the present disclosure, and Fig. 8 is a structural diagram of a further pixel-driver semiconductor section, a further pixel-connector semiconductor section, and a further reference signal line according to an embodiment of the present disclosure. As shown in Fig. 7 and Fig. 8, two fixed-potential nodes N comprise the first node N1 and the second node N2. As shown in Fig. 7, the second node N2 is electrically connected to the reference signal line Vref, and the first node N1 is electrically connected to the reference signal line Vref via the pixel-connector semiconductor section 12 and the second node N2; alternatively, as shown in Fig.Figure 8 shows the first node N1 electrically connected to the reference signal line Vref, and the second node N2 is electrically connected to the reference signal line Vref via the pixel connection semiconductor section 12 and the first node N1. From several pixel control semiconductor sections 11, which are arranged sequentially in the column direction, the second node N2 in the pixel control semiconductor section 11 in the current stage is electrically connected to the first node N1 in the pixel control semiconductor section 11 in the next stage via the pixel connection semiconductor section 12. It is known from the foregoing that the reference signal provided by the reference signal line Vref can be a signal with a negative potential, which can be used to reset both the first node N1 and the second node N2. As shown in Figs. 7 and 8, only one reference signal line Vref is provided, which ensures a simple arrangement of the reference signal line Vref. Furthermore, the first node N1 can be directly electrically connected to the reference signal line Vref, and in this case, the second node N2 can be electrically connected to the reference signal line Vref via the pixel connection semiconductor section 12 and the first node N1, as shown in Fig. 8; alternatively, the second node N2 can be directly electrically connected to the reference signal line Vref, and in this case, the first node N1 can be electrically connected to the reference signal line Vref via the pixel connection semiconductor section 12 and the second node N2, as shown in Fig. 7. In this way, it can be achieved that both the first node N1 and the second node N2 are electrically connected to the reference signal line Vref to ensure that the gate of the driver transistor and the anode of the light-emitting element can be reset so that the display field can show normally. With further reference to Figs. 7 and 8, the second node N2 of the pixel control semiconductor section 11 in the current stage is electrically connected to the first node N1 of the pixel control semiconductor section 11 in the next stage via the pixel connection semiconductor section 12, and thus the multiple pixel control semiconductor sections 11 are connected in the column direction via the pixel connection semiconductor sections 12, forming a continuous semiconductor track. In this way, static electricity can be distributed uniformly along the continuous semiconductor track, and furthermore, the reliability and uniformity of the performance of the pixel control semiconductor sections 11 can be improved in the subsequent high-temperature manufacturing process.Therefore, the control capabilities of the pixel circuits can be essentially consistent, the uniformity of the display can be achieved, and the display effect can be improved. Furthermore, the pixel interconnect semiconductor section 12 and the pixel driver semiconductor section 11 can be arranged in the same layer, made of the same material, and manufactured in the same process, ensuring that the display panel has a simple structure and is easy to manufacture. As a further implementable embodiment, Fig. 9 is a structural diagram of a further pixel-driver semiconductor section, a further pixel-connector semiconductor section, and a further reference signal line according to an embodiment of the present disclosure, and Fig. 10 is a structural diagram of a further pixel-driver semiconductor section, a further pixel-connector semiconductor section, and a further reference signal line according to an embodiment of the present disclosure. As shown in Fig. 9 and Fig. 10, the reference signal line Vref comprises the first reference signal line Vref1 and the second reference signal line Vref2, which extend in series and are parallel to each other, and two fixed-potential nodes N comprise the first node N1 and the second node N2.In the same pixel control semiconductor section 11, the first node N1 is electrically connected to the first reference signal line Vref1, and the second node N2 is electrically connected to the second reference signal line Vref2. Two pixel control semiconductor sections 11, which are adjacent in series, comprise a first pixel control semiconductor section 11-1 and a second pixel control semiconductor section 11-2, and the first node N1 in the first pixel control semiconductor section 11-1 is electrically connected to the first node N1 in the second pixel control semiconductor section 11-2 via the pixel linking semiconductor section 12, or the second node N2 in the first pixel control semiconductor section 11-1 is electrically connected to the second node N2 in the second pixel control semiconductor section 11-2 via the pixel linking semiconductor section. As can be seen from the description above, the reference signal received by the first node N1 is used to reset the gate of the driver transistor T3, and the reference signal received by the second node N2 is used to reset the anode of the light-emitting element. Therefore, the first node N1 and the second node N2 must receive different reference signals due to the different structures that need to be reset. Accordingly, in the embodiment of the present disclosure, the reference signal line Vref comprises the first reference signal line Vref1 and the second reference signal line Vref2, which extend in series and are parallel to each other.and the two fixed-potential nodes comprise the first node N1 and the second node N2, and in the same pixel-driver semiconductor section 11, the first node N1 is electrically connected to the first reference signal line Vref1, the second node N2 is electrically connected to the second reference signal line Vref2, and the first reference signal line Vref1 and the second reference signal line Vref2 can provide different reference signals to ensure separate reset of the gate of the driver transistor T3 and the anode of the light-emitting element and to ensure a good effect of the reset of the gate of the driver transistor T3 and the anode of the light-emitting element. Furthermore, as shown in Fig. 9, in two adjacent pixel control semiconductor sections 11 arranged in series, the first node N1 in the first pixel control semiconductor section 11-1 is electrically connected to the first node N1 in the second pixel control semiconductor section 11-2 via the pixel link semiconductor section 12; and as shown in Fig. 10, in the two adjacent pixel control semiconductor sections 11 arranged in series, the second node N2 in the first pixel control semiconductor section 11-1 is electrically connected to the second node N2 in the second pixel control semiconductor section 11-2 via the pixel link semiconductor section. Thus, several pixel control semiconductor sections 11 are connected to each other in series via the pixel link semiconductor sections 12 such that a continuous semiconductor track is formed.In this way, static electricity can be distributed evenly along the continuous semiconductor track, and furthermore, the reliability and uniformity of the performance of the pixel-drive semiconductor sections 11 can be improved in the subsequent high-temperature manufacturing process. Therefore, the drive capabilities of the pixel circuits can be essentially consistent, display uniformity can be achieved, and the display effect can be improved. It should be noted that the only difference between Fig. 9 and Fig. 10 is that the first pixel-driver semiconductor section 11-1 and the second pixel-driver semiconductor section 11-2 are determined differently. As can be seen from Fig. 9 and Fig. 10, the only difference between Fig. 9 and Fig. 10 is that the first pixel-driver semiconductor section 11-1 in Fig. 9 corresponds to the second pixel-driver semiconductor section 11-2 in Fig. 10, and vice versa. Therefore, the structure shown in Fig. 9 and the one shown in Fig. 10 are identical.In the structure shown in Figure 10, several pixel control semiconductor sections 11 are connected in series via the pixel link semiconductor sections 12 in such a way that a continuous semiconductor track is formed, ensuring that the control capabilities of the pixel circuits are essentially consistent, uniformity of the display is achieved and the display effect is improved. Furthermore, the pixel interconnect semiconductor section 12 and the pixel driver semiconductor section 11 can be arranged in the same layer, made of the same material, and manufactured in the same process, ensuring that the display panel has a simple structure and is easy to manufacture. Based on the embodiments described above, there can be several different arrangement types in which several pixel control semiconductor sections 11 can be connected to each other in series via the pixel connection semiconductor section 12, which are described by using implementable arrangement types among these arrangement types as examples. As one implementable embodiment, with reference to Fig. 9 and Fig. 10, the first node N1 and the second node N2 in the pixel control semiconductor section 11 are arranged in the first direction on two opposite sides of the pixel control semiconductor section 11, the first direction being parallel to the column direction, or the angle between the first direction and the column direction being an acute angle, and the pixel control semiconductor sections 11 in the two pixel circuits have the same pattern. By way of example, in the embodiments of the present disclosure, the first direction is not limited, and the first direction can be parallel to the column direction Y, or the angle between the first direction and the column direction Y is an acute angle. In Figs. 9 and 10, it is assumed, by way of example, that the first direction is approximately parallel to the column direction Y, i.e., the included angle between the first direction and the column direction Y is an acute angle. As shown in Figs. 9 and 10, the patterns of the pixel driver semiconductor sections 11 are also identical in any two pixel circuits, so that the drive capabilities of any two driver circuits can be the same, thereby ensuring good display uniformity of the display field.Furthermore, the patterns of the pixel control semiconductor sections 11 in any two pixel circuits that are identical can further ensure that the pixel control semiconductor sections 11 can be provided in a simple manner and that the mask reticulum has a simple structure in the masking process.Therefore, in the scheme of the embodiment of the present disclosure, the gate of the driver transistor T3 and the anode of the light-emitting element are reset separately, so that the effective resetting of the gate of the driver transistor T3 and the anode of the light-emitting element can be ensured, and several pixel drive semiconductor sections 11 can be connected in series via the pixel link semiconductor sections 12 such that a continuous semiconductor track is formed, so that the basic consistency of the drive capabilities of the pixel circuits can be ensured and the display uniformity can be improved based on achieving display uniformity, and it can be ensured that the pixel drive semiconductor section 11 can be provided in a simple way and that the mask grid has a simple structure in the masking process. It should be noted that in Figures 9 and 10, in the pixel control semiconductor sections 11, the first node N1 and the second node N2 are offset in the column direction Y in two adjacent stages. For example, the second node N2 in the pixel control semiconductor section 11 in the preceding stage is located above the first node N1 in the pixel control semiconductor section 11 in the current stage. This arrangement serves only to simplify the illustration of the pixel interconnect semiconductor section 12 in Figures 9 and 10 and does not restrict the design of the embodiment. For example, in pixel control semiconductor sections 11 on two adjacent stages, the first node N1 and the second node N2 can also be offset in the column direction Y.By adjusting the arrangements of the pixel interconnect semiconductor sections 12, it is ensured that the first node N1 in the first pixel control semiconductor section 11-1 is electrically connected via the pixel interconnect semiconductor section 12 to the first node N1 in the second pixel control semiconductor section 11-2, or in two adjacent pixel control semiconductor sections 11 arranged in series, the second node N2 in the first pixel control semiconductor section 11-1 is electrically connected via the pixel interconnect semiconductor section to the second node N2 in the second pixel control semiconductor section 11-2. As a further implementable embodiment, Fig. 11 is a structure diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section and a further reference signal line according to an embodiment of the present disclosure, Fig. 12 is a structure diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section and a further reference signal line according to an embodiment of the present disclosure, Fig. 13 is a structure diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section and a further reference signal line according to an embodiment of the present disclosure and Fig. 14 is a structure diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section and a further reference signal line according to an embodiment of the present disclosure.Referring to Figs. 11, 12, 13 to 14, the first node N1 and the second node N2 in the pixel driver semiconductor section 11 are arranged in a second direction on two opposite sides of the pixel driver semiconductor section 11, and the second direction is parallel to the plane in which the array substrate is arranged, and the second direction is parallel to the column direction, or the included angle between the second direction and the column direction is an acute angle. In the series direction, the patterns of the pixel driver semiconductor sections 11 in two adjacent pixel circuits arranged sequentially are different, and the patterns of two pixel driver semiconductor sections 11 spaced apart by a pixel driver semiconductor section 11 are the same. By way of example, in the embodiments of the present disclosure, the second direction is not limited, and the second direction can be parallel to the series direction X, or the included angle between the second direction and the series direction X is an acute direction. In Figs. 11, 12, 13 to 14, it is assumed by way of example, for illustration, that the included angle between the second direction and the series direction X is an acute direction. As in Figs. 11, 12, 13 to 14,As shown in Figure 14, the first node N1 and the second node N2 in the pixel control semiconductor section 11 are arranged on two opposite sides of the pixel control semiconductor section 11 in the second direction, so that in pixel control semiconductor sections 11 in two adjacent stages, the first node N1 in the pixel control semiconductor section 11 in the current stage does not overlap with the second node N2 in the pixel control semiconductor section 11 in the previous stage.In this way, the first node N1 in the pixel-driver semiconductor section 11 in the current stage and the second node N2 in the pixel-driver semiconductor section 11 in the previous stage can be arranged side by side in a row, so that the distance between the pixel-driver semiconductor sections 11 in two adjacent stages can be reduced in a column direction and the compact arrangement of the pixel-driver semiconductor sections 11 can be ensured, which facilitates an increase in the number of pixel-driver semiconductor sections 11 per unit area, i.e., an increase in the resolution of the display field. This improves the display effect of the display field.Furthermore, in the series direction, the patterns of the pixel driver semiconductor sections 11 in two adjacent pixel circuits arranged sequentially are different, and the patterns of two pixel driver semiconductor sections 11 separated by a pixel driver semiconductor section 11 are identical. In this way, the first node N1 and / or the second node N2 in two adjacent pixel driver semiconductor sections 11 can be positioned closer together in the series direction, which facilitates the reduction of the extension length of the pixel interconnect semiconductor section 12 and the reduction of the area of ​​multiple pixel driver semiconductor sections 11 in the display field, thereby reducing signal loss during transmission in the pixel interconnect semiconductor sections 12. Moreover, it facilitates the improvement of the display field resolution and the display effect.Therefore, in the scheme of the embodiment of the present disclosure, the gate of the driver transistor T3 and the anode of the light-emitting element are adjusted separately, so that the good effect of resetting the gate of the driver transistor T3 and the anode of the light-emitting element is ensured, and several pixel control semiconductor sections 11 can be connected in series via the pixel connection semiconductor sections 12 such that a continuous semiconductor track is formed, so that the basic consistency of the control capabilities of the pixel circuits is ensured, the resolution of the display field can be improved on the basis of achieving display uniformity, and the display effect of the display field can be improved. Furthermore, in the row direction, the patterns of the pixel control semiconductor sections 11 in the two adjacent pixel circuits, which are arranged sequentially, are different, and the patterns of two pixel control semiconductor sections 11 spaced apart by one pixel control semiconductor section 11 are the same, i.e., in each row, the pixel control semiconductor sections 11 at positions of odd columns have the same structure, and the pixel control semiconductor sections 11 at positions of even columns have the same structure, as shown in Figs. 11, 12, 13 to 14. Furthermore, based on the embodiment described above, as shown in Figs. 11 and 12, in any two rows, the pixel control semiconductor sections 11 at positions of odd columns have the same structure, and the pixel control semiconductor sections 11 at positions of even columns have the same structure. Alternatively, as shown in Figs. 13 and 14, the patterns of the pixel control semiconductor sections 11 at positions of odd columns and the pixel control semiconductor sections 11 at positions of even columns can be arranged in the same way.As shown in Figure 14, in two adjacent rows the pixel control semiconductor sections 11 at positions of odd columns in the first row and the pixel control semiconductor sections 11 at positions of even columns in the second row have the same structure, and the pixel control semiconductor sections 11 at positions of even columns in the first row and the pixel control semiconductor sections 11 at positions of odd columns in the second row have the same structure.In the embodiments of the present disclosure, the specific arrangement of the pixel control semiconductor sections 11 is not restricted, as long as it can be ensured that, in the series direction, the patterns of the pixel control semiconductor sections 11 in two adjacent pixel circuits arranged sequentially are different, and the patterns of two pixel control semiconductor sections 11 spaced apart by a pixel control semiconductor section 11 are the same, thereby ensuring that the pixel control semiconductor sections 11 can be arranged in a compact manner, which facilitates the improvement of the number of pixel control semiconductor sections 11 per unit area, i.e., the improvement of the resolution of the display field. The above embodiments are described below using the example of the first reset transistor, which is a transistor with a single gate. Based on the embodiments described above, further with reference to Figs. 11, 12, 13 to 14, any two adjacent pixel-control semiconductor sections 11, arranged sequentially in the row direction X, comprise the first pixel-control semiconductor section 11-1 and the second pixel-control semiconductor section 11-2; the pixel-control semiconductor section 11, which is arranged in the column direction Y on a first side of the first pixel-control semiconductor section 11-1, is a third pixel-control semiconductor section 11-3, and the pixel-control semiconductor section 11, which is arranged in the column direction Y on a first side of the second pixel-control semiconductor section 11-2, is a fourth pixel-control semiconductor section 11-4. The first node N1 in the first pixel control semiconductor section 11-1, the first node N1 in the second pixel control semiconductor section 11-2, the second node N2 in the third pixel control semiconductor section 11-3 and the second node N2 in the fourth pixel control semiconductor section 11-4 are arranged in series direction X.The first node N1 in the first pixel control semiconductor section 11-1 and the first node N1 in the second pixel control semiconductor section 11-2 are located in series direction X between the second node in the third pixel control semiconductor section 11-3 and the second node in the fourth pixel control semiconductor section 11-4; or the second node N2 in the third pixel control semiconductor section 11-3 and the second node N2 in the fourth pixel control semiconductor section 11-4 are located in series direction X between the first node N1 in the first pixel control semiconductor section 11-1 and the first node N1 in the second pixel control semiconductor section 11-2. As shown by way of example in Fig. 11, Fig. 12, Fig. 13 to Fig. 14, it is provided that the first node N1 and the second node N2 in the pixel control semiconductor section 11 are located on two opposite sides of the pixel control semiconductor section 11 in the second direction, and in the series direction the patterns of the pixel control semiconductor sections 11 are different in two adjacent, sequentially arranged pixel circuits, and the patterns of two pixel control semiconductor sections 11 that are spaced apart by a pixel control semiconductor section 11 are the same. Therefore, it can be ensured that the first node N1 in the first pixel control semiconductor section 11-1, the first node N1 in the second pixel control semiconductor section 11-2, the second node N2 in the third pixel control semiconductor section 11-3, and the second node N2 in the fourth pixel control semiconductor section 11-4 are arranged in series direction X, i.e.in the horizontal direction at the same height. In this way, the pixel-driven semiconductor sections 11 can be arranged compactly, which facilitates increasing the number of pixel-driven semiconductor sections 11 per unit area, i.e., improving the resolution of the display field. In particular, in Fig. 11 and Fig. 13, for illustrative purposes, it is assumed that the first node N1 in the first pixel-driven semiconductor section 11-1 and the first node N1 in the second pixel-driven semiconductor section 11-2 are located in the row direction X between the second node in the third pixel-driven semiconductor section 11-3 and the second node in the fourth pixel-driven semiconductor section 11-4; and in Fig. 12 and Fig.14 is assumed as an example for illustration that the second node N2 in the third pixel control semiconductor section 11-3 and the second node N2 in the fourth pixel control semiconductor section 11-4 are located in series direction X between the first node N1 in the first pixel control semiconductor section 11-1 and the first node N1 in the second pixel control semiconductor section 11-2. In the embodiments described above, using the example of the first reset transistor, which is a transistor with a single gate, it is described in detail that by a sensible arrangement of the pixel control semiconductor sections 11, it can be ensured that the pixel control semiconductor sections are arranged compactly, which facilitates the increase of the number of pixel control semiconductor sections 11 per unit area, i.e. the improvement of the resolution of the display field and the improvement of the display effect of the display field. Next, as an example for illustration, it is assumed that the first reset transistor is a dual-gate transistor. Fig. 15 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure, and Fig. 16 is a structural diagram of a further pixel control semiconductor section, a further pixel interconnect semiconductor section, and a further reference signal line according to an embodiment of the present disclosure. Referring to Fig. 15 and Fig. 16, the pixel control semiconductor section 11 has a U-shaped part, wherein the U-shaped part comprises a connecting part U1, a first branching part U2, and a second branching part U3, wherein the first branching part U2 and the second branching part U3 are each connected to two ends of the connecting part U1, and the first branching part U2 and the second branching part U3 are arranged in the series direction X and extend in the column direction.The first node N1 is the end of the first branching section U2 that is furthest from the connecting section U1. In the X-direction, the first branching parts U2 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 are arranged on the side of the second branching parts U3 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 at a distance from the second nodes N2 in the third pixel control semiconductor section 11-3 and in the fourth pixel control semiconductor section 11-4. Alternatively, in the X-direction, the second nodes N2 in the third pixel control semiconductor section 11-3 and in the fourth pixel control semiconductor section 11-4 are arranged on the side of the second branching parts U3 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 at a distance from the first nodes N1 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2. As shown in Figs. 15 and 16, for example, the pixel driver semiconductor section 11 has the U-shaped part; in a direction perpendicular to the plane in which the substrate is arranged, there are two overlapping regions between the first scanning line Scan1 and the U-shaped part; and the two overlapping regions form corresponding channel regions of a dual-gate transistor, i.e., the first reset transistor is a dual-gate transistor, which ensures a small leakage current of the first reset transistor and a stable gate potential of the driver transistor. Furthermore, the U-shaped part comprises the connecting section U1, the first branching section U2, and the second branching section U3, and the first branching section U2 and the second branching section U3 are each connected to two ends of the connecting section U1.The first branch U2 and the second branch U3 are arranged in the series direction X and extend in the column direction. A terminal of the first branch U2, located away from the connecting section U1, is the first node N1. The first branch U2 and the second branch U3 are arranged differently for the pixel control semiconductor sections 11 at different positions. As shown in Fig. 15, in particular, in the series direction X, the first branch U2 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 are arranged away from the second nodes N2 in the third pixel control semiconductor section 11-3 and in the fourth pixel control semiconductor section 11-4, i.e.,h, the nodes N2 in the third pixel driver semiconductor section 11-3 and in the fourth pixel driver semiconductor section 11-4 are located closer together, and the nodes N2 in the third pixel driver semiconductor section 11-3 and in the fourth pixel driver semiconductor section 11-4 in the same row and adjacent to each other are connected via the pixel link semiconductor section 12, which ensures that the pixel link semiconductor section 12 is easily provided and that the extension length of the pixel link semiconductor section 12 in the row direction X is short. Therefore, it can be ensured that the transmission loss of the signal on the pixel link semiconductor section 12 is low and the display effect of the display field is good. As shown in Fig.As shown in Figure 16, in the row direction X, the first branching parts U2 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 are arranged on the side of the second branching parts U3 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 away from the second nodes N2 in the third pixel control semiconductor section 11-3 and in the fourth pixel control semiconductor section 11-4, i.e., the first branching parts U2 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 are closer together, and the first branching parts U2 in the first pixel control semiconductor section 11-1 and in the second pixel control semiconductor section 11-2 in the same row and adjacent to each other are connected via the pixel linking semiconductor section 12.The nodes N1 in the first pixel drive semiconductor section 11-1 and in the second pixel drive semiconductor section 11-2, in the same row and adjacent to each other, are connected via the pixel link semiconductor section 12. This ensures that the pixel link semiconductor section 12 is easily provided and that its extension length in the row direction X is short. Therefore, it can be ensured that the signal transmission loss on the pixel link semiconductor section 12 is low and the display effect of the display field is good. In summary, the embodiment described above describes several ways of arranging the pixel interconnect semiconductors. Arranging the pixel interconnect semiconductor section as part of the pixel driver semiconductor section ensures that the pixel interconnect semiconductor section can be arranged easily. Alternatively, arranging the pixel interconnect semiconductor section to connect multiple pixel driver semiconductor sections in a column or row direction to form a continuous semiconductor track ensures that static electricity can be distributed evenly along the continuous semiconductor track. Furthermore, this can improve the reliability and uniformity of the performance of the pixel driver semiconductor sections 11 in the subsequent high-temperature manufacturing process.Therefore, the pixel control capabilities can be essentially consistent, display uniformity can be achieved, and the display effect can be improved. Furthermore, in cases where multiple pixel control semiconductor sections are arranged in series to form a continuous semiconductor track through the pixel interconnect semiconductor sections, it is ensured that the pixel interconnect semiconductor section can be easily arranged, or that multiple pixel control semiconductor sections can be arranged in a compact structure, by sensibly adjusting the positional relationship between the first and second nodes in the pixel control semiconductor section. This facilitates an increase in the number of pixel control semiconductor sections per unit area, thus improving the resolution of the display field and the overall display effect. Based on the embodiment described above, Fig. 17 is a structural diagram of another display field according to an embodiment of the present disclosure, and Fig. 18 is an enlarged exemplary view of an area A in Fig. 17. As shown in Fig. 17 and Fig. 18, the array substrate 100 can have a functional area FU, and the pixel circuits 10 are arranged in a row direction (direction X, as shown in Fig. 17 and Fig. 18) or in a column direction (direction Y, as shown in Fig. 17 and Fig. 18) on two sides of the functional area FU. The array substrate 100 also features a region compound semiconductor section 13. The area interconnect semiconductor section 13 extends around the functional area FU. The fixed-potential nodes in the pixel control semiconductor sections 11, which are located in a row or column direction on two sides of the functional area FU, are connected to the area interconnect semiconductor section 13. The array substrate 100 exemplarily includes the functional area FU, and functional devices such as a camera, a handheld device, or an optical fingerprint sensor can be arranged at the position corresponding to the functional area FU. The shape of the functional area FU can be circular, rectangular, rounded rectangular, or similar, which is not limited in the present application. One or more functional areas FU can be provided, which is not limited in the present application. The functional area FU can be a non-display area or a display area. If the functional area FU is the display area, it can be assumed that the functional area FU also includes corresponding pixel circuits. To improve the light transmission of the functional area FU, the pixel circuit corresponding to the functional area FU can be arranged in a different area than the functional area FU, e.g.,The pixel circuits 10 are arranged in column direction Y on two sides of the function area FU. As shown in Fig. 18, fixed-potential nodes in the pixel control semiconductor sections 11, which are arranged in the row or column direction on two sides of the functional area FU, are connected to the area interconnect semiconductor section 13. The fixed-potential nodes in the pixel control semiconductor sections 11, which are located on one and the other side of the functional area FU, are connected via the area interconnect semiconductor section 13, so that the pixel control semiconductor sections 11, which are arranged in the row or column direction on one and the other side of the functional area FU, are no longer separated. The pixel control semiconductor sections 11, which are arranged in the row or column direction on one and the other side of the functional area FU, and the area interconnect semiconductor section 13 can be understood as also forming a continuous semiconductor track. Therefore, static electricity can be distributed evenly on the continuous semiconductor track corresponding to the functional area FU, and furthermore, the reliability and uniformity of performance of the pixel control semiconductor sections 11 on both sides of the functional area FU in the series direction or in the column direction can be improved in the subsequent high-temperature manufacturing process, the control capabilities of the pixel circuits can be essentially consistent, display uniformity can be achieved, and the display effect can be improved. It should be noted that in Fig. 18 the pixel control semiconductor sections 11, which lie in series on one and the other side of the functional area FU and are connected to the area interconnect semiconductor section 13, are used as an example for illustration, and that the pixel control semiconductor sections 11, which lie in columns on one and the other side of the functional area FU, are connected to the area interconnect semiconductor section 13 in the same way as described above, which is not described again here.In each of the following embodiments, the pixel control semiconductor sections 11, which are arranged and connected in series on one and the other side of the functional area FU, are used as an example for illustration, and the connection of the pixel control semiconductor sections in column direction is the same as the connection of the pixel control semiconductor sections in series direction, which is not described again below. It should also be noted that in Fig. 18 only one structure of the pixel control semiconductor section 11 is used as an example for illustration, and the connection relationship between the area interconnect semiconductor section 13 and the other structures of the pixel control semiconductor section 11 is the same as the connection relationship described above, which is not described again here. Based on the embodiments described above, Fig. 19 is another enlarged example diagram of region A in Fig. 17. As shown in Fig. 19, the reference signal line comprises the first reference signal line and the second reference signal line, which extend in series and parallel to each other, and two fixed-potential nodes comprise the first node and the second node. In the same pixel-driver semiconductor section, the first node is electrically connected to the first reference signal line and the second node is electrically connected to the second reference signal line.The area interconnect semiconductor section 13 comprises a first area interconnect semiconductor section 131 and connects a second area interconnect semiconductor section 132, and the pixel driver semiconductor section 11, which adjoins the functional area FU, comprises a fifth pixel driver semiconductor section 11-5 and a sixth pixel driver semiconductor section 11-6. In the row direction X or in the column direction Y, the second node N2 in the pixel driver semiconductor section 11, which is located on the side of the fifth pixel driver semiconductor section 11-5 furthest from the functional area FU, is connected via the pixel interconnect semiconductor section 12 to the second node N2 in the fifth pixel driver semiconductor section 11-5.In the row direction X or in the column direction Y, the first node N1 in the pixel control semiconductor section 11, located on the side of the sixth pixel control semiconductor section 11-6 furthest from the functional area FU, is connected via the pixel connection semiconductor section 12 to the first node N1 in the sixth pixel control semiconductor section 11-6. In the row direction X or in the column direction Y, the first nodes N1 in at least two fifth pixel control semiconductor sections 11-5, located on opposite sides of the functional area FU, are connected via the first area connection semiconductor section 131. In the row direction X or in the column direction Y, the second nodes N2 in at least two sixth pixel control semiconductor sections 11-6, located on opposite sides of the functional area FU, are connected via the second area connection semiconductor section 132. The reference signal line is not shown in Fig. 19, and for details of the scheme, in which the reference signal line comprises the first and second reference signal lines, reference can be made to Figs. 2, 6, 9, 10, 11, 12, 13, 14, 15 to 16, which are not described again here. By providing two reference signal lines, independent reference signals can be provided for the first node N1 and the second node N2, ensuring independent reset of the gate of the driver transistor and the anode of the light-emitting element, and thus guaranteeing a good reset effect. Furthermore, in the row direction X or in the column direction Y, the second node N2 in the pixel control semiconductor section 11, which is located on the side of the fifth pixel control semiconductor section 11-5 away from the functional area FU, is connected via the pixel link semiconductor section 12 to the second node N2 in the fifth pixel control semiconductor section 11-5, and the first node N1 in the pixel control semiconductor section 11, which is located on the side of the sixth pixel control semiconductor section 11-6 away from the functional area FU, is connected via the pixel link semiconductor section 12 to the first node N1 in the sixth pixel control semiconductor section 11-6, so that static electricity can be distributed evenly on the continuous semiconductor track that corresponds to the two sides of the functional area FU.Furthermore, the reliability and uniformity of performance of the pixel drive semiconductor sections 11 on both sides of the functional area FU in the series or column direction can be improved in the subsequent high-temperature manufacturing process. Therefore, the drive capabilities of the pixel circuits can be essentially consistent, display uniformity can be achieved, and the display effect can be improved. Furthermore, at least the first nodes N1 in the fifth pixel control semiconductor sections 11-5, which are located on two sides of the functional area FU, are connected via the first area interconnect semiconductor section 131, and the first area interconnect semiconductor section 131 can transmit the first reference signal Vref to ensure that a reset signal is provided for the first nodes N1 in the fifth pixel control semiconductor sections 11-5, which are connected to the first area interconnect semiconductor section 131, thereby resetting the gates of the drive transistors in the fifth pixel control semiconductor sections 11-5.From the pixel control semiconductor sections 11, which are located on two sides of the functional area FU, at least the second nodes N2 in the sixth pixel control semiconductor sections 11-6 are connected via the second area interconnect semiconductor section 132, and the second area interconnect semiconductor section 132 can transmit the second reference signal Vref to ensure that a reset signal is provided for the second nodes N2 in the sixth pixel control semiconductor sections 11-6, which are connected to the second area interconnect semiconductor section 132, thereby resetting the anodes of the light-emitting elements according to the sixth pixel control semiconductor sections 11-6.In summary, the area compound semiconductor section 13 comprises the first area compound semiconductor section 131 and the second area compound semiconductor section 132, and the first area compound semiconductor section 131 and the second area compound semiconductor section 132 can transmit different reference signals, thereby ensuring that the first nodes N1 and the second nodes N2, located on opposite sides of the functional area FU, receive different signals separately, and ensuring that the pixel driver semiconductor sections 11, located on opposite sides of the functional area FU, can supply different reset signals to the gates of the driver transistors and the anodes of their corresponding light-emitting elements, thus ensuring the good reset effect. Based on the embodiment described above, Fig. 20 is a further enlarged exemplary view of area A in Fig. 17. As shown in Fig. 20, the area interconnect semiconductor section 13 has a third area interconnect semiconductor section 133, and two first nodes N1 in pixel driver semiconductor sections 11, arranged in the row direction or in the column direction and each located on two sides of the functional area FU, are connected via the third area interconnect semiconductor section 133; and / or the area interconnect semiconductor section 13 has a fourth area interconnect semiconductor section, and two second nodes N2 in pixel driver semiconductor sections 11, arranged in the row direction or in the column direction and each located on two sides of the functional area FU, are connected via the fourth area interconnect semiconductor section;and / or the area interconnect semiconductor section 13 has a fifth area interconnect semiconductor section 135, and the first node N1 and the second node N2 in two pixel control semiconductor sections 11, which are arranged in series or in columns and each lie on two sides of the functional area FU, are connected via the fifth area interconnect semiconductor section 135. Figure 20 shows, by way of example, only the third area interconnect semiconductor section 133 and the fifth area interconnect semiconductor section 135, while the fourth area interconnect semiconductor section is not shown in Figure 20. The fourth area interconnect semiconductor section is configured to connect two second nodes N2 in the pixel control semiconductor sections 11, which are arranged in a row or column direction and each lie on two sides of the functional area FU. The way in which the fourth area interconnect semiconductor section is connected to the second nodes N2 can be compared to the way in which the third area interconnect semiconductor section 133 is connected to the first node N1, which is not described again here. In particular, the third area interconnect semiconductor section 133 is configured to connect two first nodes N1 in the pixel control semiconductor sections 11, which are arranged in series on opposite sides of the functional area FU; the fourth area interconnect semiconductor section is configured to connect two second nodes N2 in the pixel control semiconductor sections 11, which are arranged in series on opposite sides of the functional area FU; and the fifth area interconnect semiconductor section 135 is configured to connect the first node N1 and the second node N2 in the pixel control semiconductor sections 11, which are arranged in series on opposite sides of the functional area FU, to ensure that two pixel control semiconductor sections 11, which are arranged in series on opposite sides of the functional area FU, are connected to form a continuous semiconductor track.so that static electricity can be evenly distributed on the continuous semiconductor track corresponding to both sides of the FU functional area, and furthermore, the reliability and uniformity of the performance of the pixel drive semiconductor sections 11 on both sides of the FU functional area in series can be improved in the subsequent high-temperature manufacturing process. Therefore, the drive capabilities of the pixel circuits can be essentially consistent, display uniformity can be achieved, and the display effect can be improved. Furthermore, the first reference signal Vref can be transmitted via the third area compound semiconductor section 133 to ensure that a reset signal is provided for the first nodes N1 in the pixel drive semiconductor sections 11 which are connected to the third area compound semiconductor section 133, thereby resetting the gates of the driver transistors in the pixel drive semiconductor sections 11.The second reference signal Vref can be transmitted via the fourth area compound semiconductor section to ensure that a reset signal is provided for the second nodes N2 in the pixel drive semiconductor sections 11 connected to the fourth area compound semiconductor section, thereby resetting the anodes of the light-emitting elements corresponding to the pixel drive semiconductor sections 11 and ensuring the normal operation of the display circuits and the light-emitting elements connected to the pixel circuits. Referring to Figures 18, 19, and 20, if the functional area is present and blocks the connection of the pixel control semiconductor sections, a region interconnection semiconductor section can be provided to connect the pixel control semiconductor sections that are arranged in a row or column on one side and the other of the functional area. Depending on the connection configuration, the region interconnection semiconductor section can be further subdivided into several fields, such as the first region interconnection semiconductor section, the second region interconnection semiconductor section, the third region interconnection semiconductor section, the fourth region interconnection semiconductor section, and the fifth region interconnection semiconductor section. For further details, please refer to the description above.The area compound semiconductor section according to the embodiment of the present disclosure can be formed in the same film layer, made from the same material and manufactured in the same process as the pixel control semiconductor section, thereby ensuring a simple arrangement of the area compound semiconductor section and a simple manufacture of the display field. Based on the embodiments mentioned above, and with reference to Fig. 20, the domain compound semiconductor section 13 further comprises the fifth domain compound semiconductor section 135, and the array substrate 100 further comprises a control section 14. The control section 14 overlaps at least partially with the fifth domain compound semiconductor section 135 in the direction perpendicular to the plane in which the array substrate is arranged, and the control section 14 and the fifth domain compound semiconductor section 135 form a switching element.The fifth area interconnect semiconductor section 135 is configured to connect the first node N1 and the second node N2 in the pixel control semiconductor sections 11, which are arranged in series on two sides of the functional area FU; however, since the reference signals required for the first node N1 and the second node N2 are different, the control section 14 can be provided, and the control section 14 and the fifth area interconnect semiconductor section 135 form a switching element.Furthermore, the switching element is controlled to switch off in order to control the open circuit between the first node N1 and the second node N2, in order to prevent the first node N1 and the second node N2 from being supplied with the same reference signal transmitted via the fifth area compound semiconductor section 135, thus avoiding the problem of the accuracy of resetting the gate of the driver transistor or the anode of the light-emitting element not being high. Furthermore, the switching element is designed such that the control section 14 and the fifth-area compound semiconductor section 135 overlap at least partially in the direction perpendicular to the plane in which the array substrate is arranged. In this way, the control section 14 and the fifth-area compound semiconductor section 135 form a thin-film transistor, and an area where the control section 14 and the fifth-area compound semiconductor section 135 overlap serves as the conduction channel of the thin-film transistor. The conduction channel is controlled by the control section 14 to switch off the switching element and, furthermore, to open the circuit between the first node N1 and the second node N2. Based on the embodiment described above, the control section 14 can further be configured to be electrically connected to a fixed voltage terminal, and in this way a fixed voltage signal can be transmitted in the control section 14, and the fixed voltage signal can be used as a control signal to control the switching element that is to be switched off, in order to control the switching element so that it is kept in a switched-off state. For example, if the thin-film transistor formed by the control section 14 and the fifth-region compound semiconductor section 135 is a p-type thin-film transistor, the fixed-voltage terminal can be controlled to transmit a high-level signal, and the high-level signal can control the p-type thin-film transistor to be in an off-state. As another example, if the thin-film transistor formed by the control section 14 and the fifth-region compound semiconductor section 135 is an n-type thin-film transistor, the fixed-voltage terminal can be controlled to transmit a low-level signal, and the low-level signal can control the n-type thin-film transistor to be in an off-state.In the embodiment of the present disclosure, it is assumed, by way of example for illustration, that the thin-film transistor formed by the control section 14 and the fifth area compound semiconductor section 135 is a p-thin-film transistor. Based on the embodiment described above and with further reference to Fig. 20, the array substrate further comprises a power signal line PVDD, which extends along the column direction and is electrically connected to the pixel circuits. The power signal line PVDD includes a first branching section 15, which is also used as a control section 14. As can be seen from the description of the structure and operating procedure of the pixel circuit with reference to Fig. 2 and Fig. 4, the array substrate can further include the power signal line PVDD, and the power signal line PVDD is designed to provide a PVDD power signal to the light-emitting element to ensure that the light-emitting element can emit light normally. In general, PVDD is a high-level signal. As shown in Fig.As shown in Figure 20, the power signal line PVDD has a first branch 15, and this first branch 15 also serves as a control section 14. The high-level PVDD power signal acts as a control signal for the switching element, keeping it off and ensuring an open circuit between the first node N1 and the second node N2 in the two pixel driver semiconductor sections located on either side of the functional area FU. Furthermore, the power signal line PVDD, originally provided in the array substrate 100, serves as a control section 14, thus ensuring that the control section 14 can be easily provided. It should be noted that in Fig. 20, it is only assumed by way of example that the first branching part 15 is part of the power signal line PVDD. It can be assumed that, depending on the arrangement of the power signal line PVDD and the arrangement of the fifth area interconnect semiconductor section 135, the first branching part 15 may also comprise other arrangements, which is not limited in the embodiments of the present disclosure. It should also be noted that only two power signal lines PVDD are shown in Fig. 20. It is understood that multiple power signal lines PVDD can be provided in the array substrate; for example, one power signal line PVDD can be provided for each column of the pixel control semiconductor sections 11, and the specific arrangement of the power signal lines PVDD is not limited in the embodiment of the present disclosure. Furthermore, the power signal line PVDD shown in Fig. 20 bypasses the FU functional area and does not affect the arrangement of the components in the FU functional area. Optionally, Fig. 21 is another enlarged exemplary view of region A in Fig. 17. As shown in Fig. 21, the control section 14 comprises a first control section 141 and a second control section 142, wherein the first control section 141 and the second control section 142 overlap at least partially with the same fifth region compound semiconductor section 135 in the direction perpendicular to the plane in which the array substrate is arranged, and the first control section 141 and the second control section 142 do not overlap in the direction perpendicular to the plane in which the array substrate lies. The first control section 141 and the fifth region compound semiconductor section 135, as well as the second control section 142 and the fifth region compound semiconductor section 135, each form a first sub-switching element and a second sub-switching element.The first control section 141 and the second control section 142 each receive different electrical signals, and at any given time at least one of the first sub-switching element and the second sub-switching element is in a switched-off state. As shown in Fig. 21, the control section 14 can further comprise, by way of example, a first control section 141 and a second control section 142. In the direction perpendicular to the substrate, both the first control section 141 and the second control section 142 overlap with the fifth-region compound semiconductor section 135. Therefore, the first control section 141 and a region of the fifth-region compound semiconductor section 135 form a first sub-switch, and the second control section 142 and another region of the fifth-region compound semiconductor section 135 form a second sub-switch.The first sub-switching element and / or the second sub-switching element is in a switched-off state, ensuring that a signal transmitted in the fifth area interconnect semiconductor section 135 cannot be transmitted normally at the position of the first sub-switching element and / or the position of the second sub-switching element, and ensuring an open circuit between the first node N1 and the second node N2 in the two pixel control semiconductor sections located on one and the other side of the functional area FU. Based on the embodiment described above and with further reference to Fig. 21, the array substrate further comprises the first scanning signal line Scan1 and the second scanning signal line Scan2. The first scanning signal line Scan1 extends in series and is electrically connected to the pixel circuits; the first scanning signal line has a second branch 16, and the second branch 16 is also used as the first control section 141. The second scanning signal line Scan2 extends in series and is electrically connected to the pixel circuits; the second scanning signal line Scan2 has a third branch 17, and the third branch 17 is also used as the second control section 142. As can be seen from the description of the structure and operating process of the pixel circuits with reference to Figures 2 and 4, the array substrate also includes, by way of example, the first sampling signal line Scan1 and the second sampling signal line Scan2. The first sampling signal line Scan1 and the second sampling signal line Scan2 are designed to provide sampling signals for the thin-film transistors in the pixel circuits to ensure the normal operation of the pixel circuits. In general, it can be seen from the timing diagram shown in Figure 5 that at any given time, the first sampling signal line Scan1 and / or the second sampling signal line Scan2 is a high-level signal.Therefore, if the second branching part 16 in the first scanning signal line Scan1 is also used as the first control section 141 and the third branching part 17 in the second scanning signal line Scan2 is also used as the second control section 142, at least one signal of the signals of the second branching part 16 and the third branching part 17 is a high-level signal, so that the first sub-switching element and / or the second sub-switching element can be controlled to be in an off state.In this way, it can be ensured that the signal transmitted in the fifth area interconnect semiconductor section 135 cannot be transmitted normally at the position of the first sub-switching element and / or the position of the second sub-switching element, and the open circuit between the first node N1 and the second node N2 in the two pixel control semiconductor sections located on one side and the other side of the functional area FU can be guaranteed. Furthermore, the sampling signal line originally provided in the array substrate 100 serves as the control section 14, thus ensuring that the control section 14 can be provided in a straightforward manner. It should be noted that in Fig. 21, the first scanning signal line Scan1 and the second scanning signal line Scan2 are shown only in a region corresponding to the fifth region interconnect semiconductor section 135. According to the preceding description, each row of pixel-driven semiconductor sections 11 corresponds to two scanning signal lines, i.e., the first scanning signal line Scan1 and the second scanning signal line Scan2. In Fig. 21, for the first scanning signal line Scan1 and the second scanning signal line Scan2, which are located above the functional region FU, the third branch 17 is assumed to be part of the second scanning signal line Scan2; and for the first scanning signal line Scan1 and the second scanning signal line Scan2, which are located below the functional region FU, the third branch 17 is assumed to be part of the second scanning signal line Scan2.21 supposes that the second branching part 16 is part of the first scanning signal line Scan1. It is understood that, according to the arrangements of the first scanning signal line Scan1 and the second scanning signal line Scan2 and the arrangement of the fifth area interconnect semiconductor section 135, the second branching part 16 and the third branching part 17 may also comprise other arrangements, which is not limited in the embodiment of the present application. Based on the embodiment described above and with further reference to Fig. 2, the pixel circuit according to the embodiments of the present disclosure can further comprise a first connecting part 18 and a second connecting part 19, the reference signal line Vref comprises the first reference signal line Vref1 and the second reference signal line Vref2, which extend in series and are parallel to each other, and two fixed-potential nodes comprise a first node N1 and a second node N2. The first node N1 and the first reference signal line Vref1 are electrically connected via the first connecting part 18; and the second node N2 and the second reference signal line Vref2 are electrically connected via the second connecting part 19. Continuing with reference to Fig. 2, for example, the first node N1 is electrically connected to the first reference signal line Vref1 via the first connecting part 18 to transmit the first reference signal, thus ensuring that the gate of the driver transistor can be reset. The second node N2 is electrically connected to the second reference signal line Vref2 via the second connecting part 19 to transmit the second reference signal, thus ensuring that the anode of the light-emitting element can be reset and that the normal operation of the display panel is guaranteed. Based on the embodiments described above and further with reference to Fig. 2, the array substrate comprises a substrate and a driver circuit layer arranged on the substrate, and the driver circuit layer comprises a semiconductor layer, a first metal layer, a capacitive metal layer, a second metal layer and a third metal layer stacked in one direction away from the substrate. The pixel control semiconductor section is located on the semiconductor layer, the reference signal line is located on the first metal layer or the capacitive metal layer, and the first interconnect and the second interconnect are located on the second metal layer or the third metal layer. From the foregoing, it is known that the pixel circuit can comprise several thin-film transistors and a storage capacitor, each of which has an active layer, a gate, a source terminal, and a drain terminal, and the storage capacitor has a first capacitor plate and a second capacitor plate. The array substrate further comprises a sampling signal line, a data signal line, a reference signal line, and a power signal line. The active layer is the pixel-driver semiconductor section; that is, the active layer is located in the semiconductor layer arranged in the driver circuit layer and is situated on the side of the driver circuit layer close to the substrate. Furthermore, the gate, the first capacitor plate, and the sampling signal line can be located in the first metal layer in the driver circuit layer.The second capacitor plate can be located in the capacitive metal layer within the driver circuit layer. The source and drain terminals, as well as the data signal line, can be located in the second metal layer. The power signal line can be located in the second and / or third metal layer. Furthermore, the reference signal line can be located in the first metal layer or in the capacitive metal layer. The first and second connection points can be located in the second or third metal layer, and the first and second connection points are electrically connected to the reference signal line via contact holes to enable the transmission of reference signals.In this way, the arrangement of the first connection part and the second connection part is achieved by using the film layer in the driver circuit layer, making the arrangement of the first connection part and the second connection part simple and the film layer structure of the display field simple. Based on the same concept described above, a display device is further provided according to one embodiment of the present disclosure. Fig. 22 is a structural diagram of a display device according to one embodiment of the present disclosure. As shown in Fig. 22, the display device comprises the display field 200 from the embodiments described above. The display device comprises a display field according to any embodiment of the present disclosure, and therefore the display device according to the embodiment of the present disclosure has corresponding advantageous effects of the display field according to the embodiments of the present disclosure, the details of which are not described again here. By way of example, the display device may be a mobile phone, a computer, a smart portable device (e.g., a smartphone ...a smart clock), an onboard display device and other electronic devices, which is not limited in the embodiments of the present disclosure. It should be noted that the above descriptions are merely preferred embodiments of the present disclosure and the technical principles used therein. The person skilled in the art will understand that the present disclosure is not limited to the particular embodiments presented and that various substantial modifications, adaptations, combinations, and substitutions can be made without altering the scope of protection of the present disclosure. Although the present disclosure has been described in detail with reference to the embodiments mentioned above, it is not limited to the embodiments described above and may include further equivalent embodiments without departing from the concept of the present disclosure. The scope of the present disclosure is determined by the scope of the accompanying claims.

Claims

Display panel with an array substrate (100), wherein the array substrate (100) comprises: multiple pixel circuits (10), wherein the multiple pixel circuits (10) are arranged in an array in a row direction (X) and a column direction (Y), each of the multiple pixel circuits (10) having a pixel driver semiconductor section (11), the pixel driver semiconductor section (11) having two fixed-potential connection nodes (N) and the row direction (X) intersecting the column direction (Y); multiple reference signal lines (Vref), wherein the two fixed-potential connection nodes (N) are electrically connected to at least one of the multiple reference signal lines (Vref);and several pixel interconnect semiconductor sections (12), wherein two interconnect nodes (N) adjacent in a first direction are electrically connected at a fixed potential via one of the several pixel interconnect semiconductor sections (12), and the first direction is parallel to a plane in which the array substrate (100) is arranged; and wherein the several reference signal lines (Vref) comprise a first reference signal line (Vref1) and a second reference signal line (Vref2) extending in series direction (X); the two interconnect nodes (N) at a fixed potential comprise a first node (N1) and a second node (N2); and in one and the same pixel drive semiconductor section (11), the first node (N1) is electrically connected to the first reference signal line (Vref1) and the second node (N2) is electrically connected to the second reference signal line (Vref2);and two pixel control semiconductor sections (11) adjacent in series direction (X) comprise a first pixel control semiconductor section (11-1) and a second pixel control semiconductor section (11-2); and the first node (N1) in the first pixel control semiconductor section (11-1) is electrically connected to the first node (N1) in the second pixel control semiconductor section (11-2) via one of the multiple pixel interconnect semiconductor sections (12), or the second node (N2) in the first pixel control semiconductor section (11-1) is electrically connected to the second node (N2) in the second pixel control semiconductor section (11-2) via one of the multiple pixel interconnect semiconductor sections (12). Display field according to claim 1, wherein the pixel control semiconductor section (11) comprises one of the multiple pixel interconnect semiconductor sections (12) and the first node (N1) and the second node (N2) in one and the same pixel control semiconductor section (11) are electrically connected via one of the multiple pixel interconnect semiconductor sections (12). Display field according to claim 1, wherein the first node (N1) and the second node (N2) in the pixel control semiconductor section (11) are arranged in the first direction on two opposite sides of the pixel control semiconductor section (11); and the first direction is parallel to the column direction (Y) or an included angle between the first direction and the column direction (Y) is an acute angle; and the pixel control semiconductor sections (11) in two of the multiple pixel circuits (10) have one and the same pattern. Display field according to claim 1, wherein the first node (N1) and the second node (N2) in the pixel control semiconductor section (11) are arranged in a second direction on two opposite sides of the pixel control semiconductor section (11), the second direction being parallel to the plane in which the array substrate (100) is arranged, and the second direction being parallel to the column direction (Y), or an included angle between the second direction and the column direction (Y) being an acute angle; and in the row direction (X), the patterns of pixel control semiconductor sections (11) in two adjacent, sequentially arranged pixel circuits (10) are different, and the patterns of two pixel control semiconductor sections (11) spaced apart by a pixel control semiconductor section (11) are the same. Display field according to claim 4, wherein two adjacent pixel control semiconductor sections (11) arranged sequentially in the row direction (X) comprise a first pixel control semiconductor section (11-1) and a second pixel control semiconductor section (11-2), a pixel control semiconductor section (11) arranged on a first side of the first pixel control semiconductor section (11-1) in the column direction (Y), is a third pixel control semiconductor section (11-3), and a pixel control semiconductor section (11) arranged on a first side of the second pixel control semiconductor section (11-2) in the column direction (Y), is a fourth pixel control semiconductor section (11-4);and the first node (N1) in the first pixel control semiconductor section (11-1), the first node (N1) in the second pixel control semiconductor section (11-2), the second node (N2) in the third pixel control semiconductor section (11-3) and the second node (N2) in the fourth pixel control semiconductor section (11-4) are arranged in series direction (X);and the first node (N1) in the first pixel control semiconductor section (11-1) and the first node (N1) in the second pixel control semiconductor section (11-2) are arranged in series (X) between the second node (N2) in the third pixel control semiconductor section (11-3) and the second node (N2) in the fourth pixel control semiconductor section (11-4), or the second node (N2) in the third pixel control semiconductor section (11-3) and the second node (N2) in the fourth pixel control semiconductor section (11-4) are arranged in series (X) between the first node (N1) in the first pixel control semiconductor section (11-1) and the first node (N1) in the second pixel control semiconductor section (11-2). Display field according to claim 5, wherein the pixel control semiconductor section (11) has a U-shaped part, the U-shaped part comprising a connecting part (U1), a first branching part (U2) and a second branching part (U3); the first branching part (U2) and the second branching part (U3) are each connected to two ends of the connecting part (U1); the first branching part (U2) and the second branching part (U3) are arranged in the row direction (X) and extend in the column direction (Y); and an end of the first branching part (U2) furthest from the connecting part (U1) is the first node (N1);and in series direction (X) the first branch part (U2) in the first pixel control semiconductor section (11-1) is arranged on one side of the second branch part (U3) in the first pixel control semiconductor section (11-1) away from the second node (N2) in the third pixel control semiconductor section (11-3) and the first branch part (U2) in the second pixel control semiconductor section (11-2) is arranged on one side of the second branch part (U3) in the second pixel control semiconductor section (11-2) away from the second node (N2) in the fourth pixel control semiconductor section (11-4);or in series direction (X) the second node (N2) in the third pixel control semiconductor section (11-3) is located on one side of the second branch part (U3) in the first pixel control semiconductor section (11-1) away from the first node (N1) in the first pixel control semiconductor section (11-1), and the second node (N2) in the fourth pixel control semiconductor section (11-4) is located on one side of the second branch part (U3) in the second pixel control semiconductor section (11-2) away from the first node (N1) in the second pixel control semiconductor section (11-2). Display field according to one of the preceding claims, wherein the multiple pixel interconnect semiconductor sections (12) and the pixel control semiconductor section (11) are arranged in one and the same layer. Display field according to one of the preceding claims, wherein the first direction is the row direction (X) or the column direction (Y). Display field according to one of the preceding claims, wherein several pixel control semiconductor sections (11) comprise an i-th pixel control semiconductor section, an (i+1)-th pixel control semiconductor section and an (i+2)-th pixel control semiconductor section arranged sequentially in series direction (X), wherein i is a positive integer; the several pixel interconnect semiconductor sections (12) comprise a first pixel interconnect semiconductor section and a second pixel interconnect semiconductor section; the second node (N2) in the i-th pixel control semiconductor section and the second node (N2) in the (i+1)-th pixel control semiconductor section are electrically connected via the second pixel interconnect semiconductor section, and the first node (N1) in the (i+1)-th pixel control semiconductor section and the first node (N1) in the (i+2)-th pixel control semiconductor section are electrically connected via the first pixel interconnect semiconductor section;and the first pixel connection semiconductor section and the second pixel connection semiconductor section extend in series direction (X). Display field according to claim 9, wherein the length of the first pixel interconnect semiconductor section differs from the length of the second pixel interconnect semiconductor section. Display field according to claim 10, wherein the length of the first pixel interconnect semiconductor section is greater than the length of the second pixel interconnect semiconductor section. Display field according to one of claims 9 to 11, wherein the pixel control semiconductor sections (11) arranged in the column direction (Y) comprise pixel control semiconductor sections (11) in a j-th row and pixel control semiconductor sections (11) in a (j+1)-th row, where j is a positive integer; and in a direction extending in the row direction (X), the second pixel interconnect semiconductor section (12) connected to the pixel control semiconductor sections (11) in the j-th row overlaps the first pixel interconnect semiconductor section (12) connected to the pixel interconnect semiconductor sections (12) in the (j+1)-th row. Display field according to claim 12, wherein the second pixel interconnect semiconductor section, which is connected to the pixel control semiconductor sections (11) in the j-th row, and the first pixel interconnect semiconductor section, which is connected to the pixel control semiconductor sections (11) in the (j+1)-th row, lie on the same reactive line in the row direction (X); the first reference signal line (Vref1) is electrically connected to the first pixel interconnect semiconductor section, which is connected to the pixel control semiconductor sections (11) in the (j+1)-th row;Each of the multiple pixel circuits (10) further comprises a driver transistor (T3) and a connecting section, a light-emitting element (D), a first reset transistor (T5) and a second reset transistor (T7), wherein a first electrode of the first reset transistor (T5) is electrically connected to a gate of the driver transistor (T3), a first electrode of the second reset transistor (T7) is electrically connected to an anode of the light-emitting element (D), and the first electrode of the first reset transistor (T5) is electrically connected to the gate of the driver transistor (T3) via the connecting section; and in the column direction (Y), the first reference signal line (Vref1) is arranged between the reactive line and the connecting section in pixel circuits (10) in the j-th row. Display field according to one of claims 9 to 13, wherein several second nodes (N2) in pixel control semiconductor sections (11) are arranged in a j-th row and several first nodes (N1) in pixel control semiconductor sections (11) are arranged in a (j+1)-th row in the row direction (X). Display field according to one of claims 9 to 14, wherein in a direction perpendicular to the plane in which the display field is arranged neither the first pixel interconnect semiconductor section nor the second pixel interconnect semiconductor section overlaps with the first reference signal line (Vref1) and the second reference signal line (Vref2). Display field according to one of the preceding claims, wherein the multiple reference signal lines (Vref) further comprise a third reference signal line and a fourth reference signal line, wherein the first reference signal line (Vref1) is electrically connected to the first node (N1) via the third reference signal line and the second reference signal line (Vref2) is electrically connected to the second node (N2) via the fourth reference signal line. Display field according to claim 16, wherein the third reference signal line extends in the column direction (Y). Display field according to claim 16 or 17, wherein the array substrate (100) further comprises a substrate and a driver circuit layer arranged on the substrate, the driver circuit layer comprising a semiconductor layer, a first metal layer, a capacitive metal layer, a second metal layer and a third metal layer stacked in a direction away from the substrate; and the third reference signal line and the fourth reference signal line arranged on the second metal layer. Display field according to one of the preceding claims, wherein each of the multiple pixel circuits (10) further comprises a driver transistor (T3), a light-emitting element (D), a first reset transistor (T5) and a second reset transistor (T7), wherein the driver transistor (T3) is configured to control the light-emitting element (D) to illuminate, wherein the first reset transistor (T5) is configured to control a reference signal to reset a gate potential of the driver transistor (T3), and the second reset transistor (T7) is configured to control a reference signal to reset an anode potential of the light-emitting element (D);the array substrate (100) further comprises a first scanning signal line (Scan1) extending in the series direction (X), two overlapping regions between the first scanning signal line (Scan1) and the pixel drive semiconductor section (11) in a direction perpendicular to the plane in which the array substrate (100) is arranged, and one channel of the first reset transistor (T5) and one channel of the second reset transistor (T7) each comprise pixel drive semiconductor sections (11) in which the two overlapping regions are arranged; and one terminal of the first reset transistor (T5) is electrically connected to the first node (N1) and another terminal of the first reset transistor (T5) is electrically connected to a gate of the driver transistor (T3);and one terminal of the second reset transistor (T7) is electrically connected to the second node (N2) and another terminal of the second reset transistor (T7) is electrically connected to an anode of the light-emitting element (D). Display field according to one of the preceding claims, wherein the first reset transistor (T5) is a double-gate transistor. Display field according to one of the preceding claims, wherein each of the multiple pixel circuits (10) further comprises a first connection section and a second connection section, the first node (N1) and the first reference signal line (Vref1) are electrically connected via the first connection section and the second node (N2) and the second reference signal line (Vref2) are electrically connected via the second connection section. Display field according to claim 21, wherein the array substrate (100) further comprises a substrate and a driver circuit layer arranged on the substrate, and the driver circuit layer comprises a semiconductor layer, a first metal layer, a capacitive metal layer, a second metal layer and a third metal layer stacked in a direction away from the substrate; and the pixel control semiconductor section (11) is arranged in the semiconductor layer, several reference signal lines (Vref) are arranged in the first metal layer or in the capacitive metal layer, and the first interconnect section and the second interconnect section are arranged in the second metal layer or in the third metal layer. Display device comprising the display field according to one of the preceding claims.

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