SURFACE TREATMENT PROCESS FOR GALLIUM OXIDE-BASED SEMICONDUCTOR SUBSTRATE AND SEMICONDUCTOR DEVICE

Abstract

Surface treatment process for a gallium oxide-based semiconductor substrate (10), comprising: Flattening a surface (12s) of a gallium oxide-based semiconductor substrate (10) by dry etching with a bias voltage of 150 V or more; and Exposure of a step-terrace structure on the surface (12s) of the gallium oxide-based semiconductor substrate (10) by washing the surface (12s) of the gallium oxide-based semiconductor substrate (10) with a chemical solution containing H2SO4 after the surface (12s) of the gallium oxide-based semiconductor substrate (10) has been flattened.

Description

[0001] The present disclosure relates to a surface treatment method for a gallium oxide-based semiconductor substrate and a semiconductor device using a gallium oxide-based semiconductor substrate.

[0002] A device structure for a Schottky barrier diode fabricated using a gallium oxide substrate is disclosed in W. Li et al., “2.44 kV Ga2O3 vertical trench Schottky barrier diodes with very low reverse leakage current”, IEEE International Electron Devices Meeting Tech. Dig., 2018, pages 193-196.

[0003] Reference is also made to US 2019 / 0 363 197 A1 and “Hogan, JE [ua]: Chlorine-based dry etching of β-Ga2O3. In: Semicon. Sci-Technol., Vol. 31, 2016, 065006”, which were identified as prior art.

[0004] The aim was to improve device properties by suppressing an interfacial state on the surface of a gallium oxide-based semiconductor substrate. For example, in the case of Schottky junction formation, when the interfacial state density becomes high, the Schottky barrier height ΦB becomes low, thus increasing leakage current.

[0005] A surface treatment method for a gallium oxide-based semiconductor substrate according to a first aspect of the present disclosure includes flattening a surface of a gallium oxide-based semiconductor substrate by dry etching with an intrinsic bias of 150 V or more and exposing a step-terrace structure on the surface of the gallium oxide-based semiconductor substrate by washing the surface of the gallium oxide-based semiconductor substrate with a chemical solution containing H2SO4 after the surface of the gallium oxide-based semiconductor substrate has been flattened.

[0006] A thin film of a modified layer can form on the surface of the gallium oxide-based semiconductor substrate. If there is a region where the modified layer cannot be removed during dry etching, the modified layer acts as a mask, and the etching process does not proceed, resulting in significant surface roughness. The present inventors have found that the modified layer can be adequately removed by setting the dry etching bias voltage to 150 V or more. Consequently, the flatness after etching can be improved. The present inventors have further found that a step-terrace structure can be exposed on a surface by washing the surface after dry etching with a chemical solution containing H₂SO₄.This allows for the realization of an ideal surface condition with high flatness and no interface layer, thus suppressing the generation of the interface condition. This makes it possible to improve the device properties.

[0007] A semiconductor device according to a second aspect of the present disclosure comprises a gallium oxide-based semiconductor substrate and a metal layer arranged on a surface of the gallium oxide-based semiconductor substrate. At an interface between the gallium oxide-based semiconductor substrate and the metal layer, a step-terrace structure is exposed on the surface of the gallium oxide-based semiconductor substrate.

[0008] A semiconductor device according to a third aspect of the present disclosure comprises a gallium oxide-based semiconductor substrate, an insulating film arranged on a surface of the gallium oxide-based semiconductor substrate, and an electrode arranged on a surface of the insulating film. At an interface between the gallium oxide-based semiconductor substrate and the insulating film, a step-terrace structure is exposed on the surface of the gallium oxide-based semiconductor substrate.

[0009] Further tasks and advantages of the present disclosure will become more apparent from the following detailed description in conjunction with the drawings. These show: Fig. 1 a schematic cross-sectional view of a semiconductor device according to one embodiment; Fig. 2 a schematic view of a dry etching device; Fig. 3 a flowchart illustrating a manufacturing process of the semiconductor device; Fig. 4 a cross-sectional view of the vicinity of a front surface of a gallium oxide layer before a flattening process is performed; Fig. 5 a cross-sectional view of the vicinity of the front surface of the gallium oxide layer after a flattening process is performed; Fig. 6 a scanning electron microscope (SEM) observation image of nanopillars; Fig. 7 a correlation diagram of antenna power and self-bias; Fig. 8 a correlation diagram of preload power and self-preload; Fig. 9. An atomic force microscope (AFM) observation image of the front surface of the gallium oxide layer after dry etching; and Fig. 10 an AFM observation image of the front surface of the gallium oxide layer after washing.

[0010] Fig. Figure 1 shows a schematic cross-sectional view of a semiconductor device 1 according to one embodiment. The semiconductor device 1 is a Schottky barrier diode. The semiconductor device 1 includes a semiconductor substrate 10. The semiconductor substrate 10 has a structure in which an n-type gallium oxide layer 12 is laminated onto an n-type gallium oxide substrate 11. The semiconductor substrate 10 is an example of a gallium oxide-based semiconductor substrate. The gallium oxide layer 12 is an epitaxially grown layer produced by a hydride vapor phase epitaxy (HVPE) process. The front surfaces of the gallium oxide substrate 11 and the gallium oxide layer 12 are (001) planes. A cathode electrode 21 is arranged on a back surface of the semiconductor substrate 10. The cathode electrode 21 has a structure in which titanium (Ti) and gold (Au) are laminated.An anode electrode 22 is arranged on a front surface 12a of the semiconductor substrate 10. The anode electrode 22 is made of nickel (Ni).

[0011] Fig. Figure 2 shows a schematic view of a dry etching device 30 used in the present embodiment. The dry etching device 30 is an inductively coupled plasma (ICP) etching device. The interior of a chamber 31 is depressurized by a vacuum pump 32. A bias electrode 34 and a wafer 35 are located in the chamber 31. The bias electrode 34 is connected to a bias radio frequency (RF) power supply 33. An induction coil 37 is arranged in an upper part of the chamber 31. The induction coil 37 is connected to an antenna RF power supply 38. Etching gas is supplied to the chamber 31 via a gas supply line 36. In the present embodiment, BCl3 and Cl2 are supplied in a switchable manner.

[0012] When antenna power is applied to the induction coil 37, plasma PL is generated directly beneath the induction coil 37. If a bias power is applied to the bias electrode 34, a self-biasing voltage Vds can be generated, which is a negative DC voltage. A shell SH is generated between the plasma PL and the wafer 35. The strong electric field generated in the shell SH can accelerate ions towards the wafer 35.

[0013] The self-bias is the voltage of the shell SH. In other words, the self-bias is the potential difference between the plasma PL and the wafer 35. The self-bias is a voltage determined by various parameters such as the power of the bias RF power supply 33 and the antenna RF power supply 38, and the type of etching gas. The self-bias can be measured in any dry etching device. The self-bias can also be monitored during etching. Therefore, the self-bias is a general and versatile index for defining etching conditions.

[0014] Next, a surface treatment process for the semiconductor substrate 10 in the semiconductor device 1 is carried out according to the flowchart of Fig. 3 described. At S0, the semiconductor substrate 10 is placed in the chamber 31 of the dry etching device 30.

[0015] In S1 to S3, a flattening process is performed to flatten the front surface 12s of the semiconductor substrate 10. The flattening process comprises a first to third processing step. In the flattening process, dry etching is performed with a bias voltage of 150 V or more. Accordingly, it is possible to form a flat surface without irregularities while maintaining a consistent etch rate. The dry etching is carried out using a gas containing chlorine. In the present embodiment, the antenna RF power supply is 38,800 W, the pressure in chamber 31 is 1 Pa, the total flow rate is 30 sccm, and the etching time is 10 minutes. Each of the first to third processing steps is described below.

[0016] In S1, the first method for performing dry etching with a bias voltage of 150 V or more is carried out using BCl3. A thin film of a modified layer can form on the front surface 12s of the semiconductor substrate 10. In the first method, the modified layer can be effectively removed by bonding boron atoms to oxygen atoms of gallium oxide.

[0017] In S2, the second method for performing dry etching with a bias voltage of 150 V or more is carried out using Cl₂ gas. Since the etching gas does not contain boron, no bonding occurs between boron and oxygen atoms. Therefore, although the etch rate is reduced, the surface flatness can be improved.

[0018] In S3, the third method for performing dry etching with a bias voltage of 150 V or more is carried out using BCl3. A small amount of silicon atoms is present in chamber 31 and in the atmosphere. When the silicon atoms adsorb onto the oxygen atoms of the gallium oxide, the resistance of the gallium oxide increases. Therefore, by finishing with the etching gas containing boron, the oxygen adsorption sites can be blocked with boron atoms. It is possible to suppress the adsorption of silicon atoms onto the oxygen atom adsorption sites.

[0019] It should be noted that S1 to S3 can be carried out continuously by switching the etching gas.

[0020] In step S4, the semiconductor substrate 10, on which the flattening process was performed, is removed from chamber 31. Then, the front surface 12s of the semiconductor substrate 10 is washed with a chemical solution containing sulfuric acid (H₂SO₄). Accordingly, a step-terrace structure (i.e., a flat surface at the atomic level) can be exposed on the front surface 12s of the semiconductor substrate 10. In the present embodiment, a treatment with a sulfuric acid-hydrogen peroxide mixture (SPM) is carried out, in which sulfuric acid and hydrogen peroxide solution are mixed.

[0021] If chlorine is present on the front surface 12s of the semiconductor substrate 10, a surface condition forms. In such a case, the Schottky barrier height ΦB is lowered, causing reverse leakage. In the present embodiment, any chlorine remaining on the front surface 12s of the semiconductor substrate 10 is removed by the washing process at S4. Therefore, it is possible to suppress the formation of a surface condition.

[0022] In S5, a metal layer (anode electrode 22) is formed on the front surface 12s. In the present embodiment, a nickel layer is formed. Consequently, the Fig. 1 Semiconductor device 1 shown completed.

[0023] The reason why a bias voltage of 150 V or more is required is explained. Fig. Figure 4 shows a cross-sectional view near the front surface 12s of the gallium oxide layer 12 before the flattening process (S1 to S3) is performed. A thin film of a modified layer 12a can form on the front surface 12s. The modified layer 12a is a layer altered by adsorption of different elements and damage during the processing of the gallium oxide. If there is a region where the modified layer 12a cannot be removed during dry etching from S1 to S3, the remaining modified layer 12a becomes a mask and stops the etching. Consequently, as shown in Figure 4, the modified layer 12a is removed during dry etching from S1 to S3. Fig. Figure 5 shows nanocolumns NC (columnar foreign bodies) formed on sections of the remaining altered layer 12a.

[0024] Fig. Figure 6 shows a SEM observation image of the nanopillars NC. During the formation of the nanopillars NC, the flatness of the front surface deteriorates drastically 12s.

[0025] Therefore, the present inventors have experimentally determined the range of intrinsic bias in which no nanopillar NC is formed. Fig. 7 and Fig. Figure 8 shows experimental results. The horizontal axis in Fig. 7 is the antenna power of the antenna RF power supply 38, and the vertical axis is the self-bias. In the experiment of Fig. 7. The bias power of the bias RF power supply 33 was fixed at 30 W. The horizontal axis in Fig. 8 is the preload power and the vertical axis is the self-preload. In the experiment of Fig. In step 8, the antenna power was fixed at 800 W. In the experiments of Fig. 7 and Fig. 8. BCl3 was used as the etching gas and the total pressure was set to 1 Pa.

[0026] The flattening process (S1 to S3) was performed under conditions shown in the diagrams of Fig. 7 and Fig. Figure 8 is shown. Then it was confirmed whether or not nanopillars (NC) were generated. The white circles in Fig. 7 and Fig. 8 indicates the conditions under which nanopillars NC were not formed, and the dotted circles indicate the conditions under which nanopillars NC were formed.

[0027] As in Fig. As shown in Figure 7, the self-bias increases with decreasing antenna power, and the NC nanopillars were not formed in a region where the self-bias is 150 V or more (see region R1). Furthermore, as shown in Fig. As shown in Figure 8, the self-bias increases with increasing bias power and the nanopillars NC were not formed in a region where the self-bias is 150 V or more (see region R2).

[0028] From the foregoing, the present inventors have discovered that the modified layer 12a (cf. Fig. 4 and Fig. 5) can be adequately removed by setting the dry etching bias voltage to 150 V or more. Consequently, the formation of nanopillars NC can be prevented, thus improving the flatness after etching. Since the flatness of the interface between the front surface 12s of the gallium oxide layer 12 and the anode electrode 22 can be increased, the electric field can be suppressed. Thus, it is possible to suppress the leakage current.

[0029] Fig. 9 and Fig. Figure 10 shows AFM observation images of the front surface 12s of the gallium oxide layer 12. The plane orientation is the (001) plane. Fig. Image 9 is an image after dry etching at S3. Fig. Figure 10 shows a picture after washing at S4. Fig. 9 and Fig. 10 have the same magnification.

[0030] The arithmetic mean roughness Ra of the surface after dry etching in Fig. 9 was 0.30 nm. On the other hand, the arithmetic mean roughness Ra of the surface after washing in Fig. 10 0.17 nm. These results show that surface roughness can be reduced by washing.

[0031] In Fig. 9. No regularity is observed on the surface. On the other hand, in Fig. 10. The step-terrace structure was observed. The step-terrace structure is a structure in which ST, which is a stepped section of one or more atoms, and terrace TE, which is flat at the atomic level, are repeated.

[0032] Based on the above, the present inventors have discovered that the step-terrace structure on the front surface 12s can be exposed by washing the front surface 12s of the gallium oxide layer 12 with a chemical solution containing H₂SO₄ after dry etching. The surface on which the step-terrace structure is exposed is in an ideal surface condition with extremely high flatness and no interface layer. Consequently, the generation of the interface condition can be suppressed, thus suppressing the decrease in the Schottky barrier height ΦB (after dry etching: 1.09 eV, after washing: 1.15 eV). Therefore, it is possible to suppress the leakage current.

[0033] Although specific examples of the present disclosure have been described in detail above, these are merely examples and do not limit the scope of the claims. The techniques described in the present description include various modifications and modifications of the specific examples illustrated above. Furthermore, the technical elements described in the present description or the drawings, alone or in various combinations, have technical utility and are not limited to the combinations described in the present description at the time of filing. Moreover, the techniques illustrated in the present description or the drawings can fulfill several purposes simultaneously, and the achievement of one of the purposes is itself technically useful. (Modifications)

[0034] The techniques disclosed in this description can be applied to various device structures, not limited to the Schottky barrier diode. For example, the techniques can be applied using an insulating film on a field-effect transistor (FET) structure. In this case, electrodes are arranged above the front surface 12c of the gallium oxide layer 12 by means of an insulating film. At an interface between the gallium oxide layer 12 and the insulating film, a structure can be realized in which a step-terrace structure is exposed on the front surface 12c of the gallium oxide layer 12. Consequently, the generation of an interface state can be suppressed, thus suppressing leakage current and on-resistance. Therefore, the device characteristics can be improved.

[0035] The etching gas used in S1 and S3 is not limited to BCl3. Any gas may be used as long as it contains boron and chlorine. The etching gas used in S2 is not limited to Cl2. Any type of gas may be used as long as it contains chlorine and no boron.

[0036] The step-terrace structure of the gallium oxide layer 12 can vary. The techniques of this specification can be applied to each of the α-type and β-type layers.

[0037] The gallium oxide layer 12 can be a mixed-crystalline gallium oxide containing at least one of indium, aluminum, and zinc. In other words, the gallium oxide layer 12 can be a mixed-crystalline gallium oxide containing at least indium, a mixed-crystalline gallium oxide containing at least aluminum, or a mixed-crystalline gallium oxide containing at least zinc. Examples of mixed-crystalline gallium oxides are (InAlGA)₂O₃, (AlGa)₂O₃, InGaO₃(ZnO), and the like.

Claims

[1] Surface treatment process for a gallium oxide-based semiconductor substrate (10), comprising: Flattening a surface (12s) of a gallium oxide-based semiconductor substrate (10) by dry etching with a bias voltage of 150 V or more; and Exposure of a step-terrace structure on the surface (12s) of the gallium oxide-based semiconductor substrate (10) by washing the surface (12s) of the gallium oxide-based semiconductor substrate (10) with a chemical solution containing H2SO4 after the surface (12s) of the gallium oxide-based semiconductor substrate (10) has been flattened. [2] Surface treatment method according to claim 1, wherein the flattening includes performing dry etching using a gas containing chlorine. [3] Surface treatment method according to claim 2, wherein the flattening includes: a first method for carrying out dry etching using a gas containing boron and chlorine; a second method for carrying out dry etching using a gas containing chlorine and not containing boron, according to the first method; and a third method for carrying out dry etching using a gas containing boron and chlorine after the second processing. [4] Surface treatment method according to claim 3, wherein the first method uses the gas containing BCl3, the second method uses the gas containing Cl2, and The third method uses the gas containing BCl3. [5] Surface treatment method according to any one of claims 1 to 4, wherein the gallium oxide-based semiconductor substrate (10) is a mixed-crystalline gallium oxide substrate containing at least one of indium, aluminium and zinc. [6] Semiconductor device (1) comprising: a gallium oxide-based semiconductor substrate (10); and a metal layer (22) arranged on a surface (12s) of the gallium oxide-based semiconductor substrate, wherein at an interface between the gallium oxide-based semiconductor substrate (10) and the metal layer (22) a step-terrace structure is exposed on the surface (12s) of the gallium oxide-based semiconductor substrate (10). [7] Semiconductor device (1) according to claim 6, wherein the gallium oxide-based semiconductor substrate (10) is a mixed-crystalline gallium oxide substrate containing at least one of indium, aluminium and zinc. [8] Semiconductor device (1) comprising: a gallium oxide-based semiconductor substrate (10); an insulating film arranged on a surface (12s) of the gallium oxide-based semiconductor substrate (10); and an electrode (22) which is arranged on a surface of the insulating film, wherein at an interface between the gallium oxide-based semiconductor substrate (10) and the insulating film, a step-terrace structure is exposed on the surface (12s) of the gallium oxide-based semiconductor substrate (10). [9] Semiconductor device (1) according to claim 8, wherein the gallium oxide-based semiconductor substrate (10) is a mixed-crystalline gallium oxide substrate containing at least one of indium, aluminium and zinc.

Images