DEVICE FOR ELECTRONIC SAMPLING OF AN ANALOGUE SIGNAL

Abstract

Device for electronic sampling of an analog signal (14), comprising a sampling unit (5) with a clock generator (9) for generating a sampling clock (16), a deserializer (7) for decomposing a signal (14) into bit vectors (15) and at least one evaluation circuit (10) for evaluating the bit vectors (15), wherein the clock generator (9) is associated with a phase shifter for shifting the phase of the sampling clock (16) specified by the clock generator (9) and the evaluation circuit (10) as well as an address encoder (11) for addressing the memory locations of a histogram memory as a function of a position of the rising edge and a phase of the relevant bit vector (15) in the system clock (17), characterized in that the evaluation circuits (10) are priority encoders.

Description

[0001] The present invention relates to a device for electronically sampling an analog signal, comprising a sampling unit with a clock generator for generating a sampling clock, a deserializer for decomposing a signal into bit vectors and at least one evaluation circuit for evaluating the bit vectors, wherein the clock generator is assigned a phase shifter for shifting the phase position of the sampling clock predetermined by the clock generator and the evaluation circuit and an address encoder for addressing the memory locations of a histogram memory depending on a position of the rising edge and a phase position of the relevant bit vector in the system clock.

[0002] Such a device is already known from the publication DE 10 2011 056 963 C5. In this context, reference should also be made to DE 102 36 486 A1.

[0003] A similar method is already known from EP 2 088 453 A1. This method involves evaluating a reflected signal for distance measurement using the time-of-flight method and feeding it into various parallel delay paths during the evaluation process, thereby processing light pulses emitted with a temporal offset. This allows for parallel processing within the circuit.

[0004] Such a circuit already has the advantage of being comparatively fast and inexpensive. In particular, it is possible and intended to program the elements required for signal evaluation in a field-programmable gate array (FPGA), which can be provided relatively inexpensively. However, two clock generators are required to compensate for the inaccuracy of the analog delay elements used.

[0005] Methods are also known from the documents EP 2 189 804 B1 and EP 2 189 805 B1 in which a very finely adjustable transmission pattern is generated using two independent frequencies and is then sampled again during reception.

[0006] However, these methods have in common that the analog received signal must always remain in the linear range and necessarily requires a limiting amplifier, but above all a filter, to convert the initially unipolar signal into a bipolar signal and to linearize it. In addition, several phase-locked loops (PLLs) are required to generate the clock signals required for processing.

[0007] Against this background, the present invention is based on the object of providing a device for electronically sampling an analog signal, which enables precise sampling with a temporal resolution above the maximum possible sampling rate of the system in a simpler and more cost-effective circuit.

[0008] This is achieved with a device for electronically sampling an analog signal according to the features of independent claim 1. Useful embodiments of the device can be found in the subsequent dependent claims.

[0009] A device for electronically sampling an analog signal is provided, comprising a sampling unit with a clock generator for generating a sampling clock, a deserializer for decomposing a signal into bit vectors, and at least one evaluation circuit for evaluating the mapping into bit vectors. According to the invention, such a device is characterized in that a phase shifter for shifting the phase position of the sampling clock specified by the clock generator is assigned to the clock generator, and the evaluation circuits have address encoders for addressing the memory locations of a histogram memory depending on a position of the rising edge and a phase position of the relevant bit vector in the system clock.

[0010] In such a system, an incoming, received signal is first broken down into individual sections, so-called bit vectors, which represent the signal waveform of the received signal. This breakdown takes place in the deserializer, which can be designed, for example, as a three-stage, eight-fold shift register, and in which the phase of the sampling clock is preferably dynamically adjustable. This special design allows multiple measurements to be performed consecutively with changed phase positions, which increases the temporal resolution in the histogram memory. If a sampling clock of 400 MHz is used, this means that one period of the sampling clock lasts 2.5 nanoseconds; in Double Data Rate mode, however, the resolution is improved to 1.25 nanoseconds. However, this is not considered sufficient.The invention therefore provides that a system clock is additionally generated which is derived from the sampling clock and preferably has a quarter of the clock frequency of the sampling clock of 400 MHz, thus 100 MHz.

[0011] However, to enable a higher sampling rate, the measurement is shifted by one phase during sampling in the sampling cycle. With a shift of one-eighth of a phase length, after an initial measurement without phase shift, the measurement is shifted forward or backward by one-eighth of a phase. By serially performing multiple measurements with each changed phase shift and storing the result in the histogram memory, the resolution is improved eightfold in the case of an eighth-fold phase shift, in the example to approximately 156 picoseconds.

[0012] The evaluation circuit, which is configured as a priority encoder with a system clock counter, then evaluates the bit vectors supplied by the deserializer. With each period of the system clock, the system clock counter is incremented, and then the next bit vector is formed with the deserializer until the first rising edge is detected. The priority encoder then determines the position of the rising edge in the bit vector and passes the result on to the address encoder. The priority encoder is a digital circuit with multiple inputs, of which the active input with the highest priority is returned. If the bits are prioritized in descending chronological order, the first bit in time will have the highest priority, followed by the second, and so on. When a rising edge occurs for the first time, an input is activated, and subsequent, also active inputs are ignored.

[0013] Then, depending on the position of the rising edge in the system clock, a histogram memory is addressed using an address encoder. The histogram memory reserves one location for each possible value, and the value stored therein is incremented by one for each detected rising edge. The addressing also includes a reference to the respective value of the system clock counter and the phase position, so that the improved resolution achieved by the inventive phase shift can also be mapped to the histogram memory.

[0014] In a specific embodiment, the signal can be a reflection of a light signal emitted by an emitter from an object in the room, which is preferably derived from the clock generator without phase shift. Such an arrangement can then be used to calculate the propagation time of a signal that has traveled from an emitter to a reflecting object and then back to a detector. Based on the propagation time between the emission and the arrival of the reflected signal, the distance of the reflecting object, whose presence is to be monitored in such a case, can be determined.

[0015] Furthermore, if necessary, the signal can be sent to a signal amplifier for preprocessing before deserialization and sampling. However, this is usually not necessary. Signal shaping via filters, as in the prior art, can be omitted.

[0016] For further evaluation of the measurement results, an evaluation unit can be provided that extracts a signal distribution from the histogram memory and determines the distance of a detector capable of receiving the signal from the object in the room based on the signal distribution in the histogram. An intensity measurement based on the sampled falling edge of the signal can be used additionally for error compensation.

[0017] Particularly advantageously, the deserializer and / or the evaluation circuits and / or the address encoders and / or the histogram memory can be implemented in a field-programmable gate array (FPGA). Such FPGAs are largely freely programmable and can be adapted to the needs of the application, while also being cost-effective standard components.

[0018] The invention described above is explained in more detail below using an exemplary embodiment.

[0019] It shows Fig. 1 a simplified transmitting and receiving circuit in which the invention is embedded, in the form of a basic circuit diagram, Fig. 2 is also a purely schematic representation of a scanning unit according to the invention Fig. 3 a reproduction of various signal curves, Fig. 4 a composition of the address for the histogram memory, as well as Fig. 5 a histogram resulting from the invention.

[0020] Fig. 1 shows a highly simplified circuit to illustrate the object of the present invention. A preferred area of ​​application of the invention is the distance measurement of a detector 3 to an object in space. For this purpose, a sampling circuit 5 is provided, which outputs an output signal via an emitter circuit 2. This emitter 1, for example in the form of a light-emitting diode or laser diode, sends a light pulse, which is reflected by the object in space and received by the detector 3, for example in the form of a photodiode, SiPM, APD, or SPAD diode. If necessary, it is possible to first pre-process a signal 14 received by the detector in analog form using a signal amplifier 4 before further processing. A signal 14 thus prepared is finally processed in the sampling unit 5 as follows.

[0021] Fig. Figure 2 shows a circuit for processing signal 14 within the scanning unit 5. The entire scanning unit is not shown here. This is merely a schematic representation.

[0022] A complete measurement with storage of the measured value in the histogram memory 6 is performed with a fixed phase position of the system clock relative to the clock generator 9. The pulse for the emitter 2 is derived directly from the clock generator 9 without influence by the phase control 8. The subsequent measurements are then performed with a phase position changed, increased, or reduced by the phase control 8, so that, for example, after eight measurements have been performed, measured values ​​with eight different phases have been stored in the histogram memory 6, whereby the temporal resolution of the histogram stored in the histogram memory 6 is improved by a factor of eight.

[0023] Deserialization is performed using a three-stage, eight-fold shift register with dynamically adjustable phase, from which the evaluation circuit 10 is fed. The deserializer 7 has a sampling clock of 400 MHz and also receives a system clock of 100 MHz from a clock generator 9. With each measurement, the sampling clock is phase-shifted relative to the clock generator 9, which is achieved using a phase controller 8. Furthermore, the figure shows that a signal generator 13 is also connected to the clock generator 9 to transmit a coordinated output signal to the emitter 1, which is synchronized with the clock generator 9 to maintain a relationship between the transmitted and received signals.

[0024] The individual bit vectors 15 are then fed to the evaluation circuit 10, where they react to rising edges, i.e., a change from no detected reflection to the detection of a reflection. The evaluation circuit 10 is designed as a priority encoder with a decreasing priority over time, so that the first rising edge is detected within each bit vector 15. This information is passed to an address encoder 11, which addresses a histogram memory 6 to trigger an increment at the position in the memory that corresponds to the temporal and phase position of a rising edge.

[0025] The address 23 generated by the address encoder 11 is composed as in Fig. 4 consists of three parts. The first part, i.e., the first two bits, is the value of the system clock counter 20 at which the first positive edge was detected. The second part, i.e., the following three bits, is the result 21 of the priority encoder of the bit vector 15, in which the first positive edge was detected. The third part is the current phase angle 22 used in the measurement.

[0026] Due to the phase shift, the temporal and thus spatial resolution of the system can be increased. By evaluating the histogram memory 6, a conclusion can then be drawn about the position of an object in space.

[0027] In Fig. Figure 3 initially illustrates the timing sequence using various processes. Four system clocks 17 are shown here, corresponding to sixteen sampling clocks 16. The analog signal shown at the top is assigned a threshold value 18, which, when exceeded, triggers a rising edge in the evaluation circuit 10. When the threshold is exceeded for the first time, the evaluation circuit 10 will output the position of the first rising edge within the bit vector 15 in this system clock. This means that the threshold value 18 was exceeded by the signal 14 in this system clock. This signal is sampled with the sampling clock 16 in the deserializer 7 and output in the form of an n-bit vector, in this case an 8-bit vector, and examined by the priority encoder for the exact position of the rising edge within the system clock 17.

[0028] To increase accuracy, a phase shift occurs between system clock 17 and signal 14 during each measurement, so that the sampling time is shifted depending on the degree of the phase shift. If an eighth of a phase is used, the subsequent resolution will be eight times higher. For this purpose, the same measurement is performed eight times in succession, each time recorded in a histogram buffer, along with the temporal position of the rising edge and the respective phase angle. This allows the histogram buffer to be addressed and incremented by one for each rising edge.

[0029] It turns out that in Fig.The histogram shown in Figure 5 shows the number A of rising edges plotted against the time it takes the light to travel from the emitter to the object in the room and back. Although statistical errors occur, such as signal noise or stray light, the concentration of rising edges in certain areas allows the positions of reflective objects to be reliably detected.

[0030] What is described above is a device for electronically sampling an analog signal, which enables precise sampling with a temporal resolution above the maximum possible sampling rate of the system in a simple and cost-effective circuit. LIST OF REFERENCE SYMBOLS 1 emitter 2 emitter circuit 3 Detector 4 signal amplifiers 5 scanning unit 6 histogram memories 7 Deserializer 8 Phase control 9 clock generator 10 Evaluation circuit 11 Address encoders 12 internal memory 13 clocks 14 Signal 15 bit vectors 16 sampling clock 17 system clock 18 Threshold 19 System clock counter 20 Value of the system clock counter 21 Result of the priority encoder 22 Phase position 23 Address

Claims

[1] A device for electronically sampling an analog signal (14), comprising a sampling unit (5) with a clock generator (9) for generating a sampling clock (16), a deserializer (7) for decomposing a signal (14) into bit vectors (15), and at least one evaluation circuit (10) for evaluating the bit vectors (15), wherein the clock generator (9) is assigned a phase shifter for shifting the phase position of the sampling clock (16) predetermined by the clock generator (9), and the evaluation circuit (10) and an address encoder (11) for addressing the memory locations of a histogram memory depending on a position of the rising edge and a phase position of the relevant bit vector (15) in the system clock (17), characterized by that the evaluation circuits (10) are priority encoders. [2] Device according to claim 1, characterized bythat the deserializer is a three-stage, eight-fold shift register, which preferably operates in double data rate mode and preferably with a sampling clock (18) of 400 MHz or a higher clock frequency. [3] Device according to one of the preceding claims, characterized by that the deserializer (7) and / or the evaluation circuits (10) and / or the address encoders (11) and / or the histogram memory (12) are implemented in a field programmable gate array (FPGA).

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